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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ |
3 | * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 | |
4 | * | |
5 | * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> | |
6 | * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> | |
7 | * | |
8 | * Ani Joshi / Jeff Garzik | |
9 | * - Code cleanup | |
10 | * | |
11 | * Michel Danzer <michdaen@iiic.ethz.ch> | |
12 | * - 15/16 bit cleanup | |
13 | * - fix panning | |
14 | * | |
15 | * Benjamin Herrenschmidt | |
16 | * - pmac-specific PM stuff | |
17 | * - various fixes & cleanups | |
18 | * | |
19 | * Andreas Hundt <andi@convergence.de> | |
20 | * - FB_ACTIVATE fixes | |
21 | * | |
22 | * Paul Mackerras <paulus@samba.org> | |
23 | * - Convert to new framebuffer API, | |
24 | * fix colormap setting at 16 bits/pixel (565) | |
25 | * | |
26 | * Paul Mundt | |
27 | * - PCI hotplug | |
28 | * | |
29 | * Jon Smirl <jonsmirl@yahoo.com> | |
30 | * - PCI ID update | |
31 | * - replace ROM BIOS search | |
32 | * | |
33 | * Based off of Geert's atyfb.c and vfb.c. | |
34 | * | |
35 | * TODO: | |
36 | * - monitor sensing (DDC) | |
37 | * - virtual display | |
38 | * - other platform support (only ppc/x86 supported) | |
39 | * - hardware cursor support | |
40 | * | |
41 | * Please cc: your patches to brad@neruo.com. | |
42 | */ | |
43 | ||
44 | /* | |
45 | * A special note of gratitude to ATI's devrel for providing documentation, | |
46 | * example code and hardware. Thanks Nitya. -atong and brad | |
47 | */ | |
48 | ||
49 | ||
1da177e4 LT |
50 | #include <linux/module.h> |
51 | #include <linux/moduleparam.h> | |
52 | #include <linux/kernel.h> | |
53 | #include <linux/errno.h> | |
54 | #include <linux/string.h> | |
55 | #include <linux/mm.h> | |
1da177e4 LT |
56 | #include <linux/vmalloc.h> |
57 | #include <linux/delay.h> | |
58 | #include <linux/interrupt.h> | |
84902b7a | 59 | #include <linux/uaccess.h> |
1da177e4 LT |
60 | #include <linux/fb.h> |
61 | #include <linux/init.h> | |
62 | #include <linux/pci.h> | |
63 | #include <linux/ioport.h> | |
64 | #include <linux/console.h> | |
5474c120 | 65 | #include <linux/backlight.h> |
1da177e4 LT |
66 | #include <asm/io.h> |
67 | ||
68 | #ifdef CONFIG_PPC_PMAC | |
e8222502 | 69 | #include <asm/machdep.h> |
1da177e4 LT |
70 | #include <asm/pmac_feature.h> |
71 | #include <asm/prom.h> | |
1da177e4 LT |
72 | #include "../macmodes.h" |
73 | #endif | |
74 | ||
75 | #ifdef CONFIG_PMAC_BACKLIGHT | |
76 | #include <asm/backlight.h> | |
77 | #endif | |
78 | ||
79 | #ifdef CONFIG_BOOTX_TEXT | |
80 | #include <asm/btext.h> | |
81 | #endif /* CONFIG_BOOTX_TEXT */ | |
82 | ||
1da177e4 LT |
83 | #include <video/aty128.h> |
84 | ||
85 | /* Debug flag */ | |
86 | #undef DEBUG | |
87 | ||
88 | #ifdef DEBUG | |
659f675e EG |
89 | #define DBG(fmt, args...) \ |
90 | printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); | |
1da177e4 LT |
91 | #else |
92 | #define DBG(fmt, args...) | |
93 | #endif | |
94 | ||
95 | #ifndef CONFIG_PPC_PMAC | |
96 | /* default mode */ | |
ca9384c5 | 97 | static const struct fb_var_screeninfo default_var = { |
1da177e4 LT |
98 | /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ |
99 | 640, 480, 640, 480, 0, 0, 8, 0, | |
100 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, | |
101 | 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, | |
102 | 0, FB_VMODE_NONINTERLACED | |
103 | }; | |
104 | ||
105 | #else /* CONFIG_PPC_PMAC */ | |
106 | /* default to 1024x768 at 75Hz on PPC - this will work | |
107 | * on the iMac, the usual 640x480 @ 60Hz doesn't. */ | |
ca9384c5 | 108 | static const struct fb_var_screeninfo default_var = { |
1da177e4 LT |
109 | /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ |
110 | 1024, 768, 1024, 768, 0, 0, 8, 0, | |
111 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, | |
112 | 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, | |
113 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
114 | FB_VMODE_NONINTERLACED | |
115 | }; | |
116 | #endif /* CONFIG_PPC_PMAC */ | |
117 | ||
118 | /* default modedb mode */ | |
119 | /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ | |
58ec01ce | 120 | static const struct fb_videomode defaultmode = { |
1da177e4 LT |
121 | .refresh = 60, |
122 | .xres = 640, | |
123 | .yres = 480, | |
124 | .pixclock = 39722, | |
125 | .left_margin = 48, | |
126 | .right_margin = 16, | |
127 | .upper_margin = 33, | |
128 | .lower_margin = 10, | |
129 | .hsync_len = 96, | |
130 | .vsync_len = 2, | |
131 | .sync = 0, | |
132 | .vmode = FB_VMODE_NONINTERLACED | |
133 | }; | |
134 | ||
135 | /* Chip generations */ | |
136 | enum { | |
137 | rage_128, | |
138 | rage_128_pci, | |
139 | rage_128_pro, | |
140 | rage_128_pro_pci, | |
141 | rage_M3, | |
142 | rage_M3_pci, | |
143 | rage_M4, | |
144 | rage_128_ultra, | |
145 | }; | |
146 | ||
147 | /* Must match above enum */ | |
48c68c4f | 148 | static char * const r128_family[] = { |
1da177e4 LT |
149 | "AGP", |
150 | "PCI", | |
151 | "PRO AGP", | |
152 | "PRO PCI", | |
153 | "M3 AGP", | |
154 | "M3 PCI", | |
155 | "M4 AGP", | |
156 | "Ultra AGP", | |
157 | }; | |
158 | ||
159 | /* | |
160 | * PCI driver prototypes | |
161 | */ | |
162 | static int aty128_probe(struct pci_dev *pdev, | |
163 | const struct pci_device_id *ent); | |
164 | static void aty128_remove(struct pci_dev *pdev); | |
165 | static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); | |
166 | static int aty128_pci_resume(struct pci_dev *pdev); | |
167 | static int aty128_do_resume(struct pci_dev *pdev); | |
168 | ||
169 | /* supported Rage128 chipsets */ | |
c622d7a3 | 170 | static const struct pci_device_id aty128_pci_tbl[] = { |
1da177e4 LT |
171 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, |
172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, | |
173 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, | |
174 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, | |
175 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, | |
176 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, | |
177 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, | |
178 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, | |
179 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, | |
180 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
181 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, | |
182 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
183 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, | |
184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
185 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, | |
186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | |
187 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, | |
188 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
189 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, | |
190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
191 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, | |
192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
193 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, | |
194 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
195 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, | |
196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
197 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, | |
198 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
199 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, | |
200 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
201 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, | |
202 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
203 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, | |
204 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
205 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, | |
206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
207 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, | |
208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
209 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, | |
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | |
211 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, | |
212 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
213 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, | |
214 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | |
215 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, | |
216 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
217 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, | |
218 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
219 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, | |
220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
221 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, | |
222 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
223 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, | |
224 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
225 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, | |
226 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | |
227 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, | |
228 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | |
229 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, | |
230 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
231 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, | |
232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
233 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, | |
234 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | |
235 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, | |
236 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
237 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, | |
238 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
239 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, | |
240 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | |
241 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, | |
242 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
243 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, | |
244 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
245 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, | |
246 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
247 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, | |
248 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
249 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, | |
250 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
251 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, | |
252 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | |
253 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, | |
254 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
255 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, | |
256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
257 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, | |
258 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
259 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, | |
260 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
261 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, | |
262 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
263 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, | |
264 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | |
265 | { 0, } | |
266 | }; | |
267 | ||
268 | MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); | |
269 | ||
270 | static struct pci_driver aty128fb_driver = { | |
271 | .name = "aty128fb", | |
272 | .id_table = aty128_pci_tbl, | |
273 | .probe = aty128_probe, | |
48c68c4f | 274 | .remove = aty128_remove, |
1da177e4 LT |
275 | .suspend = aty128_pci_suspend, |
276 | .resume = aty128_pci_resume, | |
277 | }; | |
278 | ||
279 | /* packed BIOS settings */ | |
280 | #ifndef CONFIG_PPC | |
281 | typedef struct { | |
282 | u8 clock_chip_type; | |
283 | u8 struct_size; | |
284 | u8 accelerator_entry; | |
285 | u8 VGA_entry; | |
286 | u16 VGA_table_offset; | |
287 | u16 POST_table_offset; | |
288 | u16 XCLK; | |
289 | u16 MCLK; | |
290 | u8 num_PLL_blocks; | |
291 | u8 size_PLL_blocks; | |
292 | u16 PCLK_ref_freq; | |
293 | u16 PCLK_ref_divider; | |
294 | u32 PCLK_min_freq; | |
295 | u32 PCLK_max_freq; | |
296 | u16 MCLK_ref_freq; | |
297 | u16 MCLK_ref_divider; | |
298 | u32 MCLK_min_freq; | |
299 | u32 MCLK_max_freq; | |
300 | u16 XCLK_ref_freq; | |
301 | u16 XCLK_ref_divider; | |
302 | u32 XCLK_min_freq; | |
303 | u32 XCLK_max_freq; | |
304 | } __attribute__ ((packed)) PLL_BLOCK; | |
305 | #endif /* !CONFIG_PPC */ | |
306 | ||
307 | /* onboard memory information */ | |
308 | struct aty128_meminfo { | |
309 | u8 ML; | |
310 | u8 MB; | |
311 | u8 Trcd; | |
312 | u8 Trp; | |
313 | u8 Twr; | |
314 | u8 CL; | |
315 | u8 Tr2w; | |
316 | u8 LoopLatency; | |
317 | u8 DspOn; | |
318 | u8 Rloop; | |
319 | const char *name; | |
320 | }; | |
321 | ||
322 | /* various memory configurations */ | |
08424464 JL |
323 | static const struct aty128_meminfo sdr_128 = { |
324 | .ML = 4, | |
325 | .MB = 4, | |
326 | .Trcd = 3, | |
327 | .Trp = 3, | |
328 | .Twr = 1, | |
329 | .CL = 3, | |
330 | .Tr2w = 1, | |
331 | .LoopLatency = 16, | |
332 | .DspOn = 30, | |
333 | .Rloop = 16, | |
334 | .name = "128-bit SDR SGRAM (1:1)", | |
335 | }; | |
336 | ||
337 | static const struct aty128_meminfo sdr_64 = { | |
338 | .ML = 4, | |
339 | .MB = 8, | |
340 | .Trcd = 3, | |
341 | .Trp = 3, | |
342 | .Twr = 1, | |
343 | .CL = 3, | |
344 | .Tr2w = 1, | |
345 | .LoopLatency = 17, | |
346 | .DspOn = 46, | |
347 | .Rloop = 17, | |
348 | .name = "64-bit SDR SGRAM (1:1)", | |
349 | }; | |
350 | ||
351 | static const struct aty128_meminfo sdr_sgram = { | |
352 | .ML = 4, | |
353 | .MB = 4, | |
354 | .Trcd = 1, | |
355 | .Trp = 2, | |
356 | .Twr = 1, | |
357 | .CL = 2, | |
358 | .Tr2w = 1, | |
359 | .LoopLatency = 16, | |
360 | .DspOn = 24, | |
361 | .Rloop = 16, | |
362 | .name = "64-bit SDR SGRAM (2:1)", | |
363 | }; | |
364 | ||
365 | static const struct aty128_meminfo ddr_sgram = { | |
366 | .ML = 4, | |
367 | .MB = 4, | |
368 | .Trcd = 3, | |
369 | .Trp = 3, | |
370 | .Twr = 2, | |
371 | .CL = 3, | |
372 | .Tr2w = 1, | |
373 | .LoopLatency = 16, | |
374 | .DspOn = 31, | |
375 | .Rloop = 16, | |
376 | .name = "64-bit DDR SGRAM", | |
377 | }; | |
1da177e4 | 378 | |
ca9384c5 | 379 | static const struct fb_fix_screeninfo aty128fb_fix = { |
1da177e4 LT |
380 | .id = "ATY Rage128", |
381 | .type = FB_TYPE_PACKED_PIXELS, | |
382 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
383 | .xpanstep = 8, | |
384 | .ypanstep = 1, | |
385 | .mmio_len = 0x2000, | |
386 | .accel = FB_ACCEL_ATI_RAGE128, | |
387 | }; | |
388 | ||
48c68c4f | 389 | static char *mode_option = NULL; |
1da177e4 LT |
390 | |
391 | #ifdef CONFIG_PPC_PMAC | |
48c68c4f GKH |
392 | static int default_vmode = VMODE_1024_768_60; |
393 | static int default_cmode = CMODE_8; | |
1da177e4 LT |
394 | #endif |
395 | ||
48c68c4f GKH |
396 | static int default_crt_on = 0; |
397 | static int default_lcd_on = 1; | |
9a71af2c | 398 | static bool mtrr = true; |
1da177e4 | 399 | |
a79530e4 | 400 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
202d4e60 | 401 | #ifdef CONFIG_PMAC_BACKLIGHT |
48c68c4f | 402 | static int backlight = 1; |
202d4e60 | 403 | #else |
48c68c4f | 404 | static int backlight = 0; |
202d4e60 | 405 | #endif |
a79530e4 | 406 | #endif |
202d4e60 | 407 | |
1da177e4 LT |
408 | /* PLL constants */ |
409 | struct aty128_constants { | |
410 | u32 ref_clk; | |
411 | u32 ppll_min; | |
412 | u32 ppll_max; | |
413 | u32 ref_divider; | |
414 | u32 xclk; | |
415 | u32 fifo_width; | |
416 | u32 fifo_depth; | |
417 | }; | |
418 | ||
419 | struct aty128_crtc { | |
420 | u32 gen_cntl; | |
421 | u32 h_total, h_sync_strt_wid; | |
422 | u32 v_total, v_sync_strt_wid; | |
423 | u32 pitch; | |
424 | u32 offset, offset_cntl; | |
425 | u32 xoffset, yoffset; | |
426 | u32 vxres, vyres; | |
427 | u32 depth, bpp; | |
428 | }; | |
429 | ||
430 | struct aty128_pll { | |
431 | u32 post_divider; | |
432 | u32 feedback_divider; | |
433 | u32 vclk; | |
434 | }; | |
435 | ||
436 | struct aty128_ddafifo { | |
437 | u32 dda_config; | |
438 | u32 dda_on_off; | |
439 | }; | |
440 | ||
441 | /* register values for a specific mode */ | |
442 | struct aty128fb_par { | |
443 | struct aty128_crtc crtc; | |
444 | struct aty128_pll pll; | |
445 | struct aty128_ddafifo fifo_reg; | |
446 | u32 accel_flags; | |
447 | struct aty128_constants constants; /* PLL and others */ | |
448 | void __iomem *regbase; /* remapped mmio */ | |
449 | u32 vram_size; /* onboard video ram */ | |
450 | int chip_gen; | |
451 | const struct aty128_meminfo *mem; /* onboard mem info */ | |
f4447dde | 452 | int wc_cookie; |
1da177e4 LT |
453 | int blitter_may_be_busy; |
454 | int fifo_slots; /* free slots in FIFO (64 max) */ | |
455 | ||
1da177e4 LT |
456 | int crt_on, lcd_on; |
457 | struct pci_dev *pdev; | |
458 | struct fb_info *next; | |
459 | int asleep; | |
460 | int lock_blank; | |
461 | ||
462 | u8 red[32]; /* see aty128fb_setcolreg */ | |
463 | u8 green[64]; | |
464 | u8 blue[32]; | |
465 | u32 pseudo_palette[16]; /* used for TRUECOLOR */ | |
466 | }; | |
467 | ||
468 | ||
469 | #define round_div(n, d) ((n+(d/2))/d) | |
470 | ||
471 | static int aty128fb_check_var(struct fb_var_screeninfo *var, | |
472 | struct fb_info *info); | |
473 | static int aty128fb_set_par(struct fb_info *info); | |
474 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
475 | u_int transp, struct fb_info *info); | |
476 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, | |
477 | struct fb_info *fb); | |
478 | static int aty128fb_blank(int blank, struct fb_info *fb); | |
67a6680d | 479 | static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); |
1da177e4 LT |
480 | static int aty128fb_sync(struct fb_info *info); |
481 | ||
482 | /* | |
483 | * Internal routines | |
484 | */ | |
485 | ||
486 | static int aty128_encode_var(struct fb_var_screeninfo *var, | |
487 | const struct aty128fb_par *par); | |
488 | static int aty128_decode_var(struct fb_var_screeninfo *var, | |
489 | struct aty128fb_par *par); | |
490 | #if 0 | |
48c68c4f GKH |
491 | static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios); |
492 | static void __iomem *aty128_map_ROM(struct pci_dev *pdev, | |
493 | const struct aty128fb_par *par); | |
1da177e4 LT |
494 | #endif |
495 | static void aty128_timings(struct aty128fb_par *par); | |
496 | static void aty128_init_engine(struct aty128fb_par *par); | |
497 | static void aty128_reset_engine(const struct aty128fb_par *par); | |
498 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par); | |
499 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); | |
500 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par); | |
501 | static void wait_for_idle(struct aty128fb_par *par); | |
502 | static u32 depth_to_dst(u32 depth); | |
4b755999 MH |
503 | |
504 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | |
e01af038 | 505 | static void aty128_bl_set_power(struct fb_info *info, int power); |
4b755999 | 506 | #endif |
1da177e4 LT |
507 | |
508 | #define BIOS_IN8(v) (readb(bios + (v))) | |
509 | #define BIOS_IN16(v) (readb(bios + (v)) | \ | |
510 | (readb(bios + (v) + 1) << 8)) | |
511 | #define BIOS_IN32(v) (readb(bios + (v)) | \ | |
512 | (readb(bios + (v) + 1) << 8) | \ | |
513 | (readb(bios + (v) + 2) << 16) | \ | |
514 | (readb(bios + (v) + 3) << 24)) | |
515 | ||
516 | ||
517 | static struct fb_ops aty128fb_ops = { | |
518 | .owner = THIS_MODULE, | |
519 | .fb_check_var = aty128fb_check_var, | |
520 | .fb_set_par = aty128fb_set_par, | |
521 | .fb_setcolreg = aty128fb_setcolreg, | |
522 | .fb_pan_display = aty128fb_pan_display, | |
523 | .fb_blank = aty128fb_blank, | |
524 | .fb_ioctl = aty128fb_ioctl, | |
525 | .fb_sync = aty128fb_sync, | |
526 | .fb_fillrect = cfb_fillrect, | |
527 | .fb_copyarea = cfb_copyarea, | |
528 | .fb_imageblit = cfb_imageblit, | |
1da177e4 LT |
529 | }; |
530 | ||
1da177e4 LT |
531 | /* |
532 | * Functions to read from/write to the mmio registers | |
533 | * - endian conversions may possibly be avoided by | |
534 | * using the other register aperture. TODO. | |
535 | */ | |
536 | static inline u32 _aty_ld_le32(volatile unsigned int regindex, | |
537 | const struct aty128fb_par *par) | |
538 | { | |
539 | return readl (par->regbase + regindex); | |
540 | } | |
541 | ||
542 | static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, | |
543 | const struct aty128fb_par *par) | |
544 | { | |
545 | writel (val, par->regbase + regindex); | |
546 | } | |
547 | ||
548 | static inline u8 _aty_ld_8(unsigned int regindex, | |
549 | const struct aty128fb_par *par) | |
550 | { | |
551 | return readb (par->regbase + regindex); | |
552 | } | |
553 | ||
554 | static inline void _aty_st_8(unsigned int regindex, u8 val, | |
555 | const struct aty128fb_par *par) | |
556 | { | |
557 | writeb (val, par->regbase + regindex); | |
558 | } | |
559 | ||
560 | #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) | |
561 | #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) | |
562 | #define aty_ld_8(regindex) _aty_ld_8(regindex, par) | |
563 | #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) | |
564 | ||
565 | /* | |
566 | * Functions to read from/write to the pll registers | |
567 | */ | |
568 | ||
569 | #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) | |
570 | #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) | |
571 | ||
572 | ||
573 | static u32 _aty_ld_pll(unsigned int pll_index, | |
574 | const struct aty128fb_par *par) | |
575 | { | |
576 | aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); | |
577 | return aty_ld_le32(CLOCK_CNTL_DATA); | |
578 | } | |
579 | ||
580 | ||
581 | static void _aty_st_pll(unsigned int pll_index, u32 val, | |
582 | const struct aty128fb_par *par) | |
583 | { | |
584 | aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); | |
585 | aty_st_le32(CLOCK_CNTL_DATA, val); | |
586 | } | |
587 | ||
588 | ||
589 | /* return true when the PLL has completed an atomic update */ | |
590 | static int aty_pll_readupdate(const struct aty128fb_par *par) | |
591 | { | |
592 | return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); | |
593 | } | |
594 | ||
595 | ||
596 | static void aty_pll_wait_readupdate(const struct aty128fb_par *par) | |
597 | { | |
598 | unsigned long timeout = jiffies + HZ/100; // should be more than enough | |
599 | int reset = 1; | |
600 | ||
601 | while (time_before(jiffies, timeout)) | |
602 | if (aty_pll_readupdate(par)) { | |
603 | reset = 0; | |
604 | break; | |
605 | } | |
606 | ||
607 | if (reset) /* reset engine?? */ | |
608 | printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); | |
609 | } | |
610 | ||
611 | ||
612 | /* tell PLL to update */ | |
613 | static void aty_pll_writeupdate(const struct aty128fb_par *par) | |
614 | { | |
615 | aty_pll_wait_readupdate(par); | |
616 | ||
617 | aty_st_pll(PPLL_REF_DIV, | |
618 | aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); | |
619 | } | |
620 | ||
621 | ||
622 | /* write to the scratch register to test r/w functionality */ | |
48c68c4f | 623 | static int register_test(const struct aty128fb_par *par) |
1da177e4 LT |
624 | { |
625 | u32 val; | |
626 | int flag = 0; | |
627 | ||
628 | val = aty_ld_le32(BIOS_0_SCRATCH); | |
629 | ||
630 | aty_st_le32(BIOS_0_SCRATCH, 0x55555555); | |
631 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { | |
632 | aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); | |
633 | ||
634 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) | |
635 | flag = 1; | |
636 | } | |
637 | ||
638 | aty_st_le32(BIOS_0_SCRATCH, val); // restore value | |
639 | return flag; | |
640 | } | |
641 | ||
642 | ||
643 | /* | |
644 | * Accelerator engine functions | |
645 | */ | |
646 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) | |
647 | { | |
648 | int i; | |
649 | ||
650 | for (;;) { | |
651 | for (i = 0; i < 2000000; i++) { | |
652 | par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; | |
653 | if (par->fifo_slots >= entries) | |
654 | return; | |
655 | } | |
656 | aty128_reset_engine(par); | |
657 | } | |
658 | } | |
659 | ||
660 | ||
661 | static void wait_for_idle(struct aty128fb_par *par) | |
662 | { | |
663 | int i; | |
664 | ||
665 | do_wait_for_fifo(64, par); | |
666 | ||
667 | for (;;) { | |
668 | for (i = 0; i < 2000000; i++) { | |
669 | if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { | |
670 | aty128_flush_pixel_cache(par); | |
671 | par->blitter_may_be_busy = 0; | |
672 | return; | |
673 | } | |
674 | } | |
675 | aty128_reset_engine(par); | |
676 | } | |
677 | } | |
678 | ||
679 | ||
680 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par) | |
681 | { | |
682 | if (par->fifo_slots < entries) | |
683 | do_wait_for_fifo(64, par); | |
684 | par->fifo_slots -= entries; | |
685 | } | |
686 | ||
687 | ||
688 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par) | |
689 | { | |
690 | int i; | |
691 | u32 tmp; | |
692 | ||
693 | tmp = aty_ld_le32(PC_NGUI_CTLSTAT); | |
694 | tmp &= ~(0x00ff); | |
695 | tmp |= 0x00ff; | |
696 | aty_st_le32(PC_NGUI_CTLSTAT, tmp); | |
697 | ||
698 | for (i = 0; i < 2000000; i++) | |
699 | if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) | |
700 | break; | |
701 | } | |
702 | ||
703 | ||
704 | static void aty128_reset_engine(const struct aty128fb_par *par) | |
705 | { | |
706 | u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; | |
707 | ||
708 | aty128_flush_pixel_cache(par); | |
709 | ||
710 | clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); | |
711 | mclk_cntl = aty_ld_pll(MCLK_CNTL); | |
712 | ||
713 | aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); | |
714 | ||
715 | gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); | |
716 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); | |
717 | aty_ld_le32(GEN_RESET_CNTL); | |
718 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); | |
719 | aty_ld_le32(GEN_RESET_CNTL); | |
720 | ||
721 | aty_st_pll(MCLK_CNTL, mclk_cntl); | |
722 | aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); | |
723 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); | |
724 | ||
725 | /* use old pio mode */ | |
726 | aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); | |
727 | ||
728 | DBG("engine reset"); | |
729 | } | |
730 | ||
731 | ||
732 | static void aty128_init_engine(struct aty128fb_par *par) | |
733 | { | |
734 | u32 pitch_value; | |
735 | ||
736 | wait_for_idle(par); | |
737 | ||
738 | /* 3D scaler not spoken here */ | |
739 | wait_for_fifo(1, par); | |
740 | aty_st_le32(SCALE_3D_CNTL, 0x00000000); | |
741 | ||
742 | aty128_reset_engine(par); | |
743 | ||
744 | pitch_value = par->crtc.pitch; | |
745 | if (par->crtc.bpp == 24) { | |
746 | pitch_value = pitch_value * 3; | |
747 | } | |
748 | ||
749 | wait_for_fifo(4, par); | |
750 | /* setup engine offset registers */ | |
751 | aty_st_le32(DEFAULT_OFFSET, 0x00000000); | |
752 | ||
753 | /* setup engine pitch registers */ | |
754 | aty_st_le32(DEFAULT_PITCH, pitch_value); | |
755 | ||
756 | /* set the default scissor register to max dimensions */ | |
757 | aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); | |
758 | ||
759 | /* set the drawing controls registers */ | |
760 | aty_st_le32(DP_GUI_MASTER_CNTL, | |
761 | GMC_SRC_PITCH_OFFSET_DEFAULT | | |
762 | GMC_DST_PITCH_OFFSET_DEFAULT | | |
763 | GMC_SRC_CLIP_DEFAULT | | |
764 | GMC_DST_CLIP_DEFAULT | | |
765 | GMC_BRUSH_SOLIDCOLOR | | |
766 | (depth_to_dst(par->crtc.depth) << 8) | | |
767 | GMC_SRC_DSTCOLOR | | |
768 | GMC_BYTE_ORDER_MSB_TO_LSB | | |
769 | GMC_DP_CONVERSION_TEMP_6500 | | |
770 | ROP3_PATCOPY | | |
771 | GMC_DP_SRC_RECT | | |
772 | GMC_3D_FCN_EN_CLR | | |
773 | GMC_DST_CLR_CMP_FCN_CLEAR | | |
774 | GMC_AUX_CLIP_CLEAR | | |
775 | GMC_WRITE_MASK_SET); | |
776 | ||
777 | wait_for_fifo(8, par); | |
778 | /* clear the line drawing registers */ | |
779 | aty_st_le32(DST_BRES_ERR, 0); | |
780 | aty_st_le32(DST_BRES_INC, 0); | |
781 | aty_st_le32(DST_BRES_DEC, 0); | |
782 | ||
783 | /* set brush color registers */ | |
784 | aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ | |
785 | aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ | |
786 | ||
787 | /* set source color registers */ | |
788 | aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ | |
789 | aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ | |
790 | ||
791 | /* default write mask */ | |
792 | aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); | |
793 | ||
794 | /* Wait for all the writes to be completed before returning */ | |
795 | wait_for_idle(par); | |
796 | } | |
797 | ||
798 | ||
799 | /* convert depth values to their register representation */ | |
800 | static u32 depth_to_dst(u32 depth) | |
801 | { | |
802 | if (depth <= 8) | |
803 | return DST_8BPP; | |
804 | else if (depth <= 15) | |
805 | return DST_15BPP; | |
806 | else if (depth == 16) | |
807 | return DST_16BPP; | |
808 | else if (depth <= 24) | |
809 | return DST_24BPP; | |
810 | else if (depth <= 32) | |
811 | return DST_32BPP; | |
812 | ||
813 | return -EINVAL; | |
814 | } | |
815 | ||
816 | /* | |
817 | * PLL informations retreival | |
818 | */ | |
819 | ||
820 | ||
821 | #ifndef __sparc__ | |
48c68c4f GKH |
822 | static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, |
823 | struct pci_dev *dev) | |
1da177e4 LT |
824 | { |
825 | u16 dptr; | |
826 | u8 rom_type; | |
827 | void __iomem *bios; | |
828 | size_t rom_size; | |
829 | ||
830 | /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ | |
831 | unsigned int temp; | |
832 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); | |
833 | temp &= 0x00ffffffu; | |
834 | temp |= 0x04 << 24; | |
835 | aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); | |
836 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); | |
837 | ||
838 | bios = pci_map_rom(dev, &rom_size); | |
839 | ||
840 | if (!bios) { | |
841 | printk(KERN_ERR "aty128fb: ROM failed to map\n"); | |
842 | return NULL; | |
843 | } | |
844 | ||
845 | /* Very simple test to make sure it appeared */ | |
846 | if (BIOS_IN16(0) != 0xaa55) { | |
3b4abffb OH |
847 | printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " |
848 | " be 0xaa55\n", BIOS_IN16(0)); | |
1da177e4 LT |
849 | goto failed; |
850 | } | |
851 | ||
852 | /* Look for the PCI data to check the ROM type */ | |
853 | dptr = BIOS_IN16(0x18); | |
854 | ||
659f675e EG |
855 | /* Check the PCI data signature. If it's wrong, we still assume a normal |
856 | * x86 ROM for now, until I've verified this works everywhere. | |
857 | * The goal here is more to phase out Open Firmware images. | |
1da177e4 | 858 | * |
659f675e EG |
859 | * Currently, we only look at the first PCI data, we could iteratre and |
860 | * deal with them all, and we should use fb_bios_start relative to start | |
861 | * of image and not relative start of ROM, but so far, I never found a | |
862 | * dual-image ATI card. | |
1da177e4 LT |
863 | * |
864 | * typedef struct { | |
865 | * u32 signature; + 0x00 | |
866 | * u16 vendor; + 0x04 | |
867 | * u16 device; + 0x06 | |
868 | * u16 reserved_1; + 0x08 | |
869 | * u16 dlen; + 0x0a | |
870 | * u8 drevision; + 0x0c | |
871 | * u8 class_hi; + 0x0d | |
872 | * u16 class_lo; + 0x0e | |
873 | * u16 ilen; + 0x10 | |
874 | * u16 irevision; + 0x12 | |
875 | * u8 type; + 0x14 | |
876 | * u8 indicator; + 0x15 | |
877 | * u16 reserved_2; + 0x16 | |
878 | * } pci_data_t; | |
879 | */ | |
880 | if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { | |
881 | printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", | |
882 | BIOS_IN32(dptr)); | |
883 | goto anyway; | |
884 | } | |
885 | rom_type = BIOS_IN8(dptr + 0x14); | |
886 | switch(rom_type) { | |
887 | case 0: | |
888 | printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); | |
889 | break; | |
890 | case 1: | |
891 | printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); | |
892 | goto failed; | |
893 | case 2: | |
894 | printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); | |
895 | goto failed; | |
896 | default: | |
659f675e EG |
897 | printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", |
898 | rom_type); | |
1da177e4 LT |
899 | goto failed; |
900 | } | |
901 | anyway: | |
902 | return bios; | |
903 | ||
904 | failed: | |
905 | pci_unmap_rom(dev, bios); | |
906 | return NULL; | |
907 | } | |
908 | ||
48c68c4f GKH |
909 | static void aty128_get_pllinfo(struct aty128fb_par *par, |
910 | unsigned char __iomem *bios) | |
1da177e4 LT |
911 | { |
912 | unsigned int bios_hdr; | |
913 | unsigned int bios_pll; | |
914 | ||
915 | bios_hdr = BIOS_IN16(0x48); | |
916 | bios_pll = BIOS_IN16(bios_hdr + 0x30); | |
917 | ||
918 | par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); | |
919 | par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); | |
920 | par->constants.xclk = BIOS_IN16(bios_pll + 0x08); | |
921 | par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); | |
922 | par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); | |
923 | ||
924 | DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", | |
925 | par->constants.ppll_max, par->constants.ppll_min, | |
926 | par->constants.xclk, par->constants.ref_divider, | |
927 | par->constants.ref_clk); | |
928 | ||
929 | } | |
930 | ||
931 | #ifdef CONFIG_X86 | |
48c68c4f | 932 | static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) |
1da177e4 LT |
933 | { |
934 | /* I simplified this code as we used to miss the signatures in | |
935 | * a lot of case. It's now closer to XFree, we just don't check | |
936 | * for signatures at all... Something better will have to be done | |
937 | * if we end up having conflicts | |
938 | */ | |
939 | u32 segstart; | |
940 | unsigned char __iomem *rom_base = NULL; | |
941 | ||
942 | for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { | |
943 | rom_base = ioremap(segstart, 0x10000); | |
944 | if (rom_base == NULL) | |
945 | return NULL; | |
946 | if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) | |
947 | break; | |
948 | iounmap(rom_base); | |
949 | rom_base = NULL; | |
950 | } | |
951 | return rom_base; | |
952 | } | |
953 | #endif | |
954 | #endif /* ndef(__sparc__) */ | |
955 | ||
956 | /* fill in known card constants if pll_block is not available */ | |
48c68c4f | 957 | static void aty128_timings(struct aty128fb_par *par) |
1da177e4 | 958 | { |
e7b410ef | 959 | #ifdef CONFIG_PPC |
1da177e4 LT |
960 | /* instead of a table lookup, assume OF has properly |
961 | * setup the PLL registers and use their values | |
962 | * to set the XCLK values and reference divider values */ | |
963 | ||
964 | u32 x_mpll_ref_fb_div; | |
965 | u32 xclk_cntl; | |
966 | u32 Nx, M; | |
967 | unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; | |
968 | #endif | |
969 | ||
970 | if (!par->constants.ref_clk) | |
971 | par->constants.ref_clk = 2950; | |
972 | ||
e7b410ef | 973 | #ifdef CONFIG_PPC |
1da177e4 LT |
974 | x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); |
975 | xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; | |
976 | Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; | |
977 | M = x_mpll_ref_fb_div & 0x0000ff; | |
978 | ||
979 | par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), | |
980 | (M * PostDivSet[xclk_cntl])); | |
981 | ||
982 | par->constants.ref_divider = | |
983 | aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; | |
984 | #endif | |
985 | ||
986 | if (!par->constants.ref_divider) { | |
987 | par->constants.ref_divider = 0x3b; | |
988 | ||
989 | aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); | |
990 | aty_pll_writeupdate(par); | |
991 | } | |
992 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); | |
993 | aty_pll_writeupdate(par); | |
994 | ||
995 | /* from documentation */ | |
996 | if (!par->constants.ppll_min) | |
997 | par->constants.ppll_min = 12500; | |
998 | if (!par->constants.ppll_max) | |
999 | par->constants.ppll_max = 25000; /* 23000 on some cards? */ | |
1000 | if (!par->constants.xclk) | |
1001 | par->constants.xclk = 0x1d4d; /* same as mclk */ | |
1002 | ||
1003 | par->constants.fifo_width = 128; | |
1004 | par->constants.fifo_depth = 32; | |
1005 | ||
1006 | switch (aty_ld_le32(MEM_CNTL) & 0x3) { | |
1007 | case 0: | |
1008 | par->mem = &sdr_128; | |
1009 | break; | |
1010 | case 1: | |
1011 | par->mem = &sdr_sgram; | |
1012 | break; | |
1013 | case 2: | |
1014 | par->mem = &ddr_sgram; | |
1015 | break; | |
1016 | default: | |
1017 | par->mem = &sdr_sgram; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | ||
1022 | ||
1023 | /* | |
1024 | * CRTC programming | |
1025 | */ | |
1026 | ||
1027 | /* Program the CRTC registers */ | |
1028 | static void aty128_set_crtc(const struct aty128_crtc *crtc, | |
1029 | const struct aty128fb_par *par) | |
1030 | { | |
1031 | aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); | |
1032 | aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); | |
1033 | aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); | |
1034 | aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); | |
1035 | aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); | |
1036 | aty_st_le32(CRTC_PITCH, crtc->pitch); | |
1037 | aty_st_le32(CRTC_OFFSET, crtc->offset); | |
1038 | aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); | |
1039 | /* Disable ATOMIC updating. Is this the right place? */ | |
1040 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); | |
1041 | } | |
1042 | ||
1043 | ||
1044 | static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, | |
1045 | struct aty128_crtc *crtc, | |
1046 | const struct aty128fb_par *par) | |
1047 | { | |
1048 | u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; | |
1049 | u32 left, right, upper, lower, hslen, vslen, sync, vmode; | |
1050 | u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; | |
1051 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; | |
1052 | u32 depth, bytpp; | |
1053 | u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; | |
1054 | ||
1055 | /* input */ | |
1056 | xres = var->xres; | |
1057 | yres = var->yres; | |
1058 | vxres = var->xres_virtual; | |
1059 | vyres = var->yres_virtual; | |
1060 | xoffset = var->xoffset; | |
1061 | yoffset = var->yoffset; | |
1062 | bpp = var->bits_per_pixel; | |
1063 | left = var->left_margin; | |
1064 | right = var->right_margin; | |
1065 | upper = var->upper_margin; | |
1066 | lower = var->lower_margin; | |
1067 | hslen = var->hsync_len; | |
1068 | vslen = var->vsync_len; | |
1069 | sync = var->sync; | |
1070 | vmode = var->vmode; | |
1071 | ||
1072 | if (bpp != 16) | |
1073 | depth = bpp; | |
1074 | else | |
1075 | depth = (var->green.length == 6) ? 16 : 15; | |
1076 | ||
1077 | /* check for mode eligibility | |
1078 | * accept only non interlaced modes */ | |
1079 | if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) | |
1080 | return -EINVAL; | |
1081 | ||
1082 | /* convert (and round up) and validate */ | |
1083 | xres = (xres + 7) & ~7; | |
1084 | xoffset = (xoffset + 7) & ~7; | |
1085 | ||
1086 | if (vxres < xres + xoffset) | |
1087 | vxres = xres + xoffset; | |
1088 | ||
1089 | if (vyres < yres + yoffset) | |
1090 | vyres = yres + yoffset; | |
1091 | ||
1092 | /* convert depth into ATI register depth */ | |
1093 | dst = depth_to_dst(depth); | |
1094 | ||
1095 | if (dst == -EINVAL) { | |
1096 | printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
1100 | /* convert register depth to bytes per pixel */ | |
1101 | bytpp = mode_bytpp[dst]; | |
1102 | ||
1103 | /* make sure there is enough video ram for the mode */ | |
1104 | if ((u32)(vxres * vyres * bytpp) > par->vram_size) { | |
1105 | printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); | |
1106 | return -EINVAL; | |
1107 | } | |
1108 | ||
1109 | h_disp = (xres >> 3) - 1; | |
1110 | h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; | |
1111 | ||
1112 | v_disp = yres - 1; | |
1113 | v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; | |
1114 | ||
1115 | /* check to make sure h_total and v_total are in range */ | |
1116 | if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { | |
1117 | printk(KERN_ERR "aty128fb: invalid width ranges\n"); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
1121 | h_sync_wid = (hslen + 7) >> 3; | |
1122 | if (h_sync_wid == 0) | |
1123 | h_sync_wid = 1; | |
1124 | else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ | |
1125 | h_sync_wid = 0x3f; | |
1126 | ||
1127 | h_sync_strt = (h_disp << 3) + right; | |
1128 | ||
1129 | v_sync_wid = vslen; | |
1130 | if (v_sync_wid == 0) | |
1131 | v_sync_wid = 1; | |
1132 | else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ | |
1133 | v_sync_wid = 0x1f; | |
1134 | ||
1135 | v_sync_strt = v_disp + lower; | |
1136 | ||
1137 | h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; | |
1138 | v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; | |
1139 | ||
1140 | c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; | |
1141 | ||
1142 | crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); | |
1143 | ||
1144 | crtc->h_total = h_total | (h_disp << 16); | |
1145 | crtc->v_total = v_total | (v_disp << 16); | |
1146 | ||
1147 | crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | | |
1148 | (h_sync_pol << 23); | |
1149 | crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | | |
1150 | (v_sync_pol << 23); | |
1151 | ||
1152 | crtc->pitch = vxres >> 3; | |
1153 | ||
1154 | crtc->offset = 0; | |
1155 | ||
1156 | if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) | |
1157 | crtc->offset_cntl = 0x00010000; | |
1158 | else | |
1159 | crtc->offset_cntl = 0; | |
1160 | ||
1161 | crtc->vxres = vxres; | |
1162 | crtc->vyres = vyres; | |
1163 | crtc->xoffset = xoffset; | |
1164 | crtc->yoffset = yoffset; | |
1165 | crtc->depth = depth; | |
1166 | crtc->bpp = bpp; | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | ||
1172 | static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) | |
1173 | { | |
1174 | ||
1175 | /* fill in pixel info */ | |
1176 | var->red.msb_right = 0; | |
1177 | var->green.msb_right = 0; | |
1178 | var->blue.offset = 0; | |
1179 | var->blue.msb_right = 0; | |
1180 | var->transp.offset = 0; | |
1181 | var->transp.length = 0; | |
1182 | var->transp.msb_right = 0; | |
1183 | switch (pix_width) { | |
1184 | case CRTC_PIX_WIDTH_8BPP: | |
1185 | var->bits_per_pixel = 8; | |
1186 | var->red.offset = 0; | |
1187 | var->red.length = 8; | |
1188 | var->green.offset = 0; | |
1189 | var->green.length = 8; | |
1190 | var->blue.length = 8; | |
1191 | break; | |
1192 | case CRTC_PIX_WIDTH_15BPP: | |
1193 | var->bits_per_pixel = 16; | |
1194 | var->red.offset = 10; | |
1195 | var->red.length = 5; | |
1196 | var->green.offset = 5; | |
1197 | var->green.length = 5; | |
1198 | var->blue.length = 5; | |
1199 | break; | |
1200 | case CRTC_PIX_WIDTH_16BPP: | |
1201 | var->bits_per_pixel = 16; | |
1202 | var->red.offset = 11; | |
1203 | var->red.length = 5; | |
1204 | var->green.offset = 5; | |
1205 | var->green.length = 6; | |
1206 | var->blue.length = 5; | |
1207 | break; | |
1208 | case CRTC_PIX_WIDTH_24BPP: | |
1209 | var->bits_per_pixel = 24; | |
1210 | var->red.offset = 16; | |
1211 | var->red.length = 8; | |
1212 | var->green.offset = 8; | |
1213 | var->green.length = 8; | |
1214 | var->blue.length = 8; | |
1215 | break; | |
1216 | case CRTC_PIX_WIDTH_32BPP: | |
1217 | var->bits_per_pixel = 32; | |
1218 | var->red.offset = 16; | |
1219 | var->red.length = 8; | |
1220 | var->green.offset = 8; | |
1221 | var->green.length = 8; | |
1222 | var->blue.length = 8; | |
1223 | var->transp.offset = 24; | |
1224 | var->transp.length = 8; | |
1225 | break; | |
1226 | default: | |
1227 | printk(KERN_ERR "aty128fb: Invalid pixel width\n"); | |
1228 | return -EINVAL; | |
1229 | } | |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | ||
1235 | static int aty128_crtc_to_var(const struct aty128_crtc *crtc, | |
1236 | struct fb_var_screeninfo *var) | |
1237 | { | |
1238 | u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; | |
1239 | u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; | |
1240 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; | |
1241 | u32 pix_width; | |
1242 | ||
1243 | /* fun with masking */ | |
1244 | h_total = crtc->h_total & 0x1ff; | |
1245 | h_disp = (crtc->h_total >> 16) & 0xff; | |
1246 | h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; | |
1247 | h_sync_dly = crtc->h_sync_strt_wid & 0x7; | |
1248 | h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; | |
1249 | h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; | |
1250 | v_total = crtc->v_total & 0x7ff; | |
1251 | v_disp = (crtc->v_total >> 16) & 0x7ff; | |
1252 | v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; | |
1253 | v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; | |
1254 | v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; | |
1255 | c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; | |
1256 | pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; | |
1257 | ||
1258 | /* do conversions */ | |
1259 | xres = (h_disp + 1) << 3; | |
1260 | yres = v_disp + 1; | |
1261 | left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; | |
1262 | right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; | |
1263 | hslen = h_sync_wid << 3; | |
1264 | upper = v_total - v_sync_strt - v_sync_wid; | |
1265 | lower = v_sync_strt - v_disp; | |
1266 | vslen = v_sync_wid; | |
1267 | sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | | |
1268 | (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | | |
1269 | (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); | |
1270 | ||
1271 | aty128_pix_width_to_var(pix_width, var); | |
1272 | ||
1273 | var->xres = xres; | |
1274 | var->yres = yres; | |
1275 | var->xres_virtual = crtc->vxres; | |
1276 | var->yres_virtual = crtc->vyres; | |
1277 | var->xoffset = crtc->xoffset; | |
1278 | var->yoffset = crtc->yoffset; | |
1279 | var->left_margin = left; | |
1280 | var->right_margin = right; | |
1281 | var->upper_margin = upper; | |
1282 | var->lower_margin = lower; | |
1283 | var->hsync_len = hslen; | |
1284 | var->vsync_len = vslen; | |
1285 | var->sync = sync; | |
1286 | var->vmode = FB_VMODE_NONINTERLACED; | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
1da177e4 LT |
1291 | static void aty128_set_crt_enable(struct aty128fb_par *par, int on) |
1292 | { | |
1293 | if (on) { | |
659f675e EG |
1294 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | |
1295 | CRT_CRTC_ON); | |
1296 | aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | | |
1297 | DAC_PALETTE2_SNOOP_EN)); | |
1da177e4 | 1298 | } else |
659f675e EG |
1299 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & |
1300 | ~CRT_CRTC_ON); | |
1da177e4 LT |
1301 | } |
1302 | ||
1303 | static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) | |
1304 | { | |
1305 | u32 reg; | |
5474c120 MH |
1306 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1307 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
1308 | #endif | |
1da177e4 LT |
1309 | |
1310 | if (on) { | |
1311 | reg = aty_ld_le32(LVDS_GEN_CNTL); | |
1312 | reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; | |
1313 | reg &= ~LVDS_DISPLAY_DIS; | |
1314 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
5474c120 | 1315 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
e01af038 | 1316 | aty128_bl_set_power(info, FB_BLANK_UNBLANK); |
1da177e4 LT |
1317 | #endif |
1318 | } else { | |
5474c120 | 1319 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
e01af038 | 1320 | aty128_bl_set_power(info, FB_BLANK_POWERDOWN); |
1da177e4 LT |
1321 | #endif |
1322 | reg = aty_ld_le32(LVDS_GEN_CNTL); | |
1323 | reg |= LVDS_DISPLAY_DIS; | |
1324 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1325 | mdelay(100); | |
1326 | reg &= ~(LVDS_ON /*| LVDS_EN*/); | |
1327 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1328 | } | |
1329 | } | |
1da177e4 | 1330 | |
659f675e EG |
1331 | static void aty128_set_pll(struct aty128_pll *pll, |
1332 | const struct aty128fb_par *par) | |
1da177e4 LT |
1333 | { |
1334 | u32 div3; | |
1335 | ||
1336 | unsigned char post_conv[] = /* register values for post dividers */ | |
1337 | { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; | |
1338 | ||
1339 | /* select PPLL_DIV_3 */ | |
1340 | aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); | |
1341 | ||
1342 | /* reset PLL */ | |
1343 | aty_st_pll(PPLL_CNTL, | |
1344 | aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); | |
1345 | ||
1346 | /* write the reference divider */ | |
1347 | aty_pll_wait_readupdate(par); | |
1348 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); | |
1349 | aty_pll_writeupdate(par); | |
1350 | ||
1351 | div3 = aty_ld_pll(PPLL_DIV_3); | |
1352 | div3 &= ~PPLL_FB3_DIV_MASK; | |
1353 | div3 |= pll->feedback_divider; | |
1354 | div3 &= ~PPLL_POST3_DIV_MASK; | |
1355 | div3 |= post_conv[pll->post_divider] << 16; | |
1356 | ||
1357 | /* write feedback and post dividers */ | |
1358 | aty_pll_wait_readupdate(par); | |
1359 | aty_st_pll(PPLL_DIV_3, div3); | |
1360 | aty_pll_writeupdate(par); | |
1361 | ||
1362 | aty_pll_wait_readupdate(par); | |
1363 | aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ | |
1364 | aty_pll_writeupdate(par); | |
1365 | ||
1366 | /* clear the reset, just in case */ | |
1367 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); | |
1368 | } | |
1369 | ||
1370 | ||
1371 | static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, | |
1372 | const struct aty128fb_par *par) | |
1373 | { | |
1374 | const struct aty128_constants c = par->constants; | |
1375 | unsigned char post_dividers[] = {1,2,4,8,3,6,12}; | |
1376 | u32 output_freq; | |
1377 | u32 vclk; /* in .01 MHz */ | |
8e650987 | 1378 | int i = 0; |
1da177e4 LT |
1379 | u32 n, d; |
1380 | ||
1381 | vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ | |
1382 | ||
1383 | /* adjust pixel clock if necessary */ | |
1384 | if (vclk > c.ppll_max) | |
1385 | vclk = c.ppll_max; | |
1386 | if (vclk * 12 < c.ppll_min) | |
1387 | vclk = c.ppll_min/12; | |
1388 | ||
1389 | /* now, find an acceptable divider */ | |
816664f8 | 1390 | for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { |
1da177e4 | 1391 | output_freq = post_dividers[i] * vclk; |
8e650987 AD |
1392 | if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { |
1393 | pll->post_divider = post_dividers[i]; | |
1da177e4 | 1394 | break; |
8e650987 | 1395 | } |
1da177e4 LT |
1396 | } |
1397 | ||
816664f8 | 1398 | if (i == ARRAY_SIZE(post_dividers)) |
fd717689 JG |
1399 | return -EINVAL; |
1400 | ||
1da177e4 LT |
1401 | /* calculate feedback divider */ |
1402 | n = c.ref_divider * output_freq; | |
1403 | d = c.ref_clk; | |
1404 | ||
1da177e4 LT |
1405 | pll->feedback_divider = round_div(n, d); |
1406 | pll->vclk = vclk; | |
1407 | ||
1408 | DBG("post %d feedback %d vlck %d output %d ref_divider %d " | |
1409 | "vclk_per: %d\n", pll->post_divider, | |
1410 | pll->feedback_divider, vclk, output_freq, | |
1411 | c.ref_divider, period_in_ps); | |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | ||
659f675e EG |
1417 | static int aty128_pll_to_var(const struct aty128_pll *pll, |
1418 | struct fb_var_screeninfo *var) | |
1da177e4 LT |
1419 | { |
1420 | var->pixclock = 100000000 / pll->vclk; | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | ||
1426 | static void aty128_set_fifo(const struct aty128_ddafifo *dsp, | |
1427 | const struct aty128fb_par *par) | |
1428 | { | |
1429 | aty_st_le32(DDA_CONFIG, dsp->dda_config); | |
1430 | aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); | |
1431 | } | |
1432 | ||
1433 | ||
1434 | static int aty128_ddafifo(struct aty128_ddafifo *dsp, | |
1435 | const struct aty128_pll *pll, | |
1436 | u32 depth, | |
1437 | const struct aty128fb_par *par) | |
1438 | { | |
1439 | const struct aty128_meminfo *m = par->mem; | |
1440 | u32 xclk = par->constants.xclk; | |
1441 | u32 fifo_width = par->constants.fifo_width; | |
1442 | u32 fifo_depth = par->constants.fifo_depth; | |
1443 | s32 x, b, p, ron, roff; | |
1444 | u32 n, d, bpp; | |
1445 | ||
1446 | /* round up to multiple of 8 */ | |
1447 | bpp = (depth+7) & ~7; | |
1448 | ||
1449 | n = xclk * fifo_width; | |
1450 | d = pll->vclk * bpp; | |
1451 | x = round_div(n, d); | |
1452 | ||
1453 | ron = 4 * m->MB + | |
1454 | 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + | |
1455 | 2 * m->Trp + | |
1456 | m->Twr + | |
1457 | m->CL + | |
1458 | m->Tr2w + | |
1459 | x; | |
1460 | ||
1461 | DBG("x %x\n", x); | |
1462 | ||
1463 | b = 0; | |
1464 | while (x) { | |
1465 | x >>= 1; | |
1466 | b++; | |
1467 | } | |
1468 | p = b + 1; | |
1469 | ||
1470 | ron <<= (11 - p); | |
1471 | ||
1472 | n <<= (11 - p); | |
1473 | x = round_div(n, d); | |
1474 | roff = x * (fifo_depth - 4); | |
1475 | ||
1476 | if ((ron + m->Rloop) >= roff) { | |
1477 | printk(KERN_ERR "aty128fb: Mode out of range!\n"); | |
1478 | return -EINVAL; | |
1479 | } | |
1480 | ||
1481 | DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", | |
1482 | p, m->Rloop, x, ron, roff); | |
1483 | ||
1484 | dsp->dda_config = p << 16 | m->Rloop << 20 | x; | |
1485 | dsp->dda_on_off = ron << 16 | roff; | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | ||
1491 | /* | |
1492 | * This actually sets the video mode. | |
1493 | */ | |
1494 | static int aty128fb_set_par(struct fb_info *info) | |
1495 | { | |
1496 | struct aty128fb_par *par = info->par; | |
1497 | u32 config; | |
1498 | int err; | |
1499 | ||
1500 | if ((err = aty128_decode_var(&info->var, par)) != 0) | |
1501 | return err; | |
1502 | ||
1503 | if (par->blitter_may_be_busy) | |
1504 | wait_for_idle(par); | |
1505 | ||
1506 | /* clear all registers that may interfere with mode setting */ | |
1507 | aty_st_le32(OVR_CLR, 0); | |
1508 | aty_st_le32(OVR_WID_LEFT_RIGHT, 0); | |
1509 | aty_st_le32(OVR_WID_TOP_BOTTOM, 0); | |
1510 | aty_st_le32(OV0_SCALE_CNTL, 0); | |
1511 | aty_st_le32(MPP_TB_CONFIG, 0); | |
1512 | aty_st_le32(MPP_GP_CONFIG, 0); | |
1513 | aty_st_le32(SUBPIC_CNTL, 0); | |
1514 | aty_st_le32(VIPH_CONTROL, 0); | |
1515 | aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ | |
1516 | aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ | |
1517 | aty_st_le32(CAP0_TRIG_CNTL, 0); | |
1518 | aty_st_le32(CAP1_TRIG_CNTL, 0); | |
1519 | ||
1520 | aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ | |
1521 | ||
1522 | aty128_set_crtc(&par->crtc, par); | |
1523 | aty128_set_pll(&par->pll, par); | |
1524 | aty128_set_fifo(&par->fifo_reg, par); | |
1525 | ||
fe86175b | 1526 | config = aty_ld_le32(CNFG_CNTL) & ~3; |
1da177e4 LT |
1527 | |
1528 | #if defined(__BIG_ENDIAN) | |
1529 | if (par->crtc.bpp == 32) | |
1530 | config |= 2; /* make aperture do 32 bit swapping */ | |
1531 | else if (par->crtc.bpp == 16) | |
1532 | config |= 1; /* make aperture do 16 bit swapping */ | |
1533 | #endif | |
1534 | ||
fe86175b | 1535 | aty_st_le32(CNFG_CNTL, config); |
1da177e4 LT |
1536 | aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ |
1537 | ||
1538 | info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; | |
1539 | info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR | |
1540 | : FB_VISUAL_DIRECTCOLOR; | |
1541 | ||
1da177e4 LT |
1542 | if (par->chip_gen == rage_M3) { |
1543 | aty128_set_crt_enable(par, par->crt_on); | |
1544 | aty128_set_lcd_enable(par, par->lcd_on); | |
1545 | } | |
1da177e4 LT |
1546 | if (par->accel_flags & FB_ACCELF_TEXT) |
1547 | aty128_init_engine(par); | |
1548 | ||
1549 | #ifdef CONFIG_BOOTX_TEXT | |
1550 | btext_update_display(info->fix.smem_start, | |
1551 | (((par->crtc.h_total>>16) & 0xff)+1)*8, | |
1552 | ((par->crtc.v_total>>16) & 0x7ff)+1, | |
1553 | par->crtc.bpp, | |
1554 | par->crtc.vxres*par->crtc.bpp/8); | |
1555 | #endif /* CONFIG_BOOTX_TEXT */ | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * encode/decode the User Defined Part of the Display | |
1562 | */ | |
1563 | ||
659f675e EG |
1564 | static int aty128_decode_var(struct fb_var_screeninfo *var, |
1565 | struct aty128fb_par *par) | |
1da177e4 LT |
1566 | { |
1567 | int err; | |
1568 | struct aty128_crtc crtc; | |
1569 | struct aty128_pll pll; | |
1570 | struct aty128_ddafifo fifo_reg; | |
1571 | ||
1572 | if ((err = aty128_var_to_crtc(var, &crtc, par))) | |
1573 | return err; | |
1574 | ||
1575 | if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) | |
1576 | return err; | |
1577 | ||
1578 | if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) | |
1579 | return err; | |
1580 | ||
1581 | par->crtc = crtc; | |
1582 | par->pll = pll; | |
1583 | par->fifo_reg = fifo_reg; | |
1584 | par->accel_flags = var->accel_flags; | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | ||
1590 | static int aty128_encode_var(struct fb_var_screeninfo *var, | |
1591 | const struct aty128fb_par *par) | |
1592 | { | |
1593 | int err; | |
1594 | ||
1595 | if ((err = aty128_crtc_to_var(&par->crtc, var))) | |
1596 | return err; | |
1597 | ||
1598 | if ((err = aty128_pll_to_var(&par->pll, var))) | |
1599 | return err; | |
1600 | ||
1601 | var->nonstd = 0; | |
1602 | var->activate = 0; | |
1603 | ||
1604 | var->height = -1; | |
1605 | var->width = -1; | |
1606 | var->accel_flags = par->accel_flags; | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | ||
659f675e EG |
1612 | static int aty128fb_check_var(struct fb_var_screeninfo *var, |
1613 | struct fb_info *info) | |
1da177e4 LT |
1614 | { |
1615 | struct aty128fb_par par; | |
1616 | int err; | |
1617 | ||
1618 | par = *(struct aty128fb_par *)info->par; | |
1619 | if ((err = aty128_decode_var(var, &par)) != 0) | |
1620 | return err; | |
1621 | aty128_encode_var(var, &par); | |
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | ||
1626 | /* | |
1627 | * Pan or Wrap the Display | |
1628 | */ | |
659f675e EG |
1629 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, |
1630 | struct fb_info *fb) | |
1da177e4 LT |
1631 | { |
1632 | struct aty128fb_par *par = fb->par; | |
1633 | u32 xoffset, yoffset; | |
1634 | u32 offset; | |
1635 | u32 xres, yres; | |
1636 | ||
1637 | xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; | |
1638 | yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; | |
1639 | ||
1640 | xoffset = (var->xoffset +7) & ~7; | |
1641 | yoffset = var->yoffset; | |
1642 | ||
1643 | if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) | |
1644 | return -EINVAL; | |
1645 | ||
1646 | par->crtc.xoffset = xoffset; | |
1647 | par->crtc.yoffset = yoffset; | |
1648 | ||
659f675e EG |
1649 | offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) |
1650 | & ~7; | |
1da177e4 LT |
1651 | |
1652 | if (par->crtc.bpp == 24) | |
1653 | offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ | |
1654 | ||
1655 | aty_st_le32(CRTC_OFFSET, offset); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | ||
1661 | /* | |
1662 | * Helper function to store a single palette register | |
1663 | */ | |
1664 | static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, | |
1665 | struct aty128fb_par *par) | |
1666 | { | |
1667 | if (par->chip_gen == rage_M3) { | |
1668 | #if 0 | |
1669 | /* Note: For now, on M3, we set palette on both heads, which may | |
1670 | * be useless. Can someone with a M3 check this ? | |
1671 | * | |
1672 | * This code would still be useful if using the second CRTC to | |
1673 | * do mirroring | |
1674 | */ | |
1675 | ||
659f675e EG |
1676 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | |
1677 | DAC_PALETTE_ACCESS_CNTL); | |
1da177e4 LT |
1678 | aty_st_8(PALETTE_INDEX, regno); |
1679 | aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); | |
1680 | #endif | |
659f675e EG |
1681 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & |
1682 | ~DAC_PALETTE_ACCESS_CNTL); | |
1da177e4 LT |
1683 | } |
1684 | ||
1685 | aty_st_8(PALETTE_INDEX, regno); | |
1686 | aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); | |
1687 | } | |
1688 | ||
1689 | static int aty128fb_sync(struct fb_info *info) | |
1690 | { | |
1691 | struct aty128fb_par *par = info->par; | |
1692 | ||
1693 | if (par->blitter_may_be_busy) | |
1694 | wait_for_idle(par); | |
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | #ifndef MODULE | |
48c68c4f | 1699 | static int aty128fb_setup(char *options) |
1da177e4 LT |
1700 | { |
1701 | char *this_opt; | |
1702 | ||
1703 | if (!options || !*options) | |
1704 | return 0; | |
1705 | ||
1706 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1da177e4 LT |
1707 | if (!strncmp(this_opt, "lcd:", 4)) { |
1708 | default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); | |
1709 | continue; | |
1710 | } else if (!strncmp(this_opt, "crt:", 4)) { | |
1711 | default_crt_on = simple_strtoul(this_opt+4, NULL, 0); | |
1712 | continue; | |
202d4e60 | 1713 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
a79530e4 | 1714 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
202d4e60 | 1715 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
a79530e4 | 1716 | #endif |
202d4e60 | 1717 | continue; |
1da177e4 | 1718 | } |
1da177e4 | 1719 | if(!strncmp(this_opt, "nomtrr", 6)) { |
cfb810f8 | 1720 | mtrr = false; |
1da177e4 LT |
1721 | continue; |
1722 | } | |
1da177e4 LT |
1723 | #ifdef CONFIG_PPC_PMAC |
1724 | /* vmode and cmode deprecated */ | |
1725 | if (!strncmp(this_opt, "vmode:", 6)) { | |
1726 | unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); | |
1727 | if (vmode > 0 && vmode <= VMODE_MAX) | |
1728 | default_vmode = vmode; | |
1729 | continue; | |
1730 | } else if (!strncmp(this_opt, "cmode:", 6)) { | |
1731 | unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); | |
1732 | switch (cmode) { | |
1733 | case 0: | |
1734 | case 8: | |
1735 | default_cmode = CMODE_8; | |
1736 | break; | |
1737 | case 15: | |
1738 | case 16: | |
1739 | default_cmode = CMODE_16; | |
1740 | break; | |
1741 | case 24: | |
1742 | case 32: | |
1743 | default_cmode = CMODE_32; | |
1744 | break; | |
1745 | } | |
1746 | continue; | |
1747 | } | |
1748 | #endif /* CONFIG_PPC_PMAC */ | |
1749 | mode_option = this_opt; | |
1750 | } | |
1751 | return 0; | |
1752 | } | |
1753 | #endif /* MODULE */ | |
1754 | ||
5474c120 MH |
1755 | /* Backlight */ |
1756 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | |
1757 | #define MAX_LEVEL 0xFF | |
1758 | ||
5474c120 MH |
1759 | static int aty128_bl_get_level_brightness(struct aty128fb_par *par, |
1760 | int level) | |
1761 | { | |
1762 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
1763 | int atylevel; | |
1764 | ||
1765 | /* Get and convert the value */ | |
37ce69a5 | 1766 | /* No locking of bl_curve since we read a single value */ |
5474c120 MH |
1767 | atylevel = MAX_LEVEL - |
1768 | (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); | |
5474c120 MH |
1769 | |
1770 | if (atylevel < 0) | |
1771 | atylevel = 0; | |
1772 | else if (atylevel > MAX_LEVEL) | |
1773 | atylevel = MAX_LEVEL; | |
1774 | ||
1775 | return atylevel; | |
1776 | } | |
1777 | ||
1778 | /* We turn off the LCD completely instead of just dimming the backlight. | |
1779 | * This provides greater power saving and the display is useless without | |
1780 | * backlight anyway | |
1781 | */ | |
1782 | #define BACKLIGHT_LVDS_OFF | |
1783 | /* That one prevents proper CRT output with LCD off */ | |
1784 | #undef BACKLIGHT_DAC_OFF | |
1785 | ||
37ce69a5 | 1786 | static int aty128_bl_update_status(struct backlight_device *bd) |
5474c120 | 1787 | { |
655bfd7a | 1788 | struct aty128fb_par *par = bl_get_data(bd); |
5474c120 MH |
1789 | unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); |
1790 | int level; | |
1791 | ||
599a52d1 RP |
1792 | if (bd->props.power != FB_BLANK_UNBLANK || |
1793 | bd->props.fb_blank != FB_BLANK_UNBLANK || | |
5474c120 MH |
1794 | !par->lcd_on) |
1795 | level = 0; | |
1796 | else | |
599a52d1 | 1797 | level = bd->props.brightness; |
5474c120 MH |
1798 | |
1799 | reg |= LVDS_BL_MOD_EN | LVDS_BLON; | |
1800 | if (level > 0) { | |
1801 | reg |= LVDS_DIGION; | |
1802 | if (!(reg & LVDS_ON)) { | |
1803 | reg &= ~LVDS_BLON; | |
1804 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1805 | aty_ld_le32(LVDS_GEN_CNTL); | |
1806 | mdelay(10); | |
1807 | reg |= LVDS_BLON; | |
1808 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1809 | } | |
1810 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; | |
659f675e EG |
1811 | reg |= (aty128_bl_get_level_brightness(par, level) << |
1812 | LVDS_BL_MOD_LEVEL_SHIFT); | |
5474c120 MH |
1813 | #ifdef BACKLIGHT_LVDS_OFF |
1814 | reg |= LVDS_ON | LVDS_EN; | |
1815 | reg &= ~LVDS_DISPLAY_DIS; | |
1816 | #endif | |
1817 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1818 | #ifdef BACKLIGHT_DAC_OFF | |
1819 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); | |
1820 | #endif | |
1821 | } else { | |
1822 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; | |
659f675e EG |
1823 | reg |= (aty128_bl_get_level_brightness(par, 0) << |
1824 | LVDS_BL_MOD_LEVEL_SHIFT); | |
5474c120 MH |
1825 | #ifdef BACKLIGHT_LVDS_OFF |
1826 | reg |= LVDS_DISPLAY_DIS; | |
1827 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1828 | aty_ld_le32(LVDS_GEN_CNTL); | |
1829 | udelay(10); | |
1830 | reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); | |
1831 | #endif | |
1832 | aty_st_le32(LVDS_GEN_CNTL, reg); | |
1833 | #ifdef BACKLIGHT_DAC_OFF | |
1834 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); | |
1835 | #endif | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
acc2472e | 1841 | static const struct backlight_ops aty128_bl_data = { |
5474c120 | 1842 | .update_status = aty128_bl_update_status, |
5474c120 MH |
1843 | }; |
1844 | ||
e01af038 MH |
1845 | static void aty128_bl_set_power(struct fb_info *info, int power) |
1846 | { | |
a9303638 | 1847 | if (info->bl_dev) { |
599a52d1 | 1848 | info->bl_dev->props.power = power; |
37ce69a5 | 1849 | backlight_update_status(info->bl_dev); |
a9303638 | 1850 | } |
e01af038 MH |
1851 | } |
1852 | ||
5474c120 MH |
1853 | static void aty128_bl_init(struct aty128fb_par *par) |
1854 | { | |
a19a6ee6 | 1855 | struct backlight_properties props; |
5474c120 MH |
1856 | struct fb_info *info = pci_get_drvdata(par->pdev); |
1857 | struct backlight_device *bd; | |
1858 | char name[12]; | |
1859 | ||
1860 | /* Could be extended to Rage128Pro LVDS output too */ | |
1861 | if (par->chip_gen != rage_M3) | |
1862 | return; | |
1863 | ||
1864 | #ifdef CONFIG_PMAC_BACKLIGHT | |
1865 | if (!pmac_has_backlight_type("ati")) | |
1866 | return; | |
1867 | #endif | |
1868 | ||
1869 | snprintf(name, sizeof(name), "aty128bl%d", info->node); | |
1870 | ||
a19a6ee6 | 1871 | memset(&props, 0, sizeof(struct backlight_properties)); |
bb7ca747 | 1872 | props.type = BACKLIGHT_RAW; |
a19a6ee6 MG |
1873 | props.max_brightness = FB_BACKLIGHT_LEVELS - 1; |
1874 | bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, | |
1875 | &props); | |
5474c120 MH |
1876 | if (IS_ERR(bd)) { |
1877 | info->bl_dev = NULL; | |
98a3c781 | 1878 | printk(KERN_WARNING "aty128: Backlight registration failed\n"); |
5474c120 MH |
1879 | goto error; |
1880 | } | |
1881 | ||
5474c120 MH |
1882 | info->bl_dev = bd; |
1883 | fb_bl_default_curve(info, 0, | |
1884 | 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, | |
1885 | 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); | |
5474c120 | 1886 | |
599a52d1 RP |
1887 | bd->props.brightness = bd->props.max_brightness; |
1888 | bd->props.power = FB_BLANK_UNBLANK; | |
28ee086d | 1889 | backlight_update_status(bd); |
5474c120 | 1890 | |
5474c120 MH |
1891 | printk("aty128: Backlight initialized (%s)\n", name); |
1892 | ||
1893 | return; | |
1894 | ||
1895 | error: | |
1896 | return; | |
1897 | } | |
1898 | ||
37ce69a5 | 1899 | static void aty128_bl_exit(struct backlight_device *bd) |
5474c120 | 1900 | { |
321709c5 RP |
1901 | backlight_device_unregister(bd); |
1902 | printk("aty128: Backlight unloaded\n"); | |
5474c120 MH |
1903 | } |
1904 | #endif /* CONFIG_FB_ATY128_BACKLIGHT */ | |
1da177e4 LT |
1905 | |
1906 | /* | |
1907 | * Initialisation | |
1908 | */ | |
1909 | ||
d801cec7 | 1910 | #ifdef CONFIG_PPC_PMAC__disabled |
1da177e4 LT |
1911 | static void aty128_early_resume(void *data) |
1912 | { | |
1913 | struct aty128fb_par *par = data; | |
1914 | ||
ac751efa | 1915 | if (!console_trylock()) |
1da177e4 | 1916 | return; |
d801cec7 | 1917 | pci_restore_state(par->pdev); |
1da177e4 | 1918 | aty128_do_resume(par->pdev); |
ac751efa | 1919 | console_unlock(); |
1da177e4 LT |
1920 | } |
1921 | #endif /* CONFIG_PPC_PMAC */ | |
1922 | ||
48c68c4f | 1923 | static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1924 | { |
1925 | struct fb_info *info = pci_get_drvdata(pdev); | |
1926 | struct aty128fb_par *par = info->par; | |
1927 | struct fb_var_screeninfo var; | |
ca52a498 | 1928 | char video_card[50]; |
1da177e4 LT |
1929 | u8 chip_rev; |
1930 | u32 dac; | |
1931 | ||
1da177e4 | 1932 | /* Get the chip revision */ |
fe86175b | 1933 | chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; |
1da177e4 LT |
1934 | |
1935 | strcpy(video_card, "Rage128 XX "); | |
1936 | video_card[8] = ent->device >> 8; | |
1937 | video_card[9] = ent->device & 0xFF; | |
d1ae418e | 1938 | |
1da177e4 | 1939 | /* range check to make sure */ |
d1ae418e | 1940 | if (ent->driver_data < ARRAY_SIZE(r128_family)) |
659f675e EG |
1941 | strlcat(video_card, r128_family[ent->driver_data], |
1942 | sizeof(video_card)); | |
1da177e4 LT |
1943 | |
1944 | printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); | |
1945 | ||
1946 | if (par->vram_size % (1024 * 1024) == 0) | |
1947 | printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); | |
1948 | else | |
1949 | printk("%dk %s\n", par->vram_size / 1024, par->mem->name); | |
1950 | ||
1951 | par->chip_gen = ent->driver_data; | |
1952 | ||
1953 | /* fill in info */ | |
1954 | info->fbops = &aty128fb_ops; | |
1955 | info->flags = FBINFO_FLAG_DEFAULT; | |
1956 | ||
1da177e4 LT |
1957 | par->lcd_on = default_lcd_on; |
1958 | par->crt_on = default_crt_on; | |
1da177e4 LT |
1959 | |
1960 | var = default_var; | |
1961 | #ifdef CONFIG_PPC_PMAC | |
e8222502 | 1962 | if (machine_is(powermac)) { |
1da177e4 LT |
1963 | /* Indicate sleep capability */ |
1964 | if (par->chip_gen == rage_M3) { | |
1965 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); | |
659f675e EG |
1966 | #if 0 /* Disable the early video resume hack for now as it's causing problems, |
1967 | * among others we now rely on the PCI core restoring the config space | |
1968 | * for us, which isn't the case with that hack, and that code path causes | |
1969 | * various things to be called with interrupts off while they shouldn't. | |
1970 | * I'm leaving the code in as it can be useful for debugging purposes | |
d801cec7 | 1971 | */ |
1da177e4 | 1972 | pmac_set_early_video_resume(aty128_early_resume, par); |
d801cec7 | 1973 | #endif |
1da177e4 LT |
1974 | } |
1975 | ||
1976 | /* Find default mode */ | |
1977 | if (mode_option) { | |
1978 | if (!mac_find_mode(&var, info, mode_option, 8)) | |
1979 | var = default_var; | |
1980 | } else { | |
1981 | if (default_vmode <= 0 || default_vmode > VMODE_MAX) | |
1982 | default_vmode = VMODE_1024_768_60; | |
1983 | ||
1984 | /* iMacs need that resolution | |
1985 | * PowerMac2,1 first r128 iMacs | |
1986 | * PowerMac2,2 summer 2000 iMacs | |
1987 | * PowerMac4,1 january 2001 iMacs "flower power" | |
1988 | */ | |
71a157e8 GL |
1989 | if (of_machine_is_compatible("PowerMac2,1") || |
1990 | of_machine_is_compatible("PowerMac2,2") || | |
1991 | of_machine_is_compatible("PowerMac4,1")) | |
1da177e4 LT |
1992 | default_vmode = VMODE_1024_768_75; |
1993 | ||
1994 | /* iBook SE */ | |
71a157e8 | 1995 | if (of_machine_is_compatible("PowerBook2,2")) |
1da177e4 LT |
1996 | default_vmode = VMODE_800_600_60; |
1997 | ||
1998 | /* PowerBook Firewire (Pismo), iBook Dual USB */ | |
71a157e8 GL |
1999 | if (of_machine_is_compatible("PowerBook3,1") || |
2000 | of_machine_is_compatible("PowerBook4,1")) | |
1da177e4 LT |
2001 | default_vmode = VMODE_1024_768_60; |
2002 | ||
2003 | /* PowerBook Titanium */ | |
71a157e8 | 2004 | if (of_machine_is_compatible("PowerBook3,2")) |
1da177e4 LT |
2005 | default_vmode = VMODE_1152_768_60; |
2006 | ||
2007 | if (default_cmode > 16) | |
659f675e | 2008 | default_cmode = CMODE_32; |
1da177e4 | 2009 | else if (default_cmode > 8) |
659f675e | 2010 | default_cmode = CMODE_16; |
1da177e4 | 2011 | else |
659f675e | 2012 | default_cmode = CMODE_8; |
1da177e4 LT |
2013 | |
2014 | if (mac_vmode_to_var(default_vmode, default_cmode, &var)) | |
2015 | var = default_var; | |
2016 | } | |
2017 | } else | |
2018 | #endif /* CONFIG_PPC_PMAC */ | |
2019 | { | |
2020 | if (mode_option) | |
2021 | if (fb_find_mode(&var, info, mode_option, NULL, | |
2022 | 0, &defaultmode, 8) == 0) | |
2023 | var = default_var; | |
2024 | } | |
2025 | ||
2026 | var.accel_flags &= ~FB_ACCELF_TEXT; | |
2027 | // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ | |
2028 | ||
2029 | if (aty128fb_check_var(&var, info)) { | |
2030 | printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); | |
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | /* setup the DAC the way we like it */ | |
2035 | dac = aty_ld_le32(DAC_CNTL); | |
2036 | dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); | |
2037 | dac |= DAC_MASK; | |
2038 | if (par->chip_gen == rage_M3) | |
2039 | dac |= DAC_PALETTE2_SNOOP_EN; | |
2040 | aty_st_le32(DAC_CNTL, dac); | |
2041 | ||
2042 | /* turn off bus mastering, just in case */ | |
2043 | aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); | |
2044 | ||
2045 | info->var = var; | |
2046 | fb_alloc_cmap(&info->cmap, 256, 0); | |
2047 | ||
2048 | var.activate = FB_ACTIVATE_NOW; | |
2049 | ||
2050 | aty128_init_engine(par); | |
2051 | ||
1da177e4 LT |
2052 | par->pdev = pdev; |
2053 | par->asleep = 0; | |
2054 | par->lock_blank = 0; | |
5474c120 MH |
2055 | |
2056 | #ifdef CONFIG_FB_ATY128_BACKLIGHT | |
202d4e60 RP |
2057 | if (backlight) |
2058 | aty128_bl_init(par); | |
5474c120 MH |
2059 | #endif |
2060 | ||
c3760ae1 OH |
2061 | if (register_framebuffer(info) < 0) |
2062 | return 0; | |
2063 | ||
31b6780c JP |
2064 | fb_info(info, "%s frame buffer device on %s\n", |
2065 | info->fix.id, video_card); | |
1da177e4 LT |
2066 | |
2067 | return 1; /* success! */ | |
2068 | } | |
2069 | ||
2070 | #ifdef CONFIG_PCI | |
2071 | /* register a card ++ajoshi */ | |
48c68c4f | 2072 | static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2073 | { |
2074 | unsigned long fb_addr, reg_addr; | |
2075 | struct aty128fb_par *par; | |
2076 | struct fb_info *info; | |
2077 | int err; | |
2078 | #ifndef __sparc__ | |
2079 | void __iomem *bios = NULL; | |
2080 | #endif | |
2081 | ||
2082 | /* Enable device in PCI config */ | |
2083 | if ((err = pci_enable_device(pdev))) { | |
2084 | printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", | |
2085 | err); | |
2086 | return -ENODEV; | |
2087 | } | |
2088 | ||
2089 | fb_addr = pci_resource_start(pdev, 0); | |
2090 | if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), | |
2091 | "aty128fb FB")) { | |
2092 | printk(KERN_ERR "aty128fb: cannot reserve frame " | |
2093 | "buffer memory\n"); | |
2094 | return -ENODEV; | |
2095 | } | |
2096 | ||
2097 | reg_addr = pci_resource_start(pdev, 2); | |
2098 | if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), | |
2099 | "aty128fb MMIO")) { | |
2100 | printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); | |
2101 | goto err_free_fb; | |
2102 | } | |
2103 | ||
2104 | /* We have the resources. Now virtualize them */ | |
2105 | info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); | |
2106 | if (info == NULL) { | |
2107 | printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n"); | |
2108 | goto err_free_mmio; | |
2109 | } | |
2110 | par = info->par; | |
2111 | ||
2112 | info->pseudo_palette = par->pseudo_palette; | |
1da177e4 LT |
2113 | |
2114 | /* Virtualize mmio region */ | |
2115 | info->fix.mmio_start = reg_addr; | |
3c36aa5c | 2116 | par->regbase = pci_ioremap_bar(pdev, 2); |
1da177e4 LT |
2117 | if (!par->regbase) |
2118 | goto err_free_info; | |
2119 | ||
2120 | /* Grab memory size from the card */ | |
2121 | // How does this relate to the resource length from the PCI hardware? | |
fe86175b | 2122 | par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; |
1da177e4 LT |
2123 | |
2124 | /* Virtualize the framebuffer */ | |
f4447dde | 2125 | info->screen_base = ioremap_wc(fb_addr, par->vram_size); |
1da177e4 LT |
2126 | if (!info->screen_base) |
2127 | goto err_unmap_out; | |
2128 | ||
2129 | /* Set up info->fix */ | |
2130 | info->fix = aty128fb_fix; | |
2131 | info->fix.smem_start = fb_addr; | |
2132 | info->fix.smem_len = par->vram_size; | |
2133 | info->fix.mmio_start = reg_addr; | |
2134 | ||
2135 | /* If we can't test scratch registers, something is seriously wrong */ | |
2136 | if (!register_test(par)) { | |
2137 | printk(KERN_ERR "aty128fb: Can't write to video register!\n"); | |
2138 | goto err_out; | |
2139 | } | |
2140 | ||
2141 | #ifndef __sparc__ | |
2142 | bios = aty128_map_ROM(par, pdev); | |
2143 | #ifdef CONFIG_X86 | |
2144 | if (bios == NULL) | |
2145 | bios = aty128_find_mem_vbios(par); | |
2146 | #endif | |
2147 | if (bios == NULL) | |
2148 | printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); | |
2149 | else { | |
2150 | printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); | |
2151 | aty128_get_pllinfo(par, bios); | |
2152 | pci_unmap_rom(pdev, bios); | |
2153 | } | |
2154 | #endif /* __sparc__ */ | |
2155 | ||
2156 | aty128_timings(par); | |
2157 | pci_set_drvdata(pdev, info); | |
2158 | ||
2159 | if (!aty128_init(pdev, ent)) | |
2160 | goto err_out; | |
2161 | ||
f4447dde LR |
2162 | if (mtrr) |
2163 | par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, | |
2164 | par->vram_size); | |
1da177e4 LT |
2165 | return 0; |
2166 | ||
2167 | err_out: | |
2168 | iounmap(info->screen_base); | |
2169 | err_unmap_out: | |
2170 | iounmap(par->regbase); | |
2171 | err_free_info: | |
2172 | framebuffer_release(info); | |
2173 | err_free_mmio: | |
2174 | release_mem_region(pci_resource_start(pdev, 2), | |
2175 | pci_resource_len(pdev, 2)); | |
2176 | err_free_fb: | |
2177 | release_mem_region(pci_resource_start(pdev, 0), | |
2178 | pci_resource_len(pdev, 0)); | |
2179 | return -ENODEV; | |
2180 | } | |
2181 | ||
48c68c4f | 2182 | static void aty128_remove(struct pci_dev *pdev) |
1da177e4 LT |
2183 | { |
2184 | struct fb_info *info = pci_get_drvdata(pdev); | |
2185 | struct aty128fb_par *par; | |
2186 | ||
2187 | if (!info) | |
2188 | return; | |
2189 | ||
2190 | par = info->par; | |
2191 | ||
37ce69a5 RP |
2192 | unregister_framebuffer(info); |
2193 | ||
5474c120 | 2194 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
37ce69a5 | 2195 | aty128_bl_exit(info->bl_dev); |
5474c120 MH |
2196 | #endif |
2197 | ||
f4447dde | 2198 | arch_phys_wc_del(par->wc_cookie); |
1da177e4 LT |
2199 | iounmap(par->regbase); |
2200 | iounmap(info->screen_base); | |
2201 | ||
2202 | release_mem_region(pci_resource_start(pdev, 0), | |
2203 | pci_resource_len(pdev, 0)); | |
2204 | release_mem_region(pci_resource_start(pdev, 2), | |
2205 | pci_resource_len(pdev, 2)); | |
2206 | framebuffer_release(info); | |
2207 | } | |
2208 | #endif /* CONFIG_PCI */ | |
2209 | ||
2210 | ||
2211 | ||
2212 | /* | |
2213 | * Blank the display. | |
2214 | */ | |
2215 | static int aty128fb_blank(int blank, struct fb_info *fb) | |
2216 | { | |
2217 | struct aty128fb_par *par = fb->par; | |
125e1137 | 2218 | u8 state; |
1da177e4 LT |
2219 | |
2220 | if (par->lock_blank || par->asleep) | |
2221 | return 0; | |
2222 | ||
125e1137 WF |
2223 | switch (blank) { |
2224 | case FB_BLANK_NORMAL: | |
2225 | state = 4; | |
2226 | break; | |
2227 | case FB_BLANK_VSYNC_SUSPEND: | |
2228 | state = 6; | |
2229 | break; | |
2230 | case FB_BLANK_HSYNC_SUSPEND: | |
2231 | state = 5; | |
2232 | break; | |
2233 | case FB_BLANK_POWERDOWN: | |
2234 | state = 7; | |
2235 | break; | |
2236 | case FB_BLANK_UNBLANK: | |
2237 | default: | |
2238 | state = 0; | |
2239 | break; | |
2240 | } | |
1da177e4 LT |
2241 | aty_st_8(CRTC_EXT_CNTL+1, state); |
2242 | ||
1da177e4 LT |
2243 | if (par->chip_gen == rage_M3) { |
2244 | aty128_set_crt_enable(par, par->crt_on && !blank); | |
2245 | aty128_set_lcd_enable(par, par->lcd_on && !blank); | |
2246 | } | |
e01af038 | 2247 | |
1da177e4 LT |
2248 | return 0; |
2249 | } | |
2250 | ||
2251 | /* | |
2252 | * Set a single color register. The values supplied are already | |
2253 | * rounded down to the hardware's capabilities (according to the | |
2254 | * entries in the var structure). Return != 0 for invalid regno. | |
2255 | */ | |
2256 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
2257 | u_int transp, struct fb_info *info) | |
2258 | { | |
2259 | struct aty128fb_par *par = info->par; | |
2260 | ||
2261 | if (regno > 255 | |
2262 | || (par->crtc.depth == 16 && regno > 63) | |
2263 | || (par->crtc.depth == 15 && regno > 31)) | |
2264 | return 1; | |
2265 | ||
2266 | red >>= 8; | |
2267 | green >>= 8; | |
2268 | blue >>= 8; | |
2269 | ||
2270 | if (regno < 16) { | |
2271 | int i; | |
2272 | u32 *pal = info->pseudo_palette; | |
2273 | ||
2274 | switch (par->crtc.depth) { | |
2275 | case 15: | |
2276 | pal[regno] = (regno << 10) | (regno << 5) | regno; | |
2277 | break; | |
2278 | case 16: | |
2279 | pal[regno] = (regno << 11) | (regno << 6) | regno; | |
2280 | break; | |
2281 | case 24: | |
2282 | pal[regno] = (regno << 16) | (regno << 8) | regno; | |
2283 | break; | |
2284 | case 32: | |
2285 | i = (regno << 8) | regno; | |
2286 | pal[regno] = (i << 16) | i; | |
2287 | break; | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | if (par->crtc.depth == 16 && regno > 0) { | |
2292 | /* | |
2293 | * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we | |
2294 | * have 32 slots for R and B values but 64 slots for G values. | |
2295 | * Thus the R and B values go in one slot but the G value | |
2296 | * goes in a different slot, and we have to avoid disturbing | |
2297 | * the other fields in the slots we touch. | |
2298 | */ | |
2299 | par->green[regno] = green; | |
2300 | if (regno < 32) { | |
2301 | par->red[regno] = red; | |
2302 | par->blue[regno] = blue; | |
2303 | aty128_st_pal(regno * 8, red, par->green[regno*2], | |
2304 | blue, par); | |
2305 | } | |
2306 | red = par->red[regno/2]; | |
2307 | blue = par->blue[regno/2]; | |
2308 | regno <<= 2; | |
2309 | } else if (par->crtc.bpp == 16) | |
2310 | regno <<= 3; | |
2311 | aty128_st_pal(regno, red, green, blue, par); | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | ||
2316 | #define ATY_MIRROR_LCD_ON 0x00000001 | |
2317 | #define ATY_MIRROR_CRT_ON 0x00000002 | |
2318 | ||
2319 | /* out param: u32* backlight value: 0 to 15 */ | |
2320 | #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) | |
2321 | /* in param: u32* backlight value: 0 to 15 */ | |
2322 | #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) | |
2323 | ||
67a6680d | 2324 | static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) |
1da177e4 | 2325 | { |
1da177e4 LT |
2326 | struct aty128fb_par *par = info->par; |
2327 | u32 value; | |
2328 | int rc; | |
2329 | ||
2330 | switch (cmd) { | |
2331 | case FBIO_ATY128_SET_MIRROR: | |
2332 | if (par->chip_gen != rage_M3) | |
2333 | return -EINVAL; | |
2334 | rc = get_user(value, (__u32 __user *)arg); | |
2335 | if (rc) | |
2336 | return rc; | |
2337 | par->lcd_on = (value & 0x01) != 0; | |
2338 | par->crt_on = (value & 0x02) != 0; | |
2339 | if (!par->crt_on && !par->lcd_on) | |
2340 | par->lcd_on = 1; | |
2341 | aty128_set_crt_enable(par, par->crt_on); | |
2342 | aty128_set_lcd_enable(par, par->lcd_on); | |
2343 | return 0; | |
2344 | case FBIO_ATY128_GET_MIRROR: | |
2345 | if (par->chip_gen != rage_M3) | |
2346 | return -EINVAL; | |
2347 | value = (par->crt_on << 1) | par->lcd_on; | |
2348 | return put_user(value, (__u32 __user *)arg); | |
2349 | } | |
1da177e4 LT |
2350 | return -EINVAL; |
2351 | } | |
2352 | ||
1da177e4 LT |
2353 | #if 0 |
2354 | /* | |
2355 | * Accelerated functions | |
2356 | */ | |
2357 | ||
2358 | static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty, | |
2359 | u_int width, u_int height, | |
2360 | struct fb_info_aty128 *par) | |
2361 | { | |
659f675e EG |
2362 | u32 save_dp_datatype, save_dp_cntl, dstval; |
2363 | ||
2364 | if (!width || !height) | |
2365 | return; | |
2366 | ||
2367 | dstval = depth_to_dst(par->current_par.crtc.depth); | |
2368 | if (dstval == DST_24BPP) { | |
2369 | srcx *= 3; | |
2370 | dstx *= 3; | |
2371 | width *= 3; | |
2372 | } else if (dstval == -EINVAL) { | |
2373 | printk("aty128fb: invalid depth or RGBA\n"); | |
2374 | return; | |
2375 | } | |
2376 | ||
2377 | wait_for_fifo(2, par); | |
2378 | save_dp_datatype = aty_ld_le32(DP_DATATYPE); | |
2379 | save_dp_cntl = aty_ld_le32(DP_CNTL); | |
2380 | ||
2381 | wait_for_fifo(6, par); | |
2382 | aty_st_le32(SRC_Y_X, (srcy << 16) | srcx); | |
2383 | aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT); | |
2384 | aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); | |
2385 | aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR); | |
2386 | ||
2387 | aty_st_le32(DST_Y_X, (dsty << 16) | dstx); | |
2388 | aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width); | |
2389 | ||
2390 | par->blitter_may_be_busy = 1; | |
2391 | ||
2392 | wait_for_fifo(2, par); | |
2393 | aty_st_le32(DP_DATATYPE, save_dp_datatype); | |
2394 | aty_st_le32(DP_CNTL, save_dp_cntl); | |
1da177e4 LT |
2395 | } |
2396 | ||
2397 | ||
2398 | /* | |
2399 | * Text mode accelerated functions | |
2400 | */ | |
2401 | ||
659f675e EG |
2402 | static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, |
2403 | int dx, int height, int width) | |
1da177e4 | 2404 | { |
659f675e EG |
2405 | sx *= fontwidth(p); |
2406 | sy *= fontheight(p); | |
2407 | dx *= fontwidth(p); | |
2408 | dy *= fontheight(p); | |
2409 | width *= fontwidth(p); | |
2410 | height *= fontheight(p); | |
2411 | ||
2412 | aty128_rectcopy(sx, sy, dx, dy, width, height, | |
1da177e4 LT |
2413 | (struct fb_info_aty128 *)p->fb_info); |
2414 | } | |
2415 | #endif /* 0 */ | |
2416 | ||
2417 | static void aty128_set_suspend(struct aty128fb_par *par, int suspend) | |
2418 | { | |
2419 | u32 pmgt; | |
1da177e4 LT |
2420 | struct pci_dev *pdev = par->pdev; |
2421 | ||
8d0c03dd | 2422 | if (!par->pdev->pm_cap) |
1da177e4 LT |
2423 | return; |
2424 | ||
2425 | /* Set the chip into the appropriate suspend mode (we use D2, | |
2426 | * D3 would require a complete re-initialisation of the chip, | |
2427 | * including PCI config registers, clocks, AGP configuration, ...) | |
b746bb77 BH |
2428 | * |
2429 | * For resume, the core will have already brought us back to D0 | |
1da177e4 LT |
2430 | */ |
2431 | if (suspend) { | |
2432 | /* Make sure CRTC2 is reset. Remove that the day we decide to | |
2433 | * actually use CRTC2 and replace it with real code for disabling | |
2434 | * the CRTC2 output during sleep | |
2435 | */ | |
2436 | aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & | |
2437 | ~(CRTC2_EN)); | |
2438 | ||
2439 | /* Set the power management mode to be PCI based */ | |
2440 | /* Use this magic value for now */ | |
2441 | pmgt = 0x0c005407; | |
2442 | aty_st_pll(POWER_MANAGEMENT, pmgt); | |
2443 | (void)aty_ld_pll(POWER_MANAGEMENT); | |
2444 | aty_st_le32(BUS_CNTL1, 0x00000010); | |
2445 | aty_st_le32(MEM_POWER_MISC, 0x0c830000); | |
86c4e7c3 | 2446 | msleep(100); |
b746bb77 | 2447 | |
1da177e4 | 2448 | /* Switch PCI power management to D2 */ |
b746bb77 | 2449 | pci_set_power_state(pdev, PCI_D2); |
1da177e4 LT |
2450 | } |
2451 | } | |
2452 | ||
2453 | static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
2454 | { | |
2455 | struct fb_info *info = pci_get_drvdata(pdev); | |
2456 | struct aty128fb_par *par = info->par; | |
1da177e4 | 2457 | |
b746bb77 BH |
2458 | /* Because we may change PCI D state ourselves, we need to |
2459 | * first save the config space content so the core can | |
2460 | * restore it properly on resume. | |
2461 | */ | |
2462 | pci_save_state(pdev); | |
2463 | ||
1da177e4 LT |
2464 | /* We don't do anything but D2, for now we return 0, but |
2465 | * we may want to change that. How do we know if the BIOS | |
2466 | * can properly take care of D3 ? Also, with swsusp, we | |
2467 | * know we'll be rebooted, ... | |
2468 | */ | |
ca078bae | 2469 | #ifndef CONFIG_PPC_PMAC |
1da177e4 LT |
2470 | /* HACK ALERT ! Once I find a proper way to say to each driver |
2471 | * individually what will happen with it's PCI slot, I'll change | |
2472 | * that. On laptops, the AGP slot is just unclocked, so D2 is | |
2473 | * expected, while on desktops, the card is powered off | |
2474 | */ | |
ca078bae | 2475 | return 0; |
1da177e4 LT |
2476 | #endif /* CONFIG_PPC_PMAC */ |
2477 | ||
ca078bae | 2478 | if (state.event == pdev->dev.power.power_state.event) |
1da177e4 LT |
2479 | return 0; |
2480 | ||
2481 | printk(KERN_DEBUG "aty128fb: suspending...\n"); | |
2482 | ||
ac751efa | 2483 | console_lock(); |
1da177e4 LT |
2484 | |
2485 | fb_set_suspend(info, 1); | |
2486 | ||
2487 | /* Make sure engine is reset */ | |
2488 | wait_for_idle(par); | |
2489 | aty128_reset_engine(par); | |
2490 | wait_for_idle(par); | |
2491 | ||
2492 | /* Blank display and LCD */ | |
125e1137 | 2493 | aty128fb_blank(FB_BLANK_POWERDOWN, info); |
1da177e4 LT |
2494 | |
2495 | /* Sleep */ | |
2496 | par->asleep = 1; | |
2497 | par->lock_blank = 1; | |
2498 | ||
0c541b44 BH |
2499 | #ifdef CONFIG_PPC_PMAC |
2500 | /* On powermac, we have hooks to properly suspend/resume AGP now, | |
2501 | * use them here. We'll ultimately need some generic support here, | |
2502 | * but the generic code isn't quite ready for that yet | |
1da177e4 | 2503 | */ |
0c541b44 BH |
2504 | pmac_suspend_agp_for_card(pdev); |
2505 | #endif /* CONFIG_PPC_PMAC */ | |
1da177e4 LT |
2506 | |
2507 | /* We need a way to make sure the fbdev layer will _not_ touch the | |
2508 | * framebuffer before we put the chip to suspend state. On 2.4, I | |
2509 | * used dummy fb ops, 2.5 need proper support for this at the | |
2510 | * fbdev level | |
2511 | */ | |
ca078bae | 2512 | if (state.event != PM_EVENT_ON) |
1da177e4 LT |
2513 | aty128_set_suspend(par, 1); |
2514 | ||
ac751efa | 2515 | console_unlock(); |
1da177e4 LT |
2516 | |
2517 | pdev->dev.power.power_state = state; | |
2518 | ||
2519 | return 0; | |
2520 | } | |
2521 | ||
2522 | static int aty128_do_resume(struct pci_dev *pdev) | |
2523 | { | |
2524 | struct fb_info *info = pci_get_drvdata(pdev); | |
2525 | struct aty128fb_par *par = info->par; | |
2526 | ||
ca078bae | 2527 | if (pdev->dev.power.power_state.event == PM_EVENT_ON) |
1da177e4 LT |
2528 | return 0; |
2529 | ||
b746bb77 BH |
2530 | /* PCI state will have been restored by the core, so |
2531 | * we should be in D0 now with our config space fully | |
2532 | * restored | |
2533 | */ | |
2534 | ||
1da177e4 | 2535 | /* Wakeup chip */ |
ca078bae | 2536 | aty128_set_suspend(par, 0); |
1da177e4 LT |
2537 | par->asleep = 0; |
2538 | ||
2539 | /* Restore display & engine */ | |
2540 | aty128_reset_engine(par); | |
2541 | wait_for_idle(par); | |
2542 | aty128fb_set_par(info); | |
2543 | fb_pan_display(info, &info->var); | |
2544 | fb_set_cmap(&info->cmap, info); | |
2545 | ||
2546 | /* Refresh */ | |
2547 | fb_set_suspend(info, 0); | |
2548 | ||
2549 | /* Unblank */ | |
2550 | par->lock_blank = 0; | |
2551 | aty128fb_blank(0, info); | |
2552 | ||
0c541b44 BH |
2553 | #ifdef CONFIG_PPC_PMAC |
2554 | /* On powermac, we have hooks to properly suspend/resume AGP now, | |
2555 | * use them here. We'll ultimately need some generic support here, | |
2556 | * but the generic code isn't quite ready for that yet | |
2557 | */ | |
2558 | pmac_resume_agp_for_card(pdev); | |
2559 | #endif /* CONFIG_PPC_PMAC */ | |
2560 | ||
1da177e4 LT |
2561 | pdev->dev.power.power_state = PMSG_ON; |
2562 | ||
2563 | printk(KERN_DEBUG "aty128fb: resumed !\n"); | |
2564 | ||
2565 | return 0; | |
2566 | } | |
2567 | ||
2568 | static int aty128_pci_resume(struct pci_dev *pdev) | |
2569 | { | |
2570 | int rc; | |
2571 | ||
ac751efa | 2572 | console_lock(); |
1da177e4 | 2573 | rc = aty128_do_resume(pdev); |
ac751efa | 2574 | console_unlock(); |
1da177e4 LT |
2575 | |
2576 | return rc; | |
2577 | } | |
2578 | ||
2579 | ||
48c68c4f | 2580 | static int aty128fb_init(void) |
1da177e4 LT |
2581 | { |
2582 | #ifndef MODULE | |
2583 | char *option = NULL; | |
2584 | ||
2585 | if (fb_get_options("aty128fb", &option)) | |
2586 | return -ENODEV; | |
2587 | aty128fb_setup(option); | |
2588 | #endif | |
2589 | ||
2590 | return pci_register_driver(&aty128fb_driver); | |
2591 | } | |
2592 | ||
2593 | static void __exit aty128fb_exit(void) | |
2594 | { | |
2595 | pci_unregister_driver(&aty128fb_driver); | |
2596 | } | |
2597 | ||
2598 | module_init(aty128fb_init); | |
2599 | ||
2600 | module_exit(aty128fb_exit); | |
2601 | ||
2602 | MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); | |
2603 | MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); | |
2604 | MODULE_LICENSE("GPL"); | |
2605 | module_param(mode_option, charp, 0); | |
2606 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | |
1da177e4 LT |
2607 | module_param_named(nomtrr, mtrr, invbool, 0); |
2608 | MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); |