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1da177e4 LT |
1 | /* |
2 | * drivers/video/aty/radeon_base.c | |
3 | * | |
4 | * framebuffer driver for ATI Radeon chipset video boards | |
5 | * | |
6 | * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org> | |
7 | * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org> | |
8 | * | |
9 | * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net> | |
10 | * | |
11 | * Special thanks to ATI DevRel team for their hardware donations. | |
12 | * | |
13 | * ...Insert GPL boilerplate here... | |
14 | * | |
15 | * Significant portions of this driver apdated from XFree86 Radeon | |
16 | * driver which has the following copyright notice: | |
17 | * | |
18 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
19 | * VA Linux Systems Inc., Fremont, California. | |
20 | * | |
21 | * All Rights Reserved. | |
22 | * | |
23 | * Permission is hereby granted, free of charge, to any person obtaining | |
24 | * a copy of this software and associated documentation files (the | |
25 | * "Software"), to deal in the Software without restriction, including | |
26 | * without limitation on the rights to use, copy, modify, merge, | |
27 | * publish, distribute, sublicense, and/or sell copies of the Software, | |
28 | * and to permit persons to whom the Software is furnished to do so, | |
29 | * subject to the following conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice (including the | |
32 | * next paragraph) shall be included in all copies or substantial | |
33 | * portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
37 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR | |
39 | * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
41 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
42 | * DEALINGS IN THE SOFTWARE. | |
43 | * | |
44 | * XFree86 driver authors: | |
45 | * | |
46 | * Kevin E. Martin <martin@xfree86.org> | |
47 | * Rickard E. Faith <faith@valinux.com> | |
48 | * Alan Hourihane <alanh@fairlite.demon.co.uk> | |
49 | * | |
50 | */ | |
51 | ||
52 | ||
53 | #define RADEON_VERSION "0.2.0" | |
54 | ||
b0313f89 JD |
55 | #include "radeonfb.h" |
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/moduleparam.h> | |
59 | #include <linux/kernel.h> | |
60 | #include <linux/errno.h> | |
61 | #include <linux/string.h> | |
e7a18c9c | 62 | #include <linux/ctype.h> |
1da177e4 | 63 | #include <linux/mm.h> |
1da177e4 LT |
64 | #include <linux/slab.h> |
65 | #include <linux/delay.h> | |
66 | #include <linux/time.h> | |
67 | #include <linux/fb.h> | |
68 | #include <linux/ioport.h> | |
69 | #include <linux/init.h> | |
70 | #include <linux/pci.h> | |
71 | #include <linux/vmalloc.h> | |
72 | #include <linux/device.h> | |
1da177e4 LT |
73 | |
74 | #include <asm/io.h> | |
84902b7a | 75 | #include <linux/uaccess.h> |
1da177e4 | 76 | |
758ddd1d | 77 | #ifdef CONFIG_PPC |
1da177e4 | 78 | |
1da177e4 LT |
79 | #include "../macmodes.h" |
80 | ||
1da177e4 LT |
81 | #ifdef CONFIG_BOOTX_TEXT |
82 | #include <asm/btext.h> | |
83 | #endif | |
84 | ||
758ddd1d | 85 | #endif /* CONFIG_PPC */ |
1da177e4 | 86 | |
1da177e4 LT |
87 | #include <video/radeon.h> |
88 | #include <linux/radeonfb.h> | |
89 | ||
90 | #include "../edid.h" // MOVE THAT TO include/video | |
91 | #include "ati_ids.h" | |
1da177e4 LT |
92 | |
93 | #define MAX_MAPPED_VRAM (2048*2048*4) | |
94 | #define MIN_MAPPED_VRAM (1024*768*1) | |
95 | ||
96 | #define CHIP_DEF(id, family, flags) \ | |
97 | { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } | |
98 | ||
cac9559e | 99 | static const struct pci_device_id radeonfb_pci_table[] = { |
dd144713 | 100 | /* Radeon Xpress 200m */ |
101 | CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
106c4a9c | 102 | CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), |
1da177e4 LT |
103 | /* Mobility M6 */ |
104 | CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
105 | CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
106 | /* Radeon VE/7000 */ | |
107 | CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), | |
108 | CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), | |
183dee0f | 109 | CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2), |
1da177e4 LT |
110 | /* Radeon IGP320M (U1) */ |
111 | CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
112 | /* Radeon IGP320 (A3) */ | |
113 | CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
114 | /* IGP330M/340M/350M (U2) */ | |
115 | CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
116 | /* IGP330/340/350 (A4) */ | |
117 | CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
118 | /* Mobility 7000 IGP */ | |
119 | CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
120 | /* 7000 IGP (A4+) */ | |
121 | CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
122 | /* 8500 AIW */ | |
123 | CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), | |
124 | CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), | |
125 | /* 8700/8800 */ | |
126 | CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), | |
127 | /* 8500 */ | |
128 | CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), | |
129 | /* 9100 */ | |
130 | CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), | |
131 | /* Mobility M7 */ | |
132 | CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
133 | CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
134 | /* 7500 */ | |
135 | CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), | |
136 | CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), | |
137 | /* Mobility M9 */ | |
138 | CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
139 | CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
140 | CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
141 | CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
142 | /* 9000/Pro */ | |
143 | CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), | |
144 | CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), | |
0b693eaf SB |
145 | |
146 | CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
1da177e4 LT |
147 | /* Mobility 9100 IGP (U3) */ |
148 | CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
149 | CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
150 | /* 9100 IGP (A5) */ | |
151 | CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
152 | CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
153 | /* Mobility 9200 (M9+) */ | |
154 | CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
155 | CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
156 | /* 9200 */ | |
157 | CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), | |
158 | CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), | |
159 | CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), | |
160 | CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), | |
161 | /* 9500 */ | |
162 | CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), | |
163 | CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), | |
164 | /* 9600TX / FireGL Z1 */ | |
165 | CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), | |
166 | CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), | |
167 | /* 9700/9500/Pro/FireGL X1 */ | |
168 | CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), | |
169 | CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), | |
170 | CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), | |
171 | CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), | |
172 | /* Mobility M10/M11 */ | |
173 | CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
174 | CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
175 | CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
176 | CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
177 | CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
178 | CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
179 | /* 9600/FireGL T2 */ | |
180 | CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), | |
181 | CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), | |
182 | CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), | |
183 | CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), | |
184 | CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), | |
185 | CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), | |
186 | /* 9800/Pro/FileGL X2 */ | |
187 | CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), | |
188 | CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), | |
189 | CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), | |
190 | CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), | |
191 | CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), | |
192 | CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), | |
193 | CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), | |
194 | CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), | |
195 | /* Newer stuff */ | |
196 | CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), | |
197 | CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), | |
198 | CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
199 | CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
200 | CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), | |
201 | CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), | |
3050d45c | 202 | CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2), |
1da177e4 LT |
203 | CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), |
204 | CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), | |
205 | CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
206 | CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
207 | CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), | |
208 | CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), | |
209 | CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), | |
210 | CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), | |
211 | CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), | |
212 | CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), | |
213 | CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
214 | CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), | |
215 | CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), | |
216 | CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), | |
217 | CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), | |
218 | CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), | |
219 | CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), | |
220 | CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), | |
221 | CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), | |
222 | CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), | |
223 | /* Original Radeon/7200 */ | |
224 | CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), | |
225 | CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), | |
226 | CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), | |
227 | CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), | |
228 | { 0, } | |
229 | }; | |
230 | MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); | |
231 | ||
232 | ||
233 | typedef struct { | |
234 | u16 reg; | |
235 | u32 val; | |
236 | } reg_val; | |
237 | ||
238 | ||
239 | /* these common regs are cleared before mode setting so they do not | |
240 | * interfere with anything | |
241 | */ | |
242 | static reg_val common_regs[] = { | |
243 | { OVR_CLR, 0 }, | |
244 | { OVR_WID_LEFT_RIGHT, 0 }, | |
245 | { OVR_WID_TOP_BOTTOM, 0 }, | |
246 | { OV0_SCALE_CNTL, 0 }, | |
247 | { SUBPIC_CNTL, 0 }, | |
248 | { VIPH_CONTROL, 0 }, | |
249 | { I2C_CNTL_1, 0 }, | |
250 | { GEN_INT_CNTL, 0 }, | |
251 | { CAP0_TRIG_CNTL, 0 }, | |
252 | { CAP1_TRIG_CNTL, 0 }, | |
253 | }; | |
254 | ||
255 | /* | |
256 | * globals | |
257 | */ | |
258 | ||
259 | static char *mode_option; | |
260 | static char *monitor_layout; | |
90ab5ee9 | 261 | static bool noaccel = 0; |
1da177e4 | 262 | static int default_dynclk = -2; |
90ab5ee9 RR |
263 | static bool nomodeset = 0; |
264 | static bool ignore_edid = 0; | |
265 | static bool mirror = 0; | |
1da177e4 | 266 | static int panel_yres = 0; |
90ab5ee9 RR |
267 | static bool force_dfp = 0; |
268 | static bool force_measure_pll = 0; | |
90ab5ee9 | 269 | static bool nomtrr = 0; |
90ab5ee9 RR |
270 | static bool force_sleep; |
271 | static bool ignore_devlist; | |
72081524 | 272 | static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); |
1da177e4 | 273 | |
08bfb453 DV |
274 | /* Note about this function: we have some rare cases where we must not schedule, |
275 | * this typically happen with our special "wake up early" hook which allows us to | |
276 | * wake up the graphic chip (and thus get the console back) before everything else | |
277 | * on some machines that support that mechanism. At this point, interrupts are off | |
278 | * and scheduling is not permitted | |
1da177e4 | 279 | */ |
08bfb453 DV |
280 | void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) |
281 | { | |
282 | if (rinfo->no_schedule || oops_in_progress) | |
283 | mdelay(ms); | |
284 | else | |
285 | msleep(ms); | |
286 | } | |
287 | ||
288 | void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo) | |
289 | { | |
290 | /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ | |
291 | (void)INREG(CLOCK_CNTL_DATA); | |
292 | (void)INREG(CRTC_GEN_CNTL); | |
293 | } | |
294 | ||
295 | void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo) | |
296 | { | |
297 | if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { | |
298 | /* we can't deal with posted writes here ... */ | |
299 | _radeon_msleep(rinfo, 5); | |
300 | } | |
301 | if (rinfo->errata & CHIP_ERRATA_R300_CG) { | |
302 | u32 save, tmp; | |
303 | save = INREG(CLOCK_CNTL_INDEX); | |
304 | tmp = save & ~(0x3f | PLL_WR_EN); | |
305 | OUTREG(CLOCK_CNTL_INDEX, tmp); | |
306 | tmp = INREG(CLOCK_CNTL_DATA); | |
307 | OUTREG(CLOCK_CNTL_INDEX, save); | |
308 | } | |
309 | } | |
310 | ||
311 | void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) | |
312 | { | |
313 | unsigned long flags; | |
314 | unsigned int tmp; | |
315 | ||
316 | spin_lock_irqsave(&rinfo->reg_lock, flags); | |
317 | tmp = INREG(addr); | |
318 | tmp &= (mask); | |
319 | tmp |= (val); | |
320 | OUTREG(addr, tmp); | |
321 | spin_unlock_irqrestore(&rinfo->reg_lock, flags); | |
322 | } | |
323 | ||
324 | u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) | |
325 | { | |
326 | u32 data; | |
327 | ||
328 | OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); | |
329 | radeon_pll_errata_after_index(rinfo); | |
330 | data = INREG(CLOCK_CNTL_DATA); | |
331 | radeon_pll_errata_after_data(rinfo); | |
332 | return data; | |
333 | } | |
334 | ||
335 | void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) | |
336 | { | |
337 | OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); | |
338 | radeon_pll_errata_after_index(rinfo); | |
339 | OUTREG(CLOCK_CNTL_DATA, val); | |
340 | radeon_pll_errata_after_data(rinfo); | |
341 | } | |
342 | ||
343 | void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, | |
344 | u32 val, u32 mask) | |
345 | { | |
346 | unsigned int tmp; | |
347 | ||
348 | tmp = __INPLL(rinfo, index); | |
349 | tmp &= (mask); | |
350 | tmp |= (val); | |
351 | __OUTPLL(rinfo, index, tmp); | |
352 | } | |
353 | ||
354 | void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) | |
355 | { | |
356 | int i; | |
357 | ||
358 | for (i=0; i<2000000; i++) { | |
359 | if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
360 | return; | |
361 | udelay(1); | |
362 | } | |
363 | printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); | |
364 | } | |
365 | ||
366 | void radeon_engine_flush(struct radeonfb_info *rinfo) | |
367 | { | |
368 | int i; | |
369 | ||
370 | /* Initiate flush */ | |
371 | OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
372 | ~RB2D_DC_FLUSH_ALL); | |
373 | ||
374 | /* Ensure FIFO is empty, ie, make sure the flush commands | |
375 | * has reached the cache | |
376 | */ | |
377 | _radeon_fifo_wait(rinfo, 64); | |
378 | ||
379 | /* Wait for the flush to complete */ | |
380 | for (i=0; i < 2000000; i++) { | |
381 | if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
382 | return; | |
383 | udelay(1); | |
384 | } | |
385 | printk(KERN_ERR "radeonfb: Flush Timeout !\n"); | |
386 | } | |
387 | ||
388 | void _radeon_engine_idle(struct radeonfb_info *rinfo) | |
389 | { | |
390 | int i; | |
391 | ||
392 | /* ensure FIFO is empty before waiting for idle */ | |
393 | _radeon_fifo_wait(rinfo, 64); | |
394 | ||
395 | for (i=0; i<2000000; i++) { | |
396 | if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
397 | radeon_engine_flush(rinfo); | |
398 | return; | |
399 | } | |
400 | udelay(1); | |
401 | } | |
402 | printk(KERN_ERR "radeonfb: Idle Timeout !\n"); | |
403 | } | |
404 | ||
405 | ||
1da177e4 | 406 | |
1da177e4 LT |
407 | static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) |
408 | { | |
409 | if (!rinfo->bios_seg) | |
410 | return; | |
411 | pci_unmap_rom(dev, rinfo->bios_seg); | |
412 | } | |
413 | ||
48c68c4f | 414 | static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) |
1da177e4 LT |
415 | { |
416 | void __iomem *rom; | |
417 | u16 dptr; | |
418 | u8 rom_type; | |
419 | size_t rom_size; | |
420 | ||
421 | /* If this is a primary card, there is a shadow copy of the | |
422 | * ROM somewhere in the first meg. We will just ignore the copy | |
423 | * and use the ROM directly. | |
424 | */ | |
425 | ||
426 | /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ | |
427 | unsigned int temp; | |
428 | temp = INREG(MPP_TB_CONFIG); | |
429 | temp &= 0x00ffffffu; | |
430 | temp |= 0x04 << 24; | |
431 | OUTREG(MPP_TB_CONFIG, temp); | |
432 | temp = INREG(MPP_TB_CONFIG); | |
433 | ||
434 | rom = pci_map_rom(dev, &rom_size); | |
435 | if (!rom) { | |
436 | printk(KERN_ERR "radeonfb (%s): ROM failed to map\n", | |
437 | pci_name(rinfo->pdev)); | |
438 | return -ENOMEM; | |
439 | } | |
440 | ||
441 | rinfo->bios_seg = rom; | |
442 | ||
443 | /* Very simple test to make sure it appeared */ | |
444 | if (BIOS_IN16(0) != 0xaa55) { | |
3b4abffb OH |
445 | printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x " |
446 | "should be 0xaa55\n", | |
447 | pci_name(rinfo->pdev), BIOS_IN16(0)); | |
1da177e4 LT |
448 | goto failed; |
449 | } | |
450 | /* Look for the PCI data to check the ROM type */ | |
451 | dptr = BIOS_IN16(0x18); | |
452 | ||
453 | /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM | |
454 | * for now, until I've verified this works everywhere. The goal here is more | |
455 | * to phase out Open Firmware images. | |
456 | * | |
457 | * Currently, we only look at the first PCI data, we could iteratre and deal with | |
458 | * them all, and we should use fb_bios_start relative to start of image and not | |
459 | * relative start of ROM, but so far, I never found a dual-image ATI card | |
460 | * | |
461 | * typedef struct { | |
462 | * u32 signature; + 0x00 | |
463 | * u16 vendor; + 0x04 | |
464 | * u16 device; + 0x06 | |
465 | * u16 reserved_1; + 0x08 | |
466 | * u16 dlen; + 0x0a | |
467 | * u8 drevision; + 0x0c | |
468 | * u8 class_hi; + 0x0d | |
469 | * u16 class_lo; + 0x0e | |
470 | * u16 ilen; + 0x10 | |
471 | * u16 irevision; + 0x12 | |
472 | * u8 type; + 0x14 | |
473 | * u8 indicator; + 0x15 | |
474 | * u16 reserved_2; + 0x16 | |
475 | * } pci_data_t; | |
476 | */ | |
477 | if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { | |
478 | printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM" | |
479 | "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); | |
480 | goto anyway; | |
481 | } | |
482 | rom_type = BIOS_IN8(dptr + 0x14); | |
483 | switch(rom_type) { | |
484 | case 0: | |
485 | printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n"); | |
486 | break; | |
487 | case 1: | |
488 | printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n"); | |
489 | goto failed; | |
490 | case 2: | |
491 | printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); | |
492 | goto failed; | |
493 | default: | |
494 | printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type); | |
495 | goto failed; | |
496 | } | |
497 | anyway: | |
498 | /* Locate the flat panel infos, do some sanity checking !!! */ | |
499 | rinfo->fp_bios_start = BIOS_IN16(0x48); | |
500 | return 0; | |
501 | ||
502 | failed: | |
503 | rinfo->bios_seg = NULL; | |
504 | radeon_unmap_ROM(rinfo, dev); | |
505 | return -ENXIO; | |
506 | } | |
507 | ||
508 | #ifdef CONFIG_X86 | |
48c68c4f | 509 | static int radeon_find_mem_vbios(struct radeonfb_info *rinfo) |
1da177e4 LT |
510 | { |
511 | /* I simplified this code as we used to miss the signatures in | |
512 | * a lot of case. It's now closer to XFree, we just don't check | |
513 | * for signatures at all... Something better will have to be done | |
514 | * if we end up having conflicts | |
515 | */ | |
516 | u32 segstart; | |
517 | void __iomem *rom_base = NULL; | |
518 | ||
519 | for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { | |
520 | rom_base = ioremap(segstart, 0x10000); | |
521 | if (rom_base == NULL) | |
522 | return -ENOMEM; | |
523 | if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) | |
524 | break; | |
525 | iounmap(rom_base); | |
526 | rom_base = NULL; | |
527 | } | |
528 | if (rom_base == NULL) | |
529 | return -ENXIO; | |
530 | ||
531 | /* Locate the flat panel infos, do some sanity checking !!! */ | |
532 | rinfo->bios_seg = rom_base; | |
533 | rinfo->fp_bios_start = BIOS_IN16(0x48); | |
534 | ||
535 | return 0; | |
536 | } | |
537 | #endif | |
538 | ||
758ddd1d | 539 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 LT |
540 | /* |
541 | * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device | |
542 | * tree. Hopefully, ATI OF driver is kind enough to fill these | |
543 | */ | |
48c68c4f | 544 | static int radeon_read_xtal_OF(struct radeonfb_info *rinfo) |
1da177e4 LT |
545 | { |
546 | struct device_node *dp = rinfo->of_node; | |
b04e3dd4 | 547 | const u32 *val; |
1da177e4 LT |
548 | |
549 | if (dp == NULL) | |
550 | return -ENODEV; | |
40cd3a45 | 551 | val = of_get_property(dp, "ATY,RefCLK", NULL); |
1da177e4 LT |
552 | if (!val || !*val) { |
553 | printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); | |
554 | return -EINVAL; | |
555 | } | |
556 | ||
557 | rinfo->pll.ref_clk = (*val) / 10; | |
558 | ||
40cd3a45 | 559 | val = of_get_property(dp, "ATY,SCLK", NULL); |
1da177e4 LT |
560 | if (val && *val) |
561 | rinfo->pll.sclk = (*val) / 10; | |
562 | ||
40cd3a45 | 563 | val = of_get_property(dp, "ATY,MCLK", NULL); |
1da177e4 LT |
564 | if (val && *val) |
565 | rinfo->pll.mclk = (*val) / 10; | |
566 | ||
567 | return 0; | |
568 | } | |
758ddd1d | 569 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
1da177e4 LT |
570 | |
571 | /* | |
572 | * Read PLL infos from chip registers | |
573 | */ | |
48c68c4f | 574 | static int radeon_probe_pll_params(struct radeonfb_info *rinfo) |
1da177e4 LT |
575 | { |
576 | unsigned char ppll_div_sel; | |
577 | unsigned Ns, Nm, M; | |
578 | unsigned sclk, mclk, tmp, ref_div; | |
579 | int hTotal, vTotal, num, denom, m, n; | |
580 | unsigned long long hz, vclk; | |
581 | long xtal; | |
63a4be93 AB |
582 | ktime_t start_time, stop_time; |
583 | u64 total_usecs; | |
1da177e4 LT |
584 | int i; |
585 | ||
586 | /* Ugh, we cut interrupts, bad bad bad, but we want some precision | |
587 | * here, so... --BenH | |
588 | */ | |
589 | ||
590 | /* Flush PCI buffers ? */ | |
017fb98e | 591 | tmp = INREG16(DEVICE_ID); |
1da177e4 LT |
592 | |
593 | local_irq_disable(); | |
594 | ||
595 | for(i=0; i<1000000; i++) | |
596 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) | |
597 | break; | |
598 | ||
63a4be93 | 599 | start_time = ktime_get(); |
1da177e4 LT |
600 | |
601 | for(i=0; i<1000000; i++) | |
602 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) | |
603 | break; | |
604 | ||
605 | for(i=0; i<1000000; i++) | |
606 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) | |
607 | break; | |
608 | ||
63a4be93 | 609 | stop_time = ktime_get(); |
1da177e4 LT |
610 | |
611 | local_irq_enable(); | |
612 | ||
63a4be93 AB |
613 | total_usecs = ktime_us_delta(stop_time, start_time); |
614 | if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0) | |
1da177e4 | 615 | return -1; |
63a4be93 | 616 | hz = USEC_PER_SEC/(u32)total_usecs; |
1da177e4 LT |
617 | |
618 | hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; | |
619 | vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); | |
620 | vclk = (long long)hTotal * (long long)vTotal * hz; | |
621 | ||
622 | switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { | |
623 | case 0: | |
624 | default: | |
625 | num = 1; | |
626 | denom = 1; | |
627 | break; | |
628 | case 1: | |
629 | n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); | |
630 | m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); | |
631 | num = 2*n; | |
632 | denom = 2*m; | |
633 | break; | |
634 | case 2: | |
635 | n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); | |
636 | m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); | |
637 | num = 2*n; | |
638 | denom = 2*m; | |
639 | break; | |
640 | } | |
641 | ||
642 | ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; | |
643 | radeon_pll_errata_after_index(rinfo); | |
644 | ||
645 | n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); | |
646 | m = (INPLL(PPLL_REF_DIV) & 0x3ff); | |
647 | ||
648 | num *= n; | |
649 | denom *= m; | |
650 | ||
651 | switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { | |
652 | case 1: | |
653 | denom *= 2; | |
654 | break; | |
655 | case 2: | |
656 | denom *= 4; | |
657 | break; | |
658 | case 3: | |
659 | denom *= 8; | |
660 | break; | |
661 | case 4: | |
662 | denom *= 3; | |
663 | break; | |
664 | case 6: | |
665 | denom *= 6; | |
666 | break; | |
667 | case 7: | |
668 | denom *= 12; | |
669 | break; | |
670 | } | |
671 | ||
672 | vclk *= denom; | |
673 | do_div(vclk, 1000 * num); | |
674 | xtal = vclk; | |
675 | ||
676 | if ((xtal > 26900) && (xtal < 27100)) | |
677 | xtal = 2700; | |
678 | else if ((xtal > 14200) && (xtal < 14400)) | |
679 | xtal = 1432; | |
680 | else if ((xtal > 29400) && (xtal < 29600)) | |
681 | xtal = 2950; | |
682 | else { | |
683 | printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal); | |
684 | return -1; | |
685 | } | |
686 | ||
687 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
688 | ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; | |
689 | ||
690 | Ns = (tmp & 0xff0000) >> 16; | |
691 | Nm = (tmp & 0xff00) >> 8; | |
692 | M = (tmp & 0xff); | |
693 | sclk = round_div((2 * Ns * xtal), (2 * M)); | |
694 | mclk = round_div((2 * Nm * xtal), (2 * M)); | |
695 | ||
696 | /* we're done, hopefully these are sane values */ | |
697 | rinfo->pll.ref_clk = xtal; | |
698 | rinfo->pll.ref_div = ref_div; | |
699 | rinfo->pll.sclk = sclk; | |
700 | rinfo->pll.mclk = mclk; | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | /* | |
4a4efbde | 706 | * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) |
1da177e4 | 707 | */ |
48c68c4f | 708 | static void radeon_get_pllinfo(struct radeonfb_info *rinfo) |
1da177e4 LT |
709 | { |
710 | /* | |
711 | * In the case nothing works, these are defaults; they are mostly | |
712 | * incomplete, however. It does provide ppll_max and _min values | |
713 | * even for most other methods, however. | |
714 | */ | |
715 | switch (rinfo->chipset) { | |
716 | case PCI_DEVICE_ID_ATI_RADEON_QW: | |
717 | case PCI_DEVICE_ID_ATI_RADEON_QX: | |
718 | rinfo->pll.ppll_max = 35000; | |
719 | rinfo->pll.ppll_min = 12000; | |
720 | rinfo->pll.mclk = 23000; | |
721 | rinfo->pll.sclk = 23000; | |
722 | rinfo->pll.ref_clk = 2700; | |
723 | break; | |
724 | case PCI_DEVICE_ID_ATI_RADEON_QL: | |
725 | case PCI_DEVICE_ID_ATI_RADEON_QN: | |
726 | case PCI_DEVICE_ID_ATI_RADEON_QO: | |
727 | case PCI_DEVICE_ID_ATI_RADEON_Ql: | |
728 | case PCI_DEVICE_ID_ATI_RADEON_BB: | |
729 | rinfo->pll.ppll_max = 35000; | |
730 | rinfo->pll.ppll_min = 12000; | |
731 | rinfo->pll.mclk = 27500; | |
732 | rinfo->pll.sclk = 27500; | |
733 | rinfo->pll.ref_clk = 2700; | |
734 | break; | |
735 | case PCI_DEVICE_ID_ATI_RADEON_Id: | |
736 | case PCI_DEVICE_ID_ATI_RADEON_Ie: | |
737 | case PCI_DEVICE_ID_ATI_RADEON_If: | |
738 | case PCI_DEVICE_ID_ATI_RADEON_Ig: | |
739 | rinfo->pll.ppll_max = 35000; | |
740 | rinfo->pll.ppll_min = 12000; | |
741 | rinfo->pll.mclk = 25000; | |
742 | rinfo->pll.sclk = 25000; | |
743 | rinfo->pll.ref_clk = 2700; | |
744 | break; | |
745 | case PCI_DEVICE_ID_ATI_RADEON_ND: | |
746 | case PCI_DEVICE_ID_ATI_RADEON_NE: | |
747 | case PCI_DEVICE_ID_ATI_RADEON_NF: | |
748 | case PCI_DEVICE_ID_ATI_RADEON_NG: | |
749 | rinfo->pll.ppll_max = 40000; | |
750 | rinfo->pll.ppll_min = 20000; | |
751 | rinfo->pll.mclk = 27000; | |
752 | rinfo->pll.sclk = 27000; | |
753 | rinfo->pll.ref_clk = 2700; | |
754 | break; | |
755 | case PCI_DEVICE_ID_ATI_RADEON_QD: | |
756 | case PCI_DEVICE_ID_ATI_RADEON_QE: | |
757 | case PCI_DEVICE_ID_ATI_RADEON_QF: | |
758 | case PCI_DEVICE_ID_ATI_RADEON_QG: | |
759 | default: | |
760 | rinfo->pll.ppll_max = 35000; | |
761 | rinfo->pll.ppll_min = 12000; | |
762 | rinfo->pll.mclk = 16600; | |
763 | rinfo->pll.sclk = 16600; | |
764 | rinfo->pll.ref_clk = 2700; | |
765 | break; | |
766 | } | |
767 | rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; | |
768 | ||
769 | ||
758ddd1d | 770 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 | 771 | /* |
4a4efbde | 772 | * Retrieve PLL infos from Open Firmware first |
1da177e4 LT |
773 | */ |
774 | if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) { | |
4a4efbde | 775 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n"); |
1da177e4 LT |
776 | goto found; |
777 | } | |
758ddd1d | 778 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
1da177e4 LT |
779 | |
780 | /* | |
781 | * Check out if we have an X86 which gave us some PLL informations | |
4a4efbde | 782 | * and if yes, retrieve them |
1da177e4 LT |
783 | */ |
784 | if (!force_measure_pll && rinfo->bios_seg) { | |
785 | u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); | |
786 | ||
787 | rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); | |
788 | rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); | |
789 | rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); | |
790 | rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); | |
791 | rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); | |
792 | rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); | |
793 | ||
4a4efbde | 794 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); |
1da177e4 LT |
795 | goto found; |
796 | } | |
797 | ||
798 | /* | |
799 | * We didn't get PLL parameters from either OF or BIOS, we try to | |
800 | * probe them | |
801 | */ | |
802 | if (radeon_probe_pll_params(rinfo) == 0) { | |
4a4efbde | 803 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n"); |
1da177e4 LT |
804 | goto found; |
805 | } | |
806 | ||
807 | /* | |
808 | * Fall back to already-set defaults... | |
809 | */ | |
810 | printk(KERN_INFO "radeonfb: Used default PLL infos\n"); | |
811 | ||
812 | found: | |
813 | /* | |
4a4efbde | 814 | * Some methods fail to retrieve SCLK and MCLK values, we apply default |
3e621019 PM |
815 | * settings in this case (200Mhz). If that really happens often, we |
816 | * could fetch from registers instead... | |
1da177e4 LT |
817 | */ |
818 | if (rinfo->pll.mclk == 0) | |
819 | rinfo->pll.mclk = 20000; | |
820 | if (rinfo->pll.sclk == 0) | |
821 | rinfo->pll.sclk = 20000; | |
822 | ||
823 | printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", | |
824 | rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, | |
825 | rinfo->pll.ref_div, | |
826 | rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, | |
827 | rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); | |
828 | printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); | |
829 | } | |
830 | ||
831 | static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) | |
832 | { | |
833 | struct radeonfb_info *rinfo = info->par; | |
834 | struct fb_var_screeninfo v; | |
835 | int nom, den; | |
836 | unsigned int pitch; | |
837 | ||
838 | if (radeon_match_mode(rinfo, &v, var)) | |
839 | return -EINVAL; | |
840 | ||
841 | switch (v.bits_per_pixel) { | |
842 | case 0 ... 8: | |
843 | v.bits_per_pixel = 8; | |
844 | break; | |
845 | case 9 ... 16: | |
846 | v.bits_per_pixel = 16; | |
847 | break; | |
1da177e4 LT |
848 | case 25 ... 32: |
849 | v.bits_per_pixel = 32; | |
850 | break; | |
851 | default: | |
852 | return -EINVAL; | |
853 | } | |
854 | ||
855 | switch (var_to_depth(&v)) { | |
856 | case 8: | |
857 | nom = den = 1; | |
858 | v.red.offset = v.green.offset = v.blue.offset = 0; | |
859 | v.red.length = v.green.length = v.blue.length = 8; | |
860 | v.transp.offset = v.transp.length = 0; | |
861 | break; | |
862 | case 15: | |
863 | nom = 2; | |
864 | den = 1; | |
865 | v.red.offset = 10; | |
866 | v.green.offset = 5; | |
867 | v.blue.offset = 0; | |
868 | v.red.length = v.green.length = v.blue.length = 5; | |
869 | v.transp.offset = v.transp.length = 0; | |
870 | break; | |
871 | case 16: | |
872 | nom = 2; | |
873 | den = 1; | |
874 | v.red.offset = 11; | |
875 | v.green.offset = 5; | |
876 | v.blue.offset = 0; | |
877 | v.red.length = 5; | |
878 | v.green.length = 6; | |
879 | v.blue.length = 5; | |
880 | v.transp.offset = v.transp.length = 0; | |
881 | break; | |
882 | case 24: | |
883 | nom = 4; | |
884 | den = 1; | |
885 | v.red.offset = 16; | |
886 | v.green.offset = 8; | |
887 | v.blue.offset = 0; | |
888 | v.red.length = v.blue.length = v.green.length = 8; | |
889 | v.transp.offset = v.transp.length = 0; | |
890 | break; | |
891 | case 32: | |
892 | nom = 4; | |
893 | den = 1; | |
894 | v.red.offset = 16; | |
895 | v.green.offset = 8; | |
896 | v.blue.offset = 0; | |
897 | v.red.length = v.blue.length = v.green.length = 8; | |
898 | v.transp.offset = 24; | |
899 | v.transp.length = 8; | |
900 | break; | |
901 | default: | |
902 | printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n", | |
903 | var->xres, var->yres, var->bits_per_pixel); | |
904 | return -EINVAL; | |
905 | } | |
906 | ||
907 | if (v.yres_virtual < v.yres) | |
908 | v.yres_virtual = v.yres; | |
909 | if (v.xres_virtual < v.xres) | |
910 | v.xres_virtual = v.xres; | |
911 | ||
912 | ||
913 | /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree | |
914 | * with some panels, though I don't quite like this solution | |
915 | */ | |
916 | if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { | |
917 | v.xres_virtual = v.xres_virtual & ~7ul; | |
918 | } else { | |
919 | pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) | |
920 | & ~(0x3f)) >> 6; | |
921 | v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); | |
922 | } | |
923 | ||
924 | if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) | |
925 | return -EINVAL; | |
926 | ||
927 | if (v.xres_virtual < v.xres) | |
928 | v.xres = v.xres_virtual; | |
929 | ||
1da177e4 LT |
930 | if (v.xoffset > v.xres_virtual - v.xres) |
931 | v.xoffset = v.xres_virtual - v.xres - 1; | |
932 | ||
933 | if (v.yoffset > v.yres_virtual - v.yres) | |
934 | v.yoffset = v.yres_virtual - v.yres - 1; | |
935 | ||
936 | v.red.msb_right = v.green.msb_right = v.blue.msb_right = | |
937 | v.transp.offset = v.transp.length = | |
938 | v.transp.msb_right = 0; | |
939 | ||
940 | memcpy(var, &v, sizeof(v)); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | ||
946 | static int radeonfb_pan_display (struct fb_var_screeninfo *var, | |
947 | struct fb_info *info) | |
948 | { | |
949 | struct radeonfb_info *rinfo = info->par; | |
950 | ||
0e03f856 LP |
951 | if ((var->xoffset + info->var.xres > info->var.xres_virtual) |
952 | || (var->yoffset + info->var.yres > info->var.yres_virtual)) | |
953 | return -EINVAL; | |
1da177e4 LT |
954 | |
955 | if (rinfo->asleep) | |
956 | return 0; | |
957 | ||
6c34bc29 | 958 | radeon_fifo_wait(2); |
0e03f856 LP |
959 | OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + |
960 | var->xoffset * info->var.bits_per_pixel / 8) & ~7); | |
1da177e4 LT |
961 | return 0; |
962 | } | |
963 | ||
964 | ||
67a6680d CH |
965 | static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, |
966 | unsigned long arg) | |
1da177e4 LT |
967 | { |
968 | struct radeonfb_info *rinfo = info->par; | |
969 | unsigned int tmp; | |
970 | u32 value = 0; | |
971 | int rc; | |
972 | ||
973 | switch (cmd) { | |
974 | /* | |
975 | * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's | |
976 | * and do something better using 2nd CRTC instead of just hackish | |
977 | * routing to second output | |
978 | */ | |
979 | case FBIO_RADEON_SET_MIRROR: | |
980 | if (!rinfo->is_mobility) | |
981 | return -EINVAL; | |
982 | ||
983 | rc = get_user(value, (__u32 __user *)arg); | |
984 | ||
985 | if (rc) | |
986 | return rc; | |
987 | ||
6c34bc29 | 988 | radeon_fifo_wait(2); |
1da177e4 LT |
989 | if (value & 0x01) { |
990 | tmp = INREG(LVDS_GEN_CNTL); | |
991 | ||
992 | tmp |= (LVDS_ON | LVDS_BLON); | |
993 | } else { | |
994 | tmp = INREG(LVDS_GEN_CNTL); | |
995 | ||
996 | tmp &= ~(LVDS_ON | LVDS_BLON); | |
997 | } | |
998 | ||
999 | OUTREG(LVDS_GEN_CNTL, tmp); | |
1000 | ||
1001 | if (value & 0x02) { | |
1002 | tmp = INREG(CRTC_EXT_CNTL); | |
1003 | tmp |= CRTC_CRT_ON; | |
1004 | ||
1005 | mirror = 1; | |
1006 | } else { | |
1007 | tmp = INREG(CRTC_EXT_CNTL); | |
1008 | tmp &= ~CRTC_CRT_ON; | |
1009 | ||
1010 | mirror = 0; | |
1011 | } | |
1012 | ||
1013 | OUTREG(CRTC_EXT_CNTL, tmp); | |
1014 | ||
1015 | return 0; | |
1016 | case FBIO_RADEON_GET_MIRROR: | |
1017 | if (!rinfo->is_mobility) | |
1018 | return -EINVAL; | |
1019 | ||
1020 | tmp = INREG(LVDS_GEN_CNTL); | |
1021 | if ((LVDS_ON | LVDS_BLON) & tmp) | |
1022 | value |= 0x01; | |
1023 | ||
1024 | tmp = INREG(CRTC_EXT_CNTL); | |
1025 | if (CRTC_CRT_ON & tmp) | |
1026 | value |= 0x02; | |
1027 | ||
1028 | return put_user(value, (__u32 __user *)arg); | |
1029 | default: | |
1030 | return -EINVAL; | |
1031 | } | |
1032 | ||
1033 | return -EINVAL; | |
1034 | } | |
1035 | ||
1036 | ||
1037 | int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) | |
1038 | { | |
1039 | u32 val; | |
1040 | u32 tmp_pix_clks; | |
1041 | int unblank = 0; | |
1042 | ||
1043 | if (rinfo->lock_blank) | |
1044 | return 0; | |
1045 | ||
6c34bc29 | 1046 | radeon_engine_idle(); |
1da177e4 LT |
1047 | |
1048 | val = INREG(CRTC_EXT_CNTL); | |
1049 | val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | | |
1050 | CRTC_VSYNC_DIS); | |
1051 | switch (blank) { | |
1052 | case FB_BLANK_VSYNC_SUSPEND: | |
1053 | val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); | |
1054 | break; | |
1055 | case FB_BLANK_HSYNC_SUSPEND: | |
1056 | val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); | |
1057 | break; | |
1058 | case FB_BLANK_POWERDOWN: | |
1059 | val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | | |
1060 | CRTC_HSYNC_DIS); | |
1061 | break; | |
1062 | case FB_BLANK_NORMAL: | |
1063 | val |= CRTC_DISPLAY_DIS; | |
1064 | break; | |
1065 | case FB_BLANK_UNBLANK: | |
1066 | default: | |
1067 | unblank = 1; | |
1068 | } | |
1069 | OUTREG(CRTC_EXT_CNTL, val); | |
1070 | ||
1071 | ||
1072 | switch (rinfo->mon1_type) { | |
1073 | case MT_DFP: | |
1074 | if (unblank) | |
1075 | OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), | |
1076 | ~(FP_FPON | FP_TMDS_EN)); | |
1077 | else { | |
1078 | if (mode_switch || blank == FB_BLANK_NORMAL) | |
1079 | break; | |
1080 | OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); | |
1081 | } | |
1082 | break; | |
1083 | case MT_LCD: | |
1084 | del_timer_sync(&rinfo->lvds_timer); | |
1085 | val = INREG(LVDS_GEN_CNTL); | |
1086 | if (unblank) { | |
1087 | u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON | |
1088 | | LVDS_EN | (rinfo->init_state.lvds_gen_cntl | |
1089 | & (LVDS_DIGON | LVDS_BL_MOD_EN)); | |
1090 | if ((val ^ target_val) == LVDS_DISPLAY_DIS) | |
1091 | OUTREG(LVDS_GEN_CNTL, target_val); | |
1092 | else if ((val ^ target_val) != 0) { | |
1093 | OUTREG(LVDS_GEN_CNTL, target_val | |
1094 | & ~(LVDS_ON | LVDS_BL_MOD_EN)); | |
1095 | rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; | |
1096 | rinfo->init_state.lvds_gen_cntl |= | |
1097 | target_val & LVDS_STATE_MASK; | |
1098 | if (mode_switch) { | |
1099 | radeon_msleep(rinfo->panel_info.pwr_delay); | |
1100 | OUTREG(LVDS_GEN_CNTL, target_val); | |
1101 | } | |
1102 | else { | |
1103 | rinfo->pending_lvds_gen_cntl = target_val; | |
1104 | mod_timer(&rinfo->lvds_timer, | |
1105 | jiffies + | |
1106 | msecs_to_jiffies(rinfo->panel_info.pwr_delay)); | |
1107 | } | |
1108 | } | |
1109 | } else { | |
1110 | val |= LVDS_DISPLAY_DIS; | |
1111 | OUTREG(LVDS_GEN_CNTL, val); | |
1112 | ||
1113 | /* We don't do a full switch-off on a simple mode switch */ | |
1114 | if (mode_switch || blank == FB_BLANK_NORMAL) | |
1115 | break; | |
1116 | ||
1117 | /* Asic bug, when turning off LVDS_ON, we have to make sure | |
1118 | * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off | |
1119 | */ | |
1120 | tmp_pix_clks = INPLL(PIXCLKS_CNTL); | |
1121 | if (rinfo->is_mobility || rinfo->is_IGP) | |
1122 | OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); | |
1123 | val &= ~(LVDS_BL_MOD_EN); | |
1124 | OUTREG(LVDS_GEN_CNTL, val); | |
1125 | udelay(100); | |
1126 | val &= ~(LVDS_ON | LVDS_EN); | |
1127 | OUTREG(LVDS_GEN_CNTL, val); | |
1128 | val &= ~LVDS_DIGON; | |
1129 | rinfo->pending_lvds_gen_cntl = val; | |
1130 | mod_timer(&rinfo->lvds_timer, | |
1131 | jiffies + | |
1132 | msecs_to_jiffies(rinfo->panel_info.pwr_delay)); | |
1133 | rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; | |
1134 | rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; | |
1135 | if (rinfo->is_mobility || rinfo->is_IGP) | |
1136 | OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); | |
1137 | } | |
1138 | break; | |
1139 | case MT_CRT: | |
1140 | // todo: powerdown DAC | |
1141 | default: | |
1142 | break; | |
1143 | } | |
1144 | ||
7ab87670 | 1145 | return 0; |
1da177e4 LT |
1146 | } |
1147 | ||
1148 | static int radeonfb_blank (int blank, struct fb_info *info) | |
1149 | { | |
1150 | struct radeonfb_info *rinfo = info->par; | |
1151 | ||
1152 | if (rinfo->asleep) | |
1153 | return 0; | |
6c34bc29 | 1154 | |
1da177e4 LT |
1155 | return radeon_screen_blank(rinfo, blank, 0); |
1156 | } | |
1157 | ||
71494376 BH |
1158 | static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, |
1159 | unsigned blue, unsigned transp, | |
1160 | struct radeonfb_info *rinfo) | |
1da177e4 | 1161 | { |
1da177e4 LT |
1162 | u32 pindex; |
1163 | unsigned int i; | |
71494376 BH |
1164 | |
1165 | ||
1da177e4 | 1166 | if (regno > 255) |
db77ec27 | 1167 | return -EINVAL; |
1da177e4 LT |
1168 | |
1169 | red >>= 8; | |
1170 | green >>= 8; | |
1171 | blue >>= 8; | |
1172 | rinfo->palette[regno].red = red; | |
1173 | rinfo->palette[regno].green = green; | |
1174 | rinfo->palette[regno].blue = blue; | |
1175 | ||
1176 | /* default */ | |
1177 | pindex = regno; | |
1178 | ||
1179 | if (!rinfo->asleep) { | |
6c34bc29 LT |
1180 | radeon_fifo_wait(9); |
1181 | ||
1da177e4 LT |
1182 | if (rinfo->bpp == 16) { |
1183 | pindex = regno * 8; | |
1184 | ||
1185 | if (rinfo->depth == 16 && regno > 63) | |
db77ec27 | 1186 | return -EINVAL; |
1da177e4 | 1187 | if (rinfo->depth == 15 && regno > 31) |
db77ec27 | 1188 | return -EINVAL; |
1da177e4 | 1189 | |
71494376 BH |
1190 | /* For 565, the green component is mixed one order |
1191 | * below | |
1192 | */ | |
1da177e4 LT |
1193 | if (rinfo->depth == 16) { |
1194 | OUTREG(PALETTE_INDEX, pindex>>1); | |
71494376 BH |
1195 | OUTREG(PALETTE_DATA, |
1196 | (rinfo->palette[regno>>1].red << 16) | | |
1197 | (green << 8) | | |
1198 | (rinfo->palette[regno>>1].blue)); | |
1da177e4 LT |
1199 | green = rinfo->palette[regno<<1].green; |
1200 | } | |
1201 | } | |
1202 | ||
1203 | if (rinfo->depth != 16 || regno < 32) { | |
1204 | OUTREG(PALETTE_INDEX, pindex); | |
71494376 BH |
1205 | OUTREG(PALETTE_DATA, (red << 16) | |
1206 | (green << 8) | blue); | |
1da177e4 | 1207 | } |
1da177e4 LT |
1208 | } |
1209 | if (regno < 16) { | |
71494376 | 1210 | u32 *pal = rinfo->info->pseudo_palette; |
1da177e4 LT |
1211 | switch (rinfo->depth) { |
1212 | case 15: | |
1213 | pal[regno] = (regno << 10) | (regno << 5) | regno; | |
1214 | break; | |
1215 | case 16: | |
1216 | pal[regno] = (regno << 11) | (regno << 5) | regno; | |
1217 | break; | |
1218 | case 24: | |
1219 | pal[regno] = (regno << 16) | (regno << 8) | regno; | |
1220 | break; | |
1221 | case 32: | |
1222 | i = (regno << 8) | regno; | |
1223 | pal[regno] = (i << 16) | i; | |
1224 | break; | |
1225 | } | |
1226 | } | |
1227 | return 0; | |
1228 | } | |
1229 | ||
71494376 BH |
1230 | static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, |
1231 | unsigned blue, unsigned transp, | |
1232 | struct fb_info *info) | |
1233 | { | |
1234 | struct radeonfb_info *rinfo = info->par; | |
1235 | u32 dac_cntl2, vclk_cntl = 0; | |
1236 | int rc; | |
1237 | ||
1238 | if (!rinfo->asleep) { | |
1239 | if (rinfo->is_mobility) { | |
1240 | vclk_cntl = INPLL(VCLK_ECP_CNTL); | |
1241 | OUTPLL(VCLK_ECP_CNTL, | |
1242 | vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); | |
1243 | } | |
1244 | ||
1245 | /* Make sure we are on first palette */ | |
1246 | if (rinfo->has_CRTC2) { | |
1247 | dac_cntl2 = INREG(DAC_CNTL2); | |
1248 | dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; | |
1249 | OUTREG(DAC_CNTL2, dac_cntl2); | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo); | |
1254 | ||
1255 | if (!rinfo->asleep && rinfo->is_mobility) | |
1256 | OUTPLL(VCLK_ECP_CNTL, vclk_cntl); | |
1257 | ||
1258 | return rc; | |
1259 | } | |
1260 | ||
1261 | static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) | |
1262 | { | |
1263 | struct radeonfb_info *rinfo = info->par; | |
1264 | u16 *red, *green, *blue, *transp; | |
1265 | u32 dac_cntl2, vclk_cntl = 0; | |
1266 | int i, start, rc = 0; | |
1267 | ||
1268 | if (!rinfo->asleep) { | |
1269 | if (rinfo->is_mobility) { | |
1270 | vclk_cntl = INPLL(VCLK_ECP_CNTL); | |
1271 | OUTPLL(VCLK_ECP_CNTL, | |
1272 | vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); | |
1273 | } | |
1274 | ||
1275 | /* Make sure we are on first palette */ | |
1276 | if (rinfo->has_CRTC2) { | |
1277 | dac_cntl2 = INREG(DAC_CNTL2); | |
1278 | dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; | |
1279 | OUTREG(DAC_CNTL2, dac_cntl2); | |
1280 | } | |
1281 | } | |
1282 | ||
1283 | red = cmap->red; | |
1284 | green = cmap->green; | |
1285 | blue = cmap->blue; | |
1286 | transp = cmap->transp; | |
1287 | start = cmap->start; | |
1288 | ||
1289 | for (i = 0; i < cmap->len; i++) { | |
1290 | u_int hred, hgreen, hblue, htransp = 0xffff; | |
1291 | ||
1292 | hred = *red++; | |
1293 | hgreen = *green++; | |
1294 | hblue = *blue++; | |
1295 | if (transp) | |
1296 | htransp = *transp++; | |
1297 | rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp, | |
1298 | rinfo); | |
1299 | if (rc) | |
1300 | break; | |
1301 | } | |
1302 | ||
1303 | if (!rinfo->asleep && rinfo->is_mobility) | |
1304 | OUTPLL(VCLK_ECP_CNTL, vclk_cntl); | |
1305 | ||
1306 | return rc; | |
1307 | } | |
1da177e4 LT |
1308 | |
1309 | static void radeon_save_state (struct radeonfb_info *rinfo, | |
1310 | struct radeon_regs *save) | |
1311 | { | |
1312 | /* CRTC regs */ | |
1313 | save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); | |
1314 | save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); | |
1315 | save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); | |
1316 | save->dac_cntl = INREG(DAC_CNTL); | |
1317 | save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); | |
1318 | save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); | |
1319 | save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); | |
1320 | save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); | |
1321 | save->crtc_pitch = INREG(CRTC_PITCH); | |
1322 | save->surface_cntl = INREG(SURFACE_CNTL); | |
1323 | ||
1324 | /* FP regs */ | |
1325 | save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); | |
1326 | save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); | |
1327 | save->fp_gen_cntl = INREG(FP_GEN_CNTL); | |
1328 | save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); | |
1329 | save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); | |
1330 | save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); | |
1331 | save->fp_vert_stretch = INREG(FP_VERT_STRETCH); | |
1332 | save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); | |
1333 | save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); | |
1334 | save->tmds_crc = INREG(TMDS_CRC); | |
1335 | save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); | |
1336 | save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); | |
1337 | ||
1338 | /* PLL regs */ | |
1339 | save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; | |
1340 | radeon_pll_errata_after_index(rinfo); | |
1341 | save->ppll_div_3 = INPLL(PPLL_DIV_3); | |
1342 | save->ppll_ref_div = INPLL(PPLL_REF_DIV); | |
1343 | } | |
1344 | ||
1345 | ||
1346 | static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) | |
1347 | { | |
1348 | int i; | |
1349 | ||
6c34bc29 LT |
1350 | radeon_fifo_wait(20); |
1351 | ||
1da177e4 LT |
1352 | /* Workaround from XFree */ |
1353 | if (rinfo->is_mobility) { | |
83e61f71 | 1354 | /* A temporal workaround for the occasional blanking on certain laptop |
1da177e4 LT |
1355 | * panels. This appears to related to the PLL divider registers |
1356 | * (fail to lock?). It occurs even when all dividers are the same | |
1357 | * with their old settings. In this case we really don't need to | |
1358 | * fiddle with PLL registers. By doing this we can avoid the blanking | |
1359 | * problem with some panels. | |
1360 | */ | |
1361 | if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && | |
1362 | (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & | |
1363 | (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { | |
1364 | /* We still have to force a switch to selected PPLL div thanks to | |
1365 | * an XFree86 driver bug which will switch it away in some cases | |
1366 | * even when using UseFDev */ | |
1367 | OUTREGP(CLOCK_CNTL_INDEX, | |
1368 | mode->clk_cntl_index & PPLL_DIV_SEL_MASK, | |
1369 | ~PPLL_DIV_SEL_MASK); | |
1370 | radeon_pll_errata_after_index(rinfo); | |
1371 | radeon_pll_errata_after_data(rinfo); | |
1372 | return; | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ | |
1377 | OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); | |
1378 | ||
1379 | /* Reset PPLL & enable atomic update */ | |
1380 | OUTPLLP(PPLL_CNTL, | |
1381 | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, | |
1382 | ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); | |
1383 | ||
1384 | /* Switch to selected PPLL divider */ | |
1385 | OUTREGP(CLOCK_CNTL_INDEX, | |
1386 | mode->clk_cntl_index & PPLL_DIV_SEL_MASK, | |
1387 | ~PPLL_DIV_SEL_MASK); | |
1388 | radeon_pll_errata_after_index(rinfo); | |
1389 | radeon_pll_errata_after_data(rinfo); | |
1390 | ||
1391 | /* Set PPLL ref. div */ | |
a6c0c37d | 1392 | if (IS_R300_VARIANT(rinfo) || |
1da177e4 | 1393 | rinfo->family == CHIP_FAMILY_RS300 || |
a6c0c37d BH |
1394 | rinfo->family == CHIP_FAMILY_RS400 || |
1395 | rinfo->family == CHIP_FAMILY_RS480) { | |
1da177e4 LT |
1396 | if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
1397 | /* When restoring console mode, use saved PPLL_REF_DIV | |
1398 | * setting. | |
1399 | */ | |
1400 | OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); | |
1401 | } else { | |
1402 | /* R300 uses ref_div_acc field as real ref divider */ | |
1403 | OUTPLLP(PPLL_REF_DIV, | |
1404 | (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), | |
1405 | ~R300_PPLL_REF_DIV_ACC_MASK); | |
1406 | } | |
1407 | } else | |
1408 | OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); | |
1409 | ||
1410 | /* Set PPLL divider 3 & post divider*/ | |
1411 | OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); | |
1412 | OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); | |
1413 | ||
1414 | /* Write update */ | |
1415 | while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) | |
1416 | ; | |
1417 | OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); | |
1418 | ||
1419 | /* Wait read update complete */ | |
1420 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of | |
1421 | the cause yet, but this workaround will mask the problem for now. | |
1422 | Other chips usually will pass at the very first test, so the | |
1423 | workaround shouldn't have any effect on them. */ | |
1424 | for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) | |
1425 | ; | |
1426 | ||
1427 | OUTPLL(HTOTAL_CNTL, 0); | |
1428 | ||
1429 | /* Clear reset & atomic update */ | |
1430 | OUTPLLP(PPLL_CNTL, 0, | |
1431 | ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); | |
1432 | ||
1433 | /* We may want some locking ... oh well */ | |
1434 | radeon_msleep(5); | |
1435 | ||
1436 | /* Switch back VCLK source to PPLL */ | |
1437 | OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); | |
1438 | } | |
1439 | ||
1440 | /* | |
1441 | * Timer function for delayed LVDS panel power up/down | |
1442 | */ | |
6c789357 | 1443 | static void radeon_lvds_timer_func(struct timer_list *t) |
1da177e4 | 1444 | { |
6c789357 | 1445 | struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer); |
1da177e4 | 1446 | |
6c34bc29 | 1447 | radeon_engine_idle(); |
1da177e4 LT |
1448 | |
1449 | OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); | |
1450 | } | |
1451 | ||
1452 | /* | |
1453 | * Apply a video mode. This will apply the whole register set, including | |
1454 | * the PLL registers, to the card | |
1455 | */ | |
1456 | void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, | |
1457 | int regs_only) | |
1458 | { | |
1459 | int i; | |
1460 | int primary_mon = PRIMARY_MONITOR(rinfo); | |
1461 | ||
1462 | if (nomodeset) | |
1463 | return; | |
1464 | ||
1465 | if (!regs_only) | |
1466 | radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); | |
1467 | ||
6c34bc29 | 1468 | radeon_fifo_wait(31); |
1da177e4 LT |
1469 | for (i=0; i<10; i++) |
1470 | OUTREG(common_regs[i].reg, common_regs[i].val); | |
1471 | ||
1472 | /* Apply surface registers */ | |
1473 | for (i=0; i<8; i++) { | |
1474 | OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); | |
1475 | OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); | |
1476 | OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); | |
1477 | } | |
1478 | ||
1479 | OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); | |
1480 | OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, | |
1481 | ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); | |
1482 | OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); | |
1483 | OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); | |
1484 | OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); | |
1485 | OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); | |
1486 | OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); | |
1487 | OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); | |
1488 | OUTREG(CRTC_OFFSET, 0); | |
1489 | OUTREG(CRTC_OFFSET_CNTL, 0); | |
1490 | OUTREG(CRTC_PITCH, mode->crtc_pitch); | |
1491 | OUTREG(SURFACE_CNTL, mode->surface_cntl); | |
1492 | ||
1493 | radeon_write_pll_regs(rinfo, mode); | |
1494 | ||
1495 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
6c34bc29 | 1496 | radeon_fifo_wait(10); |
1da177e4 LT |
1497 | OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); |
1498 | OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); | |
1499 | OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); | |
1500 | OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); | |
1501 | OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); | |
1502 | OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); | |
1503 | OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); | |
1504 | OUTREG(TMDS_CRC, mode->tmds_crc); | |
1505 | OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); | |
1506 | } | |
1507 | ||
1508 | if (!regs_only) | |
1509 | radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); | |
1510 | ||
6c34bc29 | 1511 | radeon_fifo_wait(2); |
1da177e4 LT |
1512 | OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); |
1513 | ||
1514 | return; | |
1515 | } | |
1516 | ||
1517 | /* | |
1518 | * Calculate the PLL values for a given mode | |
1519 | */ | |
1520 | static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, | |
1521 | unsigned long freq) | |
1522 | { | |
0c09dd05 | 1523 | static const struct { |
1da177e4 LT |
1524 | int divider; |
1525 | int bitvalue; | |
1526 | } *post_div, | |
1527 | post_divs[] = { | |
1528 | { 1, 0 }, | |
1529 | { 2, 1 }, | |
1530 | { 4, 2 }, | |
1531 | { 8, 3 }, | |
1532 | { 3, 4 }, | |
1533 | { 16, 5 }, | |
1534 | { 6, 6 }, | |
1535 | { 12, 7 }, | |
1536 | { 0, 0 }, | |
1537 | }; | |
1538 | int fb_div, pll_output_freq = 0; | |
1539 | int uses_dvo = 0; | |
1540 | ||
1541 | /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm | |
1542 | * not sure which model starts having FP2_GEN_CNTL, I assume anything more | |
1543 | * recent than an r(v)100... | |
1544 | */ | |
1545 | #if 1 | |
1546 | /* XXX I had reports of flicker happening with the cinema display | |
1547 | * on TMDS1 that seem to be fixed if I also forbit odd dividers in | |
1548 | * this case. This could just be a bandwidth calculation issue, I | |
1549 | * haven't implemented the bandwidth code yet, but in the meantime, | |
1550 | * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, | |
1551 | * I haven't seen a case were were absolutely needed an odd PLL | |
1552 | * divider. I'll find a better fix once I have more infos on the | |
1553 | * real cause of the problem. | |
1554 | */ | |
1555 | while (rinfo->has_CRTC2) { | |
1556 | u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); | |
1557 | u32 disp_output_cntl; | |
1558 | int source; | |
1559 | ||
1560 | /* FP2 path not enabled */ | |
1561 | if ((fp2_gen_cntl & FP2_ON) == 0) | |
1562 | break; | |
1563 | /* Not all chip revs have the same format for this register, | |
1564 | * extract the source selection | |
1565 | */ | |
a6c0c37d | 1566 | if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { |
1da177e4 LT |
1567 | source = (fp2_gen_cntl >> 10) & 0x3; |
1568 | /* sourced from transform unit, check for transform unit | |
1569 | * own source | |
1570 | */ | |
1571 | if (source == 3) { | |
1572 | disp_output_cntl = INREG(DISP_OUTPUT_CNTL); | |
1573 | source = (disp_output_cntl >> 12) & 0x3; | |
1574 | } | |
1575 | } else | |
1576 | source = (fp2_gen_cntl >> 13) & 0x1; | |
1577 | /* sourced from CRTC2 -> exit */ | |
1578 | if (source == 1) | |
1579 | break; | |
1580 | ||
1581 | /* so we end up on CRTC1, let's set uses_dvo to 1 now */ | |
1582 | uses_dvo = 1; | |
1583 | break; | |
1584 | } | |
1585 | #else | |
1586 | uses_dvo = 1; | |
1587 | #endif | |
1588 | if (freq > rinfo->pll.ppll_max) | |
1589 | freq = rinfo->pll.ppll_max; | |
1590 | if (freq*12 < rinfo->pll.ppll_min) | |
1591 | freq = rinfo->pll.ppll_min / 12; | |
bc3bf466 | 1592 | pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n", |
1da177e4 LT |
1593 | freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); |
1594 | ||
1595 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { | |
1596 | pll_output_freq = post_div->divider * freq; | |
1597 | /* If we output to the DVO port (external TMDS), we don't allow an | |
1598 | * odd PLL divider as those aren't supported on this path | |
1599 | */ | |
1600 | if (uses_dvo && (post_div->divider & 1)) | |
1601 | continue; | |
1602 | if (pll_output_freq >= rinfo->pll.ppll_min && | |
1603 | pll_output_freq <= rinfo->pll.ppll_max) | |
1604 | break; | |
1605 | } | |
1606 | ||
1607 | /* If we fall through the bottom, try the "default value" | |
1608 | given by the terminal post_div->bitvalue */ | |
1609 | if ( !post_div->divider ) { | |
1610 | post_div = &post_divs[post_div->bitvalue]; | |
1611 | pll_output_freq = post_div->divider * freq; | |
1612 | } | |
bc3bf466 | 1613 | pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", |
1da177e4 LT |
1614 | rinfo->pll.ref_div, rinfo->pll.ref_clk, |
1615 | pll_output_freq); | |
1616 | ||
1617 | /* If we fall through the bottom, try the "default value" | |
1618 | given by the terminal post_div->bitvalue */ | |
1619 | if ( !post_div->divider ) { | |
1620 | post_div = &post_divs[post_div->bitvalue]; | |
1621 | pll_output_freq = post_div->divider * freq; | |
1622 | } | |
bc3bf466 | 1623 | pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", |
1da177e4 LT |
1624 | rinfo->pll.ref_div, rinfo->pll.ref_clk, |
1625 | pll_output_freq); | |
1626 | ||
1627 | fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, | |
1628 | rinfo->pll.ref_clk); | |
1629 | regs->ppll_ref_div = rinfo->pll.ref_div; | |
1630 | regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); | |
1631 | ||
bc3bf466 JD |
1632 | pr_debug("post div = 0x%x\n", post_div->bitvalue); |
1633 | pr_debug("fb_div = 0x%x\n", fb_div); | |
1634 | pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); | |
1da177e4 LT |
1635 | } |
1636 | ||
1637 | static int radeonfb_set_par(struct fb_info *info) | |
1638 | { | |
1639 | struct radeonfb_info *rinfo = info->par; | |
1640 | struct fb_var_screeninfo *mode = &info->var; | |
1641 | struct radeon_regs *newmode; | |
1642 | int hTotal, vTotal, hSyncStart, hSyncEnd, | |
66cc77ed | 1643 | vSyncStart, vSyncEnd; |
1da177e4 LT |
1644 | u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; |
1645 | u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; | |
1646 | u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock; | |
1647 | int i, freq; | |
1648 | int format = 0; | |
1649 | int nopllcalc = 0; | |
97e5ea1d | 1650 | int hsync_start, hsync_fudge, hsync_wid, vsync_wid; |
1da177e4 LT |
1651 | int primary_mon = PRIMARY_MONITOR(rinfo); |
1652 | int depth = var_to_depth(mode); | |
1653 | int use_rmx = 0; | |
1654 | ||
1655 | newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL); | |
1656 | if (!newmode) | |
1657 | return -ENOMEM; | |
1658 | ||
1659 | /* We always want engine to be idle on a mode switch, even | |
1660 | * if we won't actually change the mode | |
1661 | */ | |
6c34bc29 | 1662 | radeon_engine_idle(); |
1da177e4 LT |
1663 | |
1664 | hSyncStart = mode->xres + mode->right_margin; | |
1665 | hSyncEnd = hSyncStart + mode->hsync_len; | |
1666 | hTotal = hSyncEnd + mode->left_margin; | |
1667 | ||
1668 | vSyncStart = mode->yres + mode->lower_margin; | |
1669 | vSyncEnd = vSyncStart + mode->vsync_len; | |
1670 | vTotal = vSyncEnd + mode->upper_margin; | |
1671 | pixClock = mode->pixclock; | |
1672 | ||
1673 | sync = mode->sync; | |
1674 | h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; | |
1675 | v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; | |
1676 | ||
1677 | if (primary_mon == MT_DFP || primary_mon == MT_LCD) { | |
1678 | if (rinfo->panel_info.xres < mode->xres) | |
1679 | mode->xres = rinfo->panel_info.xres; | |
1680 | if (rinfo->panel_info.yres < mode->yres) | |
1681 | mode->yres = rinfo->panel_info.yres; | |
1682 | ||
1683 | hTotal = mode->xres + rinfo->panel_info.hblank; | |
1684 | hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; | |
1685 | hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; | |
1686 | ||
1687 | vTotal = mode->yres + rinfo->panel_info.vblank; | |
1688 | vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; | |
1689 | vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; | |
1690 | ||
1691 | h_sync_pol = !rinfo->panel_info.hAct_high; | |
1692 | v_sync_pol = !rinfo->panel_info.vAct_high; | |
1693 | ||
1694 | pixClock = 100000000 / rinfo->panel_info.clock; | |
1695 | ||
1696 | if (rinfo->panel_info.use_bios_dividers) { | |
1697 | nopllcalc = 1; | |
1698 | newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | | |
1699 | (rinfo->panel_info.post_divider << 16); | |
1700 | newmode->ppll_ref_div = rinfo->panel_info.ref_divider; | |
1701 | } | |
1702 | } | |
1703 | dotClock = 1000000000 / pixClock; | |
1704 | freq = dotClock / 10; /* x100 */ | |
1705 | ||
bc3bf466 | 1706 | pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n", |
1da177e4 | 1707 | hSyncStart, hSyncEnd, hTotal); |
bc3bf466 | 1708 | pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n", |
1da177e4 LT |
1709 | vSyncStart, vSyncEnd, vTotal); |
1710 | ||
1711 | hsync_wid = (hSyncEnd - hSyncStart) / 8; | |
1712 | vsync_wid = vSyncEnd - vSyncStart; | |
1713 | if (hsync_wid == 0) | |
1714 | hsync_wid = 1; | |
1715 | else if (hsync_wid > 0x3f) /* max */ | |
1716 | hsync_wid = 0x3f; | |
1717 | ||
1718 | if (vsync_wid == 0) | |
1719 | vsync_wid = 1; | |
1720 | else if (vsync_wid > 0x1f) /* max */ | |
1721 | vsync_wid = 0x1f; | |
1722 | ||
1da177e4 | 1723 | format = radeon_get_dstbpp(depth); |
1da177e4 LT |
1724 | |
1725 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) | |
1726 | hsync_fudge = hsync_fudge_fp[format-1]; | |
1727 | else | |
1728 | hsync_fudge = hsync_adj_tab[format-1]; | |
1729 | ||
1730 | hsync_start = hSyncStart - 8 + hsync_fudge; | |
1731 | ||
1732 | newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | | |
1733 | (format << 8); | |
1734 | ||
1735 | /* Clear auto-center etc... */ | |
1736 | newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; | |
1737 | newmode->crtc_more_cntl &= 0xfffffff0; | |
1738 | ||
1739 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
1740 | newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; | |
1741 | if (mirror) | |
1742 | newmode->crtc_ext_cntl |= CRTC_CRT_ON; | |
1743 | ||
1744 | newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | | |
1745 | CRTC_INTERLACE_EN); | |
1746 | } else { | |
1747 | newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | | |
1748 | CRTC_CRT_ON; | |
1749 | } | |
1750 | ||
1751 | newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | | |
1752 | DAC_8BIT_EN; | |
1753 | ||
1754 | newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | | |
1755 | (((mode->xres / 8) - 1) << 16)); | |
1756 | ||
1757 | newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | | |
1758 | (hsync_wid << 16) | (h_sync_pol << 23)); | |
1759 | ||
1760 | newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | | |
1761 | ((mode->yres - 1) << 16); | |
1762 | ||
1763 | newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | | |
1764 | (vsync_wid << 16) | (v_sync_pol << 23)); | |
1765 | ||
1766 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
1767 | /* We first calculate the engine pitch */ | |
1768 | rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) | |
1769 | & ~(0x3f)) >> 6; | |
1770 | ||
1771 | /* Then, re-multiply it to get the CRTC pitch */ | |
1772 | newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); | |
1773 | } else | |
1774 | newmode->crtc_pitch = (mode->xres_virtual >> 3); | |
1775 | ||
1776 | newmode->crtc_pitch |= (newmode->crtc_pitch << 16); | |
1777 | ||
1778 | /* | |
1779 | * It looks like recent chips have a problem with SURFACE_CNTL, | |
1780 | * setting SURF_TRANSLATION_DIS completely disables the | |
1781 | * swapper as well, so we leave it unset now. | |
1782 | */ | |
1783 | newmode->surface_cntl = 0; | |
1784 | ||
1785 | #if defined(__BIG_ENDIAN) | |
1786 | ||
1787 | /* Setup swapping on both apertures, though we currently | |
1788 | * only use aperture 0, enabling swapper on aperture 1 | |
1789 | * won't harm | |
1790 | */ | |
1791 | switch (mode->bits_per_pixel) { | |
1792 | case 16: | |
1793 | newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; | |
1794 | newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; | |
1795 | break; | |
1796 | case 24: | |
1797 | case 32: | |
1798 | newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; | |
1799 | newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; | |
1800 | break; | |
1801 | } | |
1802 | #endif | |
1803 | ||
1804 | /* Clear surface registers */ | |
1805 | for (i=0; i<8; i++) { | |
1806 | newmode->surf_lower_bound[i] = 0; | |
1807 | newmode->surf_upper_bound[i] = 0x1f; | |
1808 | newmode->surf_info[i] = 0; | |
1809 | } | |
1810 | ||
bc3bf466 | 1811 | pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n", |
1da177e4 | 1812 | newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); |
bc3bf466 | 1813 | pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n", |
1da177e4 LT |
1814 | newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); |
1815 | ||
1816 | rinfo->bpp = mode->bits_per_pixel; | |
1817 | rinfo->depth = depth; | |
1818 | ||
bc3bf466 JD |
1819 | pr_debug("pixclock = %lu\n", (unsigned long)pixClock); |
1820 | pr_debug("freq = %lu\n", (unsigned long)freq); | |
1da177e4 LT |
1821 | |
1822 | /* We use PPLL_DIV_3 */ | |
1823 | newmode->clk_cntl_index = 0x300; | |
1824 | ||
1825 | /* Calculate PPLL value if necessary */ | |
1826 | if (!nopllcalc) | |
1827 | radeon_calc_pll_regs(rinfo, newmode, freq); | |
1828 | ||
1829 | newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; | |
1830 | ||
1831 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
1832 | unsigned int hRatio, vRatio; | |
1833 | ||
1834 | if (mode->xres > rinfo->panel_info.xres) | |
1835 | mode->xres = rinfo->panel_info.xres; | |
1836 | if (mode->yres > rinfo->panel_info.yres) | |
1837 | mode->yres = rinfo->panel_info.yres; | |
1838 | ||
1839 | newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) | |
1840 | << HORZ_PANEL_SHIFT); | |
1841 | newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) | |
1842 | << VERT_PANEL_SHIFT); | |
1843 | ||
1844 | if (mode->xres != rinfo->panel_info.xres) { | |
1845 | hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, | |
1846 | rinfo->panel_info.xres); | |
1847 | newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | | |
1848 | (newmode->fp_horz_stretch & | |
1849 | (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | | |
1850 | HORZ_AUTO_RATIO_INC))); | |
1851 | newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | | |
1852 | HORZ_STRETCH_ENABLE); | |
1853 | use_rmx = 1; | |
1854 | } | |
1855 | newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; | |
1856 | ||
1857 | if (mode->yres != rinfo->panel_info.yres) { | |
1858 | vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, | |
1859 | rinfo->panel_info.yres); | |
1860 | newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | | |
1861 | (newmode->fp_vert_stretch & | |
1862 | (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); | |
1863 | newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | | |
1864 | VERT_STRETCH_ENABLE); | |
1865 | use_rmx = 1; | |
1866 | } | |
1867 | newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; | |
1868 | ||
1869 | newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) | |
1870 | ~(FP_SEL_CRTC2 | | |
1871 | FP_RMX_HVSYNC_CONTROL_EN | | |
1872 | FP_DFP_SYNC_SEL | | |
1873 | FP_CRT_SYNC_SEL | | |
1874 | FP_CRTC_LOCK_8DOT | | |
1875 | FP_USE_SHADOW_EN | | |
1876 | FP_CRTC_USE_SHADOW_VEND | | |
1877 | FP_CRT_SYNC_ALT)); | |
1878 | ||
1879 | newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | | |
1880 | FP_CRTC_DONT_SHADOW_HEND | | |
1881 | FP_PANEL_FORMAT); | |
1882 | ||
1883 | if (IS_R300_VARIANT(rinfo) || | |
1884 | (rinfo->family == CHIP_FAMILY_R200)) { | |
1885 | newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; | |
1886 | if (use_rmx) | |
1887 | newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; | |
1888 | else | |
1889 | newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; | |
1890 | } else | |
1891 | newmode->fp_gen_cntl |= FP_SEL_CRTC1; | |
1892 | ||
1893 | newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; | |
1894 | newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; | |
1895 | newmode->tmds_crc = rinfo->init_state.tmds_crc; | |
1896 | newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; | |
1897 | ||
1898 | if (primary_mon == MT_LCD) { | |
1899 | newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); | |
1900 | newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); | |
1901 | } else { | |
1902 | /* DFP */ | |
1903 | newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); | |
1904 | newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); | |
1905 | /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ | |
1906 | if (IS_R300_VARIANT(rinfo) || | |
1907 | (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) | |
1908 | newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; | |
1909 | else | |
1910 | newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; | |
1911 | newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; | |
1912 | } | |
1913 | ||
1914 | newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | | |
1915 | (((mode->xres / 8) - 1) << 16)); | |
1916 | newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | | |
1917 | ((mode->yres - 1) << 16); | |
1918 | newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | | |
1919 | (hsync_wid << 16) | (h_sync_pol << 23)); | |
1920 | newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | | |
1921 | (vsync_wid << 16) | (v_sync_pol << 23)); | |
1922 | } | |
1923 | ||
1924 | /* do it! */ | |
1925 | if (!rinfo->asleep) { | |
1926 | memcpy(&rinfo->state, newmode, sizeof(*newmode)); | |
1927 | radeon_write_mode (rinfo, newmode, 0); | |
1928 | /* (re)initialize the engine */ | |
1929 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1930 | radeonfb_engine_init (rinfo); | |
1931 | } | |
1932 | /* Update fix */ | |
1933 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1934 | info->fix.line_length = rinfo->pitch*64; | |
1935 | else | |
1936 | info->fix.line_length = mode->xres_virtual | |
1937 | * ((mode->bits_per_pixel + 1) / 8); | |
1938 | info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR | |
1939 | : FB_VISUAL_DIRECTCOLOR; | |
1940 | ||
1941 | #ifdef CONFIG_BOOTX_TEXT | |
1942 | /* Update debug text engine */ | |
1943 | btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, | |
1944 | rinfo->depth, info->fix.line_length); | |
1945 | #endif | |
1946 | ||
1947 | kfree(newmode); | |
1948 | return 0; | |
1949 | } | |
1950 | ||
6c34bc29 | 1951 | |
8a48ac33 | 1952 | static const struct fb_ops radeonfb_ops = { |
1da177e4 LT |
1953 | .owner = THIS_MODULE, |
1954 | .fb_check_var = radeonfb_check_var, | |
1955 | .fb_set_par = radeonfb_set_par, | |
1956 | .fb_setcolreg = radeonfb_setcolreg, | |
71494376 | 1957 | .fb_setcmap = radeonfb_setcmap, |
1da177e4 LT |
1958 | .fb_pan_display = radeonfb_pan_display, |
1959 | .fb_blank = radeonfb_blank, | |
1960 | .fb_ioctl = radeonfb_ioctl, | |
1961 | .fb_sync = radeonfb_sync, | |
1962 | .fb_fillrect = radeonfb_fillrect, | |
1963 | .fb_copyarea = radeonfb_copyarea, | |
1964 | .fb_imageblit = radeonfb_imageblit, | |
1da177e4 LT |
1965 | }; |
1966 | ||
1967 | ||
48c68c4f | 1968 | static int radeon_set_fbinfo(struct radeonfb_info *rinfo) |
1da177e4 LT |
1969 | { |
1970 | struct fb_info *info = rinfo->info; | |
1971 | ||
1972 | info->par = rinfo; | |
1973 | info->pseudo_palette = rinfo->pseudo_palette; | |
1974 | info->flags = FBINFO_DEFAULT | |
1975 | | FBINFO_HWACCEL_COPYAREA | |
1976 | | FBINFO_HWACCEL_FILLRECT | |
1977 | | FBINFO_HWACCEL_XPAN | |
1978 | | FBINFO_HWACCEL_YPAN; | |
1979 | info->fbops = &radeonfb_ops; | |
1980 | info->screen_base = rinfo->fb_base; | |
1981 | info->screen_size = rinfo->mapped_vram; | |
1982 | /* Fill fix common fields */ | |
1983 | strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); | |
1984 | info->fix.smem_start = rinfo->fb_base_phys; | |
1985 | info->fix.smem_len = rinfo->video_ram; | |
1986 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
1987 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
1988 | info->fix.xpanstep = 8; | |
1989 | info->fix.ypanstep = 1; | |
1990 | info->fix.ywrapstep = 0; | |
1991 | info->fix.type_aux = 0; | |
1992 | info->fix.mmio_start = rinfo->mmio_base_phys; | |
1993 | info->fix.mmio_len = RADEON_REGSIZE; | |
1994 | info->fix.accel = FB_ACCEL_ATI_RADEON; | |
1995 | ||
1996 | fb_alloc_cmap(&info->cmap, 256, 0); | |
1997 | ||
1998 | if (noaccel) | |
1999 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
2000 | ||
2001 | return 0; | |
2002 | } | |
2003 | ||
1da177e4 LT |
2004 | /* |
2005 | * This reconfigure the card's internal memory map. In theory, we'd like | |
2006 | * to setup the card's memory at the same address as it's PCI bus address, | |
2007 | * and the AGP aperture right after that so that system RAM on 32 bits | |
2008 | * machines at least, is directly accessible. However, doing so would | |
2009 | * conflict with the current XFree drivers... | |
2010 | * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree | |
2011 | * on the proper way to set this up and duplicate this here. In the meantime, | |
2012 | * I put the card's memory at 0 in card space and AGP at some random high | |
2013 | * local (0xe0000000 for now) that will be changed by XFree/DRI anyway | |
2014 | */ | |
758ddd1d | 2015 | #ifdef CONFIG_PPC |
1da177e4 LT |
2016 | #undef SET_MC_FB_FROM_APERTURE |
2017 | static void fixup_memory_mappings(struct radeonfb_info *rinfo) | |
2018 | { | |
2019 | u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; | |
2020 | u32 save_crtc_ext_cntl; | |
2021 | u32 aper_base, aper_size; | |
2022 | u32 agp_base; | |
2023 | ||
2024 | /* First, we disable display to avoid interfering */ | |
2025 | if (rinfo->has_CRTC2) { | |
2026 | save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); | |
2027 | OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); | |
2028 | } | |
2029 | save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); | |
2030 | save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); | |
2031 | ||
2032 | OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); | |
2033 | OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); | |
2034 | mdelay(100); | |
2035 | ||
fe86175b RD |
2036 | aper_base = INREG(CNFG_APER_0_BASE); |
2037 | aper_size = INREG(CNFG_APER_SIZE); | |
1da177e4 LT |
2038 | |
2039 | #ifdef SET_MC_FB_FROM_APERTURE | |
2040 | /* Set framebuffer to be at the same address as set in PCI BAR */ | |
2041 | OUTREG(MC_FB_LOCATION, | |
2042 | ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); | |
2043 | rinfo->fb_local_base = aper_base; | |
2044 | #else | |
2045 | OUTREG(MC_FB_LOCATION, 0x7fff0000); | |
2046 | rinfo->fb_local_base = 0; | |
2047 | #endif | |
2048 | agp_base = aper_base + aper_size; | |
2049 | if (agp_base & 0xf0000000) | |
2050 | agp_base = (aper_base | 0x0fffffff) + 1; | |
2051 | ||
2052 | /* Set AGP to be just after the framebuffer on a 256Mb boundary. This | |
2053 | * assumes the FB isn't mapped to 0xf0000000 or above, but this is | |
2054 | * always the case on PPCs afaik. | |
2055 | */ | |
2056 | #ifdef SET_MC_FB_FROM_APERTURE | |
2057 | OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); | |
2058 | #else | |
2059 | OUTREG(MC_AGP_LOCATION, 0xffffe000); | |
2060 | #endif | |
2061 | ||
2062 | /* Fixup the display base addresses & engine offsets while we | |
2063 | * are at it as well | |
2064 | */ | |
2065 | #ifdef SET_MC_FB_FROM_APERTURE | |
2066 | OUTREG(DISPLAY_BASE_ADDR, aper_base); | |
2067 | if (rinfo->has_CRTC2) | |
2068 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); | |
2069 | OUTREG(OV0_BASE_ADDR, aper_base); | |
2070 | #else | |
2071 | OUTREG(DISPLAY_BASE_ADDR, 0); | |
2072 | if (rinfo->has_CRTC2) | |
2073 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); | |
2074 | OUTREG(OV0_BASE_ADDR, 0); | |
2075 | #endif | |
2076 | mdelay(100); | |
2077 | ||
2078 | /* Restore display settings */ | |
2079 | OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); | |
2080 | OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); | |
2081 | if (rinfo->has_CRTC2) | |
2082 | OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); | |
2083 | ||
bc3bf466 | 2084 | pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", |
1da177e4 LT |
2085 | aper_base, |
2086 | ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), | |
2087 | 0xffff0000 | (agp_base >> 16)); | |
2088 | } | |
758ddd1d | 2089 | #endif /* CONFIG_PPC */ |
1da177e4 LT |
2090 | |
2091 | ||
2092 | static void radeon_identify_vram(struct radeonfb_info *rinfo) | |
2093 | { | |
2094 | u32 tmp; | |
2095 | ||
2096 | /* framebuffer size */ | |
2097 | if ((rinfo->family == CHIP_FAMILY_RS100) || | |
2098 | (rinfo->family == CHIP_FAMILY_RS200) || | |
dd144713 | 2099 | (rinfo->family == CHIP_FAMILY_RS300) || |
0b693eaf | 2100 | (rinfo->family == CHIP_FAMILY_RC410) || |
a6c0c37d | 2101 | (rinfo->family == CHIP_FAMILY_RS400) || |
dd144713 | 2102 | (rinfo->family == CHIP_FAMILY_RS480) ) { |
1da177e4 LT |
2103 | u32 tom = INREG(NB_TOM); |
2104 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); | |
2105 | ||
6c34bc29 | 2106 | radeon_fifo_wait(6); |
1da177e4 LT |
2107 | OUTREG(MC_FB_LOCATION, tom); |
2108 | OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | |
2109 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | |
2110 | OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); | |
2111 | ||
2112 | /* This is supposed to fix the crtc2 noise problem. */ | |
2113 | OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); | |
2114 | ||
2115 | if ((rinfo->family == CHIP_FAMILY_RS100) || | |
2116 | (rinfo->family == CHIP_FAMILY_RS200)) { | |
2117 | /* This is to workaround the asic bug for RMX, some versions | |
ff0c2642 | 2118 | of BIOS doesn't have this register initialized correctly. |
1da177e4 LT |
2119 | */ |
2120 | OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, | |
2121 | ~CRTC_H_CUTOFF_ACTIVE_EN); | |
2122 | } | |
2123 | } else { | |
fe86175b | 2124 | tmp = INREG(CNFG_MEMSIZE); |
1da177e4 LT |
2125 | } |
2126 | ||
2127 | /* mem size is bits [28:0], mask off the rest */ | |
fe86175b | 2128 | rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; |
1da177e4 LT |
2129 | |
2130 | /* | |
2131 | * Hack to get around some busted production M6's | |
2132 | * reporting no ram | |
2133 | */ | |
2134 | if (rinfo->video_ram == 0) { | |
2135 | switch (rinfo->pdev->device) { | |
2136 | case PCI_CHIP_RADEON_LY: | |
2137 | case PCI_CHIP_RADEON_LZ: | |
2138 | rinfo->video_ram = 8192 * 1024; | |
2139 | break; | |
2140 | default: | |
2141 | break; | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | ||
2146 | /* | |
2147 | * Now try to identify VRAM type | |
2148 | */ | |
2149 | if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || | |
2150 | (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) | |
2151 | rinfo->vram_ddr = 1; | |
2152 | else | |
2153 | rinfo->vram_ddr = 0; | |
2154 | ||
2155 | tmp = INREG(MEM_CNTL); | |
2156 | if (IS_R300_VARIANT(rinfo)) { | |
2157 | tmp &= R300_MEM_NUM_CHANNELS_MASK; | |
2158 | switch (tmp) { | |
2159 | case 0: rinfo->vram_width = 64; break; | |
2160 | case 1: rinfo->vram_width = 128; break; | |
2161 | case 2: rinfo->vram_width = 256; break; | |
2162 | default: rinfo->vram_width = 128; break; | |
2163 | } | |
2164 | } else if ((rinfo->family == CHIP_FAMILY_RV100) || | |
2165 | (rinfo->family == CHIP_FAMILY_RS100) || | |
2166 | (rinfo->family == CHIP_FAMILY_RS200)){ | |
2167 | if (tmp & RV100_MEM_HALF_MODE) | |
2168 | rinfo->vram_width = 32; | |
2169 | else | |
2170 | rinfo->vram_width = 64; | |
2171 | } else { | |
2172 | if (tmp & MEM_NUM_CHANNELS_MASK) | |
2173 | rinfo->vram_width = 128; | |
2174 | else | |
2175 | rinfo->vram_width = 64; | |
2176 | } | |
2177 | ||
2178 | /* This may not be correct, as some cards can have half of channel disabled | |
2179 | * ToDo: identify these cases | |
2180 | */ | |
2181 | ||
bc3bf466 | 2182 | pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n", |
1da177e4 LT |
2183 | pci_name(rinfo->pdev), |
2184 | rinfo->video_ram / 1024, | |
2185 | rinfo->vram_ddr ? "DDR" : "SDRAM", | |
2186 | rinfo->vram_width); | |
2187 | } | |
2188 | ||
2189 | /* | |
2190 | * Sysfs | |
2191 | */ | |
2192 | ||
2193 | static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) | |
2194 | { | |
a882ef47 | 2195 | return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH); |
1da177e4 LT |
2196 | } |
2197 | ||
2198 | ||
2c3c8bea | 2199 | static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj, |
91a69029 ZR |
2200 | struct bin_attribute *bin_attr, |
2201 | char *buf, loff_t off, size_t count) | |
1da177e4 LT |
2202 | { |
2203 | struct device *dev = container_of(kobj, struct device, kobj); | |
af70a486 | 2204 | struct fb_info *info = dev_get_drvdata(dev); |
1da177e4 LT |
2205 | struct radeonfb_info *rinfo = info->par; |
2206 | ||
2207 | return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); | |
2208 | } | |
2209 | ||
2210 | ||
2c3c8bea | 2211 | static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj, |
91a69029 ZR |
2212 | struct bin_attribute *bin_attr, |
2213 | char *buf, loff_t off, size_t count) | |
1da177e4 LT |
2214 | { |
2215 | struct device *dev = container_of(kobj, struct device, kobj); | |
af70a486 | 2216 | struct fb_info *info = dev_get_drvdata(dev); |
1da177e4 LT |
2217 | struct radeonfb_info *rinfo = info->par; |
2218 | ||
2219 | return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); | |
2220 | } | |
2221 | ||
598b2eed | 2222 | static const struct bin_attribute edid1_attr = { |
1da177e4 LT |
2223 | .attr = { |
2224 | .name = "edid1", | |
1da177e4 LT |
2225 | .mode = 0444, |
2226 | }, | |
2227 | .size = EDID_LENGTH, | |
2228 | .read = radeon_show_edid1, | |
2229 | }; | |
2230 | ||
598b2eed | 2231 | static const struct bin_attribute edid2_attr = { |
1da177e4 LT |
2232 | .attr = { |
2233 | .name = "edid2", | |
1da177e4 LT |
2234 | .mode = 0444, |
2235 | }, | |
2236 | .size = EDID_LENGTH, | |
2237 | .read = radeon_show_edid2, | |
2238 | }; | |
2239 | ||
069ee21a MM |
2240 | static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
2241 | { | |
2242 | struct apertures_struct *ap; | |
2243 | ||
2244 | ap = alloc_apertures(1); | |
2245 | if (!ap) | |
2246 | return -ENOMEM; | |
2247 | ||
2248 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
2249 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
2250 | ||
2251 | remove_conflicting_framebuffers(ap, KBUILD_MODNAME, false); | |
2252 | ||
2253 | kfree(ap); | |
2254 | ||
2255 | return 0; | |
2256 | } | |
1da177e4 | 2257 | |
48c68c4f GKH |
2258 | static int radeonfb_pci_register(struct pci_dev *pdev, |
2259 | const struct pci_device_id *ent) | |
1da177e4 LT |
2260 | { |
2261 | struct fb_info *info; | |
2262 | struct radeonfb_info *rinfo; | |
2263 | int ret; | |
e7a18c9c | 2264 | unsigned char c1, c2; |
fcea8030 | 2265 | int err = 0; |
1da177e4 | 2266 | |
bc3bf466 | 2267 | pr_debug("radeonfb_pci_register BEGIN\n"); |
1da177e4 LT |
2268 | |
2269 | /* Enable device in PCI config */ | |
2270 | ret = pci_enable_device(pdev); | |
2271 | if (ret < 0) { | |
2272 | printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n", | |
2273 | pci_name(pdev)); | |
2274 | goto err_out; | |
2275 | } | |
2276 | ||
2277 | info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); | |
2278 | if (!info) { | |
1da177e4 LT |
2279 | ret = -ENOMEM; |
2280 | goto err_disable; | |
2281 | } | |
2282 | rinfo = info->par; | |
2283 | rinfo->info = info; | |
2284 | rinfo->pdev = pdev; | |
2285 | ||
2286 | spin_lock_init(&rinfo->reg_lock); | |
6c789357 | 2287 | timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0); |
1da177e4 | 2288 | |
e7a18c9c AH |
2289 | c1 = ent->device >> 8; |
2290 | c2 = ent->device & 0xff; | |
2291 | if (isprint(c1) && isprint(c2)) | |
2292 | snprintf(rinfo->name, sizeof(rinfo->name), | |
2293 | "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); | |
2294 | else | |
2295 | snprintf(rinfo->name, sizeof(rinfo->name), | |
2296 | "ATI Radeon %x", ent->device & 0xffff); | |
2297 | ||
1da177e4 LT |
2298 | rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; |
2299 | rinfo->chipset = pdev->device; | |
2300 | rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; | |
2301 | rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; | |
2302 | rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; | |
2303 | ||
2304 | /* Set base addrs */ | |
2305 | rinfo->fb_base_phys = pci_resource_start (pdev, 0); | |
2306 | rinfo->mmio_base_phys = pci_resource_start (pdev, 2); | |
2307 | ||
069ee21a MM |
2308 | ret = radeon_kick_out_firmware_fb(pdev); |
2309 | if (ret) | |
fe6c6a4a | 2310 | goto err_release_fb; |
069ee21a | 2311 | |
1da177e4 | 2312 | /* request the mem regions */ |
5251bffc | 2313 | ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); |
1da177e4 | 2314 | if (ret < 0) { |
5251bffc DB |
2315 | printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n", |
2316 | pci_name(rinfo->pdev)); | |
1da177e4 LT |
2317 | goto err_release_fb; |
2318 | } | |
2319 | ||
5251bffc DB |
2320 | ret = pci_request_region(pdev, 2, "radeonfb mmio"); |
2321 | if (ret < 0) { | |
2322 | printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n", | |
2323 | pci_name(rinfo->pdev)); | |
2324 | goto err_release_pci0; | |
2325 | } | |
2326 | ||
1da177e4 LT |
2327 | /* map the regions */ |
2328 | rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); | |
2329 | if (!rinfo->mmio_base) { | |
5251bffc DB |
2330 | printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", |
2331 | pci_name(rinfo->pdev)); | |
1da177e4 | 2332 | ret = -EIO; |
5251bffc | 2333 | goto err_release_pci2; |
1da177e4 LT |
2334 | } |
2335 | ||
2336 | rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; | |
2337 | ||
2338 | /* | |
2339 | * Check for errata | |
2340 | */ | |
2341 | rinfo->errata = 0; | |
2342 | if (rinfo->family == CHIP_FAMILY_R300 && | |
fe86175b | 2343 | (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) |
1da177e4 LT |
2344 | == CFG_ATI_REV_A11) |
2345 | rinfo->errata |= CHIP_ERRATA_R300_CG; | |
2346 | ||
2347 | if (rinfo->family == CHIP_FAMILY_RV200 || | |
2348 | rinfo->family == CHIP_FAMILY_RS200) | |
2349 | rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
2350 | ||
2351 | if (rinfo->family == CHIP_FAMILY_RV100 || | |
2352 | rinfo->family == CHIP_FAMILY_RS100 || | |
2353 | rinfo->family == CHIP_FAMILY_RS200) | |
2354 | rinfo->errata |= CHIP_ERRATA_PLL_DELAY; | |
2355 | ||
758ddd1d | 2356 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 LT |
2357 | /* On PPC, we obtain the OF device-node pointer to the firmware |
2358 | * data for this chip | |
2359 | */ | |
2360 | rinfo->of_node = pci_device_to_OF_node(pdev); | |
2361 | if (rinfo->of_node == NULL) | |
2362 | printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n", | |
2363 | pci_name(rinfo->pdev)); | |
2364 | ||
758ddd1d KH |
2365 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
2366 | #ifdef CONFIG_PPC | |
1da177e4 LT |
2367 | /* On PPC, the firmware sets up a memory mapping that tends |
2368 | * to cause lockups when enabling the engine. We reconfigure | |
2369 | * the card internal memory mappings properly | |
2370 | */ | |
2371 | fixup_memory_mappings(rinfo); | |
758ddd1d | 2372 | #endif /* CONFIG_PPC */ |
1da177e4 LT |
2373 | |
2374 | /* Get VRAM size and type */ | |
2375 | radeon_identify_vram(rinfo); | |
2376 | ||
2377 | rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); | |
2378 | ||
2379 | do { | |
5e200b53 LR |
2380 | rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, |
2381 | rinfo->mapped_vram); | |
5e2daeb3 HH |
2382 | } while (rinfo->fb_base == NULL && |
2383 | ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); | |
1da177e4 | 2384 | |
8d5f7b43 BH |
2385 | if (rinfo->fb_base == NULL) { |
2386 | printk (KERN_ERR "radeonfb (%s): cannot map FB\n", | |
2387 | pci_name(rinfo->pdev)); | |
1da177e4 LT |
2388 | ret = -EIO; |
2389 | goto err_unmap_rom; | |
2390 | } | |
2391 | ||
bc3bf466 | 2392 | pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), |
1da177e4 LT |
2393 | rinfo->mapped_vram/1024); |
2394 | ||
2395 | /* | |
4a4efbde | 2396 | * Map the BIOS ROM if any and retrieve PLL parameters from |
1da177e4 LT |
2397 | * the BIOS. We skip that on mobility chips as the real panel |
2398 | * values we need aren't in the ROM but in the BIOS image in | |
2399 | * memory. This is definitely not the best meacnism though, | |
2400 | * we really need the arch code to tell us which is the "primary" | |
2401 | * video adapter to use the memory image (or better, the arch | |
2402 | * should provide us a copy of the BIOS image to shield us from | |
2403 | * archs who would store that elsewhere and/or could initialize | |
2404 | * more than one adapter during boot). | |
2405 | */ | |
2406 | if (!rinfo->is_mobility) | |
2407 | radeon_map_ROM(rinfo, pdev); | |
2408 | ||
2409 | /* | |
2410 | * On x86, the primary display on laptop may have it's BIOS | |
2411 | * ROM elsewhere, try to locate it at the legacy memory hole. | |
2412 | * We probably need to make sure this is the primary display, | |
2413 | * but that is difficult without some arch support. | |
2414 | */ | |
2415 | #ifdef CONFIG_X86 | |
2416 | if (rinfo->bios_seg == NULL) | |
2417 | radeon_find_mem_vbios(rinfo); | |
2418 | #endif | |
2419 | ||
2420 | /* If both above failed, try the BIOS ROM again for mobility | |
2421 | * chips | |
2422 | */ | |
2423 | if (rinfo->bios_seg == NULL && rinfo->is_mobility) | |
2424 | radeon_map_ROM(rinfo, pdev); | |
2425 | ||
2426 | /* Get informations about the board's PLL */ | |
2427 | radeon_get_pllinfo(rinfo); | |
2428 | ||
2429 | #ifdef CONFIG_FB_RADEON_I2C | |
2430 | /* Register I2C bus */ | |
2431 | radeon_create_i2c_busses(rinfo); | |
2432 | #endif | |
2433 | ||
2434 | /* set all the vital stuff */ | |
2435 | radeon_set_fbinfo (rinfo); | |
2436 | ||
2437 | /* Probe screen types */ | |
2438 | radeon_probe_screens(rinfo, monitor_layout, ignore_edid); | |
2439 | ||
2440 | /* Build mode list, check out panel native model */ | |
2441 | radeon_check_modes(rinfo, mode_option); | |
2442 | ||
2443 | /* Register some sysfs stuff (should be done better) */ | |
2444 | if (rinfo->mon1_EDID) | |
fcea8030 TB |
2445 | err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, |
2446 | &edid1_attr); | |
1da177e4 | 2447 | if (rinfo->mon2_EDID) |
fcea8030 TB |
2448 | err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, |
2449 | &edid2_attr); | |
2450 | if (err) | |
6f9655b1 JP |
2451 | pr_warn("%s() Creating sysfs files failed, continuing\n", |
2452 | __func__); | |
1da177e4 LT |
2453 | |
2454 | /* save current mode regs before we switch into the new one | |
2455 | * so we can restore this upon __exit | |
2456 | */ | |
2457 | radeon_save_state (rinfo, &rinfo->init_state); | |
2458 | memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); | |
2459 | ||
2460 | /* Setup Power Management capabilities */ | |
2461 | if (default_dynclk < -1) { | |
2462 | /* -2 is special: means ON on mobility chips and do not | |
2463 | * change on others | |
2464 | */ | |
994aad25 | 2465 | radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); |
1da177e4 | 2466 | } else |
994aad25 | 2467 | radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep); |
1da177e4 LT |
2468 | |
2469 | pci_set_drvdata(pdev, info); | |
2470 | ||
2471 | /* Register with fbdev layer */ | |
2472 | ret = register_framebuffer(info); | |
2473 | if (ret < 0) { | |
2474 | printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", | |
2475 | pci_name(rinfo->pdev)); | |
2476 | goto err_unmap_fb; | |
2477 | } | |
2478 | ||
5e200b53 LR |
2479 | if (!nomtrr) |
2480 | rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, | |
2481 | rinfo->video_ram); | |
1da177e4 | 2482 | |
202d4e60 RP |
2483 | if (backlight) |
2484 | radeonfb_bl_init(rinfo); | |
1da177e4 LT |
2485 | |
2486 | printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); | |
2487 | ||
2488 | if (rinfo->bios_seg) | |
2489 | radeon_unmap_ROM(rinfo, pdev); | |
bc3bf466 | 2490 | pr_debug("radeonfb_pci_register END\n"); |
1da177e4 LT |
2491 | |
2492 | return 0; | |
2493 | err_unmap_fb: | |
2494 | iounmap(rinfo->fb_base); | |
2495 | err_unmap_rom: | |
2496 | kfree(rinfo->mon1_EDID); | |
2497 | kfree(rinfo->mon2_EDID); | |
2498 | if (rinfo->mon1_modedb) | |
2499 | fb_destroy_modedb(rinfo->mon1_modedb); | |
2500 | fb_dealloc_cmap(&info->cmap); | |
2501 | #ifdef CONFIG_FB_RADEON_I2C | |
2502 | radeon_delete_i2c_busses(rinfo); | |
2503 | #endif | |
2504 | if (rinfo->bios_seg) | |
2505 | radeon_unmap_ROM(rinfo, pdev); | |
2506 | iounmap(rinfo->mmio_base); | |
5251bffc DB |
2507 | err_release_pci2: |
2508 | pci_release_region(pdev, 2); | |
2509 | err_release_pci0: | |
2510 | pci_release_region(pdev, 0); | |
1da177e4 | 2511 | err_release_fb: |
5251bffc | 2512 | framebuffer_release(info); |
1da177e4 | 2513 | err_disable: |
1da177e4 LT |
2514 | err_out: |
2515 | return ret; | |
2516 | } | |
2517 | ||
2518 | ||
2519 | ||
48c68c4f | 2520 | static void radeonfb_pci_unregister(struct pci_dev *pdev) |
1da177e4 LT |
2521 | { |
2522 | struct fb_info *info = pci_get_drvdata(pdev); | |
2523 | struct radeonfb_info *rinfo = info->par; | |
2524 | ||
2525 | if (!rinfo) | |
2526 | return; | |
5474c120 | 2527 | |
1da177e4 LT |
2528 | radeonfb_pm_exit(rinfo); |
2529 | ||
3ca34fcb JS |
2530 | if (rinfo->mon1_EDID) |
2531 | sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); | |
2532 | if (rinfo->mon2_EDID) | |
2533 | sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); | |
2534 | ||
1da177e4 | 2535 | del_timer_sync(&rinfo->lvds_timer); |
5e200b53 | 2536 | arch_phys_wc_del(rinfo->wc_cookie); |
1da177e4 LT |
2537 | unregister_framebuffer(info); |
2538 | ||
37ce69a5 RP |
2539 | radeonfb_bl_exit(rinfo); |
2540 | ||
1da177e4 LT |
2541 | iounmap(rinfo->mmio_base); |
2542 | iounmap(rinfo->fb_base); | |
2543 | ||
5251bffc DB |
2544 | pci_release_region(pdev, 2); |
2545 | pci_release_region(pdev, 0); | |
1da177e4 LT |
2546 | |
2547 | kfree(rinfo->mon1_EDID); | |
2548 | kfree(rinfo->mon2_EDID); | |
2549 | if (rinfo->mon1_modedb) | |
2550 | fb_destroy_modedb(rinfo->mon1_modedb); | |
2551 | #ifdef CONFIG_FB_RADEON_I2C | |
2552 | radeon_delete_i2c_busses(rinfo); | |
2553 | #endif | |
2554 | fb_dealloc_cmap(&info->cmap); | |
2555 | framebuffer_release(info); | |
1da177e4 LT |
2556 | } |
2557 | ||
8e0bd31d VG |
2558 | #ifdef CONFIG_PM |
2559 | #define RADEONFB_PCI_PM_OPS (&radeonfb_pci_pm_ops) | |
2560 | #else | |
2561 | #define RADEONFB_PCI_PM_OPS NULL | |
2562 | #endif | |
1da177e4 LT |
2563 | |
2564 | static struct pci_driver radeonfb_driver = { | |
2565 | .name = "radeonfb", | |
2566 | .id_table = radeonfb_pci_table, | |
2567 | .probe = radeonfb_pci_register, | |
48c68c4f | 2568 | .remove = radeonfb_pci_unregister, |
8e0bd31d | 2569 | .driver.pm = RADEONFB_PCI_PM_OPS, |
1da177e4 LT |
2570 | }; |
2571 | ||
2572 | #ifndef MODULE | |
2573 | static int __init radeonfb_setup (char *options) | |
2574 | { | |
2575 | char *this_opt; | |
2576 | ||
2577 | if (!options || !*options) | |
2578 | return 0; | |
2579 | ||
2580 | while ((this_opt = strsep (&options, ",")) != NULL) { | |
2581 | if (!*this_opt) | |
2582 | continue; | |
2583 | ||
2584 | if (!strncmp(this_opt, "noaccel", 7)) { | |
2585 | noaccel = 1; | |
2586 | } else if (!strncmp(this_opt, "mirror", 6)) { | |
2587 | mirror = 1; | |
2588 | } else if (!strncmp(this_opt, "force_dfp", 9)) { | |
2589 | force_dfp = 1; | |
2590 | } else if (!strncmp(this_opt, "panel_yres:", 11)) { | |
2591 | panel_yres = simple_strtoul((this_opt+11), NULL, 0); | |
202d4e60 RP |
2592 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
2593 | backlight = simple_strtoul(this_opt+10, NULL, 0); | |
1da177e4 LT |
2594 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
2595 | nomtrr = 1; | |
1da177e4 LT |
2596 | } else if (!strncmp(this_opt, "nomodeset", 9)) { |
2597 | nomodeset = 1; | |
2598 | } else if (!strncmp(this_opt, "force_measure_pll", 17)) { | |
2599 | force_measure_pll = 1; | |
2600 | } else if (!strncmp(this_opt, "ignore_edid", 11)) { | |
2601 | ignore_edid = 1; | |
994aad25 VB |
2602 | #if defined(CONFIG_PM) && defined(CONFIG_X86) |
2603 | } else if (!strncmp(this_opt, "force_sleep", 11)) { | |
2604 | force_sleep = 1; | |
2605 | } else if (!strncmp(this_opt, "ignore_devlist", 14)) { | |
2606 | ignore_devlist = 1; | |
2607 | #endif | |
1da177e4 LT |
2608 | } else |
2609 | mode_option = this_opt; | |
2610 | } | |
2611 | return 0; | |
2612 | } | |
2613 | #endif /* MODULE */ | |
2614 | ||
2615 | static int __init radeonfb_init (void) | |
2616 | { | |
2617 | #ifndef MODULE | |
2618 | char *option = NULL; | |
2619 | ||
2620 | if (fb_get_options("radeonfb", &option)) | |
2621 | return -ENODEV; | |
2622 | radeonfb_setup(option); | |
2623 | #endif | |
2624 | return pci_register_driver (&radeonfb_driver); | |
2625 | } | |
2626 | ||
2627 | ||
2628 | static void __exit radeonfb_exit (void) | |
2629 | { | |
2630 | pci_unregister_driver (&radeonfb_driver); | |
2631 | } | |
2632 | ||
2633 | module_init(radeonfb_init); | |
2634 | module_exit(radeonfb_exit); | |
2635 | ||
2636 | MODULE_AUTHOR("Ani Joshi"); | |
2637 | MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); | |
2638 | MODULE_LICENSE("GPL"); | |
2639 | module_param(noaccel, bool, 0); | |
2640 | module_param(default_dynclk, int, 0); | |
2641 | MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on"); | |
2642 | MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); | |
2643 | module_param(nomodeset, bool, 0); | |
2644 | MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode"); | |
2645 | module_param(mirror, bool, 0); | |
2646 | MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors"); | |
2647 | module_param(force_dfp, bool, 0); | |
2648 | MODULE_PARM_DESC(force_dfp, "bool: force display to dfp"); | |
2649 | module_param(ignore_edid, bool, 0); | |
2650 | MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe"); | |
2651 | module_param(monitor_layout, charp, 0); | |
2652 | MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); | |
2653 | module_param(force_measure_pll, bool, 0); | |
2654 | MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); | |
1da177e4 LT |
2655 | module_param(nomtrr, bool, 0); |
2656 | MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); | |
1da177e4 LT |
2657 | module_param(panel_yres, int, 0); |
2658 | MODULE_PARM_DESC(panel_yres, "int: set panel yres"); | |
2659 | module_param(mode_option, charp, 0); | |
2660 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | |
994aad25 VB |
2661 | #if defined(CONFIG_PM) && defined(CONFIG_X86) |
2662 | module_param(force_sleep, bool, 0); | |
2663 | MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware"); | |
2664 | module_param(ignore_devlist, bool, 0); | |
2665 | MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops"); | |
2666 | #endif |