[mirror_ubuntu-jammy-kernel.git] / drivers / video / fbdev / cg14.c

// SPDX-License-Identifier: GPL-2.0-only
/* cg14.c: CGFOURTEEN frame buffer driver
 *
 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
 *
 * Driver layout based loosely on tgafb.c, see that file for credits.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <linux/of_device.h>

#include <asm/io.h>
#include <asm/fbio.h>

#include "sbuslib.h"

/*
 * Local functions.
 */

static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
			 unsigned, struct fb_info *);

static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);

/*
 *  Frame buffer operations
 */

static struct fb_ops cg14_ops = {
	.owner			= THIS_MODULE,
	.fb_setcolreg		= cg14_setcolreg,
	.fb_pan_display		= cg14_pan_display,
	.fb_fillrect		= cfb_fillrect,
	.fb_copyarea		= cfb_copyarea,
	.fb_imageblit		= cfb_imageblit,
	.fb_mmap		= cg14_mmap,
	.fb_ioctl		= cg14_ioctl,
#ifdef CONFIG_COMPAT
	.fb_compat_ioctl	= sbusfb_compat_ioctl,
#endif
};

#define CG14_MCR_INTENABLE_SHIFT	7
#define CG14_MCR_INTENABLE_MASK		0x80
#define CG14_MCR_VIDENABLE_SHIFT	6
#define CG14_MCR_VIDENABLE_MASK		0x40
#define CG14_MCR_PIXMODE_SHIFT		4
#define CG14_MCR_PIXMODE_MASK		0x30
#define CG14_MCR_TMR_SHIFT		2
#define CG14_MCR_TMR_MASK		0x0c
#define CG14_MCR_TMENABLE_SHIFT		1
#define CG14_MCR_TMENABLE_MASK		0x02
#define CG14_MCR_RESET_SHIFT		0
#define CG14_MCR_RESET_MASK		0x01
#define CG14_REV_REVISION_SHIFT		4
#define CG14_REV_REVISION_MASK		0xf0
#define CG14_REV_IMPL_SHIFT		0
#define CG14_REV_IMPL_MASK		0x0f
#define CG14_VBR_FRAMEBASE_SHIFT	12
#define CG14_VBR_FRAMEBASE_MASK		0x00fff000
#define CG14_VMCR1_SETUP_SHIFT		0
#define CG14_VMCR1_SETUP_MASK		0x000001ff
#define CG14_VMCR1_VCONFIG_SHIFT	9
#define CG14_VMCR1_VCONFIG_MASK		0x00000e00
#define CG14_VMCR2_REFRESH_SHIFT	0
#define CG14_VMCR2_REFRESH_MASK		0x00000001
#define CG14_VMCR2_TESTROWCNT_SHIFT	1
#define CG14_VMCR2_TESTROWCNT_MASK	0x00000002
#define CG14_VMCR2_FBCONFIG_SHIFT	2
#define CG14_VMCR2_FBCONFIG_MASK	0x0000000c
#define CG14_VCR_REFRESHREQ_SHIFT	0
#define CG14_VCR_REFRESHREQ_MASK	0x000003ff
#define CG14_VCR1_REFRESHENA_SHIFT	10
#define CG14_VCR1_REFRESHENA_MASK	0x00000400
#define CG14_VCA_CAD_SHIFT		0
#define CG14_VCA_CAD_MASK		0x000003ff
#define CG14_VCA_VERS_SHIFT		10
#define CG14_VCA_VERS_MASK		0x00000c00
#define CG14_VCA_RAMSPEED_SHIFT		12
#define CG14_VCA_RAMSPEED_MASK		0x00001000
#define CG14_VCA_8MB_SHIFT		13
#define CG14_VCA_8MB_MASK		0x00002000

#define CG14_MCR_PIXMODE_8		0
#define CG14_MCR_PIXMODE_16		2
#define CG14_MCR_PIXMODE_32		3

struct cg14_regs{
	u8 mcr;	/* Master Control Reg */
	u8 ppr;	/* Packed Pixel Reg */
	u8 tms[2];	/* Test Mode Status Regs */
	u8 msr;	/* Master Status Reg */
	u8 fsr;	/* Fault Status Reg */
	u8 rev;	/* Revision & Impl */
	u8 ccr;	/* Clock Control Reg */
	u32 tmr;	/* Test Mode Read Back */
	u8 mod;	/* Monitor Operation Data Reg */
	u8 acr;	/* Aux Control */
	u8 xxx0[6];
	u16 hct;	/* Hor Counter */
	u16 vct;	/* Vert Counter */
	u16 hbs;	/* Hor Blank Start */
	u16 hbc;	/* Hor Blank Clear */
	u16 hss;	/* Hor Sync Start */
	u16 hsc;	/* Hor Sync Clear */
	u16 csc;	/* Composite Sync Clear */
	u16 vbs;	/* Vert Blank Start */
	u16 vbc;	/* Vert Blank Clear */
	u16 vss;	/* Vert Sync Start */
	u16 vsc;	/* Vert Sync Clear */
	u16 xcs;
	u16 xcc;
	u16 fsa;	/* Fault Status Address */
	u16 adr;	/* Address Registers */
	u8 xxx1[0xce];
	u8 pcg[0x100]; /* Pixel Clock Generator */
	u32 vbr;	/* Frame Base Row */
	u32 vmcr;	/* VBC Master Control */
	u32 vcr;	/* VBC refresh */
	u32 vca;	/* VBC Config */
};

#define CG14_CCR_ENABLE	0x04
#define CG14_CCR_SELECT 0x02	/* HW/Full screen */

struct cg14_cursor {
	u32 cpl0[32];	/* Enable plane 0 */
	u32 cpl1[32];  /* Color selection plane */
	u8 ccr;	/* Cursor Control Reg */
	u8 xxx0[3];
	u16 cursx;	/* Cursor x,y position */
	u16 cursy;	/* Cursor x,y position */
	u32 color0;
	u32 color1;
	u32 xxx1[0x1bc];
	u32 cpl0i[32];	/* Enable plane 0 autoinc */
	u32 cpl1i[32]; /* Color selection autoinc */
};

struct cg14_dac {
	u8 addr;	/* Address Register */
	u8 xxx0[255];
	u8 glut;	/* Gamma table */
	u8 xxx1[255];
	u8 select;	/* Register Select */
	u8 xxx2[255];
	u8 mode;	/* Mode Register */
};

struct cg14_xlut{
	u8 x_xlut [256];
	u8 x_xlutd [256];
	u8 xxx0[0x600];
	u8 x_xlut_inc [256];
	u8 x_xlutd_inc [256];
};

/* Color look up table (clut) */
/* Each one of these arrays hold the color lookup table (for 256
 * colors) for each MDI page (I assume then there should be 4 MDI
 * pages, I still wonder what they are.  I have seen NeXTStep split
 * the screen in four parts, while operating in 24 bits mode.  Each
 * integer holds 4 values: alpha value (transparency channel, thanks
 * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
 *
 * I currently use the clut instead of the Xlut
 */
struct cg14_clut {
	u32 c_clut [256];
	u32 c_clutd [256];    /* i wonder what the 'd' is for */
	u32 c_clut_inc [256];
	u32 c_clutd_inc [256];
};

#define CG14_MMAP_ENTRIES	16

struct cg14_par {
	spinlock_t		lock;
	struct cg14_regs	__iomem *regs;
	struct cg14_clut	__iomem *clut;
	struct cg14_cursor	__iomem *cursor;

	u32			flags;
#define CG14_FLAG_BLANKED	0x00000001

	unsigned long		iospace;

	struct sbus_mmap_map	mmap_map[CG14_MMAP_ENTRIES];

	int			mode;
	int			ramsize;
};

static void __cg14_reset(struct cg14_par *par)
{
	struct cg14_regs __iomem *regs = par->regs;
	u8 val;

	val = sbus_readb(&regs->mcr);
	val &= ~(CG14_MCR_PIXMODE_MASK);
	sbus_writeb(val, &regs->mcr);
}

static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	unsigned long flags;

	/* We just use this to catch switches out of
	 * graphics mode.
	 */
	spin_lock_irqsave(&par->lock, flags);
	__cg14_reset(par);
	spin_unlock_irqrestore(&par->lock, flags);

	if (var->xoffset || var->yoffset || var->vmode)
		return -EINVAL;
	return 0;
}

/**
 *      cg14_setcolreg - Optional function. Sets a color register.
 *      @regno: boolean, 0 copy local, 1 get_user() function
 *      @red: frame buffer colormap structure
 *      @green: The green value which can be up to 16 bits wide
 *      @blue:  The blue value which can be up to 16 bits wide.
 *      @transp: If supported the alpha value which can be up to 16 bits wide.
 *      @info: frame buffer info structure
 */
static int cg14_setcolreg(unsigned regno,
			  unsigned red, unsigned green, unsigned blue,
			  unsigned transp, struct fb_info *info)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	struct cg14_clut __iomem *clut = par->clut;
	unsigned long flags;
	u32 val;

	if (regno >= 256)
		return 1;

	red >>= 8;
	green >>= 8;
	blue >>= 8;
	val = (red | (green << 8) | (blue << 16));

	spin_lock_irqsave(&par->lock, flags);
	sbus_writel(val, &clut->c_clut[regno]);
	spin_unlock_irqrestore(&par->lock, flags);

	return 0;
}

static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
	struct cg14_par *par = (struct cg14_par *) info->par;

	return sbusfb_mmap_helper(par->mmap_map,
				  info->fix.smem_start, info->fix.smem_len,
				  par->iospace, vma);
}

static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	struct cg14_regs __iomem *regs = par->regs;
	struct mdi_cfginfo kmdi, __user *mdii;
	unsigned long flags;
	int cur_mode, mode, ret = 0;

	switch (cmd) {
	case MDI_RESET:
		spin_lock_irqsave(&par->lock, flags);
		__cg14_reset(par);
		spin_unlock_irqrestore(&par->lock, flags);
		break;

	case MDI_GET_CFGINFO:
		memset(&kmdi, 0, sizeof(kmdi));

		spin_lock_irqsave(&par->lock, flags);
		kmdi.mdi_type = FBTYPE_MDICOLOR;
		kmdi.mdi_height = info->var.yres;
		kmdi.mdi_width = info->var.xres;
		kmdi.mdi_mode = par->mode;
		kmdi.mdi_pixfreq = 72; /* FIXME */
		kmdi.mdi_size = par->ramsize;
		spin_unlock_irqrestore(&par->lock, flags);

		mdii = (struct mdi_cfginfo __user *) arg;
		if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
			ret = -EFAULT;
		break;

	case MDI_SET_PIXELMODE:
		if (get_user(mode, (int __user *) arg)) {
			ret = -EFAULT;
			break;
		}

		spin_lock_irqsave(&par->lock, flags);
		cur_mode = sbus_readb(&regs->mcr);
		cur_mode &= ~CG14_MCR_PIXMODE_MASK;
		switch(mode) {
		case MDI_32_PIX:
			cur_mode |= (CG14_MCR_PIXMODE_32 <<
				     CG14_MCR_PIXMODE_SHIFT);
			break;

		case MDI_16_PIX:
			cur_mode |= (CG14_MCR_PIXMODE_16 <<
				     CG14_MCR_PIXMODE_SHIFT);
			break;

		case MDI_8_PIX:
			break;

		default:
			ret = -ENOSYS;
			break;
		}
		if (!ret) {
			sbus_writeb(cur_mode, &regs->mcr);
			par->mode = mode;
		}
		spin_unlock_irqrestore(&par->lock, flags);
		break;

	default:
		ret = sbusfb_ioctl_helper(cmd, arg, info,
					  FBTYPE_MDICOLOR, 8,
					  info->fix.smem_len);
		break;
	}

	return ret;
}

/*
 *  Initialisation
 */

static void cg14_init_fix(struct fb_info *info, int linebytes,
			  struct device_node *dp)
{
	snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);

	info->fix.type = FB_TYPE_PACKED_PIXELS;
	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	info->fix.line_length = linebytes;

	info->fix.accel = FB_ACCEL_SUN_CG14;
}

static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
	{
		.voff	= CG14_REGS,
		.poff	= 0x80000000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_XLUT,
		.poff	= 0x80003000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT1,
		.poff	= 0x80004000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT2,
		.poff	= 0x80005000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT3,
		.poff	= 0x80006000,
		.size	= 0x1000
	},
	{
		.voff	= CG3_MMAP_OFFSET - 0x7000,
		.poff	= 0x80000000,
		.size	= 0x7000
	},
	{
		.voff	= CG3_MMAP_OFFSET,
		.poff	= 0x00000000,
		.size	= SBUS_MMAP_FBSIZE(1)
	},
	{
		.voff	= MDI_CURSOR_MAP,
		.poff	= 0x80001000,
		.size	= 0x1000
	},
	{
		.voff	= MDI_CHUNKY_BGR_MAP,
		.poff	= 0x01000000,
		.size	= 0x400000
	},
	{
		.voff	= MDI_PLANAR_X16_MAP,
		.poff	= 0x02000000,
		.size	= 0x200000
	},
	{
		.voff	= MDI_PLANAR_C16_MAP,
		.poff	= 0x02800000,
		.size	= 0x200000
	},
	{
		.voff	= MDI_PLANAR_X32_MAP,
		.poff	= 0x03000000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_B32_MAP,
		.poff	= 0x03400000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_G32_MAP,
		.poff	= 0x03800000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_R32_MAP,
		.poff	= 0x03c00000,
		.size	= 0x100000
	},
	{ .size = 0 }
};

static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
			    struct cg14_par *par)
{
	if (par->regs)
		of_iounmap(&op->resource[0],
			   par->regs, sizeof(struct cg14_regs));
	if (par->clut)
		of_iounmap(&op->resource[0],
			   par->clut, sizeof(struct cg14_clut));
	if (par->cursor)
		of_iounmap(&op->resource[0],
			   par->cursor, sizeof(struct cg14_cursor));
	if (info->screen_base)
		of_iounmap(&op->resource[1],
			   info->screen_base, info->fix.smem_len);
}

static int cg14_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	struct fb_info *info;
	struct cg14_par *par;
	int is_8mb, linebytes, i, err;

	info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);

	err = -ENOMEM;
	if (!info)
		goto out_err;
	par = info->par;

	spin_lock_init(&par->lock);

	sbusfb_fill_var(&info->var, dp, 8);
	info->var.red.length = 8;
	info->var.green.length = 8;
	info->var.blue.length = 8;

	linebytes = of_getintprop_default(dp, "linebytes",
					  info->var.xres);
	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);

	if (of_node_name_eq(dp->parent, "sbus") ||
	    of_node_name_eq(dp->parent, "sbi")) {
		info->fix.smem_start = op->resource[0].start;
		par->iospace = op->resource[0].flags & IORESOURCE_BITS;
	} else {
		info->fix.smem_start = op->resource[1].start;
		par->iospace = op->resource[0].flags & IORESOURCE_BITS;
	}

	par->regs = of_ioremap(&op->resource[0], 0,
			       sizeof(struct cg14_regs), "cg14 regs");
	par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
			       sizeof(struct cg14_clut), "cg14 clut");
	par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
				 sizeof(struct cg14_cursor), "cg14 cursor");

	info->screen_base = of_ioremap(&op->resource[1], 0,
				       info->fix.smem_len, "cg14 ram");

	if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
		goto out_unmap_regs;

	is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
		  (8 * 1024 * 1024));

	BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
		
	memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));

	for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
		struct sbus_mmap_map *map = &par->mmap_map[i];

		if (!map->size)
			break;
		if (map->poff & 0x80000000)
			map->poff = (map->poff & 0x7fffffff) +
				(op->resource[0].start -
				 op->resource[1].start);
		if (is_8mb &&
		    map->size >= 0x100000 &&
		    map->size <= 0x400000)
			map->size *= 2;
	}

	par->mode = MDI_8_PIX;
	par->ramsize = (is_8mb ? 0x800000 : 0x400000);

	info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
	info->fbops = &cg14_ops;

	__cg14_reset(par);

	if (fb_alloc_cmap(&info->cmap, 256, 0))
		goto out_unmap_regs;

	fb_set_cmap(&info->cmap, info);

	cg14_init_fix(info, linebytes, dp);

	err = register_framebuffer(info);
	if (err < 0)
		goto out_dealloc_cmap;

	dev_set_drvdata(&op->dev, info);

	printk(KERN_INFO "%pOF: cgfourteen at %lx:%lx, %dMB\n",
	       dp,
	       par->iospace, info->fix.smem_start,
	       par->ramsize >> 20);

	return 0;

out_dealloc_cmap:
	fb_dealloc_cmap(&info->cmap);

out_unmap_regs:
	cg14_unmap_regs(op, info, par);
	framebuffer_release(info);

out_err:
	return err;
}

static int cg14_remove(struct platform_device *op)
{
	struct fb_info *info = dev_get_drvdata(&op->dev);
	struct cg14_par *par = info->par;

	unregister_framebuffer(info);
	fb_dealloc_cmap(&info->cmap);

	cg14_unmap_regs(op, info, par);

	framebuffer_release(info);

	return 0;
}

static const struct of_device_id cg14_match[] = {
	{
		.name = "cgfourteen",
	},
	{},
};
MODULE_DEVICE_TABLE(of, cg14_match);

static struct platform_driver cg14_driver = {
	.driver = {
		.name = "cg14",
		.of_match_table = cg14_match,
	},
	.probe		= cg14_probe,
	.remove		= cg14_remove,
};

static int __init cg14_init(void)
{
	if (fb_get_options("cg14fb", NULL))
		return -ENODEV;

	return platform_driver_register(&cg14_driver);
}

static void __exit cg14_exit(void)
{
	platform_driver_unregister(&cg14_driver);
}

module_init(cg14_init);
module_exit(cg14_exit);

MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/* cg14.c: CGFOURTEEN frame buffer driver
1da177e4 LT	3	*
50312ce9	4	* Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
1da177e4 LT	5	* Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
	6	* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
	7	*
	8	* Driver layout based loosely on tgafb.c, see that file for credits.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/errno.h>
	14	#include <linux/string.h>
1da177e4 LT	15	#include <linux/delay.h>
	16	#include <linux/init.h>
	17	#include <linux/fb.h>
	18	#include <linux/mm.h>
631a9dca	19	#include <linux/uaccess.h>
6cd5a86b	20	#include <linux/of_device.h>
1da177e4 LT	21
1da177e4 LT	22	#include <asm/io.h>
1da177e4 LT	23	#include <asm/fbio.h>
	24
	25	#include "sbuslib.h"
	26
	27	/*
	28	* Local functions.
	29	*/
	30
	31	static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
	32	unsigned, struct fb_info *);
	33
216d526c	34	static int cg14_mmap(struct fb_info , struct vm_area_struct );
67a6680d	35	static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
1da177e4 LT	36	static int cg14_pan_display(struct fb_var_screeninfo , struct fb_info );
	37
	38	/*
	39	* Frame buffer operations
	40	*/
	41
	42	static struct fb_ops cg14_ops = {
	43	.owner = THIS_MODULE,
	44	.fb_setcolreg = cg14_setcolreg,
	45	.fb_pan_display = cg14_pan_display,
	46	.fb_fillrect = cfb_fillrect,
	47	.fb_copyarea = cfb_copyarea,
	48	.fb_imageblit = cfb_imageblit,
	49	.fb_mmap = cg14_mmap,
	50	.fb_ioctl = cg14_ioctl,
9ffb83bc CH	51	#ifdef CONFIG_COMPAT
	52	.fb_compat_ioctl = sbusfb_compat_ioctl,
	53	#endif
1da177e4 LT	54	};
	55
	56	#define CG14_MCR_INTENABLE_SHIFT 7
	57	#define CG14_MCR_INTENABLE_MASK 0x80
	58	#define CG14_MCR_VIDENABLE_SHIFT 6
	59	#define CG14_MCR_VIDENABLE_MASK 0x40
	60	#define CG14_MCR_PIXMODE_SHIFT 4
	61	#define CG14_MCR_PIXMODE_MASK 0x30
	62	#define CG14_MCR_TMR_SHIFT 2
	63	#define CG14_MCR_TMR_MASK 0x0c
	64	#define CG14_MCR_TMENABLE_SHIFT 1
	65	#define CG14_MCR_TMENABLE_MASK 0x02
	66	#define CG14_MCR_RESET_SHIFT 0
	67	#define CG14_MCR_RESET_MASK 0x01
	68	#define CG14_REV_REVISION_SHIFT 4
	69	#define CG14_REV_REVISION_MASK 0xf0
	70	#define CG14_REV_IMPL_SHIFT 0
	71	#define CG14_REV_IMPL_MASK 0x0f
	72	#define CG14_VBR_FRAMEBASE_SHIFT 12
	73	#define CG14_VBR_FRAMEBASE_MASK 0x00fff000
	74	#define CG14_VMCR1_SETUP_SHIFT 0
	75	#define CG14_VMCR1_SETUP_MASK 0x000001ff
	76	#define CG14_VMCR1_VCONFIG_SHIFT 9
	77	#define CG14_VMCR1_VCONFIG_MASK 0x00000e00
	78	#define CG14_VMCR2_REFRESH_SHIFT 0
	79	#define CG14_VMCR2_REFRESH_MASK 0x00000001
	80	#define CG14_VMCR2_TESTROWCNT_SHIFT 1
	81	#define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
	82	#define CG14_VMCR2_FBCONFIG_SHIFT 2
	83	#define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
	84	#define CG14_VCR_REFRESHREQ_SHIFT 0
	85	#define CG14_VCR_REFRESHREQ_MASK 0x000003ff
	86	#define CG14_VCR1_REFRESHENA_SHIFT 10
	87	#define CG14_VCR1_REFRESHENA_MASK 0x00000400
	88	#define CG14_VCA_CAD_SHIFT 0
	89	#define CG14_VCA_CAD_MASK 0x000003ff
	90	#define CG14_VCA_VERS_SHIFT 10
	91	#define CG14_VCA_VERS_MASK 0x00000c00
	92	#define CG14_VCA_RAMSPEED_SHIFT 12
	93	#define CG14_VCA_RAMSPEED_MASK 0x00001000
	94	#define CG14_VCA_8MB_SHIFT 13
	95	#define CG14_VCA_8MB_MASK 0x00002000
	96
	97	#define CG14_MCR_PIXMODE_8 0
	98	#define CG14_MCR_PIXMODE_16 2
	99	#define CG14_MCR_PIXMODE_32 3
	100
	101	struct cg14_regs{
50312ce9 DM	102	u8 mcr; /* Master Control Reg */
	103	u8 ppr; /* Packed Pixel Reg */
	104	u8 tms[2]; /* Test Mode Status Regs */
	105	u8 msr; /* Master Status Reg */
	106	u8 fsr; /* Fault Status Reg */
	107	u8 rev; /* Revision & Impl */
	108	u8 ccr; /* Clock Control Reg */
	109	u32 tmr; /* Test Mode Read Back */
	110	u8 mod; /* Monitor Operation Data Reg */
	111	u8 acr; /* Aux Control */
1da177e4	112	u8 xxx0[6];
50312ce9 DM	113	u16 hct; /* Hor Counter */
	114	u16 vct; /* Vert Counter */
	115	u16 hbs; /* Hor Blank Start */
	116	u16 hbc; /* Hor Blank Clear */
	117	u16 hss; /* Hor Sync Start */
	118	u16 hsc; /* Hor Sync Clear */
	119	u16 csc; /* Composite Sync Clear */
	120	u16 vbs; /* Vert Blank Start */
	121	u16 vbc; /* Vert Blank Clear */
	122	u16 vss; /* Vert Sync Start */
	123	u16 vsc; /* Vert Sync Clear */
	124	u16 xcs;
	125	u16 xcc;
	126	u16 fsa; /* Fault Status Address */
	127	u16 adr; /* Address Registers */
1da177e4	128	u8 xxx1[0xce];
50312ce9 DM	129	u8 pcg[0x100]; /* Pixel Clock Generator */
	130	u32 vbr; /* Frame Base Row */
	131	u32 vmcr; /* VBC Master Control */
	132	u32 vcr; /* VBC refresh */
	133	u32 vca; /* VBC Config */
1da177e4 LT	134	};
	135
	136	#define CG14_CCR_ENABLE 0x04
	137	#define CG14_CCR_SELECT 0x02 /* HW/Full screen */
	138
	139	struct cg14_cursor {
50312ce9 DM	140	u32 cpl0[32]; /* Enable plane 0 */
	141	u32 cpl1[32]; /* Color selection plane */
	142	u8 ccr; /* Cursor Control Reg */
1da177e4	143	u8 xxx0[3];
50312ce9 DM	144	u16 cursx; /* Cursor x,y position */
	145	u16 cursy; /* Cursor x,y position */
	146	u32 color0;
	147	u32 color1;
1da177e4	148	u32 xxx1[0x1bc];
50312ce9 DM	149	u32 cpl0i[32]; /* Enable plane 0 autoinc */
50312ce9 DM	150	u32 cpl1i[32]; /* Color selection autoinc */
1da177e4 LT	151	};
	152
	153	struct cg14_dac {
50312ce9	154	u8 addr; /* Address Register */
1da177e4	155	u8 xxx0[255];
50312ce9	156	u8 glut; /* Gamma table */
1da177e4	157	u8 xxx1[255];
50312ce9	158	u8 select; /* Register Select */
1da177e4	159	u8 xxx2[255];
50312ce9	160	u8 mode; /* Mode Register */
1da177e4 LT	161	};
	162
	163	struct cg14_xlut{
50312ce9 DM	164	u8 x_xlut [256];
50312ce9 DM	165	u8 x_xlutd [256];
1da177e4	166	u8 xxx0[0x600];
50312ce9 DM	167	u8 x_xlut_inc [256];
50312ce9 DM	168	u8 x_xlutd_inc [256];
1da177e4 LT	169	};
	170
	171	/* Color look up table (clut) */
	172	/* Each one of these arrays hold the color lookup table (for 256
	173	* colors) for each MDI page (I assume then there should be 4 MDI
	174	* pages, I still wonder what they are. I have seen NeXTStep split
	175	* the screen in four parts, while operating in 24 bits mode. Each
	176	* integer holds 4 values: alpha value (transparency channel, thanks
	177	* go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
	178	*
	179	* I currently use the clut instead of the Xlut
	180	*/
	181	struct cg14_clut {
	182	u32 c_clut [256];
	183	u32 c_clutd [256]; /* i wonder what the 'd' is for */
	184	u32 c_clut_inc [256];
	185	u32 c_clutd_inc [256];
	186	};
	187
	188	#define CG14_MMAP_ENTRIES 16
	189
	190	struct cg14_par {
	191	spinlock_t lock;
	192	struct cg14_regs __iomem *regs;
	193	struct cg14_clut __iomem *clut;
	194	struct cg14_cursor __iomem *cursor;
	195
	196	u32 flags;
	197	#define CG14_FLAG_BLANKED 0x00000001
	198
1da177e4	199	unsigned long iospace;
1da177e4 LT	200
	201	struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
	202
	203	int mode;
	204	int ramsize;
1da177e4 LT	205	};
	206
	207	static void __cg14_reset(struct cg14_par *par)
	208	{
	209	struct cg14_regs __iomem *regs = par->regs;
	210	u8 val;
	211
	212	val = sbus_readb(&regs->mcr);
	213	val &= ~(CG14_MCR_PIXMODE_MASK);
	214	sbus_writeb(val, &regs->mcr);
	215	}
	216
	217	static int cg14_pan_display(struct fb_var_screeninfo var, struct fb_info info)
	218	{
	219	struct cg14_par par = (struct cg14_par ) info->par;
	220	unsigned long flags;
	221
	222	/* We just use this to catch switches out of
	223	* graphics mode.
	224	*/
	225	spin_lock_irqsave(&par->lock, flags);
	226	__cg14_reset(par);
	227	spin_unlock_irqrestore(&par->lock, flags);
	228
	229	if (var->xoffset \|\| var->yoffset \|\| var->vmode)
	230	return -EINVAL;
	231	return 0;
	232	}
	233
	234	/**
	235	* cg14_setcolreg - Optional function. Sets a color register.
	236	* @regno: boolean, 0 copy local, 1 get_user() function
	237	* @red: frame buffer colormap structure
	238	* @green: The green value which can be up to 16 bits wide
	239	* @blue: The blue value which can be up to 16 bits wide.
	240	* @transp: If supported the alpha value which can be up to 16 bits wide.
	241	* @info: frame buffer info structure
	242	*/
	243	static int cg14_setcolreg(unsigned regno,
	244	unsigned red, unsigned green, unsigned blue,
	245	unsigned transp, struct fb_info *info)
	246	{
	247	struct cg14_par par = (struct cg14_par ) info->par;
	248	struct cg14_clut __iomem *clut = par->clut;
	249	unsigned long flags;
	250	u32 val;
	251
	252	if (regno >= 256)
	253	return 1;
	254
	255	red >>= 8;
	256	green >>= 8;
	257	blue >>= 8;
	258	val = (red \| (green << 8) \| (blue << 16));
	259
	260	spin_lock_irqsave(&par->lock, flags);
	261	sbus_writel(val, &clut->c_clut[regno]);
	262	spin_unlock_irqrestore(&par->lock, flags);
	263
	264	return 0;
	265	}
	266
216d526c	267	static int cg14_mmap(struct fb_info info, struct vm_area_struct vma)
1da177e4 LT	268	{
	269	struct cg14_par par = (struct cg14_par ) info->par;
	270
	271	return sbusfb_mmap_helper(par->mmap_map,
de4dc48e	272	info->fix.smem_start, info->fix.smem_len,
1da177e4 LT	273	par->iospace, vma);
	274	}
	275
67a6680d	276	static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
1da177e4 LT	277	{
	278	struct cg14_par par = (struct cg14_par ) info->par;
	279	struct cg14_regs __iomem *regs = par->regs;
	280	struct mdi_cfginfo kmdi, __user *mdii;
	281	unsigned long flags;
	282	int cur_mode, mode, ret = 0;
	283
	284	switch (cmd) {
	285	case MDI_RESET:
	286	spin_lock_irqsave(&par->lock, flags);
	287	__cg14_reset(par);
	288	spin_unlock_irqrestore(&par->lock, flags);
	289	break;
	290
	291	case MDI_GET_CFGINFO:
	292	memset(&kmdi, 0, sizeof(kmdi));
	293
	294	spin_lock_irqsave(&par->lock, flags);
	295	kmdi.mdi_type = FBTYPE_MDICOLOR;
	296	kmdi.mdi_height = info->var.yres;
	297	kmdi.mdi_width = info->var.xres;
	298	kmdi.mdi_mode = par->mode;
	299	kmdi.mdi_pixfreq = 72; /* FIXME */
	300	kmdi.mdi_size = par->ramsize;
	301	spin_unlock_irqrestore(&par->lock, flags);
	302
	303	mdii = (struct mdi_cfginfo __user *) arg;
	304	if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
	305	ret = -EFAULT;
	306	break;
	307
	308	case MDI_SET_PIXELMODE:
	309	if (get_user(mode, (int __user *) arg)) {
	310	ret = -EFAULT;
	311	break;
	312	}
	313
	314	spin_lock_irqsave(&par->lock, flags);
	315	cur_mode = sbus_readb(&regs->mcr);
	316	cur_mode &= ~CG14_MCR_PIXMODE_MASK;
	317	switch(mode) {
	318	case MDI_32_PIX:
	319	cur_mode \|= (CG14_MCR_PIXMODE_32 <<
	320	CG14_MCR_PIXMODE_SHIFT);
	321	break;
	322
	323	case MDI_16_PIX:
	324	cur_mode \|= (CG14_MCR_PIXMODE_16 <<
	325	CG14_MCR_PIXMODE_SHIFT);
	326	break;
	327
	328	case MDI_8_PIX:
	329	break;
	330
	331	default:
	332	ret = -ENOSYS;
	333	break;
cf6ac4ce	334	}
1da177e4 LT	335	if (!ret) {
	336	sbus_writeb(cur_mode, &regs->mcr);
	337	par->mode = mode;
	338	}
	339	spin_unlock_irqrestore(&par->lock, flags);
	340	break;
	341
	342	default:
	343	ret = sbusfb_ioctl_helper(cmd, arg, info,
de4dc48e KH	344	FBTYPE_MDICOLOR, 8,
de4dc48e KH	345	info->fix.smem_len);
1da177e4	346	break;
cf6ac4ce	347	}
1da177e4 LT	348
	349	return ret;
	350	}
	351
	352	/*
	353	* Initialisation
	354	*/
	355
48c68c4f GKH	356	static void cg14_init_fix(struct fb_info *info, int linebytes,
48c68c4f GKH	357	struct device_node *dp)
1da177e4	358	{
5c63e407	359	snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
1da177e4 LT	360
	361	info->fix.type = FB_TYPE_PACKED_PIXELS;
	362	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	363
	364	info->fix.line_length = linebytes;
	365
	366	info->fix.accel = FB_ACCEL_SUN_CG14;
	367	}
	368
48c68c4f	369	static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
1da177e4 LT	370	{
	371	.voff = CG14_REGS,
	372	.poff = 0x80000000,
	373	.size = 0x1000
	374	},
	375	{
	376	.voff = CG14_XLUT,
	377	.poff = 0x80003000,
	378	.size = 0x1000
	379	},
	380	{
	381	.voff = CG14_CLUT1,
	382	.poff = 0x80004000,
	383	.size = 0x1000
	384	},
	385	{
	386	.voff = CG14_CLUT2,
	387	.poff = 0x80005000,
	388	.size = 0x1000
	389	},
	390	{
	391	.voff = CG14_CLUT3,
	392	.poff = 0x80006000,
	393	.size = 0x1000
	394	},
	395	{
	396	.voff = CG3_MMAP_OFFSET - 0x7000,
	397	.poff = 0x80000000,
	398	.size = 0x7000
	399	},
	400	{
	401	.voff = CG3_MMAP_OFFSET,
	402	.poff = 0x00000000,
	403	.size = SBUS_MMAP_FBSIZE(1)
	404	},
	405	{
	406	.voff = MDI_CURSOR_MAP,
	407	.poff = 0x80001000,
	408	.size = 0x1000
	409	},
	410	{
	411	.voff = MDI_CHUNKY_BGR_MAP,
	412	.poff = 0x01000000,
	413	.size = 0x400000
	414	},
	415	{
	416	.voff = MDI_PLANAR_X16_MAP,
	417	.poff = 0x02000000,
	418	.size = 0x200000
	419	},
	420	{
	421	.voff = MDI_PLANAR_C16_MAP,
	422	.poff = 0x02800000,
	423	.size = 0x200000
	424	},
	425	{
	426	.voff = MDI_PLANAR_X32_MAP,
	427	.poff = 0x03000000,
	428	.size = 0x100000
	429	},
	430	{
	431	.voff = MDI_PLANAR_B32_MAP,
	432	.poff = 0x03400000,
	433	.size = 0x100000
434	},
435	{
436	.voff = MDI_PLANAR_G32_MAP,
437	.poff = 0x03800000,
438	.size = 0x100000
439	},
440	{
441	.voff = MDI_PLANAR_R32_MAP,
442	.poff = 0x03c00000,
443	.size = 0x100000
444	},
445	{ .size = 0 }
446	};
447
2dc11581	448	static void cg14_unmap_regs(struct platform_device op, struct fb_info info,
c7f439b9	449	struct cg14_par *par)
1da177e4	450	{
c7f439b9	451	if (par->regs)
e3a411a3	452	of_iounmap(&op->resource[0],
c7f439b9 DM	453	par->regs, sizeof(struct cg14_regs));
c7f439b9 DM	454	if (par->clut)
e3a411a3	455	of_iounmap(&op->resource[0],
c7f439b9 DM	456	par->clut, sizeof(struct cg14_clut));
c7f439b9 DM	457	if (par->cursor)
e3a411a3	458	of_iounmap(&op->resource[0],
c7f439b9 DM	459	par->cursor, sizeof(struct cg14_cursor));
c7f439b9 DM	460	if (info->screen_base)
e3a411a3	461	of_iounmap(&op->resource[1],
de4dc48e	462	info->screen_base, info->fix.smem_len);
50312ce9	463	}
1da177e4	464
48c68c4f	465	static int cg14_probe(struct platform_device *op)
50312ce9	466	{
d4b8b2c2	467	struct device_node *dp = op->dev.of_node;
c7f439b9 DM	468	struct fb_info *info;
c7f439b9 DM	469	struct cg14_par *par;
50312ce9	470	int is_8mb, linebytes, i, err;
1da177e4	471
c7f439b9 DM	472	info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
	473
	474	err = -ENOMEM;
	475	if (!info)
	476	goto out_err;
	477	par = info->par;
1da177e4	478
c7f439b9	479	spin_lock_init(&par->lock);
1da177e4	480
6cd5a86b	481	sbusfb_fill_var(&info->var, dp, 8);
c7f439b9 DM	482	info->var.red.length = 8;
	483	info->var.green.length = 8;
	484	info->var.blue.length = 8;
1da177e4	485
50312ce9	486	linebytes = of_getintprop_default(dp, "linebytes",
c7f439b9	487	info->var.xres);
de4dc48e	488	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
1da177e4	489
a6f13af4 RH	490	if (of_node_name_eq(dp->parent, "sbus") \|\|
a6f13af4 RH	491	of_node_name_eq(dp->parent, "sbi")) {
de4dc48e	492	info->fix.smem_start = op->resource[0].start;
c7f439b9	493	par->iospace = op->resource[0].flags & IORESOURCE_BITS;
1da177e4	494	} else {
de4dc48e	495	info->fix.smem_start = op->resource[1].start;
c7f439b9	496	par->iospace = op->resource[0].flags & IORESOURCE_BITS;
1da177e4 LT	497	}
1da177e4 LT	498
c7f439b9 DM	499	par->regs = of_ioremap(&op->resource[0], 0,
	500	sizeof(struct cg14_regs), "cg14 regs");
	501	par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
	502	sizeof(struct cg14_clut), "cg14 clut");
	503	par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
	504	sizeof(struct cg14_cursor), "cg14 cursor");
1da177e4	505
c7f439b9	506	info->screen_base = of_ioremap(&op->resource[1], 0,
de4dc48e	507	info->fix.smem_len, "cg14 ram");
1da177e4	508
c7f439b9 DM	509	if (!par->regs \|\| !par->clut \|\| !par->cursor \|\| !info->screen_base)
c7f439b9 DM	510	goto out_unmap_regs;
50312ce9 DM	511
	512	is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
	513	(8 * 1024 * 1024));
	514
c7f439b9	515	BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
1da177e4	516
c7f439b9	517	memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
50312ce9	518
1da177e4	519	for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
c7f439b9	520	struct sbus_mmap_map *map = &par->mmap_map[i];
1da177e4 LT	521
	522	if (!map->size)
	523	break;
	524	if (map->poff & 0x80000000)
50312ce9 DM	525	map->poff = (map->poff & 0x7fffffff) +
	526	(op->resource[0].start -
	527	op->resource[1].start);
1da177e4 LT	528	if (is_8mb &&
	529	map->size >= 0x100000 &&
	530	map->size <= 0x400000)
	531	map->size *= 2;
	532	}
	533
c7f439b9 DM	534	par->mode = MDI_8_PIX;
c7f439b9 DM	535	par->ramsize = (is_8mb ? 0x800000 : 0x400000);
1da177e4	536
c7f439b9 DM	537	info->flags = FBINFO_DEFAULT \| FBINFO_HWACCEL_YPAN;
c7f439b9 DM	538	info->fbops = &cg14_ops;
1da177e4	539
c7f439b9	540	__cg14_reset(par);
1da177e4	541
c7f439b9 DM	542	if (fb_alloc_cmap(&info->cmap, 256, 0))
c7f439b9 DM	543	goto out_unmap_regs;
1da177e4	544
c7f439b9	545	fb_set_cmap(&info->cmap, info);
1da177e4	546
c7f439b9 DM	547	cg14_init_fix(info, linebytes, dp);
	548
	549	err = register_framebuffer(info);
	550	if (err < 0)
	551	goto out_dealloc_cmap;
1da177e4	552
c7f439b9	553	dev_set_drvdata(&op->dev, info);
1da177e4	554
6d7e6533 RH	555	printk(KERN_INFO "%pOF: cgfourteen at %lx:%lx, %dMB\n",
6d7e6533 RH	556	dp,
de4dc48e	557	par->iospace, info->fix.smem_start,
c7f439b9	558	par->ramsize >> 20);
1da177e4	559
50312ce9	560	return 0;
1da177e4	561
c7f439b9 DM	562	out_dealloc_cmap:
	563	fb_dealloc_cmap(&info->cmap);
	564
	565	out_unmap_regs:
	566	cg14_unmap_regs(op, info, par);
6359691d	567	framebuffer_release(info);
1da177e4	568
c7f439b9 DM	569	out_err:
c7f439b9 DM	570	return err;
50312ce9	571	}
1da177e4	572
48c68c4f	573	static int cg14_remove(struct platform_device *op)
50312ce9	574	{
c7f439b9 DM	575	struct fb_info *info = dev_get_drvdata(&op->dev);
c7f439b9 DM	576	struct cg14_par *par = info->par;
50312ce9	577
c7f439b9 DM	578	unregister_framebuffer(info);
c7f439b9 DM	579	fb_dealloc_cmap(&info->cmap);
50312ce9	580
c7f439b9	581	cg14_unmap_regs(op, info, par);
50312ce9	582
c7f439b9	583	framebuffer_release(info);
50312ce9	584
1da177e4 LT	585	return 0;
	586	}
	587
fd098316	588	static const struct of_device_id cg14_match[] = {
50312ce9 DM	589	{
	590	.name = "cgfourteen",
	591	},
	592	{},
	593	};
	594	MODULE_DEVICE_TABLE(of, cg14_match);
1da177e4	595
28541d0f	596	static struct platform_driver cg14_driver = {
4018294b GL	597	.driver = {
4018294b GL	598	.name = "cg14",
4018294b GL	599	.of_match_table = cg14_match,
4018294b GL	600	},
50312ce9	601	.probe = cg14_probe,
48c68c4f	602	.remove = cg14_remove,
50312ce9	603	};
1da177e4	604
54433000	605	static int __init cg14_init(void)
50312ce9 DM	606	{
	607	if (fb_get_options("cg14fb", NULL))
	608	return -ENODEV;
	609
28541d0f	610	return platform_driver_register(&cg14_driver);
1da177e4 LT	611	}
1da177e4 LT	612
54433000	613	static void __exit cg14_exit(void)
1da177e4	614	{
28541d0f	615	platform_driver_unregister(&cg14_driver);
1da177e4 LT	616	}
	617
	618	module_init(cg14_init);
1da177e4	619	module_exit(cg14_exit);
1da177e4 LT	620
1da177e4 LT	621	MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
50312ce9 DM	622	MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
50312ce9 DM	623	MODULE_VERSION("2.0");
1da177e4	624	MODULE_LICENSE("GPL");