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Commit | Line | Data |
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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
4ed824d9 SR |
2 | /* |
3 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
4 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
5 | * | |
6 | * Based on the LCD driver for TI Avalanche processors written by | |
7 | * Ajay Singh and Shalom Hai. | |
4ed824d9 SR |
8 | */ |
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/fb.h> | |
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/uaccess.h> | |
9dd44d5d | 16 | #include <linux/pm_runtime.h> |
4ed824d9 | 17 | #include <linux/interrupt.h> |
a481b37a | 18 | #include <linux/wait.h> |
4ed824d9 | 19 | #include <linux/clk.h> |
e04e5483 | 20 | #include <linux/cpufreq.h> |
1d3c6c7b | 21 | #include <linux/console.h> |
deb95c6c | 22 | #include <linux/spinlock.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
a0239073 | 24 | #include <linux/delay.h> |
3b9cc4ea | 25 | #include <linux/lcm.h> |
4ed824d9 | 26 | #include <video/da8xx-fb.h> |
12fa8350 | 27 | #include <asm/div64.h> |
4ed824d9 SR |
28 | |
29 | #define DRIVER_NAME "da8xx_lcdc" | |
30 | ||
c6daf05b MP |
31 | #define LCD_VERSION_1 1 |
32 | #define LCD_VERSION_2 2 | |
33 | ||
4ed824d9 | 34 | /* LCD Status Register */ |
1f9c3e1f | 35 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 36 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 37 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
38 | #define LCD_FIFO_UNDERFLOW BIT(5) |
39 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 40 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
41 | |
42 | /* LCD DMA Control Register */ | |
43 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
44 | #define LCD_DMA_BURST_1 0x0 | |
45 | #define LCD_DMA_BURST_2 0x1 | |
46 | #define LCD_DMA_BURST_4 0x2 | |
47 | #define LCD_DMA_BURST_8 0x3 | |
48 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
49 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
50 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
51 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
52 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
53 | ||
54 | /* LCD Control Register */ | |
55 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
56 | #define LCD_RASTER_MODE 0x01 | |
57 | ||
58 | /* LCD Raster Control Register */ | |
59 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
60 | #define PALETTE_AND_DATA 0x00 | |
61 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 62 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
63 | |
64 | #define LCD_MONO_8BIT_MODE BIT(9) | |
65 | #define LCD_RASTER_ORDER BIT(8) | |
66 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
67 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
68 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
69 | #define LCD_V1_PL_INT_ENA BIT(4) | |
70 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
71 | #define LCD_MONOCHROME_MODE BIT(1) |
72 | #define LCD_RASTER_ENABLE BIT(0) | |
73 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
74 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
75 | #define LCD_V2_DMA_CLK_EN BIT(2) |
76 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
77 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
78 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
79 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
80 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
81 | |
82 | /* LCD Raster Timing 2 Register */ | |
83 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
84 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
85 | #define LCD_SYNC_CTRL BIT(25) | |
86 | #define LCD_SYNC_EDGE BIT(24) | |
87 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
88 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
89 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
90 | ||
91 | /* LCD Block */ | |
c6daf05b | 92 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
93 | #define LCD_CTRL_REG 0x4 |
94 | #define LCD_STAT_REG 0x8 | |
95 | #define LCD_RASTER_CTRL_REG 0x28 | |
96 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
97 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
98 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
99 | #define LCD_DMA_CTRL_REG 0x40 | |
100 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
101 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
102 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
103 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
104 | ||
c6daf05b MP |
105 | /* Interrupt Registers available only in Version 2 */ |
106 | #define LCD_RAW_STAT_REG 0x58 | |
107 | #define LCD_MASKED_STAT_REG 0x5c | |
108 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
109 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
110 | #define LCD_END_OF_INT_IND_REG 0x68 | |
111 | ||
112 | /* Clock registers available only on Version 2 */ | |
113 | #define LCD_CLK_ENABLE_REG 0x6c | |
114 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 115 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 116 | |
1f9c3e1f | 117 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 | 118 | |
4ed824d9 | 119 | #define PALETTE_SIZE 256 |
4ed824d9 | 120 | |
2dfa77a2 DE |
121 | #define CLK_MIN_DIV 2 |
122 | #define CLK_MAX_DIV 255 | |
123 | ||
34aef6eb | 124 | static void __iomem *da8xx_fb_reg_base; |
c6daf05b MP |
125 | static unsigned int lcd_revision; |
126 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
127 | static wait_queue_head_t frame_done_wq; |
128 | static int frame_done_flag; | |
4ed824d9 | 129 | |
a9cd67c8 | 130 | static unsigned int lcdc_read(unsigned int addr) |
4ed824d9 SR |
131 | { |
132 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
133 | } | |
134 | ||
a9cd67c8 | 135 | static void lcdc_write(unsigned int val, unsigned int addr) |
4ed824d9 SR |
136 | { |
137 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
138 | } | |
139 | ||
140 | struct da8xx_fb_par { | |
dbe8e48a | 141 | struct device *dev; |
ef88ee4e | 142 | dma_addr_t p_palette_base; |
4ed824d9 | 143 | unsigned char *v_palette_base; |
1f9c3e1f MA |
144 | dma_addr_t vram_phys; |
145 | unsigned long vram_size; | |
146 | void *vram_virt; | |
147 | unsigned int dma_start; | |
148 | unsigned int dma_end; | |
4ed824d9 SR |
149 | struct clk *lcdc_clk; |
150 | int irq; | |
4ed824d9 | 151 | unsigned int palette_sz; |
36113804 | 152 | int blank; |
1f9c3e1f MA |
153 | wait_queue_head_t vsync_wait; |
154 | int vsync_flag; | |
155 | int vsync_timeout; | |
deb95c6c MP |
156 | spinlock_t lock_for_chan_update; |
157 | ||
158 | /* | |
159 | * LCDC has 2 ping pong DMA channels, channel 0 | |
160 | * and channel 1. | |
161 | */ | |
162 | unsigned int which_dma_channel_done; | |
e04e5483 C |
163 | #ifdef CONFIG_CPU_FREQ |
164 | struct notifier_block freq_transition; | |
165 | #endif | |
0715c72d | 166 | unsigned int lcdc_clk_rate; |
36113804 | 167 | void (*panel_power_ctrl)(int); |
1a2b750c | 168 | u32 pseudo_palette[16]; |
b6dbe8e4 AM |
169 | struct fb_videomode mode; |
170 | struct lcd_ctrl_config cfg; | |
4ed824d9 SR |
171 | }; |
172 | ||
be0f6dbc | 173 | static struct fb_var_screeninfo da8xx_fb_var; |
4ed824d9 | 174 | |
48c68c4f | 175 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
4ed824d9 SR |
176 | .id = "DA8xx FB Drv", |
177 | .type = FB_TYPE_PACKED_PIXELS, | |
178 | .type_aux = 0, | |
179 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 180 | .xpanstep = 0, |
4ed824d9 | 181 | .ypanstep = 1, |
1f9c3e1f | 182 | .ywrapstep = 0, |
4ed824d9 SR |
183 | .accel = FB_ACCEL_NONE |
184 | }; | |
185 | ||
f772fabd | 186 | static struct fb_videomode known_lcd_panels[] = { |
4ed824d9 SR |
187 | /* Sharp LCD035Q3DG01 */ |
188 | [0] = { | |
f772fabd MP |
189 | .name = "Sharp_LCD035Q3DG01", |
190 | .xres = 320, | |
191 | .yres = 240, | |
a6a799f8 | 192 | .pixclock = KHZ2PICOS(4607), |
f772fabd MP |
193 | .left_margin = 6, |
194 | .right_margin = 8, | |
195 | .upper_margin = 2, | |
196 | .lower_margin = 2, | |
197 | .hsync_len = 0, | |
198 | .vsync_len = 0, | |
713fced8 | 199 | .sync = FB_SYNC_CLK_INVERT, |
4ed824d9 SR |
200 | }, |
201 | /* Sharp LK043T1DG01 */ | |
202 | [1] = { | |
f772fabd MP |
203 | .name = "Sharp_LK043T1DG01", |
204 | .xres = 480, | |
205 | .yres = 272, | |
a6a799f8 | 206 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
207 | .left_margin = 2, |
208 | .right_margin = 2, | |
209 | .upper_margin = 2, | |
210 | .lower_margin = 2, | |
211 | .hsync_len = 41, | |
212 | .vsync_len = 10, | |
713fced8 | 213 | .sync = 0, |
f772fabd | 214 | .flag = 0, |
4ed824d9 | 215 | }, |
f413070e AG |
216 | [2] = { |
217 | /* Hitachi SP10Q010 */ | |
f772fabd MP |
218 | .name = "SP10Q010", |
219 | .xres = 320, | |
220 | .yres = 240, | |
a6a799f8 | 221 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
222 | .left_margin = 10, |
223 | .right_margin = 10, | |
224 | .upper_margin = 10, | |
225 | .lower_margin = 10, | |
226 | .hsync_len = 10, | |
227 | .vsync_len = 10, | |
713fced8 | 228 | .sync = 0, |
f772fabd | 229 | .flag = 0, |
f413070e | 230 | }, |
f474f0e1 JR |
231 | [3] = { |
232 | /* Densitron 84-0023-001T */ | |
233 | .name = "Densitron_84-0023-001T", | |
234 | .xres = 320, | |
235 | .yres = 240, | |
236 | .pixclock = KHZ2PICOS(6400), | |
237 | .left_margin = 0, | |
238 | .right_margin = 0, | |
239 | .upper_margin = 0, | |
240 | .lower_margin = 0, | |
241 | .hsync_len = 30, | |
242 | .vsync_len = 3, | |
243 | .sync = 0, | |
244 | }, | |
4ed824d9 SR |
245 | }; |
246 | ||
a9cd67c8 | 247 | static bool da8xx_fb_is_raster_enabled(void) |
fe8c98f0 DE |
248 | { |
249 | return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE); | |
250 | } | |
251 | ||
36113804 | 252 | /* Enable the Raster Engine of the LCD Controller */ |
a9cd67c8 | 253 | static void lcd_enable_raster(void) |
36113804 C |
254 | { |
255 | u32 reg; | |
256 | ||
92b4e450 MP |
257 | /* Put LCDC in reset for several cycles */ |
258 | if (lcd_revision == LCD_VERSION_2) | |
259 | /* Write 1 to reset LCDC */ | |
260 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
261 | mdelay(1); | |
262 | ||
74a0efde MP |
263 | /* Bring LCDC out of reset */ |
264 | if (lcd_revision == LCD_VERSION_2) | |
265 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 266 | mdelay(1); |
74a0efde | 267 | |
92b4e450 | 268 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
269 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
270 | if (!(reg & LCD_RASTER_ENABLE)) | |
271 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
272 | } | |
273 | ||
4ed824d9 | 274 | /* Disable the Raster Engine of the LCD Controller */ |
a9cd67c8 | 275 | static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done) |
4ed824d9 | 276 | { |
4ed824d9 | 277 | u32 reg; |
a481b37a | 278 | int ret; |
4ed824d9 SR |
279 | |
280 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 281 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 282 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
283 | else |
284 | /* return if already disabled */ | |
285 | return; | |
286 | ||
26e71645 DE |
287 | if ((wait_for_frame_done == DA8XX_FRAME_WAIT) && |
288 | (lcd_revision == LCD_VERSION_2)) { | |
a481b37a MP |
289 | frame_done_flag = 0; |
290 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
291 | frame_done_flag != 0, | |
292 | msecs_to_jiffies(50)); | |
293 | if (ret == 0) | |
294 | pr_err("LCD Controller timed out\n"); | |
295 | } | |
4ed824d9 SR |
296 | } |
297 | ||
298 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
299 | { | |
1f9c3e1f MA |
300 | u32 start; |
301 | u32 end; | |
302 | u32 reg_ras; | |
303 | u32 reg_dma; | |
c6daf05b | 304 | u32 reg_int; |
1f9c3e1f MA |
305 | |
306 | /* init reg to clear PLM (loading mode) fields */ | |
307 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
308 | reg_ras &= ~(3 << 20); | |
309 | ||
310 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
311 | ||
312 | if (load_mode == LOAD_DATA) { | |
313 | start = par->dma_start; | |
314 | end = par->dma_end; | |
315 | ||
316 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
317 | if (lcd_revision == LCD_VERSION_1) { |
318 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
319 | } else { | |
320 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
321 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a | 322 | LCD_V2_END_OF_FRAME1_INT_ENA | |
e4008e22 | 323 | LCD_FRAME_DONE | LCD_SYNC_LOST; |
c6daf05b MP |
324 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
325 | } | |
1f9c3e1f MA |
326 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
327 | ||
328 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
329 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
330 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
331 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
332 | } else if (load_mode == LOAD_PALETTE) { | |
333 | start = par->p_palette_base; | |
334 | end = start + par->palette_sz - 1; | |
335 | ||
336 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
337 | |
338 | if (lcd_revision == LCD_VERSION_1) { | |
339 | reg_ras |= LCD_V1_PL_INT_ENA; | |
340 | } else { | |
341 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
342 | LCD_V2_PL_INT_ENA; | |
343 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
344 | } | |
1f9c3e1f MA |
345 | |
346 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
347 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
348 | } | |
4ed824d9 | 349 | |
1f9c3e1f MA |
350 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
351 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 352 | |
1f9c3e1f MA |
353 | /* |
354 | * The Raster enable bit must be set after all other control fields are | |
355 | * set. | |
356 | */ | |
357 | lcd_enable_raster(); | |
4ed824d9 SR |
358 | } |
359 | ||
fb8fa943 MP |
360 | /* Configure the Burst Size and fifo threhold of DMA */ |
361 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
362 | { |
363 | u32 reg; | |
364 | ||
365 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
366 | switch (burst_size) { | |
367 | case 1: | |
368 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
369 | break; | |
370 | case 2: | |
371 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
372 | break; | |
373 | case 4: | |
374 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
375 | break; | |
376 | case 8: | |
377 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
378 | break; | |
379 | case 16: | |
3b43ad20 | 380 | default: |
4ed824d9 SR |
381 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
382 | break; | |
4ed824d9 | 383 | } |
fb8fa943 MP |
384 | |
385 | reg |= (fifo_th << 8); | |
386 | ||
2f93e8f4 | 387 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
388 | |
389 | return 0; | |
390 | } | |
391 | ||
392 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
393 | { | |
394 | u32 reg; | |
395 | ||
396 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
397 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
398 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
399 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
400 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
401 | } | |
402 | ||
403 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
404 | int front_porch) | |
405 | { | |
406 | u32 reg; | |
407 | ||
4d4e2c00 | 408 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff; |
83edd73a DE |
409 | reg |= (((back_porch-1) & 0xff) << 24) |
410 | | (((front_porch-1) & 0xff) << 16) | |
411 | | (((pulse_width-1) & 0x3f) << 10); | |
4ed824d9 | 412 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
2645ad16 DE |
413 | |
414 | /* | |
415 | * LCDC Version 2 adds some extra bits that increase the allowable | |
416 | * size of the horizontal timing registers. | |
417 | * remember that the registers use 0 to represent 1 so all values | |
418 | * that get set into register need to be decremented by 1 | |
419 | */ | |
420 | if (lcd_revision == LCD_VERSION_2) { | |
421 | /* Mask off the bits we want to change */ | |
422 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff; | |
423 | reg |= ((front_porch-1) & 0x300) >> 8; | |
424 | reg |= ((back_porch-1) & 0x300) >> 4; | |
425 | reg |= ((pulse_width-1) & 0x3c0) << 21; | |
426 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
427 | } | |
4ed824d9 SR |
428 | } |
429 | ||
430 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
431 | int front_porch) | |
432 | { | |
433 | u32 reg; | |
434 | ||
435 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
436 | reg |= ((back_porch & 0xff) << 24) | |
437 | | ((front_porch & 0xff) << 16) | |
83edd73a | 438 | | (((pulse_width-1) & 0x3f) << 10); |
4ed824d9 SR |
439 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); |
440 | } | |
441 | ||
3b43ad20 MP |
442 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, |
443 | struct fb_videomode *panel) | |
4ed824d9 SR |
444 | { |
445 | u32 reg; | |
c6daf05b | 446 | u32 reg_int; |
4ed824d9 SR |
447 | |
448 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
449 | LCD_MONO_8BIT_MODE | | |
450 | LCD_MONOCHROME_MODE); | |
451 | ||
3b43ad20 | 452 | switch (cfg->panel_shade) { |
4ed824d9 SR |
453 | case MONOCHROME: |
454 | reg |= LCD_MONOCHROME_MODE; | |
455 | if (cfg->mono_8bit_mode) | |
456 | reg |= LCD_MONO_8BIT_MODE; | |
457 | break; | |
458 | case COLOR_ACTIVE: | |
459 | reg |= LCD_TFT_MODE; | |
460 | if (cfg->tft_alt_mode) | |
461 | reg |= LCD_TFT_ALT_ENABLE; | |
462 | break; | |
463 | ||
464 | case COLOR_PASSIVE: | |
3b43ad20 MP |
465 | /* AC bias applicable only for Pasive panels */ |
466 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
467 | if (cfg->bpp == 12 && cfg->stn_565_mode) | |
4ed824d9 SR |
468 | reg |= LCD_STN_565_ENABLE; |
469 | break; | |
470 | ||
471 | default: | |
472 | return -EINVAL; | |
473 | } | |
474 | ||
475 | /* enable additional interrupts here */ | |
c6daf05b MP |
476 | if (lcd_revision == LCD_VERSION_1) { |
477 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
478 | } else { | |
479 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
480 | LCD_V2_UNDERFLOW_INT_ENA; | |
481 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
482 | } | |
4ed824d9 SR |
483 | |
484 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
485 | ||
486 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
487 | ||
3b43ad20 | 488 | reg |= LCD_SYNC_CTRL; |
4ed824d9 SR |
489 | |
490 | if (cfg->sync_edge) | |
491 | reg |= LCD_SYNC_EDGE; | |
492 | else | |
493 | reg &= ~LCD_SYNC_EDGE; | |
494 | ||
028cd86b | 495 | if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0) |
4ed824d9 SR |
496 | reg |= LCD_INVERT_LINE_CLOCK; |
497 | else | |
498 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
499 | ||
028cd86b | 500 | if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0) |
4ed824d9 SR |
501 | reg |= LCD_INVERT_FRAME_CLOCK; |
502 | else | |
503 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
504 | ||
505 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
511 | u32 bpp, u32 raster_order) | |
512 | { | |
1f9c3e1f | 513 | u32 reg; |
4ed824d9 | 514 | |
1a2b750c MP |
515 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
516 | return -EINVAL; | |
517 | ||
4ed824d9 SR |
518 | /* Set the Panel Width */ |
519 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
520 | if (lcd_revision == LCD_VERSION_1) { |
521 | /* | |
522 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
523 | * pixels. | |
524 | */ | |
525 | width &= 0x3f0; | |
526 | } else { | |
527 | /* | |
528 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
529 | * pixels. | |
530 | */ | |
531 | width &= 0x7f0; | |
532 | } | |
533 | ||
4ed824d9 SR |
534 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
535 | reg &= 0xfffffc00; | |
4d740801 MP |
536 | if (lcd_revision == LCD_VERSION_1) { |
537 | reg |= ((width >> 4) - 1) << 4; | |
538 | } else { | |
539 | width = (width >> 4) - 1; | |
540 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
541 | } | |
4ed824d9 SR |
542 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
543 | ||
544 | /* Set the Panel Height */ | |
4d740801 | 545 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
546 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
547 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
548 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
549 | ||
4d740801 MP |
550 | /* Set bit 10 of Lines Per Pixel */ |
551 | if (lcd_revision == LCD_VERSION_2) { | |
552 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
553 | reg |= ((height - 1) & 0x400) << 16; | |
554 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
555 | } | |
556 | ||
4ed824d9 SR |
557 | /* Set the Raster Order of the Frame Buffer */ |
558 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
559 | if (raster_order) | |
560 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
561 | |
562 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
563 | |
564 | switch (bpp) { | |
565 | case 1: | |
566 | case 2: | |
567 | case 4: | |
568 | case 16: | |
1a2b750c MP |
569 | break; |
570 | case 24: | |
571 | reg |= LCD_V2_TFT_24BPP_MODE; | |
fa8a00cc | 572 | break; |
1a2b750c | 573 | case 32: |
fa8a00cc | 574 | reg |= LCD_V2_TFT_24BPP_MODE; |
1a2b750c | 575 | reg |= LCD_V2_TFT_24BPP_UNPACK; |
4ed824d9 | 576 | break; |
4ed824d9 SR |
577 | case 8: |
578 | par->palette_sz = 256 * 2; | |
579 | break; | |
580 | ||
581 | default: | |
582 | return -EINVAL; | |
583 | } | |
584 | ||
1a2b750c MP |
585 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
586 | ||
4ed824d9 SR |
587 | return 0; |
588 | } | |
589 | ||
1a2b750c | 590 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
591 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
592 | unsigned blue, unsigned transp, | |
593 | struct fb_info *info) | |
594 | { | |
595 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 596 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 597 | u_short pal; |
1f9c3e1f | 598 | int update_hw = 0; |
4ed824d9 SR |
599 | |
600 | if (regno > 255) | |
601 | return 1; | |
602 | ||
603 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
604 | return 1; | |
605 | ||
1a2b750c MP |
606 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
607 | return -EINVAL; | |
f413070e | 608 | |
1a2b750c MP |
609 | switch (info->fix.visual) { |
610 | case FB_VISUAL_TRUECOLOR: | |
611 | red = CNVT_TOHW(red, info->var.red.length); | |
612 | green = CNVT_TOHW(green, info->var.green.length); | |
613 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
614 | break; | |
615 | case FB_VISUAL_PSEUDOCOLOR: | |
616 | switch (info->var.bits_per_pixel) { | |
617 | case 4: | |
618 | if (regno > 15) | |
619 | return -EINVAL; | |
620 | ||
621 | if (info->var.grayscale) { | |
622 | pal = regno; | |
623 | } else { | |
624 | red >>= 4; | |
625 | green >>= 8; | |
626 | blue >>= 12; | |
627 | ||
628 | pal = red & 0x0f00; | |
629 | pal |= green & 0x00f0; | |
630 | pal |= blue & 0x000f; | |
631 | } | |
632 | if (regno == 0) | |
633 | pal |= 0x2000; | |
634 | palette[regno] = pal; | |
635 | break; | |
636 | ||
637 | case 8: | |
f413070e AG |
638 | red >>= 4; |
639 | green >>= 8; | |
640 | blue >>= 12; | |
641 | ||
642 | pal = (red & 0x0f00); | |
643 | pal |= (green & 0x00f0); | |
644 | pal |= (blue & 0x000f); | |
4ed824d9 | 645 | |
1a2b750c MP |
646 | if (palette[regno] != pal) { |
647 | update_hw = 1; | |
648 | palette[regno] = pal; | |
649 | } | |
650 | break; | |
1f9c3e1f | 651 | } |
1a2b750c MP |
652 | break; |
653 | } | |
4ed824d9 | 654 | |
1a2b750c MP |
655 | /* Truecolor has hardware independent palette */ |
656 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
657 | u32 v; | |
4ed824d9 | 658 | |
1a2b750c MP |
659 | if (regno > 15) |
660 | return -EINVAL; | |
4ed824d9 | 661 | |
1a2b750c MP |
662 | v = (red << info->var.red.offset) | |
663 | (green << info->var.green.offset) | | |
664 | (blue << info->var.blue.offset); | |
4ed824d9 | 665 | |
8d018647 | 666 | ((u32 *) (info->pseudo_palette))[regno] = v; |
1f9c3e1f MA |
667 | if (palette[0] != 0x4000) { |
668 | update_hw = 1; | |
669 | palette[0] = 0x4000; | |
670 | } | |
4ed824d9 SR |
671 | } |
672 | ||
1f9c3e1f MA |
673 | /* Update the palette in the h/w as needed. */ |
674 | if (update_hw) | |
675 | lcd_blit(LOAD_PALETTE, par); | |
676 | ||
4ed824d9 SR |
677 | return 0; |
678 | } | |
1a2b750c | 679 | #undef CNVT_TOHW |
4ed824d9 | 680 | |
39c87d45 | 681 | static void da8xx_fb_lcd_reset(void) |
4ed824d9 | 682 | { |
4ed824d9 SR |
683 | /* DMA has to be disabled */ |
684 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
685 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 686 | |
74a0efde | 687 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 688 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
689 | /* Write 1 to reset */ |
690 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
691 | lcdc_write(0, LCD_CLK_RESET_REG); | |
692 | } | |
4ed824d9 SR |
693 | } |
694 | ||
2dfa77a2 DE |
695 | static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par, |
696 | unsigned lcdc_clk_div, | |
697 | unsigned lcdc_clk_rate) | |
404fdfe7 | 698 | { |
2dfa77a2 | 699 | int ret; |
404fdfe7 | 700 | |
0715c72d | 701 | if (par->lcdc_clk_rate != lcdc_clk_rate) { |
2dfa77a2 | 702 | ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate); |
287980e4 | 703 | if (ret) { |
2dfa77a2 DE |
704 | dev_err(par->dev, |
705 | "unable to set clock rate at %u\n", | |
706 | lcdc_clk_rate); | |
707 | return ret; | |
708 | } | |
0715c72d | 709 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); |
2dfa77a2 | 710 | } |
404fdfe7 | 711 | |
8097b174 | 712 | /* Configure the LCD clock divisor. */ |
2dfa77a2 | 713 | lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) | |
8097b174 | 714 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); |
c6daf05b MP |
715 | |
716 | if (lcd_revision == LCD_VERSION_2) | |
717 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
718 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
2dfa77a2 DE |
719 | |
720 | return 0; | |
a6a799f8 DE |
721 | } |
722 | ||
2dfa77a2 DE |
723 | static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, |
724 | unsigned pixclock, | |
725 | unsigned *lcdc_clk_rate) | |
a6a799f8 | 726 | { |
2dfa77a2 DE |
727 | unsigned lcdc_clk_div; |
728 | ||
729 | pixclock = PICOS2KHZ(pixclock) * 1000; | |
730 | ||
0715c72d | 731 | *lcdc_clk_rate = par->lcdc_clk_rate; |
c6daf05b | 732 | |
2dfa77a2 DE |
733 | if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) { |
734 | *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, | |
735 | pixclock * CLK_MAX_DIV); | |
736 | lcdc_clk_div = CLK_MAX_DIV; | |
737 | } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) { | |
738 | *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, | |
739 | pixclock * CLK_MIN_DIV); | |
740 | lcdc_clk_div = CLK_MIN_DIV; | |
741 | } else { | |
742 | lcdc_clk_div = *lcdc_clk_rate / pixclock; | |
743 | } | |
744 | ||
745 | return lcdc_clk_div; | |
746 | } | |
747 | ||
748 | static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, | |
749 | struct fb_videomode *mode) | |
750 | { | |
751 | unsigned lcdc_clk_rate; | |
752 | unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock, | |
753 | &lcdc_clk_rate); | |
754 | ||
755 | return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate); | |
756 | } | |
757 | ||
a9cd67c8 | 758 | static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par, |
2dfa77a2 DE |
759 | unsigned pixclock) |
760 | { | |
761 | unsigned lcdc_clk_div, lcdc_clk_rate; | |
762 | ||
763 | lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate); | |
764 | return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div)); | |
8097b174 C |
765 | } |
766 | ||
4ed824d9 | 767 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
f772fabd | 768 | struct fb_videomode *panel) |
4ed824d9 SR |
769 | { |
770 | u32 bpp; | |
771 | int ret = 0; | |
772 | ||
2dfa77a2 | 773 | ret = da8xx_fb_calc_config_clk_divider(par, panel); |
287980e4 | 774 | if (ret) { |
2dfa77a2 DE |
775 | dev_err(par->dev, "unable to configure clock\n"); |
776 | return ret; | |
777 | } | |
4ed824d9 | 778 | |
f772fabd | 779 | if (panel->sync & FB_SYNC_CLK_INVERT) |
2f93e8f4 SR |
780 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
781 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
782 | else | |
783 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
784 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
785 | ||
fb8fa943 MP |
786 | /* Configure the DMA burst size and fifo threshold. */ |
787 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
788 | if (ret < 0) |
789 | return ret; | |
790 | ||
4ed824d9 | 791 | /* Configure the vertical and horizontal sync properties. */ |
a592d9fd DE |
792 | lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len, |
793 | panel->lower_margin); | |
794 | lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len, | |
795 | panel->right_margin); | |
4ed824d9 SR |
796 | |
797 | /* Configure for disply */ | |
3b43ad20 | 798 | ret = lcd_cfg_display(cfg, panel); |
4ed824d9 SR |
799 | if (ret < 0) |
800 | return ret; | |
801 | ||
3b43ad20 | 802 | bpp = cfg->bpp; |
4ed824d9 | 803 | |
4ed824d9 SR |
804 | if (bpp == 12) |
805 | bpp = 16; | |
f772fabd MP |
806 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, |
807 | (unsigned int)panel->yres, bpp, | |
4ed824d9 SR |
808 | cfg->raster_order); |
809 | if (ret < 0) | |
810 | return ret; | |
811 | ||
812 | /* Configure FDD */ | |
813 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
814 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
c6daf05b MP |
819 | /* IRQ handler for version 2 of LCDC */ |
820 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
821 | { | |
822 | struct da8xx_fb_par *par = arg; | |
823 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
824 | |
825 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
26e71645 | 826 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
c6daf05b MP |
827 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
828 | lcd_enable_raster(); | |
829 | } else if (stat & LCD_PL_LOAD_DONE) { | |
830 | /* | |
831 | * Must disable raster before changing state of any control bit. | |
832 | * And also must be disabled before clearing the PL loading | |
833 | * interrupt via the following write to the status register. If | |
834 | * this is done after then one gets multiple PL done interrupts. | |
835 | */ | |
26e71645 | 836 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
c6daf05b MP |
837 | |
838 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
839 | ||
8a81dccd MP |
840 | /* Disable PL completion interrupt */ |
841 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
842 | |
843 | /* Setup and start data loading mode */ | |
844 | lcd_blit(LOAD_DATA, par); | |
845 | } else { | |
846 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
847 | ||
848 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 849 | par->which_dma_channel_done = 0; |
c6daf05b MP |
850 | lcdc_write(par->dma_start, |
851 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
852 | lcdc_write(par->dma_end, | |
853 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
854 | par->vsync_flag = 1; | |
855 | wake_up_interruptible(&par->vsync_wait); | |
856 | } | |
857 | ||
858 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 859 | par->which_dma_channel_done = 1; |
c6daf05b MP |
860 | lcdc_write(par->dma_start, |
861 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
862 | lcdc_write(par->dma_end, | |
863 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
864 | par->vsync_flag = 1; | |
865 | wake_up_interruptible(&par->vsync_wait); | |
866 | } | |
a481b37a MP |
867 | |
868 | /* Set only when controller is disabled and at the end of | |
869 | * active frame | |
870 | */ | |
871 | if (stat & BIT(0)) { | |
872 | frame_done_flag = 1; | |
873 | wake_up_interruptible(&frame_done_wq); | |
874 | } | |
c6daf05b MP |
875 | } |
876 | ||
877 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
878 | return IRQ_HANDLED; | |
879 | } | |
880 | ||
881 | /* IRQ handler for version 1 LCDC */ | |
882 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 883 | { |
1f9c3e1f | 884 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 885 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 886 | u32 reg_ras; |
4ed824d9 SR |
887 | |
888 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
26e71645 | 889 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
4ed824d9 | 890 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 891 | lcd_enable_raster(); |
1f9c3e1f MA |
892 | } else if (stat & LCD_PL_LOAD_DONE) { |
893 | /* | |
894 | * Must disable raster before changing state of any control bit. | |
895 | * And also must be disabled before clearing the PL loading | |
896 | * interrupt via the following write to the status register. If | |
897 | * this is done after then one gets multiple PL done interrupts. | |
898 | */ | |
26e71645 | 899 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
1f9c3e1f | 900 | |
4ed824d9 SR |
901 | lcdc_write(stat, LCD_STAT_REG); |
902 | ||
1f9c3e1f MA |
903 | /* Disable PL completion inerrupt */ |
904 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 905 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
906 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
907 | ||
908 | /* Setup and start data loading mode */ | |
909 | lcd_blit(LOAD_DATA, par); | |
910 | } else { | |
911 | lcdc_write(stat, LCD_STAT_REG); | |
912 | ||
913 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 914 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
915 | lcdc_write(par->dma_start, |
916 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
917 | lcdc_write(par->dma_end, | |
918 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
919 | par->vsync_flag = 1; | |
920 | wake_up_interruptible(&par->vsync_wait); | |
921 | } | |
922 | ||
923 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 924 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
925 | lcdc_write(par->dma_start, |
926 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
927 | lcdc_write(par->dma_end, | |
928 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
929 | par->vsync_flag = 1; | |
930 | wake_up_interruptible(&par->vsync_wait); | |
931 | } | |
932 | } | |
933 | ||
4ed824d9 SR |
934 | return IRQ_HANDLED; |
935 | } | |
936 | ||
937 | static int fb_check_var(struct fb_var_screeninfo *var, | |
938 | struct fb_info *info) | |
939 | { | |
940 | int err = 0; | |
87dac71d AM |
941 | struct da8xx_fb_par *par = info->par; |
942 | int bpp = var->bits_per_pixel >> 3; | |
943 | unsigned long line_size = var->xres_virtual * bpp; | |
4ed824d9 | 944 | |
1a2b750c MP |
945 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
946 | return -EINVAL; | |
947 | ||
4ed824d9 SR |
948 | switch (var->bits_per_pixel) { |
949 | case 1: | |
950 | case 8: | |
951 | var->red.offset = 0; | |
952 | var->red.length = 8; | |
953 | var->green.offset = 0; | |
954 | var->green.length = 8; | |
955 | var->blue.offset = 0; | |
956 | var->blue.length = 8; | |
957 | var->transp.offset = 0; | |
958 | var->transp.length = 0; | |
f413070e | 959 | var->nonstd = 0; |
4ed824d9 SR |
960 | break; |
961 | case 4: | |
962 | var->red.offset = 0; | |
963 | var->red.length = 4; | |
964 | var->green.offset = 0; | |
965 | var->green.length = 4; | |
966 | var->blue.offset = 0; | |
967 | var->blue.length = 4; | |
968 | var->transp.offset = 0; | |
969 | var->transp.length = 0; | |
f413070e | 970 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
971 | break; |
972 | case 16: /* RGB 565 */ | |
3510b8f7 | 973 | var->red.offset = 11; |
4ed824d9 SR |
974 | var->red.length = 5; |
975 | var->green.offset = 5; | |
976 | var->green.length = 6; | |
3510b8f7 | 977 | var->blue.offset = 0; |
4ed824d9 SR |
978 | var->blue.length = 5; |
979 | var->transp.offset = 0; | |
980 | var->transp.length = 0; | |
f413070e | 981 | var->nonstd = 0; |
4ed824d9 | 982 | break; |
1a2b750c MP |
983 | case 24: |
984 | var->red.offset = 16; | |
985 | var->red.length = 8; | |
986 | var->green.offset = 8; | |
987 | var->green.length = 8; | |
988 | var->blue.offset = 0; | |
989 | var->blue.length = 8; | |
990 | var->nonstd = 0; | |
991 | break; | |
992 | case 32: | |
993 | var->transp.offset = 24; | |
994 | var->transp.length = 8; | |
995 | var->red.offset = 16; | |
996 | var->red.length = 8; | |
997 | var->green.offset = 8; | |
998 | var->green.length = 8; | |
999 | var->blue.offset = 0; | |
1000 | var->blue.length = 8; | |
1001 | var->nonstd = 0; | |
1002 | break; | |
4ed824d9 SR |
1003 | default: |
1004 | err = -EINVAL; | |
1005 | } | |
1006 | ||
1007 | var->red.msb_right = 0; | |
1008 | var->green.msb_right = 0; | |
1009 | var->blue.msb_right = 0; | |
1010 | var->transp.msb_right = 0; | |
87dac71d AM |
1011 | |
1012 | if (line_size * var->yres_virtual > par->vram_size) | |
1013 | var->yres_virtual = par->vram_size / line_size; | |
1014 | ||
1015 | if (var->yres > var->yres_virtual) | |
1016 | var->yres = var->yres_virtual; | |
1017 | ||
1018 | if (var->xres > var->xres_virtual) | |
1019 | var->xres = var->xres_virtual; | |
1020 | ||
1021 | if (var->xres + var->xoffset > var->xres_virtual) | |
1022 | var->xoffset = var->xres_virtual - var->xres; | |
1023 | if (var->yres + var->yoffset > var->yres_virtual) | |
1024 | var->yoffset = var->yres_virtual - var->yres; | |
1025 | ||
404fdfe7 AM |
1026 | var->pixclock = da8xx_fb_round_clk(par, var->pixclock); |
1027 | ||
4ed824d9 SR |
1028 | return err; |
1029 | } | |
1030 | ||
e04e5483 C |
1031 | #ifdef CONFIG_CPU_FREQ |
1032 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
1033 | unsigned long val, void *data) | |
1034 | { | |
1035 | struct da8xx_fb_par *par; | |
e04e5483 C |
1036 | |
1037 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a | 1038 | if (val == CPUFREQ_POSTCHANGE) { |
0715c72d DE |
1039 | if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) { |
1040 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); | |
26e71645 | 1041 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
a6a799f8 | 1042 | da8xx_fb_calc_config_clk_divider(par, &par->mode); |
67900814 MP |
1043 | if (par->blank == FB_BLANK_UNBLANK) |
1044 | lcd_enable_raster(); | |
f820917a | 1045 | } |
e04e5483 C |
1046 | } |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
a9cd67c8 | 1051 | static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) |
e04e5483 C |
1052 | { |
1053 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
1054 | ||
1055 | return cpufreq_register_notifier(&par->freq_transition, | |
1056 | CPUFREQ_TRANSITION_NOTIFIER); | |
1057 | } | |
1058 | ||
a9cd67c8 | 1059 | static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) |
e04e5483 C |
1060 | { |
1061 | cpufreq_unregister_notifier(&par->freq_transition, | |
1062 | CPUFREQ_TRANSITION_NOTIFIER); | |
1063 | } | |
1064 | #endif | |
1065 | ||
48c68c4f | 1066 | static int fb_remove(struct platform_device *dev) |
4ed824d9 SR |
1067 | { |
1068 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
1069 | |
1070 | if (info) { | |
1071 | struct da8xx_fb_par *par = info->par; | |
1072 | ||
e04e5483 C |
1073 | #ifdef CONFIG_CPU_FREQ |
1074 | lcd_da8xx_cpufreq_deregister(par); | |
1075 | #endif | |
36113804 C |
1076 | if (par->panel_power_ctrl) |
1077 | par->panel_power_ctrl(0); | |
1078 | ||
26e71645 | 1079 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
4ed824d9 SR |
1080 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1081 | ||
1082 | /* disable DMA */ | |
1083 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1084 | ||
1085 | unregister_framebuffer(info); | |
1086 | fb_dealloc_cmap(&info->cmap); | |
12a7b035 | 1087 | dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base, |
1f9c3e1f | 1088 | par->p_palette_base); |
12a7b035 | 1089 | dma_free_coherent(par->dev, par->vram_size, par->vram_virt, |
1f9c3e1f | 1090 | par->vram_phys); |
9dd44d5d MP |
1091 | pm_runtime_put_sync(&dev->dev); |
1092 | pm_runtime_disable(&dev->dev); | |
4ed824d9 | 1093 | framebuffer_release(info); |
4ed824d9 SR |
1094 | |
1095 | } | |
2f93e8f4 | 1096 | return 0; |
4ed824d9 SR |
1097 | } |
1098 | ||
1f9c3e1f MA |
1099 | /* |
1100 | * Function to wait for vertical sync which for this LCD peripheral | |
1101 | * translates into waiting for the current raster frame to complete. | |
1102 | */ | |
1103 | static int fb_wait_for_vsync(struct fb_info *info) | |
1104 | { | |
1105 | struct da8xx_fb_par *par = info->par; | |
1106 | int ret; | |
1107 | ||
1108 | /* | |
1109 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1110 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1111 | * just after this set. But since we are just coarsely waiting for |
1112 | * a frame to complete then that's OK. i.e. if the frame completed | |
1113 | * just before this code executed then we have to wait another full | |
1114 | * frame time but there is no way to avoid such a situation. On the | |
1115 | * other hand if the frame completed just after then we don't need | |
1116 | * to wait long at all. Either way we are guaranteed to return to the | |
1117 | * user immediately after a frame completion which is all that is | |
1118 | * required. | |
1119 | */ | |
1120 | par->vsync_flag = 0; | |
1121 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1122 | par->vsync_flag != 0, | |
1123 | par->vsync_timeout); | |
1124 | if (ret < 0) | |
1125 | return ret; | |
1126 | if (ret == 0) | |
1127 | return -ETIMEDOUT; | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
4ed824d9 SR |
1132 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1133 | unsigned long arg) | |
1134 | { | |
1135 | struct lcd_sync_arg sync_arg; | |
1136 | ||
1137 | switch (cmd) { | |
1138 | case FBIOGET_CONTRAST: | |
1139 | case FBIOPUT_CONTRAST: | |
1140 | case FBIGET_BRIGHTNESS: | |
1141 | case FBIPUT_BRIGHTNESS: | |
1142 | case FBIGET_COLOR: | |
1143 | case FBIPUT_COLOR: | |
2f93e8f4 | 1144 | return -ENOTTY; |
4ed824d9 SR |
1145 | case FBIPUT_HSYNC: |
1146 | if (copy_from_user(&sync_arg, (char *)arg, | |
1147 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1148 | return -EFAULT; |
4ed824d9 SR |
1149 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1150 | sync_arg.pulse_width, | |
1151 | sync_arg.front_porch); | |
1152 | break; | |
1153 | case FBIPUT_VSYNC: | |
1154 | if (copy_from_user(&sync_arg, (char *)arg, | |
1155 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1156 | return -EFAULT; |
4ed824d9 SR |
1157 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1158 | sync_arg.pulse_width, | |
1159 | sync_arg.front_porch); | |
1160 | break; | |
1f9c3e1f MA |
1161 | case FBIO_WAITFORVSYNC: |
1162 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1163 | default: |
1164 | return -EINVAL; | |
1165 | } | |
1166 | return 0; | |
1167 | } | |
1168 | ||
312d9715 C |
1169 | static int cfb_blank(int blank, struct fb_info *info) |
1170 | { | |
1171 | struct da8xx_fb_par *par = info->par; | |
1172 | int ret = 0; | |
1173 | ||
1174 | if (par->blank == blank) | |
1175 | return 0; | |
1176 | ||
1177 | par->blank = blank; | |
1178 | switch (blank) { | |
1179 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1180 | lcd_enable_raster(); |
1181 | ||
312d9715 C |
1182 | if (par->panel_power_ctrl) |
1183 | par->panel_power_ctrl(1); | |
312d9715 | 1184 | break; |
99a647d1 YY |
1185 | case FB_BLANK_NORMAL: |
1186 | case FB_BLANK_VSYNC_SUSPEND: | |
1187 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1188 | case FB_BLANK_POWERDOWN: |
1189 | if (par->panel_power_ctrl) | |
1190 | par->panel_power_ctrl(0); | |
1191 | ||
26e71645 | 1192 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
312d9715 C |
1193 | break; |
1194 | default: | |
1195 | ret = -EINVAL; | |
1196 | } | |
1197 | ||
1198 | return ret; | |
1199 | } | |
1200 | ||
1f9c3e1f MA |
1201 | /* |
1202 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1203 | * to the new mode. | |
1204 | */ | |
1205 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1206 | struct fb_info *fbi) | |
1207 | { | |
1208 | int ret = 0; | |
1209 | struct fb_var_screeninfo new_var; | |
1210 | struct da8xx_fb_par *par = fbi->par; | |
1211 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1212 | unsigned int end; | |
1213 | unsigned int start; | |
deb95c6c | 1214 | unsigned long irq_flags; |
1f9c3e1f MA |
1215 | |
1216 | if (var->xoffset != fbi->var.xoffset || | |
1217 | var->yoffset != fbi->var.yoffset) { | |
1218 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1219 | new_var.xoffset = var->xoffset; | |
1220 | new_var.yoffset = var->yoffset; | |
1221 | if (fb_check_var(&new_var, fbi)) | |
1222 | ret = -EINVAL; | |
1223 | else { | |
1224 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1225 | ||
1226 | start = fix->smem_start + | |
1227 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1228 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1229 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1230 | par->dma_start = start; |
1231 | par->dma_end = end; | |
deb95c6c MP |
1232 | spin_lock_irqsave(&par->lock_for_chan_update, |
1233 | irq_flags); | |
1234 | if (par->which_dma_channel_done == 0) { | |
1235 | lcdc_write(par->dma_start, | |
1236 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1237 | lcdc_write(par->dma_end, | |
1238 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1239 | } else if (par->which_dma_channel_done == 1) { | |
1240 | lcdc_write(par->dma_start, | |
1241 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1242 | lcdc_write(par->dma_end, | |
1243 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1244 | } | |
1245 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1246 | irq_flags); | |
1f9c3e1f MA |
1247 | } |
1248 | } | |
1249 | ||
1250 | return ret; | |
1251 | } | |
1252 | ||
fe8c98f0 DE |
1253 | static int da8xxfb_set_par(struct fb_info *info) |
1254 | { | |
1255 | struct da8xx_fb_par *par = info->par; | |
1256 | int ret; | |
1257 | bool raster = da8xx_fb_is_raster_enabled(); | |
1258 | ||
1259 | if (raster) | |
26e71645 | 1260 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
fe8c98f0 DE |
1261 | |
1262 | fb_var_to_videomode(&par->mode, &info->var); | |
1263 | ||
1264 | par->cfg.bpp = info->var.bits_per_pixel; | |
1265 | ||
1266 | info->fix.visual = (par->cfg.bpp <= 8) ? | |
1267 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
1268 | info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8; | |
1269 | ||
1270 | ret = lcd_init(par, &par->cfg, &par->mode); | |
1271 | if (ret < 0) { | |
1272 | dev_err(par->dev, "lcd init failed\n"); | |
1273 | return ret; | |
1274 | } | |
1275 | ||
1276 | par->dma_start = info->fix.smem_start + | |
1277 | info->var.yoffset * info->fix.line_length + | |
1278 | info->var.xoffset * info->var.bits_per_pixel / 8; | |
1279 | par->dma_end = par->dma_start + | |
1280 | info->var.yres * info->fix.line_length - 1; | |
1281 | ||
1282 | lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1283 | lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1284 | lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1285 | lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1286 | ||
1287 | if (raster) | |
1288 | lcd_enable_raster(); | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
4ed824d9 SR |
1293 | static struct fb_ops da8xx_fb_ops = { |
1294 | .owner = THIS_MODULE, | |
1295 | .fb_check_var = fb_check_var, | |
fe8c98f0 | 1296 | .fb_set_par = da8xxfb_set_par, |
4ed824d9 | 1297 | .fb_setcolreg = fb_setcolreg, |
1f9c3e1f | 1298 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1299 | .fb_ioctl = fb_ioctl, |
1300 | .fb_fillrect = cfb_fillrect, | |
1301 | .fb_copyarea = cfb_copyarea, | |
1302 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1303 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1304 | }; |
1305 | ||
2bdff068 AM |
1306 | static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) |
1307 | { | |
700601d2 | 1308 | struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev); |
2bdff068 AM |
1309 | struct fb_videomode *lcdc_info; |
1310 | int i; | |
1311 | ||
1312 | for (i = 0, lcdc_info = known_lcd_panels; | |
1313 | i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) { | |
1314 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1315 | break; | |
1316 | } | |
1317 | ||
1318 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1319 | dev_err(&dev->dev, "no panel found\n"); | |
1320 | return NULL; | |
1321 | } | |
1322 | dev_info(&dev->dev, "found %s panel\n", lcdc_info->name); | |
1323 | ||
1324 | return lcdc_info; | |
1325 | } | |
1326 | ||
48c68c4f | 1327 | static int fb_probe(struct platform_device *device) |
4ed824d9 SR |
1328 | { |
1329 | struct da8xx_lcdc_platform_data *fb_pdata = | |
700601d2 | 1330 | dev_get_platdata(&device->dev); |
0ae6ee00 | 1331 | struct resource *lcdc_regs; |
4ed824d9 | 1332 | struct lcd_ctrl_config *lcd_cfg; |
f772fabd | 1333 | struct fb_videomode *lcdc_info; |
4ed824d9 | 1334 | struct fb_info *da8xx_fb_info; |
4ed824d9 | 1335 | struct da8xx_fb_par *par; |
0715c72d | 1336 | struct clk *tmp_lcdc_clk; |
2bdff068 | 1337 | int ret; |
3b9cc4ea | 1338 | unsigned long ulcm; |
4ed824d9 SR |
1339 | |
1340 | if (fb_pdata == NULL) { | |
1341 | dev_err(&device->dev, "Can not get platform data\n"); | |
1342 | return -ENOENT; | |
1343 | } | |
1344 | ||
2bdff068 AM |
1345 | lcdc_info = da8xx_fb_get_videomode(device); |
1346 | if (lcdc_info == NULL) | |
1347 | return -ENODEV; | |
1348 | ||
4ed824d9 | 1349 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); |
c45757f0 DE |
1350 | da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs); |
1351 | if (IS_ERR(da8xx_fb_reg_base)) | |
1352 | return PTR_ERR(da8xx_fb_reg_base); | |
4ed824d9 | 1353 | |
0715c72d DE |
1354 | tmp_lcdc_clk = devm_clk_get(&device->dev, "fck"); |
1355 | if (IS_ERR(tmp_lcdc_clk)) { | |
4ed824d9 | 1356 | dev_err(&device->dev, "Can not get device clock\n"); |
0715c72d | 1357 | return PTR_ERR(tmp_lcdc_clk); |
4ed824d9 | 1358 | } |
9dd44d5d MP |
1359 | |
1360 | pm_runtime_enable(&device->dev); | |
1361 | pm_runtime_get_sync(&device->dev); | |
4ed824d9 | 1362 | |
c6daf05b MP |
1363 | /* Determine LCD IP Version */ |
1364 | switch (lcdc_read(LCD_PID_REG)) { | |
1365 | case 0x4C100102: | |
1366 | lcd_revision = LCD_VERSION_1; | |
1367 | break; | |
1368 | case 0x4F200800: | |
8f22e8ea | 1369 | case 0x4F201000: |
c6daf05b MP |
1370 | lcd_revision = LCD_VERSION_2; |
1371 | break; | |
1372 | default: | |
1373 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1374 | "defaulting to LCD revision 1\n", | |
1375 | lcdc_read(LCD_PID_REG)); | |
1376 | lcd_revision = LCD_VERSION_1; | |
1377 | break; | |
1378 | } | |
1379 | ||
4ed824d9 SR |
1380 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; |
1381 | ||
3a58101d AM |
1382 | if (!lcd_cfg) { |
1383 | ret = -EINVAL; | |
1384 | goto err_pm_runtime_disable; | |
1385 | } | |
1386 | ||
4ed824d9 SR |
1387 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), |
1388 | &device->dev); | |
1389 | if (!da8xx_fb_info) { | |
4ed824d9 | 1390 | ret = -ENOMEM; |
9dd44d5d | 1391 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1392 | } |
1393 | ||
1394 | par = da8xx_fb_info->par; | |
dbe8e48a | 1395 | par->dev = &device->dev; |
0715c72d DE |
1396 | par->lcdc_clk = tmp_lcdc_clk; |
1397 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); | |
36113804 C |
1398 | if (fb_pdata->panel_power_ctrl) { |
1399 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1400 | par->panel_power_ctrl(1); | |
1401 | } | |
4ed824d9 | 1402 | |
b866458b | 1403 | fb_videomode_to_var(&da8xx_fb_var, lcdc_info); |
b6dbe8e4 | 1404 | par->cfg = *lcd_cfg; |
b866458b | 1405 | |
fe8c98f0 | 1406 | da8xx_fb_lcd_reset(); |
4ed824d9 SR |
1407 | |
1408 | /* allocate frame buffer */ | |
f772fabd MP |
1409 | par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; |
1410 | ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); | |
3b9cc4ea | 1411 | par->vram_size = roundup(par->vram_size/8, ulcm); |
1f9c3e1f MA |
1412 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1413 | ||
12a7b035 | 1414 | par->vram_virt = dma_alloc_coherent(par->dev, |
1f9c3e1f | 1415 | par->vram_size, |
ef88ee4e | 1416 | &par->vram_phys, |
1f9c3e1f MA |
1417 | GFP_KERNEL | GFP_DMA); |
1418 | if (!par->vram_virt) { | |
4ed824d9 SR |
1419 | dev_err(&device->dev, |
1420 | "GLCD: kmalloc for frame buffer failed\n"); | |
1421 | ret = -EINVAL; | |
1422 | goto err_release_fb; | |
1423 | } | |
1424 | ||
1f9c3e1f MA |
1425 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1426 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1427 | da8xx_fb_fix.smem_len = par->vram_size; | |
f772fabd | 1428 | da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; |
1f9c3e1f MA |
1429 | |
1430 | par->dma_start = par->vram_phys; | |
f772fabd | 1431 | par->dma_end = par->dma_start + lcdc_info->yres * |
1f9c3e1f MA |
1432 | da8xx_fb_fix.line_length - 1; |
1433 | ||
1434 | /* allocate palette buffer */ | |
12a7b035 | 1435 | par->v_palette_base = dma_alloc_coherent(par->dev, PALETTE_SIZE, |
750afb08 LC |
1436 | &par->p_palette_base, |
1437 | GFP_KERNEL | GFP_DMA); | |
1f9c3e1f MA |
1438 | if (!par->v_palette_base) { |
1439 | dev_err(&device->dev, | |
1440 | "GLCD: kmalloc for palette buffer failed\n"); | |
1441 | ret = -EINVAL; | |
1442 | goto err_release_fb_mem; | |
1443 | } | |
4ed824d9 | 1444 | |
4ed824d9 SR |
1445 | par->irq = platform_get_irq(device, 0); |
1446 | if (par->irq < 0) { | |
1447 | ret = -ENOENT; | |
1f9c3e1f | 1448 | goto err_release_pl_mem; |
4ed824d9 SR |
1449 | } |
1450 | ||
4ed824d9 | 1451 | da8xx_fb_var.grayscale = |
3b43ad20 | 1452 | lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; |
4ed824d9 | 1453 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
4ed824d9 SR |
1454 | |
1455 | /* Initialize fbinfo */ | |
1456 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1457 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1458 | da8xx_fb_info->var = da8xx_fb_var; | |
1459 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1460 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1461 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1462 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1463 | |
1464 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1465 | if (ret) | |
93c176f3 | 1466 | goto err_release_pl_mem; |
4ed824d9 SR |
1467 | da8xx_fb_info->cmap.len = par->palette_sz; |
1468 | ||
4ed824d9 SR |
1469 | /* initialize var_screeninfo */ |
1470 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1471 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1472 | ||
1473 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1474 | |
1475 | /* initialize the vsync wait queue */ | |
1476 | init_waitqueue_head(&par->vsync_wait); | |
1477 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1478 | par->which_dma_channel_done = -1; |
1479 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1480 | |
4ed824d9 SR |
1481 | /* Register the Frame Buffer */ |
1482 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1483 | dev_err(&device->dev, | |
1484 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1485 | ret = -EINVAL; | |
1486 | goto err_dealloc_cmap; | |
1487 | } | |
1488 | ||
e04e5483 C |
1489 | #ifdef CONFIG_CPU_FREQ |
1490 | ret = lcd_da8xx_cpufreq_register(par); | |
1491 | if (ret) { | |
1492 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1493 | goto err_cpu_freq; | |
1494 | } | |
1495 | #endif | |
93c176f3 | 1496 | |
c6daf05b MP |
1497 | if (lcd_revision == LCD_VERSION_1) |
1498 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1499 | else { |
1500 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1501 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1502 | } |
c6daf05b | 1503 | |
c45757f0 DE |
1504 | ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0, |
1505 | DRIVER_NAME, par); | |
93c176f3 CA |
1506 | if (ret) |
1507 | goto irq_freq; | |
4ed824d9 SR |
1508 | return 0; |
1509 | ||
93c176f3 | 1510 | irq_freq: |
e04e5483 | 1511 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1512 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1513 | err_cpu_freq: |
3a84409c | 1514 | #endif |
e04e5483 | 1515 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1516 | |
4ed824d9 SR |
1517 | err_dealloc_cmap: |
1518 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1519 | ||
1f9c3e1f | 1520 | err_release_pl_mem: |
12a7b035 | 1521 | dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base, |
1f9c3e1f MA |
1522 | par->p_palette_base); |
1523 | ||
4ed824d9 | 1524 | err_release_fb_mem: |
12a7b035 CH |
1525 | dma_free_coherent(par->dev, par->vram_size, par->vram_virt, |
1526 | par->vram_phys); | |
4ed824d9 SR |
1527 | |
1528 | err_release_fb: | |
1529 | framebuffer_release(da8xx_fb_info); | |
1530 | ||
9dd44d5d MP |
1531 | err_pm_runtime_disable: |
1532 | pm_runtime_put_sync(&device->dev); | |
1533 | pm_runtime_disable(&device->dev); | |
4ed824d9 | 1534 | |
4ed824d9 SR |
1535 | return ret; |
1536 | } | |
1537 | ||
622f7c9b | 1538 | #ifdef CONFIG_PM_SLEEP |
58f3853a | 1539 | static struct lcdc_context { |
7a93cbbb MP |
1540 | u32 clk_enable; |
1541 | u32 ctrl; | |
1542 | u32 dma_ctrl; | |
1543 | u32 raster_timing_0; | |
1544 | u32 raster_timing_1; | |
1545 | u32 raster_timing_2; | |
1546 | u32 int_enable_set; | |
1547 | u32 dma_frm_buf_base_addr_0; | |
1548 | u32 dma_frm_buf_ceiling_addr_0; | |
1549 | u32 dma_frm_buf_base_addr_1; | |
1550 | u32 dma_frm_buf_ceiling_addr_1; | |
1551 | u32 raster_ctrl; | |
1552 | } reg_context; | |
1553 | ||
1554 | static void lcd_context_save(void) | |
1555 | { | |
1556 | if (lcd_revision == LCD_VERSION_2) { | |
1557 | reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); | |
1558 | reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); | |
1559 | } | |
1560 | ||
1561 | reg_context.ctrl = lcdc_read(LCD_CTRL_REG); | |
1562 | reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); | |
1563 | reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); | |
1564 | reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); | |
1565 | reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
1566 | reg_context.dma_frm_buf_base_addr_0 = | |
1567 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1568 | reg_context.dma_frm_buf_ceiling_addr_0 = | |
1569 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1570 | reg_context.dma_frm_buf_base_addr_1 = | |
1571 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1572 | reg_context.dma_frm_buf_ceiling_addr_1 = | |
1573 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1574 | reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); | |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | static void lcd_context_restore(void) | |
1579 | { | |
1580 | if (lcd_revision == LCD_VERSION_2) { | |
1581 | lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); | |
1582 | lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); | |
1583 | } | |
1584 | ||
1585 | lcdc_write(reg_context.ctrl, LCD_CTRL_REG); | |
1586 | lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); | |
1587 | lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); | |
1588 | lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); | |
1589 | lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); | |
1590 | lcdc_write(reg_context.dma_frm_buf_base_addr_0, | |
1591 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1592 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, | |
1593 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1594 | lcdc_write(reg_context.dma_frm_buf_base_addr_1, | |
1595 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1596 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, | |
1597 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1598 | lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); | |
1599 | return; | |
1600 | } | |
1601 | ||
622f7c9b | 1602 | static int fb_suspend(struct device *dev) |
4ed824d9 | 1603 | { |
622f7c9b | 1604 | struct fb_info *info = dev_get_drvdata(dev); |
1d3c6c7b C |
1605 | struct da8xx_fb_par *par = info->par; |
1606 | ||
ac751efa | 1607 | console_lock(); |
1d3c6c7b C |
1608 | if (par->panel_power_ctrl) |
1609 | par->panel_power_ctrl(0); | |
1610 | ||
1611 | fb_set_suspend(info, 1); | |
26e71645 | 1612 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
7a93cbbb | 1613 | lcd_context_save(); |
622f7c9b | 1614 | pm_runtime_put_sync(dev); |
ac751efa | 1615 | console_unlock(); |
1d3c6c7b C |
1616 | |
1617 | return 0; | |
4ed824d9 | 1618 | } |
622f7c9b | 1619 | static int fb_resume(struct device *dev) |
4ed824d9 | 1620 | { |
622f7c9b | 1621 | struct fb_info *info = dev_get_drvdata(dev); |
1d3c6c7b C |
1622 | struct da8xx_fb_par *par = info->par; |
1623 | ||
ac751efa | 1624 | console_lock(); |
622f7c9b | 1625 | pm_runtime_get_sync(dev); |
7a93cbbb | 1626 | lcd_context_restore(); |
67900814 MP |
1627 | if (par->blank == FB_BLANK_UNBLANK) { |
1628 | lcd_enable_raster(); | |
f7c848b6 | 1629 | |
67900814 MP |
1630 | if (par->panel_power_ctrl) |
1631 | par->panel_power_ctrl(1); | |
1632 | } | |
1d3c6c7b | 1633 | |
1d3c6c7b | 1634 | fb_set_suspend(info, 0); |
ac751efa | 1635 | console_unlock(); |
1d3c6c7b C |
1636 | |
1637 | return 0; | |
4ed824d9 | 1638 | } |
4ed824d9 SR |
1639 | #endif |
1640 | ||
622f7c9b MB |
1641 | static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume); |
1642 | ||
4ed824d9 SR |
1643 | static struct platform_driver da8xx_fb_driver = { |
1644 | .probe = fb_probe, | |
48c68c4f | 1645 | .remove = fb_remove, |
4ed824d9 SR |
1646 | .driver = { |
1647 | .name = DRIVER_NAME, | |
622f7c9b | 1648 | .pm = &fb_pm_ops, |
4ed824d9 SR |
1649 | }, |
1650 | }; | |
44f544f7 | 1651 | module_platform_driver(da8xx_fb_driver); |
4ed824d9 SR |
1652 | |
1653 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1654 | MODULE_AUTHOR("Texas Instruments"); | |
1655 | MODULE_LICENSE("GPL"); |