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Commit | Line | Data |
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7c2f891c | 1 | /* |
7c2f891c SH |
2 | * Freescale i.MX Frame Buffer device driver |
3 | * | |
4 | * Copyright (C) 2004 Sascha Hauer, Pengutronix | |
5 | * Based on acornfb.c Copyright (C) Russell King. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | * | |
11 | * Please direct your questions and comments on this driver to the following | |
12 | * email address: | |
13 | * | |
14 | * linux-arm-kernel@lists.arm.linux.org.uk | |
15 | */ | |
16 | ||
7c2f891c SH |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
7c2f891c SH |
19 | #include <linux/errno.h> |
20 | #include <linux/string.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/slab.h> | |
27ac792c | 23 | #include <linux/mm.h> |
7c2f891c SH |
24 | #include <linux/fb.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/cpufreq.h> | |
f909ef64 | 29 | #include <linux/clk.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
7c2f891c | 31 | #include <linux/dma-mapping.h> |
72330b0e | 32 | #include <linux/io.h> |
9fe21fdc | 33 | #include <linux/lcd.h> |
f909ef64 | 34 | #include <linux/math64.h> |
1b6c7936 MP |
35 | #include <linux/of.h> |
36 | #include <linux/of_device.h> | |
37 | ||
9fe21fdc AS |
38 | #include <linux/regulator/consumer.h> |
39 | ||
1b6c7936 MP |
40 | #include <video/of_display_timing.h> |
41 | #include <video/of_videomode.h> | |
42 | #include <video/videomode.h> | |
7c2f891c | 43 | |
82906b13 | 44 | #include <linux/platform_data/video-imxfb.h> |
7c2f891c SH |
45 | |
46 | /* | |
47 | * Complain if VAR is out of range. | |
48 | */ | |
49 | #define DEBUG_VAR 1 | |
50 | ||
72330b0e JB |
51 | #define DRIVER_NAME "imx-fb" |
52 | ||
53 | #define LCDC_SSA 0x00 | |
54 | ||
55 | #define LCDC_SIZE 0x04 | |
56 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | |
1d0f9870 | 57 | |
e69dc9a9 SG |
58 | #define YMAX_MASK_IMX1 0x1ff |
59 | #define YMAX_MASK_IMX21 0x3ff | |
72330b0e JB |
60 | |
61 | #define LCDC_VPW 0x08 | |
62 | #define VPW_VPW(x) ((x) & 0x3ff) | |
63 | ||
64 | #define LCDC_CPOS 0x0C | |
65 | #define CPOS_CC1 (1<<31) | |
66 | #define CPOS_CC0 (1<<30) | |
67 | #define CPOS_OP (1<<28) | |
68 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | |
1d0f9870 | 69 | |
72330b0e JB |
70 | #define LCDC_LCWHB 0x10 |
71 | #define LCWHB_BK_EN (1<<31) | |
72 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | |
73 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | |
74 | #define LCWHB_BD(x) ((x) & 0xff) | |
75 | ||
76 | #define LCDC_LCHCC 0x14 | |
1d0f9870 | 77 | |
72330b0e JB |
78 | #define LCDC_PCR 0x18 |
79 | ||
80 | #define LCDC_HCR 0x1C | |
81 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | |
82 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | |
83 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | |
84 | ||
85 | #define LCDC_VCR 0x20 | |
86 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | |
87 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | |
88 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | |
89 | ||
90 | #define LCDC_POS 0x24 | |
91 | #define POS_POS(x) ((x) & 1f) | |
92 | ||
93 | #define LCDC_LSCR1 0x28 | |
94 | /* bit fields in imxfb.h */ | |
95 | ||
96 | #define LCDC_PWMR 0x2C | |
97 | /* bit fields in imxfb.h */ | |
98 | ||
99 | #define LCDC_DMACR 0x30 | |
100 | /* bit fields in imxfb.h */ | |
101 | ||
102 | #define LCDC_RMCR 0x34 | |
1d0f9870 | 103 | |
f142b619 | 104 | #define RMCR_LCDC_EN_MX1 (1<<1) |
1d0f9870 | 105 | |
72330b0e JB |
106 | #define RMCR_SELF_REF (1<<0) |
107 | ||
108 | #define LCDC_LCDICR 0x38 | |
109 | #define LCDICR_INT_SYN (1<<2) | |
110 | #define LCDICR_INT_CON (1) | |
111 | ||
112 | #define LCDC_LCDISR 0x40 | |
113 | #define LCDISR_UDR_ERR (1<<3) | |
114 | #define LCDISR_ERR_RES (1<<2) | |
115 | #define LCDISR_EOF (1<<1) | |
116 | #define LCDISR_BOF (1<<0) | |
117 | ||
1b6c7936 MP |
118 | #define IMXFB_LSCR1_DEFAULT 0x00120300 |
119 | ||
b62ea411 MK |
120 | #define LCDC_LAUSCR 0x80 |
121 | #define LAUSCR_AUS_MODE (1<<31) | |
122 | ||
343684ff SH |
123 | /* Used fb-mode. Can be set on kernel command line, therefore file-static. */ |
124 | static const char *fb_mode; | |
125 | ||
24b9baf7 SH |
126 | /* |
127 | * These are the bitfields for each | |
128 | * display depth that we support. | |
129 | */ | |
130 | struct imxfb_rgb { | |
131 | struct fb_bitfield red; | |
132 | struct fb_bitfield green; | |
133 | struct fb_bitfield blue; | |
134 | struct fb_bitfield transp; | |
135 | }; | |
136 | ||
e69dc9a9 SG |
137 | enum imxfb_type { |
138 | IMX1_FB, | |
139 | IMX21_FB, | |
140 | }; | |
141 | ||
24b9baf7 SH |
142 | struct imxfb_info { |
143 | struct platform_device *pdev; | |
144 | void __iomem *regs; | |
13aaea03 SH |
145 | struct clk *clk_ipg; |
146 | struct clk *clk_ahb; | |
147 | struct clk *clk_per; | |
e69dc9a9 | 148 | enum imxfb_type devtype; |
e6b267ce | 149 | bool enabled; |
24b9baf7 | 150 | |
24b9baf7 SH |
151 | /* |
152 | * These are the addresses we mapped | |
153 | * the framebuffer memory region to. | |
154 | */ | |
155 | dma_addr_t map_dma; | |
24b9baf7 SH |
156 | u_int map_size; |
157 | ||
24b9baf7 SH |
158 | u_int palette_size; |
159 | ||
160 | dma_addr_t dbar1; | |
161 | dma_addr_t dbar2; | |
162 | ||
163 | u_int pcr; | |
b62ea411 | 164 | u_int lauscr; |
24b9baf7 SH |
165 | u_int pwmr; |
166 | u_int lscr1; | |
167 | u_int dmacr; | |
b7d2d372 AS |
168 | bool cmap_inverse; |
169 | bool cmap_static; | |
24b9baf7 | 170 | |
343684ff SH |
171 | struct imx_fb_videomode *mode; |
172 | int num_modes; | |
173 | ||
9fe21fdc | 174 | struct regulator *lcd_pwr; |
5c694f80 | 175 | int lcd_pwr_enabled; |
24b9baf7 SH |
176 | }; |
177 | ||
bd388a2c | 178 | static const struct platform_device_id imxfb_devtype[] = { |
e69dc9a9 SG |
179 | { |
180 | .name = "imx1-fb", | |
181 | .driver_data = IMX1_FB, | |
182 | }, { | |
183 | .name = "imx21-fb", | |
184 | .driver_data = IMX21_FB, | |
185 | }, { | |
186 | /* sentinel */ | |
187 | } | |
188 | }; | |
189 | MODULE_DEVICE_TABLE(platform, imxfb_devtype); | |
190 | ||
5d802441 | 191 | static const struct of_device_id imxfb_of_dev_id[] = { |
1b6c7936 MP |
192 | { |
193 | .compatible = "fsl,imx1-fb", | |
194 | .data = &imxfb_devtype[IMX1_FB], | |
195 | }, { | |
196 | .compatible = "fsl,imx21-fb", | |
197 | .data = &imxfb_devtype[IMX21_FB], | |
198 | }, { | |
199 | /* sentinel */ | |
200 | } | |
201 | }; | |
202 | MODULE_DEVICE_TABLE(of, imxfb_of_dev_id); | |
203 | ||
e69dc9a9 SG |
204 | static inline int is_imx1_fb(struct imxfb_info *fbi) |
205 | { | |
206 | return fbi->devtype == IMX1_FB; | |
207 | } | |
208 | ||
24b9baf7 SH |
209 | #define IMX_NAME "IMX" |
210 | ||
211 | /* | |
212 | * Minimum X and Y resolutions | |
213 | */ | |
214 | #define MIN_XRES 64 | |
215 | #define MIN_YRES 64 | |
216 | ||
1512222b SH |
217 | /* Actually this really is 18bit support, the lowest 2 bits of each colour |
218 | * are unused in hardware. We claim to have 24bit support to make software | |
219 | * like X work, which does not support 18bit. | |
220 | */ | |
221 | static struct imxfb_rgb def_rgb_18 = { | |
222 | .red = {.offset = 16, .length = 8,}, | |
223 | .green = {.offset = 8, .length = 8,}, | |
224 | .blue = {.offset = 0, .length = 8,}, | |
225 | .transp = {.offset = 0, .length = 0,}, | |
226 | }; | |
227 | ||
80eee6bc SH |
228 | static struct imxfb_rgb def_rgb_16_tft = { |
229 | .red = {.offset = 11, .length = 5,}, | |
230 | .green = {.offset = 5, .length = 6,}, | |
231 | .blue = {.offset = 0, .length = 5,}, | |
232 | .transp = {.offset = 0, .length = 0,}, | |
233 | }; | |
234 | ||
235 | static struct imxfb_rgb def_rgb_16_stn = { | |
66c8719b SH |
236 | .red = {.offset = 8, .length = 4,}, |
237 | .green = {.offset = 4, .length = 4,}, | |
238 | .blue = {.offset = 0, .length = 4,}, | |
239 | .transp = {.offset = 0, .length = 0,}, | |
7c2f891c SH |
240 | }; |
241 | ||
242 | static struct imxfb_rgb def_rgb_8 = { | |
66c8719b SH |
243 | .red = {.offset = 0, .length = 8,}, |
244 | .green = {.offset = 0, .length = 8,}, | |
245 | .blue = {.offset = 0, .length = 8,}, | |
246 | .transp = {.offset = 0, .length = 0,}, | |
7c2f891c SH |
247 | }; |
248 | ||
66c8719b SH |
249 | static int imxfb_activate_var(struct fb_var_screeninfo *var, |
250 | struct fb_info *info); | |
7c2f891c SH |
251 | |
252 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
253 | { | |
254 | chan &= 0xffff; | |
255 | chan >>= 16 - bf->length; | |
256 | return chan << bf->offset; | |
257 | } | |
258 | ||
66c8719b SH |
259 | static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, |
260 | u_int trans, struct fb_info *info) | |
7c2f891c SH |
261 | { |
262 | struct imxfb_info *fbi = info->par; | |
263 | u_int val, ret = 1; | |
264 | ||
265 | #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) | |
266 | if (regno < fbi->palette_size) { | |
267 | val = (CNVT_TOHW(red, 4) << 8) | | |
268 | (CNVT_TOHW(green,4) << 4) | | |
269 | CNVT_TOHW(blue, 4); | |
270 | ||
72330b0e | 271 | writel(val, fbi->regs + 0x800 + (regno << 2)); |
7c2f891c SH |
272 | ret = 0; |
273 | } | |
274 | return ret; | |
275 | } | |
276 | ||
66c8719b | 277 | static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
7c2f891c SH |
278 | u_int trans, struct fb_info *info) |
279 | { | |
280 | struct imxfb_info *fbi = info->par; | |
281 | unsigned int val; | |
282 | int ret = 1; | |
283 | ||
284 | /* | |
285 | * If inverse mode was selected, invert all the colours | |
286 | * rather than the register number. The register number | |
287 | * is what you poke into the framebuffer to produce the | |
288 | * colour you requested. | |
289 | */ | |
290 | if (fbi->cmap_inverse) { | |
291 | red = 0xffff - red; | |
292 | green = 0xffff - green; | |
293 | blue = 0xffff - blue; | |
294 | } | |
295 | ||
296 | /* | |
297 | * If greyscale is true, then we convert the RGB value | |
298 | * to greyscale no mater what visual we are using. | |
299 | */ | |
300 | if (info->var.grayscale) | |
301 | red = green = blue = (19595 * red + 38470 * green + | |
302 | 7471 * blue) >> 16; | |
303 | ||
304 | switch (info->fix.visual) { | |
305 | case FB_VISUAL_TRUECOLOR: | |
306 | /* | |
307 | * 12 or 16-bit True Colour. We encode the RGB value | |
308 | * according to the RGB bitfield information. | |
309 | */ | |
310 | if (regno < 16) { | |
311 | u32 *pal = info->pseudo_palette; | |
312 | ||
313 | val = chan_to_field(red, &info->var.red); | |
314 | val |= chan_to_field(green, &info->var.green); | |
315 | val |= chan_to_field(blue, &info->var.blue); | |
316 | ||
317 | pal[regno] = val; | |
318 | ret = 0; | |
319 | } | |
320 | break; | |
321 | ||
322 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
323 | case FB_VISUAL_PSEUDOCOLOR: | |
324 | ret = imxfb_setpalettereg(regno, red, green, blue, trans, info); | |
325 | break; | |
326 | } | |
327 | ||
328 | return ret; | |
329 | } | |
330 | ||
343684ff SH |
331 | static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi) |
332 | { | |
333 | struct imx_fb_videomode *m; | |
334 | int i; | |
335 | ||
1b6c7936 MP |
336 | if (!fb_mode) |
337 | return &fbi->mode[0]; | |
338 | ||
343684ff SH |
339 | for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) { |
340 | if (!strcmp(m->mode.name, fb_mode)) | |
341 | return m; | |
342 | } | |
343 | return NULL; | |
344 | } | |
345 | ||
7c2f891c SH |
346 | /* |
347 | * imxfb_check_var(): | |
348 | * Round up in the following order: bits_per_pixel, xres, | |
349 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
350 | * bitfields, horizontal timing, vertical timing. | |
351 | */ | |
66c8719b | 352 | static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
7c2f891c SH |
353 | { |
354 | struct imxfb_info *fbi = info->par; | |
80eee6bc | 355 | struct imxfb_rgb *rgb; |
343684ff SH |
356 | const struct imx_fb_videomode *imxfb_mode; |
357 | unsigned long lcd_clk; | |
358 | unsigned long long tmp; | |
359 | u32 pcr = 0; | |
7c2f891c SH |
360 | |
361 | if (var->xres < MIN_XRES) | |
362 | var->xres = MIN_XRES; | |
363 | if (var->yres < MIN_YRES) | |
364 | var->yres = MIN_YRES; | |
343684ff SH |
365 | |
366 | imxfb_mode = imxfb_find_mode(fbi); | |
367 | if (!imxfb_mode) | |
368 | return -EINVAL; | |
369 | ||
370 | var->xres = imxfb_mode->mode.xres; | |
371 | var->yres = imxfb_mode->mode.yres; | |
372 | var->bits_per_pixel = imxfb_mode->bpp; | |
373 | var->pixclock = imxfb_mode->mode.pixclock; | |
374 | var->hsync_len = imxfb_mode->mode.hsync_len; | |
375 | var->left_margin = imxfb_mode->mode.left_margin; | |
376 | var->right_margin = imxfb_mode->mode.right_margin; | |
377 | var->vsync_len = imxfb_mode->mode.vsync_len; | |
378 | var->upper_margin = imxfb_mode->mode.upper_margin; | |
379 | var->lower_margin = imxfb_mode->mode.lower_margin; | |
380 | var->sync = imxfb_mode->mode.sync; | |
381 | var->xres_virtual = max(var->xres_virtual, var->xres); | |
382 | var->yres_virtual = max(var->yres_virtual, var->yres); | |
7c2f891c SH |
383 | |
384 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); | |
343684ff | 385 | |
13aaea03 | 386 | lcd_clk = clk_get_rate(fbi->clk_per); |
343684ff SH |
387 | |
388 | tmp = var->pixclock * (unsigned long long)lcd_clk; | |
389 | ||
390 | do_div(tmp, 1000000); | |
391 | ||
392 | if (do_div(tmp, 1000000) > 500000) | |
393 | tmp++; | |
394 | ||
395 | pcr = (unsigned int)tmp; | |
396 | ||
397 | if (--pcr > 0x3F) { | |
398 | pcr = 0x3F; | |
399 | printk(KERN_WARNING "Must limit pixel clock to %luHz\n", | |
400 | lcd_clk / pcr); | |
401 | } | |
402 | ||
7c2f891c | 403 | switch (var->bits_per_pixel) { |
1512222b | 404 | case 32: |
343684ff | 405 | pcr |= PCR_BPIX_18; |
1512222b SH |
406 | rgb = &def_rgb_18; |
407 | break; | |
7c2f891c | 408 | case 16: |
80eee6bc | 409 | default: |
e69dc9a9 | 410 | if (is_imx1_fb(fbi)) |
343684ff SH |
411 | pcr |= PCR_BPIX_12; |
412 | else | |
413 | pcr |= PCR_BPIX_16; | |
414 | ||
415 | if (imxfb_mode->pcr & PCR_TFT) | |
80eee6bc SH |
416 | rgb = &def_rgb_16_tft; |
417 | else | |
418 | rgb = &def_rgb_16_stn; | |
7c2f891c SH |
419 | break; |
420 | case 8: | |
343684ff | 421 | pcr |= PCR_BPIX_8; |
80eee6bc | 422 | rgb = &def_rgb_8; |
7c2f891c | 423 | break; |
7c2f891c SH |
424 | } |
425 | ||
343684ff SH |
426 | /* add sync polarities */ |
427 | pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25)); | |
428 | ||
429 | fbi->pcr = pcr; | |
b62ea411 MK |
430 | /* |
431 | * The LCDC AUS Mode Control Register does not exist on imx1. | |
432 | */ | |
433 | if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode) | |
434 | fbi->lauscr = LAUSCR_AUS_MODE; | |
343684ff | 435 | |
7c2f891c SH |
436 | /* |
437 | * Copy the RGB parameters for this display | |
438 | * from the machine specific parameters. | |
439 | */ | |
80eee6bc SH |
440 | var->red = rgb->red; |
441 | var->green = rgb->green; | |
442 | var->blue = rgb->blue; | |
443 | var->transp = rgb->transp; | |
7c2f891c SH |
444 | |
445 | pr_debug("RGBT length = %d:%d:%d:%d\n", | |
446 | var->red.length, var->green.length, var->blue.length, | |
447 | var->transp.length); | |
448 | ||
449 | pr_debug("RGBT offset = %d:%d:%d:%d\n", | |
450 | var->red.offset, var->green.offset, var->blue.offset, | |
451 | var->transp.offset); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | /* | |
457 | * imxfb_set_par(): | |
458 | * Set the user defined part of the display for the specified console | |
459 | */ | |
460 | static int imxfb_set_par(struct fb_info *info) | |
461 | { | |
462 | struct imxfb_info *fbi = info->par; | |
463 | struct fb_var_screeninfo *var = &info->var; | |
464 | ||
1512222b | 465 | if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) |
7c2f891c SH |
466 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
467 | else if (!fbi->cmap_static) | |
468 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
469 | else { | |
470 | /* | |
471 | * Some people have weird ideas about wanting static | |
472 | * pseudocolor maps. I suspect their user space | |
473 | * applications are broken. | |
474 | */ | |
475 | info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
476 | } | |
477 | ||
66c8719b | 478 | info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; |
7c2f891c SH |
479 | fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; |
480 | ||
481 | imxfb_activate_var(var, info); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
cc6df3a2 | 486 | static int imxfb_enable_controller(struct imxfb_info *fbi) |
7c2f891c | 487 | { |
cc6df3a2 | 488 | int ret; |
e6b267ce FE |
489 | |
490 | if (fbi->enabled) | |
cc6df3a2 | 491 | return 0; |
e6b267ce | 492 | |
7c2f891c SH |
493 | pr_debug("Enabling LCD controller\n"); |
494 | ||
b7d2d372 | 495 | writel(fbi->map_dma, fbi->regs + LCDC_SSA); |
7c2f891c | 496 | |
72330b0e JB |
497 | /* panning offset 0 (0 pixel offset) */ |
498 | writel(0x00000000, fbi->regs + LCDC_POS); | |
7c2f891c SH |
499 | |
500 | /* disable hardware cursor */ | |
72330b0e JB |
501 | writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), |
502 | fbi->regs + LCDC_CPOS); | |
7c2f891c | 503 | |
f142b619 SH |
504 | /* |
505 | * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt | |
506 | * on other SoCs | |
507 | */ | |
508 | writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR); | |
7c2f891c | 509 | |
cc6df3a2 UKK |
510 | ret = clk_prepare_enable(fbi->clk_ipg); |
511 | if (ret) | |
512 | goto err_enable_ipg; | |
513 | ||
514 | ret = clk_prepare_enable(fbi->clk_ahb); | |
515 | if (ret) | |
516 | goto err_enable_ahb; | |
517 | ||
518 | ret = clk_prepare_enable(fbi->clk_per); | |
519 | if (ret) | |
520 | goto err_enable_per; | |
521 | ||
e6b267ce | 522 | fbi->enabled = true; |
cc6df3a2 UKK |
523 | return 0; |
524 | ||
525 | err_enable_per: | |
526 | clk_disable_unprepare(fbi->clk_ahb); | |
527 | err_enable_ahb: | |
528 | clk_disable_unprepare(fbi->clk_ipg); | |
529 | err_enable_ipg: | |
530 | writel(0, fbi->regs + LCDC_RMCR); | |
531 | ||
532 | return ret; | |
7c2f891c SH |
533 | } |
534 | ||
535 | static void imxfb_disable_controller(struct imxfb_info *fbi) | |
536 | { | |
e6b267ce FE |
537 | if (!fbi->enabled) |
538 | return; | |
539 | ||
7c2f891c SH |
540 | pr_debug("Disabling LCD controller\n"); |
541 | ||
13aaea03 | 542 | clk_disable_unprepare(fbi->clk_per); |
13aaea03 | 543 | clk_disable_unprepare(fbi->clk_ahb); |
cc6df3a2 | 544 | clk_disable_unprepare(fbi->clk_ipg); |
e6b267ce | 545 | fbi->enabled = false; |
f909ef64 | 546 | |
72330b0e | 547 | writel(0, fbi->regs + LCDC_RMCR); |
7c2f891c SH |
548 | } |
549 | ||
550 | static int imxfb_blank(int blank, struct fb_info *info) | |
551 | { | |
552 | struct imxfb_info *fbi = info->par; | |
553 | ||
554 | pr_debug("imxfb_blank: blank=%d\n", blank); | |
555 | ||
556 | switch (blank) { | |
557 | case FB_BLANK_POWERDOWN: | |
558 | case FB_BLANK_VSYNC_SUSPEND: | |
559 | case FB_BLANK_HSYNC_SUSPEND: | |
560 | case FB_BLANK_NORMAL: | |
561 | imxfb_disable_controller(fbi); | |
562 | break; | |
563 | ||
564 | case FB_BLANK_UNBLANK: | |
cc6df3a2 | 565 | return imxfb_enable_controller(fbi); |
7c2f891c SH |
566 | } |
567 | return 0; | |
568 | } | |
569 | ||
8a48ac33 | 570 | static const struct fb_ops imxfb_ops = { |
7c2f891c SH |
571 | .owner = THIS_MODULE, |
572 | .fb_check_var = imxfb_check_var, | |
573 | .fb_set_par = imxfb_set_par, | |
574 | .fb_setcolreg = imxfb_setcolreg, | |
575 | .fb_fillrect = cfb_fillrect, | |
576 | .fb_copyarea = cfb_copyarea, | |
577 | .fb_imageblit = cfb_imageblit, | |
578 | .fb_blank = imxfb_blank, | |
7c2f891c SH |
579 | }; |
580 | ||
581 | /* | |
582 | * imxfb_activate_var(): | |
583 | * Configures LCD Controller based on entries in var parameter. Settings are | |
584 | * only written to the controller if changes were made. | |
585 | */ | |
586 | static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
587 | { | |
588 | struct imxfb_info *fbi = info->par; | |
e69dc9a9 | 589 | u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21; |
f909ef64 | 590 | |
7c2f891c SH |
591 | pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", |
592 | var->xres, var->hsync_len, | |
593 | var->left_margin, var->right_margin); | |
594 | pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n", | |
595 | var->yres, var->vsync_len, | |
596 | var->upper_margin, var->lower_margin); | |
597 | ||
598 | #if DEBUG_VAR | |
599 | if (var->xres < 16 || var->xres > 1024) | |
600 | printk(KERN_ERR "%s: invalid xres %d\n", | |
601 | info->fix.id, var->xres); | |
602 | if (var->hsync_len < 1 || var->hsync_len > 64) | |
603 | printk(KERN_ERR "%s: invalid hsync_len %d\n", | |
604 | info->fix.id, var->hsync_len); | |
605 | if (var->left_margin > 255) | |
606 | printk(KERN_ERR "%s: invalid left_margin %d\n", | |
607 | info->fix.id, var->left_margin); | |
608 | if (var->right_margin > 255) | |
609 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
610 | info->fix.id, var->right_margin); | |
e69dc9a9 | 611 | if (var->yres < 1 || var->yres > ymax_mask) |
7c2f891c SH |
612 | printk(KERN_ERR "%s: invalid yres %d\n", |
613 | info->fix.id, var->yres); | |
614 | if (var->vsync_len > 100) | |
615 | printk(KERN_ERR "%s: invalid vsync_len %d\n", | |
616 | info->fix.id, var->vsync_len); | |
617 | if (var->upper_margin > 63) | |
618 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
619 | info->fix.id, var->upper_margin); | |
620 | if (var->lower_margin > 255) | |
621 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
622 | info->fix.id, var->lower_margin); | |
623 | #endif | |
624 | ||
343684ff SH |
625 | /* physical screen start address */ |
626 | writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4), | |
627 | fbi->regs + LCDC_VPW); | |
628 | ||
7e8549bc SH |
629 | writel(HCR_H_WIDTH(var->hsync_len - 1) | |
630 | HCR_H_WAIT_1(var->right_margin - 1) | | |
631 | HCR_H_WAIT_2(var->left_margin - 3), | |
72330b0e | 632 | fbi->regs + LCDC_HCR); |
7c2f891c | 633 | |
72330b0e | 634 | writel(VCR_V_WIDTH(var->vsync_len) | |
d6ed5755 SH |
635 | VCR_V_WAIT_1(var->lower_margin) | |
636 | VCR_V_WAIT_2(var->upper_margin), | |
72330b0e | 637 | fbi->regs + LCDC_VCR); |
7c2f891c | 638 | |
e69dc9a9 | 639 | writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask), |
72330b0e | 640 | fbi->regs + LCDC_SIZE); |
f909ef64 | 641 | |
343684ff | 642 | writel(fbi->pcr, fbi->regs + LCDC_PCR); |
1b6c7936 MP |
643 | if (fbi->pwmr) |
644 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); | |
72330b0e | 645 | writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); |
1b6c7936 MP |
646 | |
647 | /* dmacr = 0 is no valid value, as we need DMA control marks. */ | |
648 | if (fbi->dmacr) | |
649 | writel(fbi->dmacr, fbi->regs + LCDC_DMACR); | |
7c2f891c | 650 | |
b62ea411 MK |
651 | if (fbi->lauscr) |
652 | writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR); | |
653 | ||
7c2f891c SH |
654 | return 0; |
655 | } | |
656 | ||
1b6c7936 | 657 | static int imxfb_init_fbinfo(struct platform_device *pdev) |
7c2f891c | 658 | { |
1c8034c7 | 659 | struct imx_fb_platform_data *pdata = dev_get_platdata(&pdev->dev); |
72330b0e | 660 | struct fb_info *info = dev_get_drvdata(&pdev->dev); |
7c2f891c | 661 | struct imxfb_info *fbi = info->par; |
1b6c7936 | 662 | struct device_node *np; |
7c2f891c | 663 | |
5ae12170 | 664 | pr_debug("%s\n",__func__); |
7c2f891c | 665 | |
6da2ec56 | 666 | info->pseudo_palette = kmalloc_array(16, sizeof(u32), GFP_KERNEL); |
7c2f891c SH |
667 | if (!info->pseudo_palette) |
668 | return -ENOMEM; | |
669 | ||
670 | memset(fbi, 0, sizeof(struct imxfb_info)); | |
7c2f891c | 671 | |
afc10301 GGM |
672 | fbi->devtype = pdev->id_entry->driver_data; |
673 | ||
7c2f891c SH |
674 | strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); |
675 | ||
66c8719b | 676 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
7c2f891c SH |
677 | info->fix.type_aux = 0; |
678 | info->fix.xpanstep = 0; | |
679 | info->fix.ypanstep = 0; | |
680 | info->fix.ywrapstep = 0; | |
66c8719b | 681 | info->fix.accel = FB_ACCEL_NONE; |
7c2f891c SH |
682 | |
683 | info->var.nonstd = 0; | |
684 | info->var.activate = FB_ACTIVATE_NOW; | |
685 | info->var.height = -1; | |
686 | info->var.width = -1; | |
687 | info->var.accel_flags = 0; | |
66c8719b | 688 | info->var.vmode = FB_VMODE_NONINTERLACED; |
7c2f891c SH |
689 | |
690 | info->fbops = &imxfb_ops; | |
66c8719b SH |
691 | info->flags = FBINFO_FLAG_DEFAULT | |
692 | FBINFO_READS_FAST; | |
1b6c7936 | 693 | if (pdata) { |
1b6c7936 MP |
694 | fbi->lscr1 = pdata->lscr1; |
695 | fbi->dmacr = pdata->dmacr; | |
696 | fbi->pwmr = pdata->pwmr; | |
1b6c7936 MP |
697 | } else { |
698 | np = pdev->dev.of_node; | |
699 | info->var.grayscale = of_property_read_bool(np, | |
700 | "cmap-greyscale"); | |
701 | fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse"); | |
702 | fbi->cmap_static = of_property_read_bool(np, "cmap-static"); | |
703 | ||
704 | fbi->lscr1 = IMXFB_LSCR1_DEFAULT; | |
cf071d2a DC |
705 | |
706 | of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr); | |
707 | ||
1b6c7936 MP |
708 | of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1); |
709 | ||
710 | of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); | |
1b6c7936 MP |
711 | } |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int imxfb_of_read_mode(struct device *dev, struct device_node *np, | |
717 | struct imx_fb_videomode *imxfb_mode) | |
718 | { | |
719 | int ret; | |
720 | struct fb_videomode *of_mode = &imxfb_mode->mode; | |
721 | u32 bpp; | |
722 | u32 pcr; | |
723 | ||
724 | ret = of_property_read_string(np, "model", &of_mode->name); | |
725 | if (ret) | |
726 | of_mode->name = NULL; | |
727 | ||
728 | ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE); | |
729 | if (ret) { | |
730 | dev_err(dev, "Failed to get videomode from DT\n"); | |
731 | return ret; | |
732 | } | |
733 | ||
734 | ret = of_property_read_u32(np, "bits-per-pixel", &bpp); | |
735 | ret |= of_property_read_u32(np, "fsl,pcr", &pcr); | |
736 | ||
737 | if (ret) { | |
738 | dev_err(dev, "Failed to read bpp and pcr from DT\n"); | |
739 | return -EINVAL; | |
740 | } | |
741 | ||
742 | if (bpp < 1 || bpp > 255) { | |
743 | dev_err(dev, "Bits per pixel have to be between 1 and 255\n"); | |
744 | return -EINVAL; | |
745 | } | |
746 | ||
747 | imxfb_mode->bpp = bpp; | |
748 | imxfb_mode->pcr = pcr; | |
7c2f891c | 749 | |
b62ea411 MK |
750 | /* |
751 | * fsl,aus-mode is optional | |
752 | */ | |
753 | imxfb_mode->aus_mode = of_property_read_bool(np, "fsl,aus-mode"); | |
754 | ||
7c2f891c SH |
755 | return 0; |
756 | } | |
757 | ||
9fe21fdc AS |
758 | static int imxfb_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi) |
759 | { | |
760 | struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); | |
761 | ||
762 | if (!fi || fi->par == fbi) | |
763 | return 1; | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
f590f99a AS |
768 | static int imxfb_lcd_get_contrast(struct lcd_device *lcddev) |
769 | { | |
770 | struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); | |
771 | ||
772 | return fbi->pwmr & 0xff; | |
773 | } | |
774 | ||
775 | static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast) | |
776 | { | |
777 | struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); | |
778 | ||
779 | if (fbi->pwmr && fbi->enabled) { | |
780 | if (contrast > 255) | |
781 | contrast = 255; | |
782 | else if (contrast < 0) | |
783 | contrast = 0; | |
784 | ||
785 | fbi->pwmr &= ~0xff; | |
786 | fbi->pwmr |= contrast; | |
787 | ||
788 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); | |
789 | } | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
9fe21fdc AS |
794 | static int imxfb_lcd_get_power(struct lcd_device *lcddev) |
795 | { | |
796 | struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); | |
797 | ||
46ffe109 UKK |
798 | if (!IS_ERR(fbi->lcd_pwr) && |
799 | !regulator_is_enabled(fbi->lcd_pwr)) | |
800 | return FB_BLANK_POWERDOWN; | |
9fe21fdc | 801 | |
46ffe109 | 802 | return FB_BLANK_UNBLANK; |
9fe21fdc AS |
803 | } |
804 | ||
5c694f80 UKK |
805 | static int imxfb_regulator_set(struct imxfb_info *fbi, int enable) |
806 | { | |
807 | int ret; | |
808 | ||
809 | if (enable == fbi->lcd_pwr_enabled) | |
810 | return 0; | |
811 | ||
812 | if (enable) | |
813 | ret = regulator_enable(fbi->lcd_pwr); | |
814 | else | |
815 | ret = regulator_disable(fbi->lcd_pwr); | |
816 | ||
817 | if (ret == 0) | |
818 | fbi->lcd_pwr_enabled = enable; | |
819 | ||
820 | return ret; | |
821 | } | |
822 | ||
9fe21fdc AS |
823 | static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power) |
824 | { | |
825 | struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); | |
826 | ||
5c694f80 UKK |
827 | if (!IS_ERR(fbi->lcd_pwr)) |
828 | return imxfb_regulator_set(fbi, power == FB_BLANK_UNBLANK); | |
9fe21fdc AS |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
833 | static struct lcd_ops imxfb_lcd_ops = { | |
834 | .check_fb = imxfb_lcd_check_fb, | |
f590f99a AS |
835 | .get_contrast = imxfb_lcd_get_contrast, |
836 | .set_contrast = imxfb_lcd_set_contrast, | |
9fe21fdc AS |
837 | .get_power = imxfb_lcd_get_power, |
838 | .set_power = imxfb_lcd_set_power, | |
839 | }; | |
840 | ||
de501362 AS |
841 | static int imxfb_setup(void) |
842 | { | |
843 | char *opt, *options = NULL; | |
844 | ||
845 | if (fb_get_options("imxfb", &options)) | |
846 | return -ENODEV; | |
847 | ||
848 | if (!options || !*options) | |
849 | return 0; | |
850 | ||
851 | while ((opt = strsep(&options, ",")) != NULL) { | |
852 | if (!*opt) | |
853 | continue; | |
854 | else | |
855 | fb_mode = opt; | |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
1b6c7936 | 861 | static int imxfb_probe(struct platform_device *pdev) |
7c2f891c | 862 | { |
7c2f891c | 863 | struct imxfb_info *fbi; |
9fe21fdc | 864 | struct lcd_device *lcd; |
7c2f891c | 865 | struct fb_info *info; |
27889273 | 866 | struct imx_fb_platform_data *pdata; |
7c2f891c | 867 | struct resource *res; |
1b6c7936 MP |
868 | struct imx_fb_videomode *m; |
869 | const struct of_device_id *of_id; | |
343684ff | 870 | int ret, i; |
1b6c7936 | 871 | int bytes_per_pixel; |
7c2f891c | 872 | |
d6b51502 | 873 | dev_info(&pdev->dev, "i.MX Framebuffer driver\n"); |
7c2f891c | 874 | |
de501362 AS |
875 | ret = imxfb_setup(); |
876 | if (ret < 0) | |
877 | return ret; | |
878 | ||
1b6c7936 MP |
879 | of_id = of_match_device(imxfb_of_dev_id, &pdev->dev); |
880 | if (of_id) | |
881 | pdev->id_entry = of_id->data; | |
882 | ||
7c2f891c | 883 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
66c8719b | 884 | if (!res) |
7c2f891c SH |
885 | return -ENODEV; |
886 | ||
1c8034c7 | 887 | pdata = dev_get_platdata(&pdev->dev); |
7c2f891c | 888 | |
3ae5eaec | 889 | info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); |
66c8719b | 890 | if (!info) |
7c2f891c SH |
891 | return -ENOMEM; |
892 | ||
893 | fbi = info->par; | |
894 | ||
3ae5eaec | 895 | platform_set_drvdata(pdev, info); |
7c2f891c | 896 | |
72330b0e | 897 | ret = imxfb_init_fbinfo(pdev); |
66c8719b | 898 | if (ret < 0) |
7c2f891c SH |
899 | goto failed_init; |
900 | ||
1b6c7936 MP |
901 | if (pdata) { |
902 | if (!fb_mode) | |
903 | fb_mode = pdata->mode[0].mode.name; | |
904 | ||
905 | fbi->mode = pdata->mode; | |
906 | fbi->num_modes = pdata->num_modes; | |
907 | } else { | |
908 | struct device_node *display_np; | |
909 | fb_mode = NULL; | |
910 | ||
911 | display_np = of_parse_phandle(pdev->dev.of_node, "display", 0); | |
912 | if (!display_np) { | |
913 | dev_err(&pdev->dev, "No display defined in devicetree\n"); | |
914 | ret = -EINVAL; | |
915 | goto failed_of_parse; | |
916 | } | |
917 | ||
918 | /* | |
919 | * imxfb does not support more modes, we choose only the native | |
920 | * mode. | |
921 | */ | |
922 | fbi->num_modes = 1; | |
923 | ||
924 | fbi->mode = devm_kzalloc(&pdev->dev, | |
925 | sizeof(struct imx_fb_videomode), GFP_KERNEL); | |
926 | if (!fbi->mode) { | |
927 | ret = -ENOMEM; | |
928 | goto failed_of_parse; | |
929 | } | |
930 | ||
931 | ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode); | |
932 | if (ret) | |
933 | goto failed_of_parse; | |
934 | } | |
935 | ||
936 | /* Calculate maximum bytes used per pixel. In most cases this should | |
937 | * be the same as m->bpp/8 */ | |
938 | m = &fbi->mode[0]; | |
939 | bytes_per_pixel = (m->bpp + 7) / 8; | |
940 | for (i = 0; i < fbi->num_modes; i++, m++) | |
941 | info->fix.smem_len = max_t(size_t, info->fix.smem_len, | |
942 | m->mode.xres * m->mode.yres * bytes_per_pixel); | |
943 | ||
72330b0e JB |
944 | res = request_mem_region(res->start, resource_size(res), |
945 | DRIVER_NAME); | |
7c2f891c SH |
946 | if (!res) { |
947 | ret = -EBUSY; | |
72330b0e JB |
948 | goto failed_req; |
949 | } | |
950 | ||
13aaea03 SH |
951 | fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
952 | if (IS_ERR(fbi->clk_ipg)) { | |
953 | ret = PTR_ERR(fbi->clk_ipg); | |
954 | goto failed_getclock; | |
955 | } | |
956 | ||
b82fe6dd FE |
957 | /* |
958 | * The LCDC controller does not have an enable bit. The | |
959 | * controller starts directly when the clocks are enabled. | |
960 | * If the clocks are enabled when the controller is not yet | |
961 | * programmed with proper register values (enabled at the | |
962 | * bootloader, for example) then it just goes into some undefined | |
963 | * state. | |
964 | * To avoid this issue, let's enable and disable LCDC IPG clock | |
965 | * so that we force some kind of 'reset' to the LCDC block. | |
966 | */ | |
967 | ret = clk_prepare_enable(fbi->clk_ipg); | |
968 | if (ret) | |
969 | goto failed_getclock; | |
970 | clk_disable_unprepare(fbi->clk_ipg); | |
971 | ||
13aaea03 SH |
972 | fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
973 | if (IS_ERR(fbi->clk_ahb)) { | |
974 | ret = PTR_ERR(fbi->clk_ahb); | |
975 | goto failed_getclock; | |
976 | } | |
977 | ||
978 | fbi->clk_per = devm_clk_get(&pdev->dev, "per"); | |
979 | if (IS_ERR(fbi->clk_per)) { | |
980 | ret = PTR_ERR(fbi->clk_per); | |
f909ef64 SH |
981 | goto failed_getclock; |
982 | } | |
983 | ||
72330b0e JB |
984 | fbi->regs = ioremap(res->start, resource_size(res)); |
985 | if (fbi->regs == NULL) { | |
d6b51502 | 986 | dev_err(&pdev->dev, "Cannot map frame buffer registers\n"); |
caf0a5c9 | 987 | ret = -ENOMEM; |
72330b0e | 988 | goto failed_ioremap; |
7c2f891c SH |
989 | } |
990 | ||
b7d2d372 | 991 | fbi->map_size = PAGE_ALIGN(info->fix.smem_len); |
739a6439 BZ |
992 | info->screen_buffer = dma_alloc_wc(&pdev->dev, fbi->map_size, |
993 | &fbi->map_dma, GFP_KERNEL); | |
732146a3 | 994 | if (!info->screen_buffer) { |
b7d2d372 AS |
995 | dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); |
996 | ret = -ENOMEM; | |
997 | goto failed_map; | |
7c2f891c SH |
998 | } |
999 | ||
b7d2d372 AS |
1000 | info->fix.smem_start = fbi->map_dma; |
1001 | ||
1b6c7936 | 1002 | if (pdata && pdata->init) { |
c0b90a31 SH |
1003 | ret = pdata->init(fbi->pdev); |
1004 | if (ret) | |
1005 | goto failed_platform_init; | |
1006 | } | |
1007 | ||
343684ff SH |
1008 | |
1009 | INIT_LIST_HEAD(&info->modelist); | |
1b6c7936 MP |
1010 | for (i = 0; i < fbi->num_modes; i++) |
1011 | fb_add_videomode(&fbi->mode[i].mode, &info->modelist); | |
343684ff | 1012 | |
7c2f891c SH |
1013 | /* |
1014 | * This makes sure that our colour bitfield | |
1015 | * descriptors are correctly initialised. | |
1016 | */ | |
1017 | imxfb_check_var(&info->var, info); | |
1018 | ||
dc312120 MK |
1019 | /* |
1020 | * For modes > 8bpp, the color map is bypassed. | |
1021 | * Therefore, 256 entries are enough. | |
1022 | */ | |
1023 | ret = fb_alloc_cmap(&info->cmap, 256, 0); | |
7c2f891c SH |
1024 | if (ret < 0) |
1025 | goto failed_cmap; | |
1026 | ||
7c2f891c SH |
1027 | imxfb_set_par(info); |
1028 | ret = register_framebuffer(info); | |
1029 | if (ret < 0) { | |
f99c8929 | 1030 | dev_err(&pdev->dev, "failed to register framebuffer\n"); |
7c2f891c SH |
1031 | goto failed_register; |
1032 | } | |
1033 | ||
9fe21fdc | 1034 | fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd"); |
45586c70 | 1035 | if (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER) { |
9fe21fdc AS |
1036 | ret = -EPROBE_DEFER; |
1037 | goto failed_lcd; | |
1038 | } | |
1039 | ||
1040 | lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi, | |
1041 | &imxfb_lcd_ops); | |
1042 | if (IS_ERR(lcd)) { | |
1043 | ret = PTR_ERR(lcd); | |
1044 | goto failed_lcd; | |
1045 | } | |
1046 | ||
f590f99a AS |
1047 | lcd->props.max_contrast = 0xff; |
1048 | ||
7c2f891c | 1049 | imxfb_enable_controller(fbi); |
7a2bb23c | 1050 | fbi->pdev = pdev; |
7c2f891c SH |
1051 | |
1052 | return 0; | |
1053 | ||
9fe21fdc AS |
1054 | failed_lcd: |
1055 | unregister_framebuffer(info); | |
1056 | ||
7c2f891c SH |
1057 | failed_register: |
1058 | fb_dealloc_cmap(&info->cmap); | |
1059 | failed_cmap: | |
1b6c7936 | 1060 | if (pdata && pdata->exit) |
c0b90a31 SH |
1061 | pdata->exit(fbi->pdev); |
1062 | failed_platform_init: | |
739a6439 | 1063 | dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, |
f6e45661 | 1064 | fbi->map_dma); |
7c2f891c | 1065 | failed_map: |
72330b0e JB |
1066 | iounmap(fbi->regs); |
1067 | failed_ioremap: | |
609d3bbf | 1068 | failed_getclock: |
d6b51502 | 1069 | release_mem_region(res->start, resource_size(res)); |
72330b0e | 1070 | failed_req: |
1b6c7936 | 1071 | failed_of_parse: |
72330b0e | 1072 | kfree(info->pseudo_palette); |
7c2f891c | 1073 | failed_init: |
7c2f891c SH |
1074 | framebuffer_release(info); |
1075 | return ret; | |
1076 | } | |
1077 | ||
48c68c4f | 1078 | static int imxfb_remove(struct platform_device *pdev) |
7c2f891c | 1079 | { |
c0b90a31 | 1080 | struct imx_fb_platform_data *pdata; |
3ae5eaec | 1081 | struct fb_info *info = platform_get_drvdata(pdev); |
772a9e63 | 1082 | struct imxfb_info *fbi = info->par; |
7c2f891c SH |
1083 | struct resource *res; |
1084 | ||
1085 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1086 | ||
772a9e63 | 1087 | imxfb_disable_controller(fbi); |
7c2f891c SH |
1088 | |
1089 | unregister_framebuffer(info); | |
5ae29649 | 1090 | fb_dealloc_cmap(&info->cmap); |
1c8034c7 | 1091 | pdata = dev_get_platdata(&pdev->dev); |
1b6c7936 | 1092 | if (pdata && pdata->exit) |
c0b90a31 | 1093 | pdata->exit(fbi->pdev); |
739a6439 | 1094 | dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, |
f6e45661 | 1095 | fbi->map_dma); |
72330b0e | 1096 | iounmap(fbi->regs); |
d6b51502 | 1097 | release_mem_region(res->start, resource_size(res)); |
5ae29649 DC |
1098 | kfree(info->pseudo_palette); |
1099 | framebuffer_release(info); | |
f909ef64 | 1100 | |
7c2f891c SH |
1101 | return 0; |
1102 | } | |
1103 | ||
f1d2ff8b | 1104 | static int __maybe_unused imxfb_suspend(struct device *dev) |
7c2f891c | 1105 | { |
f1d2ff8b | 1106 | struct fb_info *info = dev_get_drvdata(dev); |
772a9e63 | 1107 | struct imxfb_info *fbi = info->par; |
f1d2ff8b | 1108 | |
772a9e63 | 1109 | imxfb_disable_controller(fbi); |
f1d2ff8b AS |
1110 | |
1111 | return 0; | |
7c2f891c SH |
1112 | } |
1113 | ||
f1d2ff8b AS |
1114 | static int __maybe_unused imxfb_resume(struct device *dev) |
1115 | { | |
1116 | struct fb_info *info = dev_get_drvdata(dev); | |
1117 | struct imxfb_info *fbi = info->par; | |
1118 | ||
1119 | imxfb_enable_controller(fbi); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume); | |
1125 | ||
3ae5eaec | 1126 | static struct platform_driver imxfb_driver = { |
3ae5eaec | 1127 | .driver = { |
72330b0e | 1128 | .name = DRIVER_NAME, |
1b6c7936 | 1129 | .of_match_table = imxfb_of_dev_id, |
f1d2ff8b | 1130 | .pm = &imxfb_pm_ops, |
3ae5eaec | 1131 | }, |
f1d2ff8b AS |
1132 | .probe = imxfb_probe, |
1133 | .remove = imxfb_remove, | |
e69dc9a9 | 1134 | .id_table = imxfb_devtype, |
7c2f891c | 1135 | }; |
de501362 | 1136 | module_platform_driver(imxfb_driver); |
7c2f891c | 1137 | |
e3d5fb71 | 1138 | MODULE_DESCRIPTION("Freescale i.MX framebuffer driver"); |
7c2f891c SH |
1139 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1140 | MODULE_LICENSE("GPL"); |