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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.h | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #ifndef __OMAP2_DSS_H | |
24 | #define __OMAP2_DSS_H | |
25 | ||
96e2e637 TV |
26 | #include <linux/interrupt.h> |
27 | ||
702d267e CM |
28 | #ifdef pr_fmt |
29 | #undef pr_fmt | |
559d6701 TV |
30 | #endif |
31 | ||
702d267e CM |
32 | #ifdef DSS_SUBSYS_NAME |
33 | #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt | |
34 | #else | |
35 | #define pr_fmt(fmt) fmt | |
559d6701 TV |
36 | #endif |
37 | ||
702d267e CM |
38 | #define DSSDBG(format, ...) \ |
39 | pr_debug(format, ## __VA_ARGS__) | |
559d6701 TV |
40 | |
41 | #ifdef DSS_SUBSYS_NAME | |
42 | #define DSSERR(format, ...) \ | |
43 | printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ | |
44 | ## __VA_ARGS__) | |
45 | #else | |
46 | #define DSSERR(format, ...) \ | |
47 | printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) | |
48 | #endif | |
49 | ||
50 | #ifdef DSS_SUBSYS_NAME | |
51 | #define DSSINFO(format, ...) \ | |
52 | printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ | |
53 | ## __VA_ARGS__) | |
54 | #else | |
55 | #define DSSINFO(format, ...) \ | |
56 | printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) | |
57 | #endif | |
58 | ||
59 | #ifdef DSS_SUBSYS_NAME | |
60 | #define DSSWARN(format, ...) \ | |
61 | printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ | |
62 | ## __VA_ARGS__) | |
63 | #else | |
64 | #define DSSWARN(format, ...) \ | |
65 | printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) | |
66 | #endif | |
67 | ||
68 | /* OMAP TRM gives bitfields as start:end, where start is the higher bit | |
69 | number. For example 7:0 */ | |
70 | #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) | |
71 | #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) | |
72 | #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) | |
73 | #define FLD_MOD(orig, val, start, end) \ | |
74 | (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) | |
75 | ||
569969d6 AT |
76 | enum dss_io_pad_mode { |
77 | DSS_IO_PAD_MODE_RESET, | |
78 | DSS_IO_PAD_MODE_RFBI, | |
79 | DSS_IO_PAD_MODE_BYPASS, | |
559d6701 TV |
80 | }; |
81 | ||
7ed024aa M |
82 | enum dss_hdmi_venc_clk_source_select { |
83 | DSS_VENC_TV_CLK = 0, | |
84 | DSS_HDMI_M_PCLK = 1, | |
85 | }; | |
86 | ||
6ff8aa31 AT |
87 | enum dss_dsi_content_type { |
88 | DSS_DSI_CONTENT_DCS, | |
89 | DSS_DSI_CONTENT_GENERIC, | |
90 | }; | |
91 | ||
d9ac773c AT |
92 | enum dss_writeback_channel { |
93 | DSS_WB_LCD1_MGR = 0, | |
94 | DSS_WB_LCD2_MGR = 1, | |
95 | DSS_WB_TV_MGR = 2, | |
96 | DSS_WB_OVL0 = 3, | |
97 | DSS_WB_OVL1 = 4, | |
98 | DSS_WB_OVL2 = 5, | |
99 | DSS_WB_OVL3 = 6, | |
100 | DSS_WB_LCD3_MGR = 7, | |
101 | }; | |
102 | ||
64e22ffd TV |
103 | enum dss_pll_id { |
104 | DSS_PLL_DSI1, | |
105 | DSS_PLL_DSI2, | |
106 | DSS_PLL_HDMI, | |
6d817880 TV |
107 | DSS_PLL_VIDEO1, |
108 | DSS_PLL_VIDEO2, | |
64e22ffd TV |
109 | }; |
110 | ||
0a20170a TV |
111 | struct dss_pll; |
112 | ||
113 | #define DSS_PLL_MAX_HSDIVS 4 | |
114 | ||
115 | /* | |
116 | * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. | |
117 | * Type-B PLLs: clkout[0] refers to m2. | |
118 | */ | |
119 | struct dss_pll_clock_info { | |
120 | /* rates that we get with dividers below */ | |
121 | unsigned long fint; | |
122 | unsigned long clkdco; | |
123 | unsigned long clkout[DSS_PLL_MAX_HSDIVS]; | |
124 | ||
125 | /* dividers */ | |
126 | u16 n; | |
127 | u16 m; | |
128 | u32 mf; | |
129 | u16 mX[DSS_PLL_MAX_HSDIVS]; | |
130 | u16 sd; | |
131 | }; | |
132 | ||
133 | struct dss_pll_ops { | |
134 | int (*enable)(struct dss_pll *pll); | |
135 | void (*disable)(struct dss_pll *pll); | |
136 | int (*set_config)(struct dss_pll *pll, | |
137 | const struct dss_pll_clock_info *cinfo); | |
138 | }; | |
139 | ||
140 | struct dss_pll_hw { | |
141 | unsigned n_max; | |
142 | unsigned m_min; | |
143 | unsigned m_max; | |
144 | unsigned mX_max; | |
145 | ||
146 | unsigned long fint_min, fint_max; | |
147 | unsigned long clkdco_min, clkdco_low, clkdco_max; | |
148 | ||
149 | u8 n_msb, n_lsb; | |
150 | u8 m_msb, m_lsb; | |
151 | u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS]; | |
152 | ||
153 | bool has_stopmode; | |
154 | bool has_freqsel; | |
155 | bool has_selfreqdco; | |
156 | bool has_refsel; | |
157 | }; | |
158 | ||
159 | struct dss_pll { | |
160 | const char *name; | |
64e22ffd | 161 | enum dss_pll_id id; |
0a20170a TV |
162 | |
163 | struct clk *clkin; | |
164 | struct regulator *regulator; | |
165 | ||
166 | void __iomem *base; | |
167 | ||
168 | const struct dss_pll_hw *hw; | |
169 | ||
170 | const struct dss_pll_ops *ops; | |
171 | ||
172 | struct dss_pll_clock_info cinfo; | |
173 | }; | |
174 | ||
559d6701 TV |
175 | struct dispc_clock_info { |
176 | /* rates that we get with dividers below */ | |
177 | unsigned long lck; | |
178 | unsigned long pck; | |
179 | ||
180 | /* dividers */ | |
181 | u16 lck_div; | |
182 | u16 pck_div; | |
183 | }; | |
184 | ||
c56fb3ef AT |
185 | struct dss_lcd_mgr_config { |
186 | enum dss_io_pad_mode io_pad_mode; | |
187 | ||
188 | bool stallmode; | |
189 | bool fifohandcheck; | |
190 | ||
191 | struct dispc_clock_info clock_info; | |
192 | ||
193 | int video_port_width; | |
194 | ||
195 | int lcden_sig_polarity; | |
196 | }; | |
197 | ||
559d6701 TV |
198 | struct seq_file; |
199 | struct platform_device; | |
200 | ||
201 | /* core */ | |
8f46efad | 202 | struct platform_device *dss_get_core_pdev(void); |
00928eaf TV |
203 | int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); |
204 | void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); | |
a8081d31 | 205 | int dss_set_min_bus_tput(struct device *dev, unsigned long tput); |
e40402cf | 206 | int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); |
559d6701 TV |
207 | |
208 | /* display */ | |
209 | int dss_suspend_all_devices(void); | |
210 | int dss_resume_all_devices(void); | |
211 | void dss_disable_all_devices(void); | |
212 | ||
94140f0d TV |
213 | int display_init_sysfs(struct platform_device *pdev); |
214 | void display_uninit_sysfs(struct platform_device *pdev); | |
559d6701 TV |
215 | |
216 | /* manager */ | |
7f7cdbd6 TV |
217 | int dss_init_overlay_managers(void); |
218 | void dss_uninit_overlay_managers(void); | |
219 | int dss_init_overlay_managers_sysfs(struct platform_device *pdev); | |
220 | void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev); | |
54540d41 TV |
221 | int dss_mgr_simple_check(struct omap_overlay_manager *mgr, |
222 | const struct omap_overlay_manager_info *info); | |
b917fa39 AT |
223 | int dss_mgr_check_timings(struct omap_overlay_manager *mgr, |
224 | const struct omap_video_timings *timings); | |
6ac48d1e | 225 | int dss_mgr_check(struct omap_overlay_manager *mgr, |
6ac48d1e | 226 | struct omap_overlay_manager_info *info, |
228b2134 | 227 | const struct omap_video_timings *mgr_timings, |
6e543595 | 228 | const struct dss_lcd_mgr_config *config, |
6ac48d1e | 229 | struct omap_overlay_info **overlay_infos); |
559d6701 | 230 | |
f476ae9d AT |
231 | static inline bool dss_mgr_is_lcd(enum omap_channel id) |
232 | { | |
233 | if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || | |
234 | id == OMAP_DSS_CHANNEL_LCD3) | |
235 | return true; | |
236 | else | |
237 | return false; | |
238 | } | |
239 | ||
f6a0492e TV |
240 | int dss_manager_kobj_init(struct omap_overlay_manager *mgr, |
241 | struct platform_device *pdev); | |
242 | void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr); | |
243 | ||
559d6701 TV |
244 | /* overlay */ |
245 | void dss_init_overlays(struct platform_device *pdev); | |
246 | void dss_uninit_overlays(struct platform_device *pdev); | |
559d6701 | 247 | void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); |
54540d41 TV |
248 | int dss_ovl_simple_check(struct omap_overlay *ovl, |
249 | const struct omap_overlay_info *info); | |
228b2134 AT |
250 | int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info, |
251 | const struct omap_video_timings *mgr_timings); | |
6c6f510a AT |
252 | bool dss_ovl_use_replication(struct dss_lcd_mgr_config config, |
253 | enum omap_color_mode mode); | |
91691516 TV |
254 | int dss_overlay_kobj_init(struct omap_overlay *ovl, |
255 | struct platform_device *pdev); | |
256 | void dss_overlay_kobj_uninit(struct omap_overlay *ovl); | |
559d6701 TV |
257 | |
258 | /* DSS */ | |
6e7e8f06 | 259 | int dss_init_platform_driver(void) __init; |
96c401bc | 260 | void dss_uninit_platform_driver(void); |
559d6701 | 261 | |
99767548 TV |
262 | int dss_runtime_get(void); |
263 | void dss_runtime_put(void); | |
264 | ||
5aaee69d | 265 | unsigned long dss_get_dispc_clk_rate(void); |
064c2a47 | 266 | int dss_dpi_select_source(int port, enum omap_channel channel); |
7ed024aa | 267 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); |
4a61e267 | 268 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); |
89a35e51 | 269 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src); |
8b9cb3a8 | 270 | void dss_dump_clocks(struct seq_file *s); |
559d6701 | 271 | |
99767548 TV |
272 | /* DSS VIDEO PLL */ |
273 | struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, | |
274 | struct regulator *regulator); | |
275 | void dss_video_pll_uninit(struct dss_pll *pll); | |
276 | ||
ef691ff4 AT |
277 | /* dss-of */ |
278 | struct device_node *dss_of_port_get_parent_device(struct device_node *port); | |
279 | u32 dss_of_port_get_port_number(struct device_node *port); | |
280 | ||
1b3bcb33 | 281 | #if defined(CONFIG_OMAP2_DSS_DEBUGFS) |
8b9cb3a8 SG |
282 | void dss_debug_dump_clocks(struct seq_file *s); |
283 | #endif | |
559d6701 | 284 | |
be40eecf TV |
285 | void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); |
286 | void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id, | |
287 | enum omap_channel channel); | |
288 | ||
889b4fd7 | 289 | void dss_sdi_init(int datapairs); |
559d6701 TV |
290 | int dss_sdi_enable(void); |
291 | void dss_sdi_disable(void); | |
292 | ||
5a8b572d AT |
293 | void dss_select_dsi_clk_source(int dsi_module, |
294 | enum omap_dss_clk_source clk_src); | |
ea75159e | 295 | void dss_select_lcd_clk_source(enum omap_channel channel, |
89a35e51 AT |
296 | enum omap_dss_clk_source clk_src); |
297 | enum omap_dss_clk_source dss_get_dispc_clk_source(void); | |
5a8b572d | 298 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module); |
89a35e51 | 299 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); |
2f18c4d8 | 300 | |
559d6701 TV |
301 | void dss_set_venc_output(enum omap_dss_venc_type type); |
302 | void dss_set_dac_pwrdn_bgz(bool enable); | |
303 | ||
d0f58bd3 | 304 | int dss_set_fck_rate(unsigned long rate); |
559d6701 | 305 | |
d0f58bd3 | 306 | typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); |
688af02d TV |
307 | bool dss_div_calc(unsigned long pck, unsigned long fck_min, |
308 | dss_div_calc_func func, void *data); | |
43417823 | 309 | |
559d6701 | 310 | /* SDI */ |
6e7e8f06 | 311 | int sdi_init_platform_driver(void) __init; |
ede92695 | 312 | void sdi_uninit_platform_driver(void); |
559d6701 | 313 | |
387ce9f2 | 314 | #ifdef CONFIG_OMAP2_DSS_SDI |
ede92695 TV |
315 | int sdi_init_port(struct platform_device *pdev, struct device_node *port); |
316 | void sdi_uninit_port(struct device_node *port); | |
387ce9f2 | 317 | #else |
ede92695 | 318 | static inline int sdi_init_port(struct platform_device *pdev, |
387ce9f2 AT |
319 | struct device_node *port) |
320 | { | |
321 | return 0; | |
322 | } | |
ede92695 | 323 | static inline void sdi_uninit_port(struct device_node *port) |
387ce9f2 AT |
324 | { |
325 | } | |
326 | #endif | |
2ecef246 | 327 | |
559d6701 | 328 | /* DSI */ |
989c79a8 | 329 | |
368a148e | 330 | #ifdef CONFIG_OMAP2_DSS_DSI |
5a8b572d AT |
331 | |
332 | struct dentry; | |
333 | struct file_operations; | |
334 | ||
6e7e8f06 | 335 | int dsi_init_platform_driver(void) __init; |
ede92695 | 336 | void dsi_uninit_platform_driver(void); |
559d6701 TV |
337 | |
338 | void dsi_dump_clocks(struct seq_file *s); | |
559d6701 | 339 | |
559d6701 | 340 | void dsi_irq_handler(void); |
a3b3cc2b AT |
341 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt); |
342 | ||
368a148e | 343 | #else |
a3b3cc2b AT |
344 | static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
345 | { | |
85d90b12 DC |
346 | WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n", |
347 | __func__); | |
a3b3cc2b AT |
348 | return 0; |
349 | } | |
368a148e | 350 | #endif |
559d6701 TV |
351 | |
352 | /* DPI */ | |
6e7e8f06 | 353 | int dpi_init_platform_driver(void) __init; |
ede92695 | 354 | void dpi_uninit_platform_driver(void); |
559d6701 | 355 | |
387ce9f2 | 356 | #ifdef CONFIG_OMAP2_DSS_DPI |
ede92695 TV |
357 | int dpi_init_port(struct platform_device *pdev, struct device_node *port); |
358 | void dpi_uninit_port(struct device_node *port); | |
387ce9f2 | 359 | #else |
ede92695 | 360 | static inline int dpi_init_port(struct platform_device *pdev, |
387ce9f2 AT |
361 | struct device_node *port) |
362 | { | |
363 | return 0; | |
364 | } | |
ede92695 | 365 | static inline void dpi_uninit_port(struct device_node *port) |
387ce9f2 AT |
366 | { |
367 | } | |
368 | #endif | |
2ecef246 | 369 | |
559d6701 | 370 | /* DISPC */ |
6e7e8f06 | 371 | int dispc_init_platform_driver(void) __init; |
ede92695 | 372 | void dispc_uninit_platform_driver(void); |
559d6701 | 373 | void dispc_dump_clocks(struct seq_file *s); |
559d6701 TV |
374 | |
375 | void dispc_enable_sidle(void); | |
376 | void dispc_disable_sidle(void); | |
377 | ||
559d6701 TV |
378 | void dispc_lcd_enable_signal(bool enable); |
379 | void dispc_pck_free_enable(bool enable); | |
cd295aeb TV |
380 | void dispc_enable_fifomerge(bool enable); |
381 | void dispc_enable_gamma_table(bool enable); | |
cd295aeb | 382 | |
7c284e6e TV |
383 | typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, |
384 | unsigned long pck, void *data); | |
385 | bool dispc_div_calc(unsigned long dispc, | |
386 | unsigned long pck_min, unsigned long pck_max, | |
387 | dispc_div_calc_func func, void *data); | |
388 | ||
8f366162 | 389 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
b917fa39 | 390 | const struct omap_video_timings *timings); |
cd295aeb TV |
391 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, |
392 | struct dispc_clock_info *cinfo); | |
393 | ||
394 | ||
6f04e1bf | 395 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high); |
83fa2f2e | 396 | void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, |
3568f2a4 TV |
397 | u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, |
398 | bool manual_update); | |
348be69d | 399 | |
f0d08f89 | 400 | void dispc_mgr_set_clock_div(enum omap_channel channel, |
a8f3fcd1 | 401 | const struct dispc_clock_info *cinfo); |
26d9dd0d | 402 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 403 | struct dispc_clock_info *cinfo); |
5391e87d | 404 | void dispc_set_tv_pclk(unsigned long pclk); |
559d6701 | 405 | |
0b23e5b8 AT |
406 | u32 dispc_wb_get_framedone_irq(void); |
407 | bool dispc_wb_go_busy(void); | |
408 | void dispc_wb_go(void); | |
409 | void dispc_wb_enable(bool enable); | |
410 | bool dispc_wb_is_enabled(void); | |
d9ac773c | 411 | void dispc_wb_set_channel_in(enum dss_writeback_channel channel); |
749feffa | 412 | int dispc_wb_setup(const struct omap_dss_writeback_info *wi, |
9e4a0fc7 | 413 | bool mem_to_mem, const struct omap_video_timings *timings); |
d9ac773c | 414 | |
559d6701 | 415 | /* VENC */ |
6e7e8f06 | 416 | int venc_init_platform_driver(void) __init; |
ede92695 | 417 | void venc_uninit_platform_driver(void); |
559d6701 | 418 | |
c3198a5e | 419 | /* HDMI */ |
ef26958a | 420 | int hdmi4_init_platform_driver(void) __init; |
ede92695 | 421 | void hdmi4_uninit_platform_driver(void); |
c3198a5e | 422 | |
f5bab222 | 423 | int hdmi5_init_platform_driver(void) __init; |
ede92695 | 424 | void hdmi5_uninit_platform_driver(void); |
f5bab222 | 425 | |
559d6701 | 426 | /* RFBI */ |
6e7e8f06 | 427 | int rfbi_init_platform_driver(void) __init; |
ede92695 | 428 | void rfbi_uninit_platform_driver(void); |
559d6701 | 429 | |
dfc0fd8d TV |
430 | |
431 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
432 | static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) | |
433 | { | |
434 | int b; | |
435 | for (b = 0; b < 32; ++b) { | |
436 | if (irqstatus & (1 << b)) | |
437 | irq_arr[b]++; | |
438 | } | |
439 | } | |
440 | #endif | |
441 | ||
0a20170a TV |
442 | /* PLL */ |
443 | typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint, | |
444 | unsigned long clkdco, void *data); | |
445 | typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, | |
446 | void *data); | |
447 | ||
448 | int dss_pll_register(struct dss_pll *pll); | |
449 | void dss_pll_unregister(struct dss_pll *pll); | |
450 | struct dss_pll *dss_pll_find(const char *name); | |
451 | int dss_pll_enable(struct dss_pll *pll); | |
452 | void dss_pll_disable(struct dss_pll *pll); | |
453 | int dss_pll_set_config(struct dss_pll *pll, | |
454 | const struct dss_pll_clock_info *cinfo); | |
455 | ||
456 | bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, | |
457 | unsigned long out_min, unsigned long out_max, | |
458 | dss_hsdiv_calc_func func, void *data); | |
459 | bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, | |
460 | unsigned long pll_min, unsigned long pll_max, | |
461 | dss_pll_calc_func func, void *data); | |
462 | int dss_pll_write_config_type_a(struct dss_pll *pll, | |
463 | const struct dss_pll_clock_info *cinfo); | |
464 | int dss_pll_write_config_type_b(struct dss_pll *pll, | |
465 | const struct dss_pll_clock_info *cinfo); | |
eb30199b | 466 | int dss_pll_wait_reset_done(struct dss_pll *pll); |
0a20170a | 467 | |
559d6701 | 468 | #endif |