]>
Commit | Line | Data |
---|---|---|
7d983f39 M |
1 | /* |
2 | * ti_hdmi_4xxx_ip.c | |
3 | * | |
4 | * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
ac9f2421 TV |
22 | #define DSS_SUBSYS_NAME "HDMICORE" |
23 | ||
7d983f39 M |
24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
425f02fd | 31 | #include <linux/platform_device.h> |
7d983f39 | 32 | #include <linux/string.h> |
162874d5 | 33 | #include <linux/seq_file.h> |
7e151f7f | 34 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
199e7fd6 | 35 | #include <sound/asound.h> |
6ec355d6 | 36 | #include <sound/asoundef.h> |
199e7fd6 | 37 | #endif |
7d983f39 | 38 | |
ef26958a | 39 | #include "hdmi4_core.h" |
6ec355d6 | 40 | #include "dss_features.h" |
7d983f39 | 41 | |
425f02fd AT |
42 | #define HDMI_CORE_AV 0x500 |
43 | ||
425f02fd | 44 | static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) |
7d983f39 | 45 | { |
425f02fd | 46 | return core->base + HDMI_CORE_AV; |
7d983f39 M |
47 | } |
48 | ||
425f02fd | 49 | static int hdmi_core_ddc_init(struct hdmi_core_data *core) |
7d983f39 | 50 | { |
425f02fd | 51 | void __iomem *base = core->base; |
7d983f39 M |
52 | |
53 | /* Turn on CLK for DDC */ | |
032b8ea5 TV |
54 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); |
55 | ||
56 | /* IN_PROG */ | |
57 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { | |
58 | /* Abort transaction */ | |
59 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); | |
60 | /* IN_PROG */ | |
61 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
62 | 4, 4, 0) != 0) { | |
63 | DSSERR("Timeout aborting DDC transaction\n"); | |
64 | return -ETIMEDOUT; | |
65 | } | |
66 | } | |
7d983f39 | 67 | |
032b8ea5 TV |
68 | /* Clk SCL Devices */ |
69 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); | |
7d983f39 | 70 | |
032b8ea5 TV |
71 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
72 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
73 | 4, 4, 0) != 0) { | |
74 | DSSERR("Timeout starting SCL clock\n"); | |
75 | return -ETIMEDOUT; | |
76 | } | |
7d983f39 | 77 | |
032b8ea5 TV |
78 | /* Clear FIFO */ |
79 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); | |
7d983f39 | 80 | |
032b8ea5 TV |
81 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
82 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
83 | 4, 4, 0) != 0) { | |
84 | DSSERR("Timeout clearing DDC fifo\n"); | |
85 | return -ETIMEDOUT; | |
86 | } | |
7d983f39 | 87 | |
032b8ea5 TV |
88 | return 0; |
89 | } | |
7d983f39 | 90 | |
425f02fd | 91 | static int hdmi_core_ddc_edid(struct hdmi_core_data *core, |
032b8ea5 TV |
92 | u8 *pedid, int ext) |
93 | { | |
425f02fd | 94 | void __iomem *base = core->base; |
937fce13 TV |
95 | u32 i; |
96 | char checksum; | |
032b8ea5 TV |
97 | u32 offset = 0; |
98 | ||
99 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ | |
100 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, | |
101 | 4, 4, 0) != 0) { | |
102 | DSSERR("Timeout waiting DDC to be ready\n"); | |
103 | return -ETIMEDOUT; | |
7d983f39 M |
104 | } |
105 | ||
032b8ea5 TV |
106 | if (ext % 2 != 0) |
107 | offset = 0x80; | |
108 | ||
7d983f39 | 109 | /* Load Segment Address Register */ |
032b8ea5 | 110 | REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); |
7d983f39 M |
111 | |
112 | /* Load Slave Address Register */ | |
032b8ea5 | 113 | REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); |
7d983f39 M |
114 | |
115 | /* Load Offset Address Register */ | |
032b8ea5 | 116 | REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); |
7d983f39 M |
117 | |
118 | /* Load Byte Count */ | |
032b8ea5 TV |
119 | REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); |
120 | REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); | |
7d983f39 M |
121 | |
122 | /* Set DDC_CMD */ | |
123 | if (ext) | |
032b8ea5 | 124 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); |
7d983f39 | 125 | else |
032b8ea5 | 126 | REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); |
7d983f39 M |
127 | |
128 | /* HDMI_CORE_DDC_STATUS_BUS_LOW */ | |
032b8ea5 | 129 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { |
ac9f2421 | 130 | DSSERR("I2C Bus Low?\n"); |
7d983f39 M |
131 | return -EIO; |
132 | } | |
133 | /* HDMI_CORE_DDC_STATUS_NO_ACK */ | |
032b8ea5 | 134 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { |
ac9f2421 | 135 | DSSERR("I2C No Ack\n"); |
7d983f39 M |
136 | return -EIO; |
137 | } | |
138 | ||
937fce13 TV |
139 | for (i = 0; i < 0x80; ++i) { |
140 | int t; | |
7d983f39 | 141 | |
937fce13 TV |
142 | /* IN_PROG */ |
143 | if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { | |
144 | DSSERR("operation stopped when reading edid\n"); | |
145 | return -EIO; | |
146 | } | |
147 | ||
148 | t = 0; | |
149 | /* FIFO_EMPTY */ | |
150 | while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { | |
151 | if (t++ > 10000) { | |
152 | DSSERR("timeout reading edid\n"); | |
153 | return -ETIMEDOUT; | |
154 | } | |
155 | udelay(1); | |
7d983f39 | 156 | } |
937fce13 TV |
157 | |
158 | pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); | |
7d983f39 M |
159 | } |
160 | ||
937fce13 TV |
161 | checksum = 0; |
162 | for (i = 0; i < 0x80; ++i) | |
163 | checksum += pedid[i]; | |
7d983f39 M |
164 | |
165 | if (checksum != 0) { | |
ac9f2421 | 166 | DSSERR("E-EDID checksum failed!!\n"); |
7d983f39 M |
167 | return -EIO; |
168 | } | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
425f02fd | 173 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) |
7d983f39 | 174 | { |
937fce13 TV |
175 | int r, l; |
176 | ||
177 | if (len < 128) | |
178 | return -EINVAL; | |
7d983f39 | 179 | |
425f02fd | 180 | r = hdmi_core_ddc_init(core); |
032b8ea5 TV |
181 | if (r) |
182 | return r; | |
183 | ||
425f02fd | 184 | r = hdmi_core_ddc_edid(core, edid, 0); |
47024565 | 185 | if (r) |
7d983f39 | 186 | return r; |
47024565 | 187 | |
937fce13 | 188 | l = 128; |
47024565 | 189 | |
937fce13 | 190 | if (len >= 128 * 2 && edid[0x7e] > 0) { |
425f02fd | 191 | r = hdmi_core_ddc_edid(core, edid + 0x80, 1); |
47024565 TV |
192 | if (r) |
193 | return r; | |
937fce13 | 194 | l += 128; |
7d983f39 | 195 | } |
47024565 | 196 | |
937fce13 | 197 | return l; |
7d983f39 M |
198 | } |
199 | ||
200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |
7d983f39 M |
201 | struct hdmi_core_packet_enable_repeat *repeat_cfg) |
202 | { | |
ac9f2421 | 203 | DSSDBG("Enter hdmi_core_init\n"); |
7d983f39 M |
204 | |
205 | /* video core */ | |
206 | video_cfg->ip_bus_width = HDMI_INPUT_8BIT; | |
207 | video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; | |
208 | video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; | |
209 | video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; | |
210 | video_cfg->hdmi_dvi = HDMI_DVI; | |
211 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; | |
212 | ||
7d983f39 M |
213 | /* packet enable and repeat */ |
214 | repeat_cfg->audio_pkt = 0; | |
215 | repeat_cfg->audio_pkt_repeat = 0; | |
216 | repeat_cfg->avi_infoframe = 0; | |
217 | repeat_cfg->avi_infoframe_repeat = 0; | |
218 | repeat_cfg->gen_cntrl_pkt = 0; | |
219 | repeat_cfg->gen_cntrl_pkt_repeat = 0; | |
220 | repeat_cfg->generic_pkt = 0; | |
221 | repeat_cfg->generic_pkt_repeat = 0; | |
222 | } | |
223 | ||
425f02fd | 224 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
7d983f39 | 225 | { |
ac9f2421 | 226 | DSSDBG("Enter hdmi_core_powerdown_disable\n"); |
425f02fd | 227 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); |
7d983f39 M |
228 | } |
229 | ||
425f02fd | 230 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) |
7d983f39 | 231 | { |
ac9f2421 | 232 | DSSDBG("Enter hdmi_core_swreset_release\n"); |
425f02fd | 233 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
7d983f39 M |
234 | } |
235 | ||
425f02fd | 236 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) |
7d983f39 | 237 | { |
ac9f2421 | 238 | DSSDBG("Enter hdmi_core_swreset_assert\n"); |
425f02fd | 239 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
7d983f39 M |
240 | } |
241 | ||
242 | /* HDMI_CORE_VIDEO_CONFIG */ | |
425f02fd | 243 | static void hdmi_core_video_config(struct hdmi_core_data *core, |
7d983f39 M |
244 | struct hdmi_core_video_config *cfg) |
245 | { | |
246 | u32 r = 0; | |
425f02fd AT |
247 | void __iomem *core_sys_base = core->base; |
248 | void __iomem *core_av_base = hdmi_av_base(core); | |
7d983f39 M |
249 | |
250 | /* sys_ctrl1 default configuration not tunable */ | |
190d57c9 RN |
251 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); |
252 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); | |
253 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); | |
254 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); | |
255 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); | |
256 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); | |
7d983f39 M |
257 | |
258 | REG_FLD_MOD(core_sys_base, | |
259 | HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); | |
260 | ||
261 | /* Vid_Mode */ | |
262 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); | |
263 | ||
264 | /* dither truncation configuration */ | |
265 | if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { | |
266 | r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); | |
267 | r = FLD_MOD(r, 1, 5, 5); | |
268 | } else { | |
269 | r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); | |
270 | r = FLD_MOD(r, 0, 5, 5); | |
271 | } | |
272 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); | |
273 | ||
274 | /* HDMI_Ctrl */ | |
425f02fd | 275 | r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); |
7d983f39 M |
276 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); |
277 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); | |
278 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); | |
425f02fd | 279 | hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); |
7d983f39 M |
280 | |
281 | /* TMDS_CTRL */ | |
282 | REG_FLD_MOD(core_sys_base, | |
283 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); | |
284 | } | |
285 | ||
425f02fd | 286 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) |
7d983f39 | 287 | { |
425f02fd | 288 | void __iomem *av_base = hdmi_av_base(core); |
db85ca7c TV |
289 | struct hdmi_avi_infoframe *frame = &core->avi_infoframe; |
290 | u8 data[HDMI_INFOFRAME_SIZE(AVI)]; | |
291 | int i; | |
292 | ||
293 | hdmi_avi_infoframe_pack(frame, data, sizeof(data)); | |
294 | ||
295 | for (i = 0; i < sizeof(data); ++i) { | |
296 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, | |
297 | data[i]); | |
298 | } | |
7d983f39 M |
299 | } |
300 | ||
425f02fd | 301 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
7d983f39 M |
302 | struct hdmi_core_packet_enable_repeat repeat_cfg) |
303 | { | |
304 | /* enable/repeat the infoframe */ | |
425f02fd | 305 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, |
7d983f39 M |
306 | (repeat_cfg.audio_pkt << 5) | |
307 | (repeat_cfg.audio_pkt_repeat << 4) | | |
308 | (repeat_cfg.avi_infoframe << 1) | | |
309 | (repeat_cfg.avi_infoframe_repeat)); | |
310 | ||
311 | /* enable/repeat the packet */ | |
425f02fd | 312 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, |
7d983f39 M |
313 | (repeat_cfg.gen_cntrl_pkt << 3) | |
314 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | | |
315 | (repeat_cfg.generic_pkt << 1) | | |
316 | (repeat_cfg.generic_pkt_repeat)); | |
317 | } | |
318 | ||
425f02fd AT |
319 | void hdmi4_configure(struct hdmi_core_data *core, |
320 | struct hdmi_wp_data *wp, struct hdmi_config *cfg) | |
7d983f39 M |
321 | { |
322 | /* HDMI */ | |
323 | struct omap_video_timings video_timing; | |
324 | struct hdmi_video_format video_format; | |
7d983f39 | 325 | /* HDMI core */ |
7d983f39 M |
326 | struct hdmi_core_video_config v_core_cfg; |
327 | struct hdmi_core_packet_enable_repeat repeat_cfg; | |
db85ca7c | 328 | struct hdmi_avi_infoframe *avi_infoframe = &core->avi_infoframe; |
7d983f39 | 329 | |
db85ca7c | 330 | hdmi_core_init(&v_core_cfg, &repeat_cfg); |
7d983f39 | 331 | |
f382d9eb | 332 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
7d983f39 | 333 | |
425f02fd | 334 | hdmi_wp_video_config_timing(wp, &video_timing); |
7d983f39 M |
335 | |
336 | /* video config */ | |
337 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; | |
338 | ||
425f02fd | 339 | hdmi_wp_video_config_format(wp, &video_format); |
7d983f39 | 340 | |
425f02fd | 341 | hdmi_wp_video_config_interface(wp, &video_timing); |
7d983f39 M |
342 | |
343 | /* | |
344 | * configure core video part | |
345 | * set software reset in the core | |
346 | */ | |
425f02fd | 347 | hdmi_core_swreset_assert(core); |
7d983f39 M |
348 | |
349 | /* power down off */ | |
425f02fd | 350 | hdmi_core_powerdown_disable(core); |
7d983f39 M |
351 | |
352 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; | |
353 | v_core_cfg.hdmi_dvi = cfg->cm.mode; | |
354 | ||
425f02fd | 355 | hdmi_core_video_config(core, &v_core_cfg); |
7d983f39 M |
356 | |
357 | /* release software reset in the core */ | |
425f02fd | 358 | hdmi_core_swreset_release(core); |
7d983f39 M |
359 | |
360 | /* | |
361 | * configure packet | |
362 | * info frame video see doc CEA861-D page 65 | |
363 | */ | |
db85ca7c TV |
364 | hdmi_avi_infoframe_init(avi_infoframe); |
365 | avi_infoframe->colorspace = HDMI_COLORSPACE_RGB; | |
366 | avi_infoframe->scan_mode = HDMI_SCAN_MODE_NONE; | |
367 | avi_infoframe->colorimetry = HDMI_COLORIMETRY_NONE; | |
368 | avi_infoframe->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | |
369 | avi_infoframe->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; | |
370 | avi_infoframe->itc = 0; | |
371 | avi_infoframe->extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; | |
372 | avi_infoframe->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | |
373 | avi_infoframe->nups = HDMI_NUPS_UNKNOWN; | |
374 | avi_infoframe->video_code = cfg->cm.code; | |
375 | avi_infoframe->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | |
376 | avi_infoframe->content_type = HDMI_CONTENT_TYPE_NONE; | |
377 | avi_infoframe->pixel_repeat = 0; | |
425f02fd | 378 | hdmi_core_aux_infoframe_avi_config(core); |
7d983f39 M |
379 | |
380 | /* enable/repeat the infoframe */ | |
381 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; | |
382 | repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; | |
383 | /* wakeup */ | |
384 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; | |
385 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; | |
425f02fd | 386 | hdmi_core_av_packet_config(core, repeat_cfg); |
7d983f39 | 387 | } |
7334167b | 388 | |
425f02fd | 389 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) |
162874d5 M |
390 | { |
391 | int i; | |
392 | ||
393 | #define CORE_REG(i, name) name(i) | |
394 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ | |
425f02fd | 395 | hdmi_read_reg(core->base, r)) |
3c7de247 | 396 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ |
425f02fd | 397 | hdmi_read_reg(hdmi_av_base(core), r)) |
3c7de247 | 398 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ |
311d5ce8 | 399 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ |
425f02fd | 400 | hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) |
162874d5 M |
401 | |
402 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); | |
403 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); | |
404 | DUMPCORE(HDMI_CORE_SYS_DEV_IDH); | |
405 | DUMPCORE(HDMI_CORE_SYS_DEV_REV); | |
406 | DUMPCORE(HDMI_CORE_SYS_SRST); | |
190d57c9 | 407 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); |
162874d5 | 408 | DUMPCORE(HDMI_CORE_SYS_SYS_STAT); |
78145a95 | 409 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); |
9b9c457b AT |
410 | DUMPCORE(HDMI_CORE_SYS_DE_DLY); |
411 | DUMPCORE(HDMI_CORE_SYS_DE_CTRL); | |
412 | DUMPCORE(HDMI_CORE_SYS_DE_TOP); | |
413 | DUMPCORE(HDMI_CORE_SYS_DE_CNTL); | |
414 | DUMPCORE(HDMI_CORE_SYS_DE_CNTH); | |
415 | DUMPCORE(HDMI_CORE_SYS_DE_LINL); | |
416 | DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); | |
78145a95 RN |
417 | DUMPCORE(HDMI_CORE_SYS_HRES_L); |
418 | DUMPCORE(HDMI_CORE_SYS_HRES_H); | |
419 | DUMPCORE(HDMI_CORE_SYS_VRES_L); | |
420 | DUMPCORE(HDMI_CORE_SYS_VRES_H); | |
421 | DUMPCORE(HDMI_CORE_SYS_IADJUST); | |
422 | DUMPCORE(HDMI_CORE_SYS_POLDETECT); | |
423 | DUMPCORE(HDMI_CORE_SYS_HWIDTH1); | |
424 | DUMPCORE(HDMI_CORE_SYS_HWIDTH2); | |
425 | DUMPCORE(HDMI_CORE_SYS_VWIDTH); | |
426 | DUMPCORE(HDMI_CORE_SYS_VID_CTRL); | |
162874d5 M |
427 | DUMPCORE(HDMI_CORE_SYS_VID_ACEN); |
428 | DUMPCORE(HDMI_CORE_SYS_VID_MODE); | |
78145a95 RN |
429 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); |
430 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); | |
431 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); | |
432 | DUMPCORE(HDMI_CORE_SYS_DC_HEADER); | |
433 | DUMPCORE(HDMI_CORE_SYS_VID_DITHER); | |
434 | DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); | |
435 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); | |
436 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); | |
437 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); | |
438 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); | |
439 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); | |
440 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); | |
441 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); | |
442 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); | |
443 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); | |
444 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); | |
445 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); | |
446 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); | |
447 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); | |
448 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); | |
449 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); | |
450 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); | |
451 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); | |
452 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); | |
453 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); | |
454 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); | |
455 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); | |
456 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); | |
457 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); | |
458 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); | |
162874d5 M |
459 | DUMPCORE(HDMI_CORE_SYS_INTR_STATE); |
460 | DUMPCORE(HDMI_CORE_SYS_INTR1); | |
461 | DUMPCORE(HDMI_CORE_SYS_INTR2); | |
462 | DUMPCORE(HDMI_CORE_SYS_INTR3); | |
463 | DUMPCORE(HDMI_CORE_SYS_INTR4); | |
78145a95 RN |
464 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); |
465 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); | |
466 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); | |
467 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); | |
468 | DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); | |
162874d5 | 469 | DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); |
162874d5 | 470 | |
162874d5 | 471 | DUMPCORE(HDMI_CORE_DDC_ADDR); |
9b9c457b | 472 | DUMPCORE(HDMI_CORE_DDC_SEGM); |
162874d5 M |
473 | DUMPCORE(HDMI_CORE_DDC_OFFSET); |
474 | DUMPCORE(HDMI_CORE_DDC_COUNT1); | |
475 | DUMPCORE(HDMI_CORE_DDC_COUNT2); | |
9b9c457b AT |
476 | DUMPCORE(HDMI_CORE_DDC_STATUS); |
477 | DUMPCORE(HDMI_CORE_DDC_CMD); | |
162874d5 | 478 | DUMPCORE(HDMI_CORE_DDC_DATA); |
3c7de247 AT |
479 | |
480 | DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); | |
481 | DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); | |
482 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); | |
483 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); | |
484 | DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); | |
485 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); | |
486 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); | |
487 | DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); | |
488 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); | |
489 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); | |
490 | DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); | |
491 | DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); | |
492 | DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); | |
493 | DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); | |
494 | DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); | |
495 | DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); | |
496 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); | |
497 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); | |
498 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); | |
499 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); | |
500 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); | |
501 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); | |
502 | DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); | |
503 | DUMPCOREAV(HDMI_CORE_AV_ASRC); | |
504 | DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); | |
505 | DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); | |
506 | DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); | |
507 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); | |
508 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); | |
509 | DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); | |
510 | DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); | |
511 | DUMPCOREAV(HDMI_CORE_AV_DPD); | |
512 | DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); | |
513 | DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); | |
514 | DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); | |
515 | DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); | |
516 | DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); | |
517 | DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); | |
9b9c457b AT |
518 | |
519 | for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) | |
520 | DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); | |
521 | ||
3c7de247 AT |
522 | DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); |
523 | DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); | |
524 | DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); | |
525 | DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); | |
9b9c457b AT |
526 | |
527 | for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) | |
528 | DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); | |
529 | ||
3c7de247 AT |
530 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); |
531 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); | |
532 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); | |
533 | DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); | |
9b9c457b AT |
534 | |
535 | for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) | |
536 | DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); | |
537 | ||
3c7de247 AT |
538 | DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); |
539 | DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); | |
540 | DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); | |
541 | DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); | |
9b9c457b AT |
542 | |
543 | for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) | |
544 | DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); | |
545 | ||
546 | for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) | |
547 | DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); | |
548 | ||
3c7de247 | 549 | DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); |
9b9c457b AT |
550 | |
551 | for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) | |
552 | DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); | |
553 | ||
3c7de247 | 554 | DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); |
162874d5 M |
555 | } |
556 | ||
7e151f7f | 557 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
425f02fd | 558 | static void hdmi_core_audio_config(struct hdmi_core_data *core, |
7334167b M |
559 | struct hdmi_core_audio_config *cfg) |
560 | { | |
561 | u32 r; | |
425f02fd | 562 | void __iomem *av_base = hdmi_av_base(core); |
7334167b | 563 | |
d8989d96 RN |
564 | /* |
565 | * Parameters for generation of Audio Clock Recovery packets | |
566 | */ | |
7334167b M |
567 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); |
568 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); | |
569 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); | |
570 | ||
571 | if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { | |
572 | REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); | |
573 | REG_FLD_MOD(av_base, | |
574 | HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); | |
575 | REG_FLD_MOD(av_base, | |
576 | HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); | |
577 | } else { | |
7334167b M |
578 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, |
579 | cfg->aud_par_busclk, 7, 0); | |
580 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, | |
581 | (cfg->aud_par_busclk >> 8), 7, 0); | |
582 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, | |
583 | (cfg->aud_par_busclk >> 16), 7, 0); | |
584 | } | |
585 | ||
d8989d96 RN |
586 | /* Set ACR clock divisor */ |
587 | REG_FLD_MOD(av_base, | |
588 | HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); | |
589 | ||
590 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); | |
591 | /* | |
592 | * Use TMDS clock for ACR packets. For devices that use | |
593 | * the MCLK, this is the first part of the MCLK initialization. | |
594 | */ | |
595 | r = FLD_MOD(r, 0, 2, 2); | |
596 | ||
597 | r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); | |
598 | r = FLD_MOD(r, cfg->cts_mode, 0, 0); | |
599 | hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); | |
600 | ||
601 | /* For devices using MCLK, this completes its initialization. */ | |
602 | if (cfg->use_mclk) | |
603 | REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); | |
604 | ||
7334167b M |
605 | /* Override of SPDIF sample frequency with value in I2S_CHST4 */ |
606 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, | |
607 | cfg->fs_override, 1, 1); | |
608 | ||
c1164ed8 RN |
609 | /* |
610 | * Set IEC-60958-3 channel status word. It is passed to the IP | |
611 | * just as it is received. The user of the driver is responsible | |
612 | * for its contents. | |
613 | */ | |
614 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, | |
615 | cfg->iec60958_cfg->status[0]); | |
616 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, | |
617 | cfg->iec60958_cfg->status[1]); | |
618 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, | |
619 | cfg->iec60958_cfg->status[2]); | |
620 | /* yes, this is correct: status[3] goes to CHST4 register */ | |
621 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, | |
622 | cfg->iec60958_cfg->status[3]); | |
623 | /* yes, this is correct: status[4] goes to CHST5 register */ | |
624 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, | |
625 | cfg->iec60958_cfg->status[4]); | |
626 | ||
627 | /* set I2S parameters */ | |
7334167b | 628 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); |
7334167b | 629 | r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); |
7334167b | 630 | r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); |
7334167b M |
631 | r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); |
632 | r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); | |
633 | r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); | |
634 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); | |
635 | ||
7334167b M |
636 | REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, |
637 | cfg->i2s_cfg.in_length_bits, 3, 0); | |
638 | ||
639 | /* Audio channels and mode parameters */ | |
640 | REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); | |
641 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); | |
642 | r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); | |
643 | r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); | |
644 | r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); | |
645 | r = FLD_MOD(r, cfg->en_spdif, 1, 1); | |
646 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); | |
24ccfc55 RN |
647 | |
648 | /* Audio channel mappings */ | |
649 | /* TODO: Make channel mapping dynamic. For now, map channels | |
650 | * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as | |
651 | * HDMI speaker order is different. See CEA-861 Section 6.6.2. | |
652 | */ | |
653 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); | |
654 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); | |
7334167b M |
655 | } |
656 | ||
425f02fd | 657 | static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, |
199e7fd6 | 658 | struct snd_cea_861_aud_if *info_aud) |
7334167b | 659 | { |
7334167b | 660 | u8 sum = 0, checksum = 0; |
425f02fd | 661 | void __iomem *av_base = hdmi_av_base(core); |
7334167b M |
662 | |
663 | /* | |
664 | * Set audio info frame type, version and length as | |
665 | * described in HDMI 1.4a Section 8.2.2 specification. | |
666 | * Checksum calculation is defined in Section 5.3.5. | |
667 | */ | |
668 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); | |
669 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); | |
670 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); | |
671 | sum += 0x84 + 0x001 + 0x00a; | |
672 | ||
199e7fd6 RN |
673 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), |
674 | info_aud->db1_ct_cc); | |
675 | sum += info_aud->db1_ct_cc; | |
7334167b | 676 | |
199e7fd6 RN |
677 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), |
678 | info_aud->db2_sf_ss); | |
679 | sum += info_aud->db2_sf_ss; | |
7334167b | 680 | |
199e7fd6 RN |
681 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); |
682 | sum += info_aud->db3; | |
7334167b | 683 | |
199e7fd6 RN |
684 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); |
685 | sum += info_aud->db4_ca; | |
7334167b | 686 | |
199e7fd6 RN |
687 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), |
688 | info_aud->db5_dminh_lsv); | |
689 | sum += info_aud->db5_dminh_lsv; | |
7334167b M |
690 | |
691 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); | |
692 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); | |
693 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); | |
694 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); | |
695 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); | |
696 | ||
697 | checksum = 0x100 - sum; | |
698 | hdmi_write_reg(av_base, | |
699 | HDMI_CORE_AV_AUDIO_CHSUM, checksum); | |
700 | ||
701 | /* | |
702 | * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing | |
703 | * is available. | |
704 | */ | |
705 | } | |
706 | ||
425f02fd | 707 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
08d83e4e | 708 | struct omap_dss_audio *audio, u32 pclk) |
6ec355d6 RN |
709 | { |
710 | struct hdmi_audio_format audio_format; | |
711 | struct hdmi_audio_dma audio_dma; | |
425f02fd | 712 | struct hdmi_core_audio_config acore; |
6ec355d6 RN |
713 | int err, n, cts, channel_count; |
714 | unsigned int fs_nr; | |
715 | bool word_length_16b = false; | |
716 | ||
425f02fd | 717 | if (!audio || !audio->iec || !audio->cea || !core) |
6ec355d6 RN |
718 | return -EINVAL; |
719 | ||
425f02fd | 720 | acore.iec60958_cfg = audio->iec; |
6ec355d6 RN |
721 | /* |
722 | * In the IEC-60958 status word, check if the audio sample word length | |
723 | * is 16-bit as several optimizations can be performed in such case. | |
724 | */ | |
725 | if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) | |
726 | if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) | |
727 | word_length_16b = true; | |
728 | ||
729 | /* I2S configuration. See Phillips' specification */ | |
730 | if (word_length_16b) | |
425f02fd | 731 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
6ec355d6 | 732 | else |
425f02fd | 733 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
6ec355d6 RN |
734 | /* |
735 | * The I2S input word length is twice the lenght given in the IEC-60958 | |
736 | * status word. If the word size is greater than | |
737 | * 20 bits, increment by one. | |
738 | */ | |
425f02fd | 739 | acore.i2s_cfg.in_length_bits = audio->iec->status[4] |
6ec355d6 RN |
740 | & IEC958_AES4_CON_WORDLEN; |
741 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) | |
425f02fd AT |
742 | acore.i2s_cfg.in_length_bits++; |
743 | acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; | |
744 | acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; | |
745 | acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; | |
746 | acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; | |
6ec355d6 RN |
747 | |
748 | /* convert sample frequency to a number */ | |
749 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { | |
750 | case IEC958_AES3_CON_FS_32000: | |
751 | fs_nr = 32000; | |
752 | break; | |
753 | case IEC958_AES3_CON_FS_44100: | |
754 | fs_nr = 44100; | |
755 | break; | |
756 | case IEC958_AES3_CON_FS_48000: | |
757 | fs_nr = 48000; | |
758 | break; | |
759 | case IEC958_AES3_CON_FS_88200: | |
760 | fs_nr = 88200; | |
761 | break; | |
762 | case IEC958_AES3_CON_FS_96000: | |
763 | fs_nr = 96000; | |
764 | break; | |
765 | case IEC958_AES3_CON_FS_176400: | |
766 | fs_nr = 176400; | |
767 | break; | |
768 | case IEC958_AES3_CON_FS_192000: | |
769 | fs_nr = 192000; | |
770 | break; | |
771 | default: | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
08d83e4e | 775 | err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); |
6ec355d6 RN |
776 | |
777 | /* Audio clock regeneration settings */ | |
425f02fd AT |
778 | acore.n = n; |
779 | acore.cts = cts; | |
6ec355d6 | 780 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
425f02fd AT |
781 | acore.aud_par_busclk = 0; |
782 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; | |
783 | acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); | |
6ec355d6 | 784 | } else { |
425f02fd AT |
785 | acore.aud_par_busclk = (((128 * 31) - 1) << 8); |
786 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; | |
787 | acore.use_mclk = true; | |
6ec355d6 RN |
788 | } |
789 | ||
425f02fd AT |
790 | if (acore.use_mclk) |
791 | acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; | |
6ec355d6 RN |
792 | |
793 | /* Audio channels settings */ | |
794 | channel_count = (audio->cea->db1_ct_cc & | |
795 | CEA861_AUDIO_INFOFRAME_DB1CC) + 1; | |
796 | ||
797 | switch (channel_count) { | |
798 | case 2: | |
799 | audio_format.active_chnnls_msk = 0x03; | |
800 | break; | |
801 | case 3: | |
802 | audio_format.active_chnnls_msk = 0x07; | |
803 | break; | |
804 | case 4: | |
805 | audio_format.active_chnnls_msk = 0x0f; | |
806 | break; | |
807 | case 5: | |
808 | audio_format.active_chnnls_msk = 0x1f; | |
809 | break; | |
810 | case 6: | |
811 | audio_format.active_chnnls_msk = 0x3f; | |
812 | break; | |
813 | case 7: | |
814 | audio_format.active_chnnls_msk = 0x7f; | |
815 | break; | |
816 | case 8: | |
817 | audio_format.active_chnnls_msk = 0xff; | |
818 | break; | |
819 | default: | |
820 | return -EINVAL; | |
821 | } | |
822 | ||
823 | /* | |
824 | * the HDMI IP needs to enable four stereo channels when transmitting | |
825 | * more than 2 audio channels | |
826 | */ | |
827 | if (channel_count == 2) { | |
828 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | |
425f02fd AT |
829 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
830 | acore.layout = HDMI_AUDIO_LAYOUT_2CH; | |
6ec355d6 RN |
831 | } else { |
832 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; | |
425f02fd | 833 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | |
6ec355d6 RN |
834 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | |
835 | HDMI_AUDIO_I2S_SD3_EN; | |
425f02fd | 836 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; |
6ec355d6 RN |
837 | } |
838 | ||
425f02fd | 839 | acore.en_spdif = false; |
6ec355d6 | 840 | /* use sample frequency from channel status word */ |
425f02fd | 841 | acore.fs_override = true; |
6ec355d6 | 842 | /* enable ACR packets */ |
425f02fd | 843 | acore.en_acr_pkt = true; |
6ec355d6 | 844 | /* disable direct streaming digital audio */ |
425f02fd | 845 | acore.en_dsd_audio = false; |
6ec355d6 | 846 | /* use parallel audio interface */ |
425f02fd | 847 | acore.en_parallel_aud_input = true; |
6ec355d6 RN |
848 | |
849 | /* DMA settings */ | |
850 | if (word_length_16b) | |
851 | audio_dma.transfer_size = 0x10; | |
852 | else | |
853 | audio_dma.transfer_size = 0x20; | |
854 | audio_dma.block_size = 0xC0; | |
855 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; | |
856 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ | |
857 | ||
858 | /* audio FIFO format settings */ | |
859 | if (word_length_16b) { | |
860 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; | |
861 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; | |
862 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; | |
863 | } else { | |
864 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; | |
865 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; | |
866 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | |
867 | } | |
868 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; | |
869 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; | |
870 | /* disable start/stop signals of IEC 60958 blocks */ | |
871 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; | |
872 | ||
873 | /* configure DMA and audio FIFO format*/ | |
425f02fd AT |
874 | hdmi_wp_audio_config_dma(wp, &audio_dma); |
875 | hdmi_wp_audio_config_format(wp, &audio_format); | |
6ec355d6 RN |
876 | |
877 | /* configure the core*/ | |
425f02fd | 878 | hdmi_core_audio_config(core, &acore); |
6ec355d6 RN |
879 | |
880 | /* configure CEA 861 audio infoframe*/ | |
425f02fd | 881 | hdmi_core_audio_infoframe_cfg(core, audio->cea); |
6ec355d6 RN |
882 | |
883 | return 0; | |
884 | } | |
885 | ||
425f02fd | 886 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
3df9fb5c | 887 | { |
425f02fd | 888 | REG_FLD_MOD(hdmi_av_base(core), |
3df9fb5c | 889 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); |
f382d9eb | 890 | |
425f02fd | 891 | hdmi_wp_audio_core_req_enable(wp, true); |
f382d9eb | 892 | |
027bdc85 RN |
893 | return 0; |
894 | } | |
895 | ||
425f02fd | 896 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
027bdc85 | 897 | { |
425f02fd | 898 | REG_FLD_MOD(hdmi_av_base(core), |
027bdc85 | 899 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); |
f382d9eb | 900 | |
425f02fd | 901 | hdmi_wp_audio_core_req_enable(wp, false); |
80a48596 | 902 | } |
d7b6f443 | 903 | |
425f02fd | 904 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size) |
d7b6f443 RN |
905 | { |
906 | if (!offset || !size) | |
907 | return -EINVAL; | |
908 | *offset = HDMI_WP_AUDIO_DATA; | |
909 | *size = 4; | |
910 | return 0; | |
911 | } | |
f382d9eb | 912 | |
7334167b | 913 | #endif |
425f02fd | 914 | |
425f02fd AT |
915 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) |
916 | { | |
917 | struct resource *res; | |
425f02fd | 918 | |
77601507 | 919 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
425f02fd | 920 | if (!res) { |
59b3d38a TV |
921 | DSSERR("can't get CORE mem resource\n"); |
922 | return -EINVAL; | |
425f02fd AT |
923 | } |
924 | ||
59b3d38a | 925 | core->base = devm_ioremap_resource(&pdev->dev, res); |
2b22df83 | 926 | if (IS_ERR(core->base)) { |
425f02fd | 927 | DSSERR("can't ioremap CORE\n"); |
2b22df83 | 928 | return PTR_ERR(core->base); |
425f02fd AT |
929 | } |
930 | ||
931 | return 0; | |
932 | } |