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f5bab222 TV |
1 | /* |
2 | * HDMI driver for OMAP5 | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments Incorporated | |
5 | * | |
6 | * Authors: | |
7 | * Yong Zhi | |
8 | * Mythri pk | |
9 | * Archit Taneja <archit@ti.com> | |
10 | * Tomi Valkeinen <tomi.valkeinen@ti.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License version 2 as published by | |
14 | * the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
25 | #define DSS_SUBSYS_NAME "HDMI" | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/mutex.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/pm_runtime.h> | |
37 | #include <linux/clk.h> | |
38 | #include <linux/gpio.h> | |
39 | #include <linux/regulator/consumer.h> | |
40 | #include <video/omapdss.h> | |
41 | ||
42 | #include "hdmi5_core.h" | |
43 | #include "dss.h" | |
44 | #include "dss_features.h" | |
45 | ||
46 | static struct { | |
47 | struct mutex lock; | |
48 | struct platform_device *pdev; | |
49 | ||
50 | struct hdmi_wp_data wp; | |
51 | struct hdmi_pll_data pll; | |
52 | struct hdmi_phy_data phy; | |
53 | struct hdmi_core_data core; | |
54 | ||
55 | struct hdmi_config cfg; | |
56 | ||
57 | struct clk *sys_clk; | |
58 | struct regulator *vdda_reg; | |
59 | ||
60 | bool core_enabled; | |
61 | ||
62 | struct omap_dss_device output; | |
63 | } hdmi; | |
64 | ||
65 | static int hdmi_runtime_get(void) | |
66 | { | |
67 | int r; | |
68 | ||
69 | DSSDBG("hdmi_runtime_get\n"); | |
70 | ||
71 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
72 | WARN_ON(r < 0); | |
73 | if (r < 0) | |
74 | return r; | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static void hdmi_runtime_put(void) | |
80 | { | |
81 | int r; | |
82 | ||
83 | DSSDBG("hdmi_runtime_put\n"); | |
84 | ||
85 | r = pm_runtime_put_sync(&hdmi.pdev->dev); | |
86 | WARN_ON(r < 0 && r != -ENOSYS); | |
87 | } | |
88 | ||
89 | static irqreturn_t hdmi_irq_handler(int irq, void *data) | |
90 | { | |
91 | struct hdmi_wp_data *wp = data; | |
92 | u32 irqstatus; | |
93 | ||
94 | irqstatus = hdmi_wp_get_irqstatus(wp); | |
95 | hdmi_wp_set_irqstatus(wp, irqstatus); | |
96 | ||
97 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | |
98 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
99 | u32 v; | |
100 | /* | |
101 | * If we get both connect and disconnect interrupts at the same | |
102 | * time, turn off the PHY, clear interrupts, and restart, which | |
103 | * raises connect interrupt if a cable is connected, or nothing | |
104 | * if cable is not connected. | |
105 | */ | |
106 | ||
107 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | |
108 | ||
109 | /* | |
110 | * We always get bogus CONNECT & DISCONNECT interrupts when | |
111 | * setting the PHY to LDOON. To ignore those, we force the RXDET | |
112 | * line to 0 until the PHY power state has been changed. | |
113 | */ | |
114 | v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); | |
115 | v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ | |
116 | v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ | |
117 | hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); | |
118 | ||
119 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | | |
120 | HDMI_IRQ_LINK_DISCONNECT); | |
121 | ||
122 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
123 | ||
124 | REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); | |
125 | ||
126 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | |
127 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); | |
128 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
129 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
130 | } | |
131 | ||
132 | return IRQ_HANDLED; | |
133 | } | |
134 | ||
135 | static int hdmi_init_regulator(void) | |
136 | { | |
137 | int r; | |
138 | struct regulator *reg; | |
139 | ||
140 | if (hdmi.vdda_reg != NULL) | |
141 | return 0; | |
142 | ||
143 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); | |
144 | if (IS_ERR(reg)) { | |
145 | DSSERR("can't get VDDA regulator\n"); | |
146 | return PTR_ERR(reg); | |
147 | } | |
148 | ||
149 | if (regulator_can_change_voltage(reg)) { | |
150 | r = regulator_set_voltage(reg, 1800000, 1800000); | |
151 | if (r) { | |
152 | devm_regulator_put(reg); | |
153 | DSSWARN("can't set the regulator voltage\n"); | |
154 | return r; | |
155 | } | |
156 | } | |
157 | ||
158 | hdmi.vdda_reg = reg; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) | |
164 | { | |
165 | int r; | |
166 | ||
167 | r = regulator_enable(hdmi.vdda_reg); | |
168 | if (r) | |
169 | return r; | |
170 | ||
171 | r = hdmi_runtime_get(); | |
172 | if (r) | |
173 | goto err_runtime_get; | |
174 | ||
175 | /* Make selection of HDMI in DSS */ | |
176 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
177 | ||
178 | hdmi.core_enabled = true; | |
179 | ||
180 | return 0; | |
181 | ||
182 | err_runtime_get: | |
183 | regulator_disable(hdmi.vdda_reg); | |
184 | ||
185 | return r; | |
186 | } | |
187 | ||
188 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | |
189 | { | |
190 | hdmi.core_enabled = false; | |
191 | ||
192 | hdmi_runtime_put(); | |
193 | regulator_disable(hdmi.vdda_reg); | |
194 | } | |
195 | ||
196 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |
197 | { | |
198 | int r; | |
199 | struct omap_video_timings *p; | |
200 | struct omap_overlay_manager *mgr = hdmi.output.manager; | |
201 | unsigned long phy; | |
202 | ||
203 | r = hdmi_power_on_core(dssdev); | |
204 | if (r) | |
205 | return r; | |
206 | ||
207 | p = &hdmi.cfg.timings; | |
208 | ||
209 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); | |
210 | ||
211 | /* the functions below use kHz pixel clock. TODO: change to Hz */ | |
212 | phy = p->pixelclock / 1000; | |
213 | ||
214 | hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); | |
215 | ||
216 | /* disable and clear irqs */ | |
217 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); | |
218 | hdmi_wp_set_irqstatus(&hdmi.wp, | |
219 | hdmi_wp_get_irqstatus(&hdmi.wp)); | |
220 | ||
221 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ | |
222 | r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); | |
223 | if (r) { | |
224 | DSSDBG("Failed to lock PLL\n"); | |
225 | goto err_pll_enable; | |
226 | } | |
227 | ||
228 | r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg); | |
229 | if (r) { | |
230 | DSSDBG("Failed to start PHY\n"); | |
231 | goto err_phy_cfg; | |
232 | } | |
233 | ||
234 | r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON); | |
235 | if (r) | |
236 | goto err_phy_pwr; | |
237 | ||
238 | hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); | |
239 | ||
240 | /* bypass TV gamma table */ | |
241 | dispc_enable_gamma_table(0); | |
242 | ||
243 | /* tv size */ | |
244 | dss_mgr_set_timings(mgr, p); | |
245 | ||
246 | r = hdmi_wp_video_start(&hdmi.wp); | |
247 | if (r) | |
248 | goto err_vid_enable; | |
249 | ||
250 | r = dss_mgr_enable(mgr); | |
251 | if (r) | |
252 | goto err_mgr_enable; | |
253 | ||
254 | hdmi_wp_set_irqenable(&hdmi.wp, | |
255 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | |
256 | ||
257 | return 0; | |
258 | ||
259 | err_mgr_enable: | |
260 | hdmi_wp_video_stop(&hdmi.wp); | |
261 | err_vid_enable: | |
262 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); | |
263 | err_phy_pwr: | |
264 | err_phy_cfg: | |
265 | hdmi_pll_disable(&hdmi.pll, &hdmi.wp); | |
266 | err_pll_enable: | |
267 | hdmi_power_off_core(dssdev); | |
268 | return -EIO; | |
269 | } | |
270 | ||
271 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) | |
272 | { | |
273 | struct omap_overlay_manager *mgr = hdmi.output.manager; | |
274 | ||
275 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); | |
276 | ||
277 | dss_mgr_disable(mgr); | |
278 | ||
279 | hdmi_wp_video_stop(&hdmi.wp); | |
280 | ||
281 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); | |
282 | ||
283 | hdmi_pll_disable(&hdmi.pll, &hdmi.wp); | |
284 | ||
285 | hdmi_power_off_core(dssdev); | |
286 | } | |
287 | ||
288 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
289 | struct omap_video_timings *timings) | |
290 | { | |
291 | struct omap_dss_device *out = &hdmi.output; | |
292 | ||
293 | if (!dispc_mgr_timings_ok(out->dispc_channel, timings)) | |
294 | return -EINVAL; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | |
300 | struct omap_video_timings *timings) | |
301 | { | |
f5bab222 TV |
302 | mutex_lock(&hdmi.lock); |
303 | ||
769dcb11 | 304 | hdmi.cfg.timings = *timings; |
f5bab222 | 305 | |
769dcb11 | 306 | dispc_set_tv_pclk(timings->pixelclock); |
f5bab222 TV |
307 | |
308 | mutex_unlock(&hdmi.lock); | |
309 | } | |
310 | ||
311 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | |
312 | struct omap_video_timings *timings) | |
313 | { | |
769dcb11 | 314 | *timings = hdmi.cfg.timings; |
f5bab222 TV |
315 | } |
316 | ||
317 | static void hdmi_dump_regs(struct seq_file *s) | |
318 | { | |
319 | mutex_lock(&hdmi.lock); | |
320 | ||
321 | if (hdmi_runtime_get()) { | |
322 | mutex_unlock(&hdmi.lock); | |
323 | return; | |
324 | } | |
325 | ||
326 | hdmi_wp_dump(&hdmi.wp, s); | |
327 | hdmi_pll_dump(&hdmi.pll, s); | |
328 | hdmi_phy_dump(&hdmi.phy, s); | |
329 | hdmi5_core_dump(&hdmi.core, s); | |
330 | ||
331 | hdmi_runtime_put(); | |
332 | mutex_unlock(&hdmi.lock); | |
333 | } | |
334 | ||
335 | static int read_edid(u8 *buf, int len) | |
336 | { | |
337 | int r; | |
338 | int idlemode; | |
339 | ||
340 | mutex_lock(&hdmi.lock); | |
341 | ||
342 | r = hdmi_runtime_get(); | |
343 | BUG_ON(r); | |
344 | ||
345 | idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); | |
346 | /* No-idle mode */ | |
347 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); | |
348 | ||
349 | r = hdmi5_read_edid(&hdmi.core, buf, len); | |
350 | ||
351 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); | |
352 | ||
353 | hdmi_runtime_put(); | |
354 | mutex_unlock(&hdmi.lock); | |
355 | ||
356 | return r; | |
357 | } | |
358 | ||
359 | static int hdmi_display_enable(struct omap_dss_device *dssdev) | |
360 | { | |
361 | struct omap_dss_device *out = &hdmi.output; | |
362 | int r = 0; | |
363 | ||
364 | DSSDBG("ENTER hdmi_display_enable\n"); | |
365 | ||
366 | mutex_lock(&hdmi.lock); | |
367 | ||
368 | if (out == NULL || out->manager == NULL) { | |
369 | DSSERR("failed to enable display: no output/manager\n"); | |
370 | r = -ENODEV; | |
371 | goto err0; | |
372 | } | |
373 | ||
374 | r = hdmi_power_on_full(dssdev); | |
375 | if (r) { | |
376 | DSSERR("failed to power on device\n"); | |
377 | goto err0; | |
378 | } | |
379 | ||
380 | mutex_unlock(&hdmi.lock); | |
381 | return 0; | |
382 | ||
383 | err0: | |
384 | mutex_unlock(&hdmi.lock); | |
385 | return r; | |
386 | } | |
387 | ||
388 | static void hdmi_display_disable(struct omap_dss_device *dssdev) | |
389 | { | |
390 | DSSDBG("Enter hdmi_display_disable\n"); | |
391 | ||
392 | mutex_lock(&hdmi.lock); | |
393 | ||
394 | hdmi_power_off_full(dssdev); | |
395 | ||
396 | mutex_unlock(&hdmi.lock); | |
397 | } | |
398 | ||
399 | static int hdmi_core_enable(struct omap_dss_device *dssdev) | |
400 | { | |
401 | int r = 0; | |
402 | ||
403 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | |
404 | ||
405 | mutex_lock(&hdmi.lock); | |
406 | ||
407 | r = hdmi_power_on_core(dssdev); | |
408 | if (r) { | |
409 | DSSERR("failed to power on device\n"); | |
410 | goto err0; | |
411 | } | |
412 | ||
413 | mutex_unlock(&hdmi.lock); | |
414 | return 0; | |
415 | ||
416 | err0: | |
417 | mutex_unlock(&hdmi.lock); | |
418 | return r; | |
419 | } | |
420 | ||
421 | static void hdmi_core_disable(struct omap_dss_device *dssdev) | |
422 | { | |
423 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | |
424 | ||
425 | mutex_lock(&hdmi.lock); | |
426 | ||
427 | hdmi_power_off_core(dssdev); | |
428 | ||
429 | mutex_unlock(&hdmi.lock); | |
430 | } | |
431 | ||
432 | static int hdmi_get_clocks(struct platform_device *pdev) | |
433 | { | |
434 | struct clk *clk; | |
435 | ||
436 | clk = devm_clk_get(&pdev->dev, "sys_clk"); | |
437 | if (IS_ERR(clk)) { | |
438 | DSSERR("can't get sys_clk\n"); | |
439 | return PTR_ERR(clk); | |
440 | } | |
441 | ||
442 | hdmi.sys_clk = clk; | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | static int hdmi_connect(struct omap_dss_device *dssdev, | |
448 | struct omap_dss_device *dst) | |
449 | { | |
450 | struct omap_overlay_manager *mgr; | |
451 | int r; | |
452 | ||
453 | r = hdmi_init_regulator(); | |
454 | if (r) | |
455 | return r; | |
456 | ||
457 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
458 | if (!mgr) | |
459 | return -ENODEV; | |
460 | ||
461 | r = dss_mgr_connect(mgr, dssdev); | |
462 | if (r) | |
463 | return r; | |
464 | ||
465 | r = omapdss_output_set_device(dssdev, dst); | |
466 | if (r) { | |
467 | DSSERR("failed to connect output to new device: %s\n", | |
468 | dst->name); | |
469 | dss_mgr_disconnect(mgr, dssdev); | |
470 | return r; | |
471 | } | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | |
477 | struct omap_dss_device *dst) | |
478 | { | |
479 | WARN_ON(dst != dssdev->dst); | |
480 | ||
481 | if (dst != dssdev->dst) | |
482 | return; | |
483 | ||
484 | omapdss_output_unset_device(dssdev); | |
485 | ||
486 | if (dssdev->manager) | |
487 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
488 | } | |
489 | ||
490 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | |
491 | u8 *edid, int len) | |
492 | { | |
493 | bool need_enable; | |
494 | int r; | |
495 | ||
496 | need_enable = hdmi.core_enabled == false; | |
497 | ||
498 | if (need_enable) { | |
499 | r = hdmi_core_enable(dssdev); | |
500 | if (r) | |
501 | return r; | |
502 | } | |
503 | ||
504 | r = read_edid(edid, len); | |
505 | ||
506 | if (need_enable) | |
507 | hdmi_core_disable(dssdev); | |
508 | ||
509 | return r; | |
510 | } | |
511 | ||
512 | #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) | |
513 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | |
514 | { | |
515 | int r; | |
516 | ||
517 | mutex_lock(&hdmi.lock); | |
518 | ||
769dcb11 | 519 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
f5bab222 TV |
520 | r = -EPERM; |
521 | goto err; | |
522 | } | |
523 | ||
524 | r = hdmi_wp_audio_enable(&hdmi.wp, true); | |
525 | if (r) | |
526 | goto err; | |
527 | ||
528 | mutex_unlock(&hdmi.lock); | |
529 | return 0; | |
530 | ||
531 | err: | |
532 | mutex_unlock(&hdmi.lock); | |
533 | return r; | |
534 | } | |
535 | ||
536 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | |
537 | { | |
538 | hdmi_wp_audio_enable(&hdmi.wp, false); | |
539 | } | |
540 | ||
541 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | |
542 | { | |
543 | return hdmi_wp_audio_core_req_enable(&hdmi.wp, true); | |
544 | } | |
545 | ||
546 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | |
547 | { | |
548 | hdmi_wp_audio_core_req_enable(&hdmi.wp, false); | |
549 | } | |
550 | ||
551 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | |
552 | { | |
553 | bool r; | |
554 | ||
555 | mutex_lock(&hdmi.lock); | |
556 | ||
769dcb11 | 557 | r = hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode); |
f5bab222 TV |
558 | |
559 | mutex_unlock(&hdmi.lock); | |
560 | return r; | |
561 | } | |
562 | ||
563 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | |
564 | struct omap_dss_audio *audio) | |
565 | { | |
566 | int r; | |
567 | u32 pclk = hdmi.cfg.timings.pixelclock; | |
568 | ||
569 | mutex_lock(&hdmi.lock); | |
570 | ||
769dcb11 | 571 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
f5bab222 TV |
572 | r = -EPERM; |
573 | goto err; | |
574 | } | |
575 | ||
576 | r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk); | |
577 | if (r) | |
578 | goto err; | |
579 | ||
580 | mutex_unlock(&hdmi.lock); | |
581 | return 0; | |
582 | ||
583 | err: | |
584 | mutex_unlock(&hdmi.lock); | |
585 | return r; | |
586 | } | |
587 | #else | |
588 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | |
589 | { | |
590 | return -EPERM; | |
591 | } | |
592 | ||
593 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | |
594 | { | |
595 | } | |
596 | ||
597 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | |
598 | { | |
599 | return -EPERM; | |
600 | } | |
601 | ||
602 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | |
603 | { | |
604 | } | |
605 | ||
606 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | |
607 | { | |
608 | return false; | |
609 | } | |
610 | ||
611 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | |
612 | struct omap_dss_audio *audio) | |
613 | { | |
614 | return -EPERM; | |
615 | } | |
616 | #endif | |
617 | ||
769dcb11 TV |
618 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, |
619 | const struct hdmi_avi_infoframe *avi) | |
620 | { | |
621 | hdmi.cfg.infoframe = *avi; | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | |
626 | bool hdmi_mode) | |
627 | { | |
628 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | |
629 | return 0; | |
630 | } | |
631 | ||
f5bab222 TV |
632 | static const struct omapdss_hdmi_ops hdmi_ops = { |
633 | .connect = hdmi_connect, | |
634 | .disconnect = hdmi_disconnect, | |
635 | ||
636 | .enable = hdmi_display_enable, | |
637 | .disable = hdmi_display_disable, | |
638 | ||
639 | .check_timings = hdmi_display_check_timing, | |
640 | .set_timings = hdmi_display_set_timing, | |
641 | .get_timings = hdmi_display_get_timings, | |
642 | ||
643 | .read_edid = hdmi_read_edid, | |
769dcb11 TV |
644 | .set_infoframe = hdmi_set_infoframe, |
645 | .set_hdmi_mode = hdmi_set_hdmi_mode, | |
f5bab222 TV |
646 | |
647 | .audio_enable = hdmi_audio_enable, | |
648 | .audio_disable = hdmi_audio_disable, | |
649 | .audio_start = hdmi_audio_start, | |
650 | .audio_stop = hdmi_audio_stop, | |
651 | .audio_supported = hdmi_audio_supported, | |
652 | .audio_config = hdmi_audio_config, | |
653 | }; | |
654 | ||
655 | static void hdmi_init_output(struct platform_device *pdev) | |
656 | { | |
657 | struct omap_dss_device *out = &hdmi.output; | |
658 | ||
659 | out->dev = &pdev->dev; | |
660 | out->id = OMAP_DSS_OUTPUT_HDMI; | |
661 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; | |
662 | out->name = "hdmi.0"; | |
663 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; | |
664 | out->ops.hdmi = &hdmi_ops; | |
665 | out->owner = THIS_MODULE; | |
666 | ||
667 | omapdss_register_output(out); | |
668 | } | |
669 | ||
670 | static void __exit hdmi_uninit_output(struct platform_device *pdev) | |
671 | { | |
672 | struct omap_dss_device *out = &hdmi.output; | |
673 | ||
674 | omapdss_unregister_output(out); | |
675 | } | |
676 | ||
677 | static int hdmi_probe_of(struct platform_device *pdev) | |
678 | { | |
679 | struct device_node *node = pdev->dev.of_node; | |
680 | struct device_node *ep; | |
681 | int r; | |
682 | ||
683 | ep = omapdss_of_get_first_endpoint(node); | |
684 | if (!ep) | |
685 | return 0; | |
686 | ||
687 | r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); | |
688 | if (r) | |
689 | goto err; | |
690 | ||
691 | of_node_put(ep); | |
692 | return 0; | |
693 | ||
694 | err: | |
695 | of_node_put(ep); | |
696 | return r; | |
697 | } | |
698 | ||
699 | /* HDMI HW IP initialisation */ | |
700 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | |
701 | { | |
702 | int r; | |
703 | int irq; | |
704 | ||
705 | hdmi.pdev = pdev; | |
706 | ||
707 | mutex_init(&hdmi.lock); | |
708 | ||
709 | if (pdev->dev.of_node) { | |
710 | r = hdmi_probe_of(pdev); | |
711 | if (r) | |
712 | return r; | |
713 | } | |
714 | ||
715 | r = hdmi_wp_init(pdev, &hdmi.wp); | |
716 | if (r) | |
717 | return r; | |
718 | ||
719 | r = hdmi_pll_init(pdev, &hdmi.pll); | |
720 | if (r) | |
721 | return r; | |
722 | ||
723 | r = hdmi_phy_init(pdev, &hdmi.phy); | |
724 | if (r) | |
725 | return r; | |
726 | ||
727 | r = hdmi5_core_init(pdev, &hdmi.core); | |
728 | if (r) | |
729 | return r; | |
730 | ||
731 | r = hdmi_get_clocks(pdev); | |
732 | if (r) { | |
733 | DSSERR("can't get clocks\n"); | |
734 | return r; | |
735 | } | |
736 | ||
737 | irq = platform_get_irq(pdev, 0); | |
738 | if (irq < 0) { | |
739 | DSSERR("platform_get_irq failed\n"); | |
740 | return -ENODEV; | |
741 | } | |
742 | ||
743 | r = devm_request_threaded_irq(&pdev->dev, irq, | |
744 | NULL, hdmi_irq_handler, | |
745 | IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); | |
746 | if (r) { | |
747 | DSSERR("HDMI IRQ request failed\n"); | |
748 | return r; | |
749 | } | |
750 | ||
751 | pm_runtime_enable(&pdev->dev); | |
752 | ||
753 | hdmi_init_output(pdev); | |
754 | ||
755 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
760 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | |
761 | { | |
762 | hdmi_uninit_output(pdev); | |
763 | ||
764 | pm_runtime_disable(&pdev->dev); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
769 | static int hdmi_runtime_suspend(struct device *dev) | |
770 | { | |
771 | clk_disable_unprepare(hdmi.sys_clk); | |
772 | ||
773 | dispc_runtime_put(); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static int hdmi_runtime_resume(struct device *dev) | |
779 | { | |
780 | int r; | |
781 | ||
782 | r = dispc_runtime_get(); | |
783 | if (r < 0) | |
784 | return r; | |
785 | ||
786 | clk_prepare_enable(hdmi.sys_clk); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | static const struct dev_pm_ops hdmi_pm_ops = { | |
792 | .runtime_suspend = hdmi_runtime_suspend, | |
793 | .runtime_resume = hdmi_runtime_resume, | |
794 | }; | |
795 | ||
796 | static const struct of_device_id hdmi_of_match[] = { | |
797 | { .compatible = "ti,omap5-hdmi", }, | |
798 | {}, | |
799 | }; | |
800 | ||
801 | static struct platform_driver omapdss_hdmihw_driver = { | |
802 | .probe = omapdss_hdmihw_probe, | |
803 | .remove = __exit_p(omapdss_hdmihw_remove), | |
804 | .driver = { | |
805 | .name = "omapdss_hdmi5", | |
806 | .owner = THIS_MODULE, | |
807 | .pm = &hdmi_pm_ops, | |
808 | .of_match_table = hdmi_of_match, | |
422ccbd5 | 809 | .suppress_bind_attrs = true, |
f5bab222 TV |
810 | }, |
811 | }; | |
812 | ||
813 | int __init hdmi5_init_platform_driver(void) | |
814 | { | |
815 | return platform_driver_register(&omapdss_hdmihw_driver); | |
816 | } | |
817 | ||
818 | void __exit hdmi5_uninit_platform_driver(void) | |
819 | { | |
820 | platform_driver_unregister(&omapdss_hdmihw_driver); | |
821 | } |