[mirror_ubuntu-zesty-kernel.git] / drivers / video / fbdev / pxafb.h

#ifndef __PXAFB_H__
#define __PXAFB_H__

/*
 * linux/drivers/video/pxafb.h
 *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
 *
 *  Copyright (C) 1999 Eric A. Thomas.
 *  Copyright (C) 2004 Jean-Frederic Clere.
 *  Copyright (C) 2004 Ian Campbell.
 *  Copyright (C) 2004 Jeff Lackey.
 *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
 *  which in turn is
 *   Based on acornfb.c Copyright (C) Russell King.
 *
 *  2001-08-03: Cliff Brake <cbrake@acclent.com>
 *	 - ported SA1100 code to PXA
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

/* PXA LCD DMA descriptor */
struct pxafb_dma_descriptor {
	unsigned int fdadr;
	unsigned int fsadr;
	unsigned int fidr;
	unsigned int ldcmd;
};

enum {
	PAL_NONE	= -1,
	PAL_BASE	= 0,
	PAL_OV1		= 1,
	PAL_OV2		= 2,
	PAL_MAX,
};

enum {
	DMA_BASE	= 0,
	DMA_UPPER	= 0,
	DMA_LOWER	= 1,
	DMA_OV1		= 1,
	DMA_OV2_Y	= 2,
	DMA_OV2_Cb	= 3,
	DMA_OV2_Cr	= 4,
	DMA_CURSOR	= 5,
	DMA_CMD		= 6,
	DMA_MAX,
};

/* maximum palette size - 256 entries, each 4 bytes long */
#define PALETTE_SIZE	(256 * 4)
#define CMD_BUFF_SIZE	(1024 * 50)

/* NOTE: the palette and frame dma descriptors are doubled to allow
 * the 2nd set for branch settings (FBRx)
 */
struct pxafb_dma_buff {
	unsigned char palette[PAL_MAX * PALETTE_SIZE];
	uint16_t cmd_buff[CMD_BUFF_SIZE];
	struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
	struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
};

enum {
	OVERLAY1,
	OVERLAY2,
};

enum {
	OVERLAY_FORMAT_RGB = 0,
	OVERLAY_FORMAT_YUV444_PACKED,
	OVERLAY_FORMAT_YUV444_PLANAR,
	OVERLAY_FORMAT_YUV422_PLANAR,
	OVERLAY_FORMAT_YUV420_PLANAR,
};

#define NONSTD_TO_XPOS(x)	(((x) >> 0)  & 0x3ff)
#define NONSTD_TO_YPOS(x)	(((x) >> 10) & 0x3ff)
#define NONSTD_TO_PFOR(x)	(((x) >> 20) & 0x7)

struct pxafb_layer;

struct pxafb_layer_ops {
	void (*enable)(struct pxafb_layer *);
	void (*disable)(struct pxafb_layer *);
	void (*setup)(struct pxafb_layer *);
};

struct pxafb_layer {
	struct fb_info		fb;
	int			id;
	int			registered;
	uint32_t		usage;
	uint32_t		control[2];

	struct pxafb_layer_ops	*ops;

	void __iomem		*video_mem;
	unsigned long		video_mem_phys;
	size_t			video_mem_size;
	struct completion	branch_done;

	struct pxafb_info	*fbi;
};

struct pxafb_info {
	struct fb_info		fb;
	struct device		*dev;
	struct clk		*clk;

	void __iomem		*mmio_base;

	struct pxafb_dma_buff	*dma_buff;
	size_t			dma_buff_size;
	dma_addr_t		dma_buff_phys;
	dma_addr_t		fdadr[DMA_MAX * 2];

	void __iomem		*video_mem;	/* virtual address of frame buffer */
	unsigned long		video_mem_phys;	/* physical address of frame buffer */
	size_t			video_mem_size;	/* size of the frame buffer */
	u16 *			palette_cpu;	/* virtual address of palette memory */
	u_int			palette_size;

	u_int			lccr0;
	u_int			lccr3;
	u_int			lccr4;
	u_int			cmap_inverse:1,
				cmap_static:1,
				unused:30;

	u_int			reg_lccr0;
	u_int			reg_lccr1;
	u_int			reg_lccr2;
	u_int			reg_lccr3;
	u_int			reg_lccr4;
	u_int			reg_cmdcr;

	unsigned long	hsync_time;

	volatile u_char		state;
	volatile u_char		task_state;
	struct mutex		ctrlr_lock;
	wait_queue_head_t	ctrlr_wait;
	struct work_struct	task;

	struct completion	disable_done;

#ifdef CONFIG_FB_PXA_SMARTPANEL
	uint16_t		*smart_cmds;
	size_t			n_smart_cmds;
	struct completion	command_done;
	struct completion	refresh_done;
	struct task_struct	*smart_thread;
#endif

#ifdef CONFIG_FB_PXA_OVERLAY
	struct pxafb_layer	overlay[2];
#endif

#ifdef CONFIG_CPU_FREQ
	struct notifier_block	freq_transition;
	struct notifier_block	freq_policy;
#endif

	void (*lcd_power)(int, struct fb_var_screeninfo *);
	void (*backlight_power)(int);

	struct pxafb_mach_info	*inf;
};

#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)

/*
 * These are the actions for set_ctrlr_state
 */
#define C_DISABLE		(0)
#define C_ENABLE		(1)
#define C_DISABLE_CLKCHANGE	(2)
#define C_ENABLE_CLKCHANGE	(3)
#define C_REENABLE		(4)
#define C_DISABLE_PM		(5)
#define C_ENABLE_PM		(6)
#define C_STARTUP		(7)

#define PXA_NAME	"PXA"

/*
 * Minimum X and Y resolutions
 */
#define MIN_XRES	64
#define MIN_YRES	64

/* maximum X and Y resolutions - note these are limits from the register
 * bits length instead of the real ones
 */
#define MAX_XRES	1024
#define MAX_YRES	1024

#endif /* __PXAFB_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __PXAFB_H__
	2	#define __PXAFB_H__
	3
	4	/*
	5	* linux/drivers/video/pxafb.h
	6	* -- Intel PXA250/210 LCD Controller Frame Buffer Device
	7	*
	8	* Copyright (C) 1999 Eric A. Thomas.
	9	* Copyright (C) 2004 Jean-Frederic Clere.
	10	* Copyright (C) 2004 Ian Campbell.
	11	* Copyright (C) 2004 Jeff Lackey.
	12	* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
	13	* which in turn is
	14	* Based on acornfb.c Copyright (C) Russell King.
	15	*
	16	* 2001-08-03: Cliff Brake <cbrake@acclent.com>
	17	* - ported SA1100 code to PXA
	18	*
	19	* This file is subject to the terms and conditions of the GNU General Public
	20	* License. See the file COPYING in the main directory of this archive
	21	* for more details.
	22	*/
	23
1da177e4 LT	24	/* PXA LCD DMA descriptor */
	25	struct pxafb_dma_descriptor {
	26	unsigned int fdadr;
	27	unsigned int fsadr;
	28	unsigned int fidr;
	29	unsigned int ldcmd;
	30	};
	31
2c42dd8e	32	enum {
	33	PAL_NONE = -1,
	34	PAL_BASE = 0,
	35	PAL_OV1 = 1,
	36	PAL_OV2 = 2,
	37	PAL_MAX,
	38	};
	39
	40	enum {
	41	DMA_BASE = 0,
	42	DMA_UPPER = 0,
	43	DMA_LOWER = 1,
	44	DMA_OV1 = 1,
	45	DMA_OV2_Y = 2,
	46	DMA_OV2_Cb = 3,
	47	DMA_OV2_Cr = 4,
	48	DMA_CURSOR = 5,
	49	DMA_CMD = 6,
	50	DMA_MAX,
	51	};
	52
	53	/* maximum palette size - 256 entries, each 4 bytes long */
	54	#define PALETTE_SIZE (256 * 4)
3c42a449	55	#define CMD_BUFF_SIZE (1024 * 50)
2c42dd8e	56
6e354846 EM	57	/* NOTE: the palette and frame dma descriptors are doubled to allow
	58	* the 2nd set for branch settings (FBRx)
	59	*/
2c42dd8e	60	struct pxafb_dma_buff {
2c42dd8e	61	unsigned char palette[PAL_MAX * PALETTE_SIZE];
3c42a449	62	uint16_t cmd_buff[CMD_BUFF_SIZE];
6e354846 EM	63	struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
6e354846 EM	64	struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
2c42dd8e	65	};
2c42dd8e	66
198fc108 EM	67	enum {
	68	OVERLAY1,
	69	OVERLAY2,
	70	};
	71
	72	enum {
	73	OVERLAY_FORMAT_RGB = 0,
	74	OVERLAY_FORMAT_YUV444_PACKED,
	75	OVERLAY_FORMAT_YUV444_PLANAR,
	76	OVERLAY_FORMAT_YUV422_PLANAR,
	77	OVERLAY_FORMAT_YUV420_PLANAR,
	78	};
	79
	80	#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
	81	#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
	82	#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
	83
	84	struct pxafb_layer;
	85
	86	struct pxafb_layer_ops {
	87	void (enable)(struct pxafb_layer );
	88	void (disable)(struct pxafb_layer );
	89	void (setup)(struct pxafb_layer );
	90	};
	91
	92	struct pxafb_layer {
	93	struct fb_info fb;
	94	int id;
1b98d7c4 VK	95	int registered;
1b98d7c4 VK	96	uint32_t usage;
198fc108 EM	97	uint32_t control[2];
	98
	99	struct pxafb_layer_ops *ops;
	100
	101	void __iomem *video_mem;
	102	unsigned long video_mem_phys;
	103	size_t video_mem_size;
	104	struct completion branch_done;
	105
	106	struct pxafb_info *fbi;
	107	};
	108
1da177e4 LT	109	struct pxafb_info {
	110	struct fb_info fb;
	111	struct device *dev;
72e3524c	112	struct clk *clk;
1da177e4	113
ce4fb7b8	114	void __iomem *mmio_base;
ce4fb7b8	115
2c42dd8e	116	struct pxafb_dma_buff *dma_buff;
77e19675	117	size_t dma_buff_size;
2c42dd8e	118	dma_addr_t dma_buff_phys;
6e354846	119	dma_addr_t fdadr[DMA_MAX * 2];
2c42dd8e	120
77e19675 EM	121	void __iomem video_mem; / virtual address of frame buffer */
	122	unsigned long video_mem_phys; /* physical address of frame buffer */
	123	size_t video_mem_size; /* size of the frame buffer */
1da177e4	124	u16 * palette_cpu; /* virtual address of palette memory */
1da177e4 LT	125	u_int palette_size;
1da177e4 LT	126
1da177e4 LT	127	u_int lccr0;
1da177e4 LT	128	u_int lccr3;
9ffa7396	129	u_int lccr4;
1da177e4 LT	130	u_int cmap_inverse:1,
	131	cmap_static:1,
	132	unused:30;
	133
	134	u_int reg_lccr0;
	135	u_int reg_lccr1;
	136	u_int reg_lccr2;
	137	u_int reg_lccr3;
9ffa7396	138	u_int reg_lccr4;
3c42a449	139	u_int reg_cmdcr;
1da177e4	140
ba44cd2d RP	141	unsigned long hsync_time;
ba44cd2d RP	142
1da177e4 LT	143	volatile u_char state;
1da177e4 LT	144	volatile u_char task_state;
b91dbce5	145	struct mutex ctrlr_lock;
1da177e4 LT	146	wait_queue_head_t ctrlr_wait;
	147	struct work_struct task;
	148
2ba162b9 EM	149	struct completion disable_done;
2ba162b9 EM	150
3c42a449 EM	151	#ifdef CONFIG_FB_PXA_SMARTPANEL
	152	uint16_t *smart_cmds;
	153	size_t n_smart_cmds;
	154	struct completion command_done;
	155	struct completion refresh_done;
	156	struct task_struct *smart_thread;
	157	#endif
	158
198fc108 EM	159	#ifdef CONFIG_FB_PXA_OVERLAY
	160	struct pxafb_layer overlay[2];
	161	#endif
	162
1da177e4 LT	163	#ifdef CONFIG_CPU_FREQ
	164	struct notifier_block freq_transition;
	165	struct notifier_block freq_policy;
	166	#endif
a5718a14 EM	167
	168	void (lcd_power)(int, struct fb_var_screeninfo );
	169	void (*backlight_power)(int);
f3621a60 RJ	170
f3621a60 RJ	171	struct pxafb_mach_info *inf;
1da177e4 LT	172	};
	173
	174	#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
	175
	176	/*
	177	* These are the actions for set_ctrlr_state
	178	*/
	179	#define C_DISABLE (0)
	180	#define C_ENABLE (1)
	181	#define C_DISABLE_CLKCHANGE (2)
	182	#define C_ENABLE_CLKCHANGE (3)
	183	#define C_REENABLE (4)
	184	#define C_DISABLE_PM (5)
	185	#define C_ENABLE_PM (6)
	186	#define C_STARTUP (7)
	187
	188	#define PXA_NAME "PXA"
	189
1da177e4 LT	190	/*
	191	* Minimum X and Y resolutions
	192	*/
	193	#define MIN_XRES 64
	194	#define MIN_YRES 64
	195
3f16ff60 EM	196	/* maximum X and Y resolutions - note these are limits from the register
	197	* bits length instead of the real ones
	198	*/
	199	#define MAX_XRES 1024
	200	#define MAX_YRES 1024
	201
1da177e4	202	#endif /* __PXAFB_H__ */