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UBUNTU: Ubuntu-5.15.0-39.42
[mirror_ubuntu-jammy-kernel.git] / drivers / video / fbdev / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
c5deac3c 15#include <linux/ctype.h>
cfb4f5d1 16#include <linux/dma-mapping.h>
f1f60b5f 17#include <linux/delay.h>
9e146700 18#include <linux/fbcon.h>
f1f60b5f 19#include <linux/init.h>
8564557a 20#include <linux/interrupt.h>
40331b21 21#include <linux/ioctl.h>
f1f60b5f
LP		 22#include <linux/kernel.h>
23#include <linux/mm.h>
355b200b 24#include <linux/module.h>
f1f60b5f
LP		 25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/videodev2.h>
29#include <linux/vmalloc.h>
30
225c9a8d 31#include <video/sh_mobile_lcdc.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
c5deac3c
LP		 35/* ----------------------------------------------------------------------------
36 * Overlay register definitions
37 */
38
39#define LDBCR 0xb00
40#define LDBCR_UPC(n) (1 << ((n) + 16))
41#define LDBCR_UPF(n) (1 << ((n) + 8))
42#define LDBCR_UPD(n) (1 << ((n) + 0))
43#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
44#define LDBBSIFR_EN (1 << 31)
45#define LDBBSIFR_VS (1 << 29)
46#define LDBBSIFR_BRSEL (1 << 28)
47#define LDBBSIFR_MX (1 << 27)
48#define LDBBSIFR_MY (1 << 26)
49#define LDBBSIFR_CV3 (3 << 24)
50#define LDBBSIFR_CV2 (2 << 24)
51#define LDBBSIFR_CV1 (1 << 24)
52#define LDBBSIFR_CV0 (0 << 24)
53#define LDBBSIFR_CV_MASK (3 << 24)
54#define LDBBSIFR_LAY_MASK (0xff << 16)
55#define LDBBSIFR_LAY_SHIFT 16
56#define LDBBSIFR_ROP3_MASK (0xff << 16)
57#define LDBBSIFR_ROP3_SHIFT 16
58#define LDBBSIFR_AL_PL8 (3 << 14)
59#define LDBBSIFR_AL_PL1 (2 << 14)
60#define LDBBSIFR_AL_PK (1 << 14)
61#define LDBBSIFR_AL_1 (0 << 14)
62#define LDBBSIFR_AL_MASK (3 << 14)
63#define LDBBSIFR_SWPL (1 << 10)
64#define LDBBSIFR_SWPW (1 << 9)
65#define LDBBSIFR_SWPB (1 << 8)
66#define LDBBSIFR_RY (1 << 7)
67#define LDBBSIFR_CHRR_420 (2 << 0)
68#define LDBBSIFR_CHRR_422 (1 << 0)
69#define LDBBSIFR_CHRR_444 (0 << 0)
70#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
71#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
72#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
73#define LDBBSIFR_RPKF_MASK (0x1f << 0)
74#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
75#define LDBBSSZR_BVSS_MASK (0xfff << 16)
76#define LDBBSSZR_BVSS_SHIFT 16
77#define LDBBSSZR_BHSS_MASK (0xfff << 0)
78#define LDBBSSZR_BHSS_SHIFT 0
79#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
80#define LDBBLOCR_CVLC_MASK (0xfff << 16)
81#define LDBBLOCR_CVLC_SHIFT 16
82#define LDBBLOCR_CHLC_MASK (0xfff << 0)
83#define LDBBLOCR_CHLC_SHIFT 0
84#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
85#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
86#define LDBBSMWR_BSMWA_SHIFT 16
87#define LDBBSMWR_BSMW_MASK (0xffff << 0)
88#define LDBBSMWR_BSMW_SHIFT 0
89#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
90#define LDBBSAYR_FG1A_MASK (0xff << 24)
91#define LDBBSAYR_FG1A_SHIFT 24
92#define LDBBSAYR_FG1R_MASK (0xff << 16)
93#define LDBBSAYR_FG1R_SHIFT 16
94#define LDBBSAYR_FG1G_MASK (0xff << 8)
95#define LDBBSAYR_FG1G_SHIFT 8
96#define LDBBSAYR_FG1B_MASK (0xff << 0)
97#define LDBBSAYR_FG1B_SHIFT 0
98#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
99#define LDBBSACR_FG2A_MASK (0xff << 24)
100#define LDBBSACR_FG2A_SHIFT 24
101#define LDBBSACR_FG2R_MASK (0xff << 16)
102#define LDBBSACR_FG2R_SHIFT 16
103#define LDBBSACR_FG2G_MASK (0xff << 8)
104#define LDBBSACR_FG2G_SHIFT 8
105#define LDBBSACR_FG2B_MASK (0xff << 0)
106#define LDBBSACR_FG2B_SHIFT 0
107#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
108#define LDBBSAAR_AP_MASK (0xff << 24)
109#define LDBBSAAR_AP_SHIFT 24
110#define LDBBSAAR_R_MASK (0xff << 16)
111#define LDBBSAAR_R_SHIFT 16
112#define LDBBSAAR_GY_MASK (0xff << 8)
113#define LDBBSAAR_GY_SHIFT 8
114#define LDBBSAAR_B_MASK (0xff << 0)
115#define LDBBSAAR_B_SHIFT 0
116#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
117#define LDBBPPCR_AP_MASK (0xff << 24)
118#define LDBBPPCR_AP_SHIFT 24
119#define LDBBPPCR_R_MASK (0xff << 16)
120#define LDBBPPCR_R_SHIFT 16
121#define LDBBPPCR_GY_MASK (0xff << 8)
122#define LDBBPPCR_GY_SHIFT 8
123#define LDBBPPCR_B_MASK (0xff << 0)
124#define LDBBPPCR_B_SHIFT 0
125#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
126#define LDBBBGCL_BGA_MASK (0xff << 24)
127#define LDBBBGCL_BGA_SHIFT 24
128#define LDBBBGCL_BGR_MASK (0xff << 16)
129#define LDBBBGCL_BGR_SHIFT 16
130#define LDBBBGCL_BGG_MASK (0xff << 8)
131#define LDBBBGCL_BGG_SHIFT 8
132#define LDBBBGCL_BGB_MASK (0xff << 0)
133#define LDBBBGCL_BGB_SHIFT 0
134
a6f15ade
PE		 135#define SIDE_B_OFFSET 0x1000
136#define MIRROR_OFFSET 0x2000
cfb4f5d1 137
d2ecbab5
GL		 138#define MAX_XRES 1920
139#define MAX_YRES 1080
cfb4f5d1 140
c5deac3c
LP		 141enum sh_mobile_lcdc_overlay_mode {
142 LCDC_OVERLAY_BLEND,
143 LCDC_OVERLAY_ROP3,
144};
145
146/*
147 * struct sh_mobile_lcdc_overlay - LCDC display overlay
148 *
149 * @channel: LCDC channel this overlay belongs to
150 * @cfg: Overlay configuration
151 * @info: Frame buffer device
152 * @index: Overlay index (0-3)
153 * @base: Overlay registers base address
154 * @enabled: True if the overlay is enabled
155 * @mode: Overlay blending mode (alpha blend or ROP3)
156 * @alpha: Global alpha blending value (0-255, for alpha blending mode)
157 * @rop3: Raster operation (for ROP3 mode)
158 * @fb_mem: Frame buffer virtual memory address
159 * @fb_size: Frame buffer size in bytes
160 * @dma_handle: Frame buffer DMA address
161 * @base_addr_y: Overlay base address (RGB or luma component)
162 * @base_addr_c: Overlay base address (chroma component)
a4aa25f6 163 * @pan_y_offset: Panning linear offset in bytes (luma component)
c5deac3c
LP		 164 * @format: Current pixelf format
165 * @xres: Horizontal visible resolution
166 * @xres_virtual: Horizontal total resolution
167 * @yres: Vertical visible resolution
168 * @yres_virtual: Vertical total resolution
169 * @pitch: Overlay line pitch
170 * @pos_x: Horizontal overlay position
171 * @pos_y: Vertical overlay position
172 */
173struct sh_mobile_lcdc_overlay {
174 struct sh_mobile_lcdc_chan *channel;
175
176 const struct sh_mobile_lcdc_overlay_cfg *cfg;
177 struct fb_info *info;
178
179 unsigned int index;
180 unsigned long base;
181
182 bool enabled;
183 enum sh_mobile_lcdc_overlay_mode mode;
184 unsigned int alpha;
185 unsigned int rop3;
186
187 void *fb_mem;
188 unsigned long fb_size;
189
190 dma_addr_t dma_handle;
191 unsigned long base_addr_y;
192 unsigned long base_addr_c;
a4aa25f6 193 unsigned long pan_y_offset;
c5deac3c
LP		 194
195 const struct sh_mobile_lcdc_format_info *format;
196 unsigned int xres;
197 unsigned int xres_virtual;
198 unsigned int yres;
199 unsigned int yres_virtual;
200 unsigned int pitch;
201 int pos_x;
202 int pos_y;
203};
204
f1f60b5f
LP		 205struct sh_mobile_lcdc_priv {
206 void __iomem *base;
207 int irq;
208 atomic_t hw_usecnt;
209 struct device *dev;
210 struct clk *dot_clk;
211 unsigned long lddckr;
c5deac3c 212
f1f60b5f 213 struct sh_mobile_lcdc_chan ch[2];
c5deac3c
LP		 214 struct sh_mobile_lcdc_overlay overlays[4];
215
f1f60b5f
LP		 216 int started;
217 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
f1f60b5f
LP		 218};
219
220/* -----------------------------------------------------------------------------
221 * Registers access
222 */
223
0246c471 224static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 225 [LDDCKPAT1R] = 0x400,
226 [LDDCKPAT2R] = 0x404,
227 [LDMT1R] = 0x418,
228 [LDMT2R] = 0x41c,
229 [LDMT3R] = 0x420,
230 [LDDFR] = 0x424,
231 [LDSM1R] = 0x428,
8564557a 232 [LDSM2R] = 0x42c,
cfb4f5d1 233 [LDSA1R] = 0x430,
53b50314 234 [LDSA2R] = 0x434,
cfb4f5d1
MD		 235 [LDMLSR] = 0x438,
236 [LDHCNR] = 0x448,
237 [LDHSYNR] = 0x44c,
238 [LDVLNR] = 0x450,
239 [LDVSYNR] = 0x454,
240 [LDPMR] = 0x460,
6011bdea 241 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 242};
243
0246c471 244static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 245 [LDDCKPAT1R] = 0x408,
246 [LDDCKPAT2R] = 0x40c,
247 [LDMT1R] = 0x600,
248 [LDMT2R] = 0x604,
249 [LDMT3R] = 0x608,
250 [LDDFR] = 0x60c,
251 [LDSM1R] = 0x610,
8564557a 252 [LDSM2R] = 0x614,
cfb4f5d1
MD		 253 [LDSA1R] = 0x618,
254 [LDMLSR] = 0x620,
255 [LDHCNR] = 0x624,
256 [LDHSYNR] = 0x628,
257 [LDVLNR] = 0x62c,
258 [LDVSYNR] = 0x630,
259 [LDPMR] = 0x63c,
260};
261
a6f15ade
PE		 262static bool banked(int reg_nr)
263{
264 switch (reg_nr) {
265 case LDMT1R:
266 case LDMT2R:
267 case LDMT3R:
268 case LDDFR:
269 case LDSM1R:
270 case LDSA1R:
53b50314 271 case LDSA2R:
a6f15ade
PE		 272 case LDMLSR:
273 case LDHCNR:
274 case LDHSYNR:
275 case LDVLNR:
276 case LDVSYNR:
277 return true;
278 }
279 return false;
280}
281
f1f60b5f
LP		 282static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
283{
b5ef967d 284 return chan->cfg->chan == LCDC_CHAN_SUBLCD;
f1f60b5f
LP		 285}
286
cfb4f5d1
MD		 287static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
288 int reg_nr, unsigned long data)
289{
290 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 291 if (banked(reg_nr))
292 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
293 SIDE_B_OFFSET);
294}
295
296static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
297 int reg_nr, unsigned long data)
298{
299 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
300 MIRROR_OFFSET);
cfb4f5d1
MD		 301}
302
303static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
304 int reg_nr)
305{
306 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
307}
308
c5deac3c
LP		 309static void lcdc_write_overlay(struct sh_mobile_lcdc_overlay *ovl,
310 int reg, unsigned long data)
311{
312 iowrite32(data, ovl->channel->lcdc->base + reg);
313 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET);
314}
315
cfb4f5d1
MD		 316static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
317 unsigned long reg_offs, unsigned long data)
318{
319 iowrite32(data, priv->base + reg_offs);
320}
321
322static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
323 unsigned long reg_offs)
324{
325 return ioread32(priv->base + reg_offs);
326}
327
328static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
329 unsigned long reg_offs,
330 unsigned long mask, unsigned long until)
331{
332 while ((lcdc_read(priv, reg_offs) & mask) != until)
333 cpu_relax();
334}
335
f1f60b5f
LP		 336/* -----------------------------------------------------------------------------
337 * Clock management
338 */
339
340static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 341{
f1f60b5f 342 if (atomic_inc_and_test(&priv->hw_usecnt)) {
5988c269 343 clk_prepare_enable(priv->dot_clk);
f1f60b5f 344 pm_runtime_get_sync(priv->dev);
f1f60b5f 345 }
cfb4f5d1
MD		 346}
347
f1f60b5f
LP		 348static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
349{
350 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
f1f60b5f 351 pm_runtime_put(priv->dev);
5988c269 352 clk_disable_unprepare(priv->dot_clk);
f1f60b5f
LP		 353 }
354}
355
0a7f17aa
LP		 356static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
357 int clock_source)
f1f60b5f 358{
4774c12a 359 struct clk *clk;
f1f60b5f
LP		 360 char *str;
361
362 switch (clock_source) {
363 case LCDC_CLK_BUS:
364 str = "bus_clk";
365 priv->lddckr = LDDCKR_ICKSEL_BUS;
366 break;
367 case LCDC_CLK_PERIPHERAL:
368 str = "peripheral_clk";
369 priv->lddckr = LDDCKR_ICKSEL_MIPI;
370 break;
371 case LCDC_CLK_EXTERNAL:
372 str = NULL;
373 priv->lddckr = LDDCKR_ICKSEL_HDMI;
374 break;
375 default:
376 return -EINVAL;
377 }
378
4774c12a
LP		 379 if (str == NULL)
380 return 0;
381
0a7f17aa 382 clk = clk_get(priv->dev, str);
4774c12a 383 if (IS_ERR(clk)) {
0a7f17aa 384 dev_err(priv->dev, "cannot get dot clock %s\n", str);
4774c12a 385 return PTR_ERR(clk);
f1f60b5f
LP		 386 }
387
4774c12a 388 priv->dot_clk = clk;
f1f60b5f
LP		 389 return 0;
390}
391
392/* -----------------------------------------------------------------------------
37c5dcc2 393 * Display, panel and deferred I/O
f1f60b5f
LP		 394 */
395
cfb4f5d1
MD		 396static void lcdc_sys_write_index(void *handle, unsigned long data)
397{
398 struct sh_mobile_lcdc_chan *ch = handle;
399
ce1c0b08
LP		 400 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
401 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
402 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
403 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
404 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 405}
406
407static void lcdc_sys_write_data(void *handle, unsigned long data)
408{
409 struct sh_mobile_lcdc_chan *ch = handle;
410
ce1c0b08
LP		 411 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
412 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
413 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
414 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
415 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 416}
417
418static unsigned long lcdc_sys_read_data(void *handle)
419{
420 struct sh_mobile_lcdc_chan *ch = handle;
421
ce1c0b08
LP		 422 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
423 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
424 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
425 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 426 udelay(1);
ce1c0b08 427 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 428
ce1c0b08 429 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 430}
431
d38d840a 432static struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
6895aff4
KC		 433 .write_index = lcdc_sys_write_index,
434 .write_data = lcdc_sys_write_data,
435 .read_data = lcdc_sys_read_data,
cfb4f5d1
MD		 436};
437
1c6a307a
PM		 438static int sh_mobile_lcdc_sginit(struct fb_info *info,
439 struct list_head *pagelist)
440{
441 struct sh_mobile_lcdc_chan *ch = info->par;
58f03d99 442 unsigned int nr_pages_max = ch->fb_size >> PAGE_SHIFT;
1c6a307a
PM		 443 struct page *page;
444 int nr_pages = 0;
445
446 sg_init_table(ch->sglist, nr_pages_max);
447
448 list_for_each_entry(page, pagelist, lru)
449 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
450
451 return nr_pages;
452}
453
8564557a
MD		 454static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
455 struct list_head *pagelist)
456{
457 struct sh_mobile_lcdc_chan *ch = info->par;
b5ef967d 458 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
8564557a
MD		 459
460 /* enable clocks before accessing hardware */
461 sh_mobile_lcdc_clk_on(ch->lcdc);
462
5c1a56b5
PM		 463 /*
464 * It's possible to get here without anything on the pagelist via
465 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
466 * invocation. In the former case, the acceleration routines are
467 * stepped in to when using the framebuffer console causing the
468 * workqueue to be scheduled without any dirty pages on the list.
469 *
470 * Despite this, a panel update is still needed given that the
471 * acceleration routines have their own methods for writing in
472 * that still need to be updated.
473 *
474 * The fsync() and empty pagelist case could be optimized for,
475 * but we don't bother, as any application exhibiting such
476 * behaviour is fundamentally broken anyways.
477 */
478 if (!list_empty(pagelist)) {
479 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
480
481 /* trigger panel update */
e8363140 482 dma_map_sg(ch->lcdc->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
afaad83b
LP		 483 if (panel->start_transfer)
484 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 485 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
e8363140
LP		 486 dma_unmap_sg(ch->lcdc->dev, ch->sglist, nr_pages,
487 DMA_TO_DEVICE);
ef61aae4 488 } else {
afaad83b
LP		 489 if (panel->start_transfer)
490 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 491 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 492 }
8564557a
MD		 493}
494
495static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
496{
497 struct fb_deferred_io *fbdefio = info->fbdefio;
498
499 if (fbdefio)
500 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
501}
502
37c5dcc2
LP		 503static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
504{
b5ef967d 505 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 506
9a2985e7 507 if (ch->tx_dev) {
458981c3
LP		 508 int ret;
509
510 ret = ch->tx_dev->ops->display_on(ch->tx_dev);
511 if (ret < 0)
9a2985e7 512 return;
458981c3
LP		 513
514 if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
515 ch->info->state = FBINFO_STATE_SUSPENDED;
9a2985e7
LP		 516 }
517
37c5dcc2 518 /* HDMI must be enabled before LCDC configuration */
afaad83b
LP		 519 if (panel->display_on)
520 panel->display_on();
37c5dcc2
LP		 521}
522
523static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
524{
b5ef967d 525 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 526
afaad83b
LP		 527 if (panel->display_off)
528 panel->display_off();
9a2985e7
LP		 529
530 if (ch->tx_dev)
531 ch->tx_dev->ops->display_off(ch->tx_dev);
37c5dcc2
LP		 532}
533
d7ad3342
LP		 534static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
535 struct fb_info *info);
ecd29947 536
f1f60b5f
LP		 537/* -----------------------------------------------------------------------------
538 * Format helpers
539 */
540
105784bb
LP		 541struct sh_mobile_lcdc_format_info {
542 u32 fourcc;
543 unsigned int bpp;
544 bool yuv;
545 u32 lddfr;
546};
547
548static const struct sh_mobile_lcdc_format_info sh_mobile_format_infos[] = {
549 {
550 .fourcc = V4L2_PIX_FMT_RGB565,
551 .bpp = 16,
552 .yuv = false,
553 .lddfr = LDDFR_PKF_RGB16,
554 }, {
555 .fourcc = V4L2_PIX_FMT_BGR24,
556 .bpp = 24,
557 .yuv = false,
558 .lddfr = LDDFR_PKF_RGB24,
559 }, {
560 .fourcc = V4L2_PIX_FMT_BGR32,
561 .bpp = 32,
562 .yuv = false,
563 .lddfr = LDDFR_PKF_ARGB32,
564 }, {
565 .fourcc = V4L2_PIX_FMT_NV12,
566 .bpp = 12,
567 .yuv = true,
568 .lddfr = LDDFR_CC | LDDFR_YF_420,
569 }, {
570 .fourcc = V4L2_PIX_FMT_NV21,
571 .bpp = 12,
572 .yuv = true,
573 .lddfr = LDDFR_CC | LDDFR_YF_420,
574 }, {
575 .fourcc = V4L2_PIX_FMT_NV16,
576 .bpp = 16,
577 .yuv = true,
578 .lddfr = LDDFR_CC | LDDFR_YF_422,
579 }, {
580 .fourcc = V4L2_PIX_FMT_NV61,
581 .bpp = 16,
582 .yuv = true,
583 .lddfr = LDDFR_CC | LDDFR_YF_422,
584 }, {
585 .fourcc = V4L2_PIX_FMT_NV24,
586 .bpp = 24,
587 .yuv = true,
588 .lddfr = LDDFR_CC | LDDFR_YF_444,
589 }, {
590 .fourcc = V4L2_PIX_FMT_NV42,
591 .bpp = 24,
592 .yuv = true,
593 .lddfr = LDDFR_CC | LDDFR_YF_444,
594 },
595};
596
597static const struct sh_mobile_lcdc_format_info *
598sh_mobile_format_info(u32 fourcc)
599{
600 unsigned int i;
601
602 for (i = 0; i < ARRAY_SIZE(sh_mobile_format_infos); ++i) {
603 if (sh_mobile_format_infos[i].fourcc == fourcc)
604 return &sh_mobile_format_infos[i];
605 }
606
607 return NULL;
608}
609
f1f60b5f
LP		 610static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
611{
612 if (var->grayscale > 1)
613 return var->grayscale;
614
615 switch (var->bits_per_pixel) {
616 case 16:
617 return V4L2_PIX_FMT_RGB565;
618 case 24:
619 return V4L2_PIX_FMT_BGR24;
620 case 32:
621 return V4L2_PIX_FMT_BGR32;
622 default:
623 return 0;
624 }
625}
626
627static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
628{
629 return var->grayscale > 1;
630}
631
f1f60b5f
LP		 632/* -----------------------------------------------------------------------------
633 * Start, stop and IRQ
634 */
635
8564557a
MD		 636static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
637{
638 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 639 struct sh_mobile_lcdc_chan *ch;
9dd38819 640 unsigned long ldintr;
2feb075a
MD		 641 int is_sub;
642 int k;
8564557a 643
dc48665f
LP		 644 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
645 ldintr = lcdc_read(priv, _LDINTR);
646 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 647
2feb075a 648 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 649 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 650
9dd38819 651 /* wake up channel and disable clocks */
2feb075a
MD		 652 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
653 ch = &priv->ch[k];
654
655 if (!ch->enabled)
656 continue;
657
dc48665f 658 /* Frame End */
9dd38819
PE		 659 if (ldintr & LDINTR_FS) {
660 if (is_sub == lcdc_chan_is_sublcd(ch)) {
661 ch->frame_end = 1;
662 wake_up(&ch->frame_end_wait);
2feb075a 663
9dd38819
PE		 664 sh_mobile_lcdc_clk_off(priv);
665 }
666 }
667
668 /* VSYNC End */
40331b21
PE		 669 if (ldintr & LDINTR_VES)
670 complete(&ch->vsync_completion);
2feb075a
MD		 671 }
672
8564557a
MD		 673 return IRQ_HANDLED;
674}
675
d7ad3342 676static int sh_mobile_lcdc_wait_for_vsync(struct sh_mobile_lcdc_chan *ch)
4976677f
LP		 677{
678 unsigned long ldintr;
679 int ret;
680
681 /* Enable VSync End interrupt and be careful not to acknowledge any
682 * pending interrupt.
683 */
684 ldintr = lcdc_read(ch->lcdc, _LDINTR);
685 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
686 lcdc_write(ch->lcdc, _LDINTR, ldintr);
687
688 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
689 msecs_to_jiffies(100));
690 if (!ret)
691 return -ETIMEDOUT;
692
693 return 0;
694}
695
cfb4f5d1
MD		 696static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
697 int start)
698{
699 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
700 int k;
701
702 /* start or stop the lcdc */
703 if (start)
ce1c0b08 704 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 705 else
ce1c0b08 706 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 707
708 /* wait until power is applied/stopped on all channels */
709 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
710 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
711 while (1) {
ce1c0b08
LP		 712 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
713 & LDPMR_LPS;
714 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 715 break;
716 if (!start && tmp == 0)
717 break;
718 cpu_relax();
719 }
720
721 if (!start)
722 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
723}
724
6011bdea
GL		 725static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
726{
2d04559d
LP		 727 const struct fb_var_screeninfo *var = &ch->info->var;
728 const struct fb_videomode *mode = &ch->display.mode;
1c120deb 729 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 730 u32 tmp;
731
732 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 733 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
734 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
b5ef967d
LP		 735 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
736 tmp |= (ch->cfg->flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
737 tmp |= (ch->cfg->flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
738 tmp |= (ch->cfg->flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
739 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 740 lcdc_write_chan(ch, LDMT1R, tmp);
741
742 /* setup SYS bus */
b5ef967d
LP		 743 lcdc_write_chan(ch, LDMT2R, ch->cfg->sys_bus_cfg.ldmt2r);
744 lcdc_write_chan(ch, LDMT3R, ch->cfg->sys_bus_cfg.ldmt3r);
6011bdea
GL		 745
746 /* horizontal configuration */
2d04559d
LP		 747 h_total = mode->xres + mode->hsync_len + mode->left_margin
748 + mode->right_margin;
6011bdea 749 tmp = h_total / 8; /* HTCN */
58f03d99 750 tmp |= (min(mode->xres, ch->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 751 lcdc_write_chan(ch, LDHCNR, tmp);
752
2d04559d 753 hsync_pos = mode->xres + mode->right_margin;
6011bdea 754 tmp = hsync_pos / 8; /* HSYNP */
2d04559d 755 tmp |= (mode->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 756 lcdc_write_chan(ch, LDHSYNR, tmp);
757
758 /* vertical configuration */
2d04559d
LP		 759 tmp = mode->yres + mode->vsync_len + mode->upper_margin
760 + mode->lower_margin; /* VTLN */
58f03d99 761 tmp |= min(mode->yres, ch->yres) << 16; /* VDLN */
6011bdea
GL		 762 lcdc_write_chan(ch, LDVLNR, tmp);
763
2d04559d
LP		 764 tmp = mode->yres + mode->lower_margin; /* VSYNP */
765 tmp |= mode->vsync_len << 16; /* VSYNW */
6011bdea
GL		 766 lcdc_write_chan(ch, LDVSYNR, tmp);
767
768 /* Adjust horizontal synchronisation for HDMI */
2d04559d
LP		 769 display_h_total = mode->xres + mode->hsync_len + mode->left_margin
770 + mode->right_margin;
771 tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
772 | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
6011bdea 773 lcdc_write_chan(ch, LDHAJR, tmp);
9beb09f1 774 lcdc_write_chan_mirror(ch, LDHAJR, tmp);
6011bdea
GL		 775}
776
c5deac3c
LP		 777static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
778{
779 u32 format = 0;
780
781 if (!ovl->enabled) {
782 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
783 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), 0);
784 lcdc_write(ovl->channel->lcdc, LDBCR,
785 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
786 return;
787 }
788
789 ovl->base_addr_y = ovl->dma_handle;
a4aa25f6
LP		 790 ovl->base_addr_c = ovl->dma_handle
791 + ovl->xres_virtual * ovl->yres_virtual;
c5deac3c
LP		 792
793 switch (ovl->mode) {
794 case LCDC_OVERLAY_BLEND:
795 format = LDBBSIFR_EN | (ovl->alpha << LDBBSIFR_LAY_SHIFT);
796 break;
797
798 case LCDC_OVERLAY_ROP3:
799 format = LDBBSIFR_EN | LDBBSIFR_BRSEL
800 | (ovl->rop3 << LDBBSIFR_ROP3_SHIFT);
801 break;
802 }
803
804 switch (ovl->format->fourcc) {
805 case V4L2_PIX_FMT_RGB565:
806 case V4L2_PIX_FMT_NV21:
807 case V4L2_PIX_FMT_NV61:
808 case V4L2_PIX_FMT_NV42:
809 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW;
810 break;
811 case V4L2_PIX_FMT_BGR24:
812 case V4L2_PIX_FMT_NV12:
813 case V4L2_PIX_FMT_NV16:
814 case V4L2_PIX_FMT_NV24:
815 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW | LDBBSIFR_SWPB;
816 break;
817 case V4L2_PIX_FMT_BGR32:
818 default:
819 format |= LDBBSIFR_SWPL;
820 break;
821 }
822
823 switch (ovl->format->fourcc) {
824 case V4L2_PIX_FMT_RGB565:
825 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB16;
826 break;
827 case V4L2_PIX_FMT_BGR24:
828 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB24;
829 break;
830 case V4L2_PIX_FMT_BGR32:
831 format |= LDBBSIFR_AL_PK | LDBBSIFR_RY | LDDFR_PKF_ARGB32;
832 break;
833 case V4L2_PIX_FMT_NV12:
834 case V4L2_PIX_FMT_NV21:
835 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_420;
836 break;
837 case V4L2_PIX_FMT_NV16:
838 case V4L2_PIX_FMT_NV61:
839 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_422;
840 break;
841 case V4L2_PIX_FMT_NV24:
842 case V4L2_PIX_FMT_NV42:
843 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_444;
844 break;
845 }
846
847 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
848
849 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), format);
850
851 lcdc_write_overlay(ovl, LDBnBSSZR(ovl->index),
852 (ovl->yres << LDBBSSZR_BVSS_SHIFT) |
853 (ovl->xres << LDBBSSZR_BHSS_SHIFT));
854 lcdc_write_overlay(ovl, LDBnBLOCR(ovl->index),
855 (ovl->pos_y << LDBBLOCR_CVLC_SHIFT) |
856 (ovl->pos_x << LDBBLOCR_CHLC_SHIFT));
857 lcdc_write_overlay(ovl, LDBnBSMWR(ovl->index),
858 ovl->pitch << LDBBSMWR_BSMW_SHIFT);
859
860 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
861 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
862
863 lcdc_write(ovl->channel->lcdc, LDBCR,
864 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
865}
866
9a217e34 867/*
d7ad3342 868 * __sh_mobile_lcdc_start - Configure and start the LCDC
9a217e34
LP		 869 * @priv: LCDC device
870 *
871 * Configure all enabled channels and start the LCDC device. All external
872 * devices (clocks, MERAM, panels, ...) are not touched by this function.
873 */
874static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 875{
876 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 877 unsigned long tmp;
9a217e34 878 int k, m;
8564557a 879
9a217e34
LP		 880 /* Enable LCDC channels. Read data from external memory, avoid using the
881 * BEU for now.
882 */
883 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 884
9a217e34 885 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 886 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 887 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 888
9a217e34 889 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 890 tmp = priv->lddckr;
891 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
892 ch = &priv->ch[k];
9a217e34 893 if (!ch->enabled)
cfb4f5d1
MD		 894 continue;
895
9a217e34
LP		 896 /* Power supply */
897 lcdc_write_chan(ch, LDPMR, 0);
898
b5ef967d 899 m = ch->cfg->clock_divider;
cfb4f5d1
MD		 900 if (!m)
901 continue;
902
505c7de5
LP		 903 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
904 * denominator.
905 */
906 lcdc_write_chan(ch, LDDCKPAT1R, 0);
907 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
908
cfb4f5d1 909 if (m == 1)
ce1c0b08 910 m = LDDCKR_MOSEL;
cfb4f5d1 911 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 912 }
913
914 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 915 lcdc_write(priv, _LDDCKSTPR, 0);
916 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
917
9a217e34 918 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 919 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
920 ch = &priv->ch[k];
cfb4f5d1
MD		 921 if (!ch->enabled)
922 continue;
923
6011bdea 924 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 925
fc9e78e6 926 tmp = ch->format->lddfr;
edd153a3 927
fc9e78e6 928 if (ch->format->yuv) {
58f03d99 929 switch (ch->colorspace) {
edd153a3
LP		 930 case V4L2_COLORSPACE_REC709:
931 tmp |= LDDFR_CF1;
53b50314 932 break;
edd153a3
LP		 933 case V4L2_COLORSPACE_JPEG:
934 tmp |= LDDFR_CF0;
53b50314
DHG		 935 break;
936 }
417d4827 937 }
7caa4342 938
9a217e34 939 lcdc_write_chan(ch, LDDFR, tmp);
72c04af9 940 lcdc_write_chan(ch, LDMLSR, ch->line_size);
9a217e34 941 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
fc9e78e6 942 if (ch->format->yuv)
9a217e34 943 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 944
9a217e34
LP		 945 /* When using deferred I/O mode, configure the LCDC for one-shot
946 * operation and enable the frame end interrupt. Otherwise use
947 * continuous read mode.
948 */
949 if (ch->ldmt1r_value & LDMT1R_IFM &&
b5ef967d 950 ch->cfg->sys_bus_cfg.deferred_io_msec) {
9a217e34
LP		 951 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
952 lcdc_write(priv, _LDINTR, LDINTR_FE);
953 } else {
954 lcdc_write_chan(ch, LDSM1R, 0);
955 }
956 }
7caa4342 957
9a217e34 958 /* Word and long word swap. */
fc9e78e6 959 switch (priv->ch[0].format->fourcc) {
edd153a3
LP		 960 case V4L2_PIX_FMT_RGB565:
961 case V4L2_PIX_FMT_NV21:
962 case V4L2_PIX_FMT_NV61:
963 case V4L2_PIX_FMT_NV42:
964 tmp = LDDDSR_LS | LDDDSR_WS;
965 break;
966 case V4L2_PIX_FMT_BGR24:
967 case V4L2_PIX_FMT_NV12:
968 case V4L2_PIX_FMT_NV16:
969 case V4L2_PIX_FMT_NV24:
9a217e34 970 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 971 break;
972 case V4L2_PIX_FMT_BGR32:
973 default:
974 tmp = LDDDSR_LS;
975 break;
9a217e34
LP		 976 }
977 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 978
9a217e34
LP		 979 /* Enable the display output. */
980 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
981 sh_mobile_lcdc_start_stop(priv, 1);
982 priv->started = 1;
983}
cfb4f5d1 984
9a217e34
LP		 985static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
986{
9a217e34
LP		 987 struct sh_mobile_lcdc_chan *ch;
988 unsigned long tmp;
989 int ret;
990 int k;
cfb4f5d1 991
9a217e34
LP		 992 /* enable clocks before accessing the hardware */
993 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
994 if (priv->ch[k].enabled)
995 sh_mobile_lcdc_clk_on(priv);
996 }
8564557a 997
9a217e34
LP		 998 /* reset */
999 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
1000 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 1001
9a217e34 1002 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
b5ef967d 1003 const struct sh_mobile_lcdc_panel_cfg *panel;
8564557a 1004
37c5dcc2 1005 ch = &priv->ch[k];
9a217e34
LP		 1006 if (!ch->enabled)
1007 continue;
1008
b5ef967d 1009 panel = &ch->cfg->panel_cfg;
afaad83b
LP		 1010 if (panel->setup_sys) {
1011 ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
9a217e34
LP		 1012 if (ret)
1013 return ret;
8564557a 1014 }
cfb4f5d1
MD		 1015 }
1016
9a217e34
LP		 1017 /* Compute frame buffer base address and pitch for each channel. */
1018 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
9a217e34
LP		 1019 ch = &priv->ch[k];
1020 if (!ch->enabled)
1021 continue;
cfb4f5d1 1022
58f03d99 1023 ch->base_addr_y = ch->dma_handle;
a4aa25f6
LP		 1024 ch->base_addr_c = ch->dma_handle
1025 + ch->xres_virtual * ch->yres_virtual;
72c04af9 1026 ch->line_size = ch->pitch;
9a217e34
LP		 1027 }
1028
c5deac3c
LP		 1029 for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
1030 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k];
1031 sh_mobile_lcdc_overlay_setup(ovl);
1032 }
1033
9a217e34
LP		 1034 /* Start the LCDC. */
1035 __sh_mobile_lcdc_start(priv);
1036
1037 /* Setup deferred I/O, tell the board code to enable the panels, and
1038 * turn backlight on.
1039 */
cfb4f5d1
MD		 1040 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1041 ch = &priv->ch[k];
21bc1f02
MD		 1042 if (!ch->enabled)
1043 continue;
1044
b5ef967d 1045 tmp = ch->cfg->sys_bus_cfg.deferred_io_msec;
9a217e34
LP		 1046 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
1047 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
1048 ch->defio.delay = msecs_to_jiffies(tmp);
1049 ch->info->fbdefio = &ch->defio;
1050 fb_deferred_io_init(ch->info);
1051 }
1052
37c5dcc2 1053 sh_mobile_lcdc_display_on(ch);
3b0fd9d7
AC		 1054
1055 if (ch->bl) {
1056 ch->bl->props.power = FB_BLANK_UNBLANK;
1057 backlight_update_status(ch->bl);
1058 }
cfb4f5d1
MD		 1059 }
1060
1061 return 0;
1062}
1063
1064static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
1065{
1066 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 1067 int k;
1068
2feb075a 1069 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 1070 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1071 ch = &priv->ch[k];
21bc1f02
MD		 1072 if (!ch->enabled)
1073 continue;
8564557a 1074
2feb075a
MD		 1075 /* deferred io mode:
1076 * flush frame, and wait for frame end interrupt
1077 * clean up deferred io and enable clock
1078 */
5ef6b505 1079 if (ch->info && ch->info->fbdefio) {
2feb075a 1080 ch->frame_end = 0;
e33afddc 1081 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 1082 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 1083 fb_deferred_io_cleanup(ch->info);
1084 ch->info->fbdefio = NULL;
2feb075a 1085 sh_mobile_lcdc_clk_on(priv);
8564557a 1086 }
2feb075a 1087
3b0fd9d7
AC		 1088 if (ch->bl) {
1089 ch->bl->props.power = FB_BLANK_POWERDOWN;
1090 backlight_update_status(ch->bl);
1091 }
1092
37c5dcc2 1093 sh_mobile_lcdc_display_off(ch);
cfb4f5d1
MD		 1094 }
1095
1096 /* stop the lcdc */
8e9bb19e
MD		 1097 if (priv->started) {
1098 sh_mobile_lcdc_start_stop(priv, 0);
1099 priv->started = 0;
1100 }
b51339ff 1101
8564557a
MD		 1102 /* stop clocks */
1103 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
1104 if (priv->ch[k].enabled)
1105 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1106}
1107
c5deac3c
LP		 1108static int __sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1109 struct fb_info *info)
1110{
1111 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
1112 return -EINVAL;
1113
1114 /* Make sure the virtual resolution is at least as big as the visible
1115 * resolution.
1116 */
1117 if (var->xres_virtual < var->xres)
1118 var->xres_virtual = var->xres;
1119 if (var->yres_virtual < var->yres)
1120 var->yres_virtual = var->yres;
1121
1122 if (sh_mobile_format_is_fourcc(var)) {
1123 const struct sh_mobile_lcdc_format_info *format;
1124
1125 format = sh_mobile_format_info(var->grayscale);
1126 if (format == NULL)
1127 return -EINVAL;
1128 var->bits_per_pixel = format->bpp;
1129
1130 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1131 * respectively.
1132 */
1133 if (!format->yuv)
1134 var->colorspace = V4L2_COLORSPACE_SRGB;
1135 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1136 var->colorspace = V4L2_COLORSPACE_JPEG;
1137 } else {
1138 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1139 var->bits_per_pixel = 16;
1140 var->red.offset = 11;
1141 var->red.length = 5;
1142 var->green.offset = 5;
1143 var->green.length = 6;
1144 var->blue.offset = 0;
1145 var->blue.length = 5;
1146 var->transp.offset = 0;
1147 var->transp.length = 0;
1148 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1149 var->bits_per_pixel = 24;
1150 var->red.offset = 16;
1151 var->red.length = 8;
1152 var->green.offset = 8;
1153 var->green.length = 8;
1154 var->blue.offset = 0;
1155 var->blue.length = 8;
1156 var->transp.offset = 0;
1157 var->transp.length = 0;
1158 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1159 var->bits_per_pixel = 32;
1160 var->red.offset = 16;
1161 var->red.length = 8;
1162 var->green.offset = 8;
1163 var->green.length = 8;
1164 var->blue.offset = 0;
1165 var->blue.length = 8;
1166 var->transp.offset = 24;
1167 var->transp.length = 8;
1168 } else
1169 return -EINVAL;
1170
1171 var->red.msb_right = 0;
1172 var->green.msb_right = 0;
1173 var->blue.msb_right = 0;
1174 var->transp.msb_right = 0;
1175 }
1176
1177 /* Make sure we don't exceed our allocated memory. */
1178 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1179 info->fix.smem_len)
1180 return -EINVAL;
1181
1182 return 0;
1183}
1184
1185/* -----------------------------------------------------------------------------
1186 * Frame buffer operations - Overlays
1187 */
1188
1189static ssize_t
1190overlay_alpha_show(struct device *dev, struct device_attribute *attr, char *buf)
1191{
1192 struct fb_info *info = dev_get_drvdata(dev);
1193 struct sh_mobile_lcdc_overlay *ovl = info->par;
1194
1195 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->alpha);
1196}
1197
1198static ssize_t
1199overlay_alpha_store(struct device *dev, struct device_attribute *attr,
1200 const char *buf, size_t count)
1201{
1202 struct fb_info *info = dev_get_drvdata(dev);
1203 struct sh_mobile_lcdc_overlay *ovl = info->par;
1204 unsigned int alpha;
1205 char *endp;
1206
1207 alpha = simple_strtoul(buf, &endp, 10);
1208 if (isspace(*endp))
1209 endp++;
1210
1211 if (endp - buf != count)
1212 return -EINVAL;
1213
1214 if (alpha > 255)
1215 return -EINVAL;
1216
1217 if (ovl->alpha != alpha) {
1218 ovl->alpha = alpha;
1219
1220 if (ovl->mode == LCDC_OVERLAY_BLEND && ovl->enabled)
1221 sh_mobile_lcdc_overlay_setup(ovl);
1222 }
1223
1224 return count;
1225}
1226
1227static ssize_t
1228overlay_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1229{
1230 struct fb_info *info = dev_get_drvdata(dev);
1231 struct sh_mobile_lcdc_overlay *ovl = info->par;
1232
1233 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->mode);
1234}
1235
1236static ssize_t
1237overlay_mode_store(struct device *dev, struct device_attribute *attr,
1238 const char *buf, size_t count)
1239{
1240 struct fb_info *info = dev_get_drvdata(dev);
1241 struct sh_mobile_lcdc_overlay *ovl = info->par;
1242 unsigned int mode;
1243 char *endp;
1244
1245 mode = simple_strtoul(buf, &endp, 10);
1246 if (isspace(*endp))
1247 endp++;
1248
1249 if (endp - buf != count)
1250 return -EINVAL;
1251
1252 if (mode != LCDC_OVERLAY_BLEND && mode != LCDC_OVERLAY_ROP3)
1253 return -EINVAL;
1254
1255 if (ovl->mode != mode) {
1256 ovl->mode = mode;
1257
1258 if (ovl->enabled)
1259 sh_mobile_lcdc_overlay_setup(ovl);
1260 }
1261
1262 return count;
1263}
1264
1265static ssize_t
1266overlay_position_show(struct device *dev, struct device_attribute *attr,
1267 char *buf)
1268{
1269 struct fb_info *info = dev_get_drvdata(dev);
1270 struct sh_mobile_lcdc_overlay *ovl = info->par;
1271
1272 return scnprintf(buf, PAGE_SIZE, "%d,%d\n", ovl->pos_x, ovl->pos_y);
1273}
1274
1275static ssize_t
1276overlay_position_store(struct device *dev, struct device_attribute *attr,
1277 const char *buf, size_t count)
1278{
1279 struct fb_info *info = dev_get_drvdata(dev);
1280 struct sh_mobile_lcdc_overlay *ovl = info->par;
1281 char *endp;
1282 int pos_x;
1283 int pos_y;
1284
1285 pos_x = simple_strtol(buf, &endp, 10);
1286 if (*endp != ',')
1287 return -EINVAL;
1288
1289 pos_y = simple_strtol(endp + 1, &endp, 10);
1290 if (isspace(*endp))
1291 endp++;
1292
1293 if (endp - buf != count)
1294 return -EINVAL;
1295
1296 if (ovl->pos_x != pos_x || ovl->pos_y != pos_y) {
1297 ovl->pos_x = pos_x;
1298 ovl->pos_y = pos_y;
1299
1300 if (ovl->enabled)
1301 sh_mobile_lcdc_overlay_setup(ovl);
1302 }
1303
1304 return count;
1305}
1306
1307static ssize_t
1308overlay_rop3_show(struct device *dev, struct device_attribute *attr, char *buf)
1309{
1310 struct fb_info *info = dev_get_drvdata(dev);
1311 struct sh_mobile_lcdc_overlay *ovl = info->par;
1312
1313 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->rop3);
1314}
1315
1316static ssize_t
1317overlay_rop3_store(struct device *dev, struct device_attribute *attr,
1318 const char *buf, size_t count)
1319{
1320 struct fb_info *info = dev_get_drvdata(dev);
1321 struct sh_mobile_lcdc_overlay *ovl = info->par;
1322 unsigned int rop3;
1323 char *endp;
1324
14048ffe 1325 rop3 = simple_strtoul(buf, &endp, 10);
c5deac3c
LP		 1326 if (isspace(*endp))
1327 endp++;
1328
1329 if (endp - buf != count)
1330 return -EINVAL;
1331
1332 if (rop3 > 255)
1333 return -EINVAL;
1334
1335 if (ovl->rop3 != rop3) {
1336 ovl->rop3 = rop3;
1337
1338 if (ovl->mode == LCDC_OVERLAY_ROP3 && ovl->enabled)
1339 sh_mobile_lcdc_overlay_setup(ovl);
1340 }
1341
1342 return count;
1343}
1344
1345static const struct device_attribute overlay_sysfs_attrs[] = {
1346 __ATTR(ovl_alpha, S_IRUGO|S_IWUSR,
1347 overlay_alpha_show, overlay_alpha_store),
1348 __ATTR(ovl_mode, S_IRUGO|S_IWUSR,
1349 overlay_mode_show, overlay_mode_store),
1350 __ATTR(ovl_position, S_IRUGO|S_IWUSR,
1351 overlay_position_show, overlay_position_store),
1352 __ATTR(ovl_rop3, S_IRUGO|S_IWUSR,
1353 overlay_rop3_show, overlay_rop3_store),
1354};
1355
1356static const struct fb_fix_screeninfo sh_mobile_lcdc_overlay_fix = {
1357 .id = "SH Mobile LCDC",
1358 .type = FB_TYPE_PACKED_PIXELS,
1359 .visual = FB_VISUAL_TRUECOLOR,
1360 .accel = FB_ACCEL_NONE,
15dede88 1361 .xpanstep = 1,
c5deac3c
LP		 1362 .ypanstep = 1,
1363 .ywrapstep = 0,
1364 .capabilities = FB_CAP_FOURCC,
1365};
1366
1367static int sh_mobile_lcdc_overlay_pan(struct fb_var_screeninfo *var,
1368 struct fb_info *info)
1369{
1370 struct sh_mobile_lcdc_overlay *ovl = info->par;
1371 unsigned long base_addr_y;
1372 unsigned long base_addr_c;
a4aa25f6 1373 unsigned long y_offset;
c5deac3c
LP		 1374 unsigned long c_offset;
1375
a4aa25f6
LP		 1376 if (!ovl->format->yuv) {
1377 y_offset = (var->yoffset * ovl->xres_virtual + var->xoffset)
1378 * ovl->format->bpp / 8;
1379 c_offset = 0;
1380 } else {
1381 unsigned int xsub = ovl->format->bpp < 24 ? 2 : 1;
1382 unsigned int ysub = ovl->format->bpp < 16 ? 2 : 1;
1383
1384 y_offset = var->yoffset * ovl->xres_virtual + var->xoffset;
1385 c_offset = var->yoffset / ysub * ovl->xres_virtual * 2 / xsub
1386 + var->xoffset * 2 / xsub;
1387 }
c5deac3c 1388
a4aa25f6
LP		 1389 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1390 * nothing to do in that case.
1391 */
1392 if (y_offset == ovl->pan_y_offset)
1393 return 0;
c5deac3c
LP		 1394
1395 /* Set the source address for the next refresh */
a4aa25f6
LP		 1396 base_addr_y = ovl->dma_handle + y_offset;
1397 base_addr_c = ovl->dma_handle + ovl->xres_virtual * ovl->yres_virtual
1398 + c_offset;
c5deac3c
LP		 1399
1400 ovl->base_addr_y = base_addr_y;
a4aa25f6
LP		 1401 ovl->base_addr_c = base_addr_c;
1402 ovl->pan_y_offset = y_offset;
c5deac3c 1403
8be7c669
LP		 1404 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
1405
c5deac3c
LP		 1406 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
1407 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
1408
8be7c669
LP		 1409 lcdc_write(ovl->channel->lcdc, LDBCR,
1410 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
1411
c5deac3c
LP		 1412 return 0;
1413}
1414
1415static int sh_mobile_lcdc_overlay_ioctl(struct fb_info *info, unsigned int cmd,
1416 unsigned long arg)
1417{
1418 struct sh_mobile_lcdc_overlay *ovl = info->par;
1419
1420 switch (cmd) {
1421 case FBIO_WAITFORVSYNC:
1422 return sh_mobile_lcdc_wait_for_vsync(ovl->channel);
1423
1424 default:
1425 return -ENOIOCTLCMD;
1426 }
1427}
1428
1429static int sh_mobile_lcdc_overlay_check_var(struct fb_var_screeninfo *var,
1430 struct fb_info *info)
1431{
1432 return __sh_mobile_lcdc_check_var(var, info);
1433}
1434
1435static int sh_mobile_lcdc_overlay_set_par(struct fb_info *info)
1436{
1437 struct sh_mobile_lcdc_overlay *ovl = info->par;
1438
1439 ovl->format =
1440 sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
1441
1442 ovl->xres = info->var.xres;
1443 ovl->xres_virtual = info->var.xres_virtual;
1444 ovl->yres = info->var.yres;
1445 ovl->yres_virtual = info->var.yres_virtual;
1446
1447 if (ovl->format->yuv)
16ca21c9 1448 ovl->pitch = info->var.xres_virtual;
c5deac3c 1449 else
16ca21c9 1450 ovl->pitch = info->var.xres_virtual * ovl->format->bpp / 8;
c5deac3c
LP		 1451
1452 sh_mobile_lcdc_overlay_setup(ovl);
1453
1454 info->fix.line_length = ovl->pitch;
1455
1456 if (sh_mobile_format_is_fourcc(&info->var)) {
1457 info->fix.type = FB_TYPE_FOURCC;
1458 info->fix.visual = FB_VISUAL_FOURCC;
1459 } else {
1460 info->fix.type = FB_TYPE_PACKED_PIXELS;
1461 info->fix.visual = FB_VISUAL_TRUECOLOR;
1462 }
1463
1464 return 0;
1465}
1466
1467/* Overlay blanking. Disable the overlay when blanked. */
1468static int sh_mobile_lcdc_overlay_blank(int blank, struct fb_info *info)
1469{
1470 struct sh_mobile_lcdc_overlay *ovl = info->par;
1471
1472 ovl->enabled = !blank;
1473 sh_mobile_lcdc_overlay_setup(ovl);
1474
1475 /* Prevent the backlight from receiving a blanking event by returning
1476 * a non-zero value.
1477 */
1478 return 1;
1479}
1480
bf10a537
HE		 1481static int
1482sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct *vma)
1483{
1484 struct sh_mobile_lcdc_overlay *ovl = info->par;
1485
1486 return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
1487 ovl->dma_handle, ovl->fb_size);
1488}
1489
8a48ac33 1490static const struct fb_ops sh_mobile_lcdc_overlay_ops = {
c5deac3c
LP		 1491 .owner = THIS_MODULE,
1492 .fb_read = fb_sys_read,
1493 .fb_write = fb_sys_write,
1494 .fb_fillrect = sys_fillrect,
1495 .fb_copyarea = sys_copyarea,
1496 .fb_imageblit = sys_imageblit,
1497 .fb_blank = sh_mobile_lcdc_overlay_blank,
1498 .fb_pan_display = sh_mobile_lcdc_overlay_pan,
1499 .fb_ioctl = sh_mobile_lcdc_overlay_ioctl,
1500 .fb_check_var = sh_mobile_lcdc_overlay_check_var,
1501 .fb_set_par = sh_mobile_lcdc_overlay_set_par,
bf10a537 1502 .fb_mmap = sh_mobile_lcdc_overlay_mmap,
c5deac3c
LP		 1503};
1504
1505static void
1506sh_mobile_lcdc_overlay_fb_unregister(struct sh_mobile_lcdc_overlay *ovl)
1507{
1508 struct fb_info *info = ovl->info;
1509
1510 if (info == NULL || info->dev == NULL)
1511 return;
1512
1513 unregister_framebuffer(ovl->info);
1514}
1515
48c68c4f 1516static int
c5deac3c
LP		 1517sh_mobile_lcdc_overlay_fb_register(struct sh_mobile_lcdc_overlay *ovl)
1518{
1519 struct sh_mobile_lcdc_priv *lcdc = ovl->channel->lcdc;
1520 struct fb_info *info = ovl->info;
1521 unsigned int i;
1522 int ret;
1523
1524 if (info == NULL)
1525 return 0;
1526
1527 ret = register_framebuffer(info);
1528 if (ret < 0)
1529 return ret;
1530
1531 dev_info(lcdc->dev, "registered %s/overlay %u as %dx%d %dbpp.\n",
1532 dev_name(lcdc->dev), ovl->index, info->var.xres,
1533 info->var.yres, info->var.bits_per_pixel);
1534
1535 for (i = 0; i < ARRAY_SIZE(overlay_sysfs_attrs); ++i) {
1536 ret = device_create_file(info->dev, &overlay_sysfs_attrs[i]);
1537 if (ret < 0)
1538 return ret;
1539 }
1540
1541 return 0;
1542}
1543
1544static void
1545sh_mobile_lcdc_overlay_fb_cleanup(struct sh_mobile_lcdc_overlay *ovl)
1546{
1547 struct fb_info *info = ovl->info;
1548
1549 if (info == NULL || info->device == NULL)
1550 return;
1551
1552 framebuffer_release(info);
1553}
1554
48c68c4f 1555static int
c5deac3c
LP		 1556sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
1557{
1558 struct sh_mobile_lcdc_priv *priv = ovl->channel->lcdc;
1559 struct fb_var_screeninfo *var;
1560 struct fb_info *info;
1561
1562 /* Allocate and initialize the frame buffer device. */
1563 info = framebuffer_alloc(0, priv->dev);
0adcdbcb 1564 if (!info)
c5deac3c 1565 return -ENOMEM;
c5deac3c
LP		 1566
1567 ovl->info = info;
1568
1569 info->flags = FBINFO_FLAG_DEFAULT;
1570 info->fbops = &sh_mobile_lcdc_overlay_ops;
1571 info->device = priv->dev;
5d30146f 1572 info->screen_buffer = ovl->fb_mem;
c5deac3c
LP		 1573 info->par = ovl;
1574
1575 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1576 * for NV12 and NV21.
1577 */
1578 info->fix = sh_mobile_lcdc_overlay_fix;
1579 snprintf(info->fix.id, sizeof(info->fix.id),
1580 "SH Mobile LCDC Overlay %u", ovl->index);
1581 info->fix.smem_start = ovl->dma_handle;
1582 info->fix.smem_len = ovl->fb_size;
1583 info->fix.line_length = ovl->pitch;
1584
1585 if (ovl->format->yuv)
1586 info->fix.visual = FB_VISUAL_FOURCC;
1587 else
1588 info->fix.visual = FB_VISUAL_TRUECOLOR;
1589
15dede88 1590 switch (ovl->format->fourcc) {
15dede88
LP		 1591 case V4L2_PIX_FMT_NV12:
1592 case V4L2_PIX_FMT_NV21:
ac33a207 1593 info->fix.ypanstep = 2;
ad04fae0 1594 fallthrough;
ac33a207
LP		 1595 case V4L2_PIX_FMT_NV16:
1596 case V4L2_PIX_FMT_NV61:
15dede88
LP		 1597 info->fix.xpanstep = 2;
1598 }
c5deac3c
LP		 1599
1600 /* Initialize variable screen information. */
1601 var = &info->var;
1602 memset(var, 0, sizeof(*var));
1603 var->xres = ovl->xres;
1604 var->yres = ovl->yres;
1605 var->xres_virtual = ovl->xres_virtual;
1606 var->yres_virtual = ovl->yres_virtual;
1607 var->activate = FB_ACTIVATE_NOW;
1608
1609 /* Use the legacy API by default for RGB formats, and the FOURCC API
1610 * for YUV formats.
1611 */
1612 if (!ovl->format->yuv)
1613 var->bits_per_pixel = ovl->format->bpp;
1614 else
1615 var->grayscale = ovl->format->fourcc;
1616
1617 return sh_mobile_lcdc_overlay_check_var(var, info);
1618}
1619
f1f60b5f 1620/* -----------------------------------------------------------------------------
c5deac3c 1621 * Frame buffer operations - main frame buffer
f1f60b5f 1622 */
cfb4f5d1
MD		 1623
1624static int sh_mobile_lcdc_setcolreg(u_int regno,
1625 u_int red, u_int green, u_int blue,
1626 u_int transp, struct fb_info *info)
1627{
1628 u32 *palette = info->pseudo_palette;
1629
1630 if (regno >= PALETTE_NR)
1631 return -EINVAL;
1632
1633 /* only FB_VISUAL_TRUECOLOR supported */
1634
1635 red >>= 16 - info->var.red.length;
1636 green >>= 16 - info->var.green.length;
1637 blue >>= 16 - info->var.blue.length;
1638 transp >>= 16 - info->var.transp.length;
1639
1640 palette[regno] = (red << info->var.red.offset) |
1641 (green << info->var.green.offset) |
1642 (blue << info->var.blue.offset) |
1643 (transp << info->var.transp.offset);
1644
1645 return 0;
1646}
1647
3281e54c 1648static const struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
cfb4f5d1
MD		 1649 .id = "SH Mobile LCDC",
1650 .type = FB_TYPE_PACKED_PIXELS,
1651 .visual = FB_VISUAL_TRUECOLOR,
1652 .accel = FB_ACCEL_NONE,
15dede88 1653 .xpanstep = 1,
9dd38819
PE		 1654 .ypanstep = 1,
1655 .ywrapstep = 0,
edd153a3 1656 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 1657};
1658
8564557a
MD		 1659static void sh_mobile_lcdc_fillrect(struct fb_info *info,
1660 const struct fb_fillrect *rect)
1661{
1662 sys_fillrect(info, rect);
1663 sh_mobile_lcdc_deferred_io_touch(info);
1664}
1665
1666static void sh_mobile_lcdc_copyarea(struct fb_info *info,
1667 const struct fb_copyarea *area)
1668{
1669 sys_copyarea(info, area);
1670 sh_mobile_lcdc_deferred_io_touch(info);
1671}
1672
1673static void sh_mobile_lcdc_imageblit(struct fb_info *info,
1674 const struct fb_image *image)
1675{
1676 sys_imageblit(info, image);
1677 sh_mobile_lcdc_deferred_io_touch(info);
1678}
1679
d7ad3342
LP		 1680static int sh_mobile_lcdc_pan(struct fb_var_screeninfo *var,
1681 struct fb_info *info)
9dd38819
PE		 1682{
1683 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 1684 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
1685 unsigned long ldrcntr;
a4aa25f6
LP		 1686 unsigned long base_addr_y, base_addr_c;
1687 unsigned long y_offset;
53b50314 1688 unsigned long c_offset;
92e1f9a7 1689
a4aa25f6
LP		 1690 if (!ch->format->yuv) {
1691 y_offset = (var->yoffset * ch->xres_virtual + var->xoffset)
1692 * ch->format->bpp / 8;
1693 c_offset = 0;
1694 } else {
1695 unsigned int xsub = ch->format->bpp < 24 ? 2 : 1;
1696 unsigned int ysub = ch->format->bpp < 16 ? 2 : 1;
9dd38819 1697
a4aa25f6
LP		 1698 y_offset = var->yoffset * ch->xres_virtual + var->xoffset;
1699 c_offset = var->yoffset / ysub * ch->xres_virtual * 2 / xsub
1700 + var->xoffset * 2 / xsub;
1701 }
9dd38819 1702
a4aa25f6
LP		 1703 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1704 * nothing to do in that case.
1705 */
1706 if (y_offset == ch->pan_y_offset)
1707 return 0;
9dd38819 1708
92e1f9a7 1709 /* Set the source address for the next refresh */
a4aa25f6
LP		 1710 base_addr_y = ch->dma_handle + y_offset;
1711 base_addr_c = ch->dma_handle + ch->xres_virtual * ch->yres_virtual
1712 + c_offset;
53b50314 1713
49d79ba2
LP		 1714 ch->base_addr_y = base_addr_y;
1715 ch->base_addr_c = base_addr_c;
a4aa25f6 1716 ch->pan_y_offset = y_offset;
7caa4342 1717
49d79ba2 1718 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
58f03d99 1719 if (ch->format->yuv)
49d79ba2 1720 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 1721
a4aa25f6 1722 ldrcntr = lcdc_read(priv, _LDRCNTR);
92e1f9a7
PE		 1723 if (lcdc_chan_is_sublcd(ch))
1724 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
1725 else
1726 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
1727
92e1f9a7
PE		 1728
1729 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 1730
1731 return 0;
1732}
1733
d7ad3342
LP		 1734static int sh_mobile_lcdc_ioctl(struct fb_info *info, unsigned int cmd,
1735 unsigned long arg)
40331b21 1736{
d7ad3342 1737 struct sh_mobile_lcdc_chan *ch = info->par;
40331b21
PE		 1738 int retval;
1739
1740 switch (cmd) {
1741 case FBIO_WAITFORVSYNC:
d7ad3342 1742 retval = sh_mobile_lcdc_wait_for_vsync(ch);
40331b21
PE		 1743 break;
1744
1745 default:
1746 retval = -ENOIOCTLCMD;
1747 break;
1748 }
1749 return retval;
1750}
1751
dd210503
GL		 1752static void sh_mobile_fb_reconfig(struct fb_info *info)
1753{
1754 struct sh_mobile_lcdc_chan *ch = info->par;
2d04559d
LP		 1755 struct fb_var_screeninfo var;
1756 struct fb_videomode mode;
dd210503
GL		 1757
1758 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1759 /* More framebuffer users are active */
1760 return;
1761
2d04559d 1762 fb_var_to_videomode(&mode, &info->var);
dd210503 1763
2d04559d 1764 if (fb_mode_is_equal(&ch->display.mode, &mode))
dd210503
GL		 1765 return;
1766
1767 /* Display has been re-plugged, framebuffer is free now, reconfigure */
2d04559d
LP		 1768 var = info->var;
1769 fb_videomode_to_var(&var, &ch->display.mode);
1770 var.width = ch->display.width;
1771 var.height = ch->display.height;
1772 var.activate = FB_ACTIVATE_NOW;
1773
1774 if (fb_set_var(info, &var) < 0)
dd210503
GL		 1775 /* Couldn't reconfigure, hopefully, can continue as before */
1776 return;
1777
9e146700 1778 fbcon_update_vcs(info, true);
dd210503
GL		 1779}
1780
1781/*
1782 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1783 * user == 1, or with console sem held, if user == 0.
1784 */
d7ad3342 1785static int sh_mobile_lcdc_release(struct fb_info *info, int user)
dd210503
GL		 1786{
1787 struct sh_mobile_lcdc_chan *ch = info->par;
1788
1789 mutex_lock(&ch->open_lock);
1790 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1791
1792 ch->use_count--;
1793
1794 /* Nothing to reconfigure, when called from fbcon */
1795 if (user) {
ac751efa 1796 console_lock();
dd210503 1797 sh_mobile_fb_reconfig(info);
ac751efa 1798 console_unlock();
dd210503
GL		 1799 }
1800
1801 mutex_unlock(&ch->open_lock);
1802
1803 return 0;
1804}
1805
d7ad3342 1806static int sh_mobile_lcdc_open(struct fb_info *info, int user)
dd210503
GL		 1807{
1808 struct sh_mobile_lcdc_chan *ch = info->par;
1809
1810 mutex_lock(&ch->open_lock);
1811 ch->use_count++;
1812
1813 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1814 mutex_unlock(&ch->open_lock);
1815
1816 return 0;
1817}
1818
d7ad3342
LP		 1819static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1820 struct fb_info *info)
dd210503
GL		 1821{
1822 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1823 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1824 unsigned int best_dist = (unsigned int)-1;
1825 unsigned int best_xres = 0;
1826 unsigned int best_yres = 0;
1827 unsigned int i;
c5deac3c 1828 int ret;
03862194
LP		 1829
1830 /* If board code provides us with a list of available modes, make sure
1831 * we use one of them. Find the mode closest to the requested one. The
1832 * distance between two modes is defined as the size of the
1833 * non-overlapping parts of the two rectangles.
1834 */
b5ef967d
LP		 1835 for (i = 0; i < ch->cfg->num_modes; ++i) {
1836 const struct fb_videomode *mode = &ch->cfg->lcd_modes[i];
03862194
LP		 1837 unsigned int dist;
1838
1839 /* We can only round up. */
1840 if (var->xres > mode->xres || var->yres > mode->yres)
1841 continue;
1842
1843 dist = var->xres * var->yres + mode->xres * mode->yres
1844 - 2 * min(var->xres, mode->xres)
1845 * min(var->yres, mode->yres);
1846
1847 if (dist < best_dist) {
1848 best_xres = mode->xres;
1849 best_yres = mode->yres;
1850 best_dist = dist;
1851 }
dd210503 1852 }
417d4827 1853
03862194 1854 /* If no available mode can be used, return an error. */
b5ef967d 1855 if (ch->cfg->num_modes != 0) {
03862194
LP		 1856 if (best_dist == (unsigned int)-1)
1857 return -EINVAL;
1858
1859 var->xres = best_xres;
1860 var->yres = best_yres;
1861 }
1862
c5deac3c
LP		 1863 ret = __sh_mobile_lcdc_check_var(var, info);
1864 if (ret < 0)
1865 return ret;
03862194 1866
edd153a3
LP		 1867 /* only accept the forced_fourcc for dual channel configurations */
1868 if (p->forced_fourcc &&
1869 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1870 return -EINVAL;
417d4827 1871
dd210503
GL		 1872 return 0;
1873}
40331b21 1874
d7ad3342 1875static int sh_mobile_lcdc_set_par(struct fb_info *info)
ed5bebf2
LP		 1876{
1877 struct sh_mobile_lcdc_chan *ch = info->par;
1878 int ret;
1879
1880 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1881
fc9e78e6 1882 ch->format = sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
58f03d99
LP		 1883 ch->colorspace = info->var.colorspace;
1884
1885 ch->xres = info->var.xres;
1886 ch->xres_virtual = info->var.xres_virtual;
1887 ch->yres = info->var.yres;
1888 ch->yres_virtual = info->var.yres_virtual;
1889
1890 if (ch->format->yuv)
16ca21c9 1891 ch->pitch = info->var.xres_virtual;
58f03d99 1892 else
16ca21c9 1893 ch->pitch = info->var.xres_virtual * ch->format->bpp / 8;
fc9e78e6 1894
ed5bebf2 1895 ret = sh_mobile_lcdc_start(ch->lcdc);
58f03d99 1896 if (ret < 0)
ed5bebf2 1897 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
58f03d99
LP		 1898
1899 info->fix.line_length = ch->pitch;
ed5bebf2 1900
edd153a3
LP		 1901 if (sh_mobile_format_is_fourcc(&info->var)) {
1902 info->fix.type = FB_TYPE_FOURCC;
1903 info->fix.visual = FB_VISUAL_FOURCC;
1904 } else {
1905 info->fix.type = FB_TYPE_PACKED_PIXELS;
1906 info->fix.visual = FB_VISUAL_TRUECOLOR;
1907 }
1908
ed5bebf2
LP		 1909 return ret;
1910}
1911
8857b9aa
AC		 1912/*
1913 * Screen blanking. Behavior is as follows:
1914 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1915 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1916 * FB_BLANK_VSYNC,
1917 * FB_BLANK_HSYNC,
1918 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1919 */
1920static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1921{
1922 struct sh_mobile_lcdc_chan *ch = info->par;
1923 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1924
1925 /* blank the screen? */
1926 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1927 struct fb_fillrect rect = {
58f03d99
LP		 1928 .width = ch->xres,
1929 .height = ch->yres,
8857b9aa
AC		 1930 };
1931 sh_mobile_lcdc_fillrect(info, &rect);
1932 }
1933 /* turn clocks on? */
1934 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1935 sh_mobile_lcdc_clk_on(p);
1936 }
1937 /* turn clocks off? */
1938 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1939 /* make sure the screen is updated with the black fill before
1940 * switching the clocks off. one vsync is not enough since
1941 * blanking may occur in the middle of a refresh. deferred io
1942 * mode will reenable the clocks and update the screen in time,
1943 * so it does not need this. */
1944 if (!info->fbdefio) {
d7ad3342
LP		 1945 sh_mobile_lcdc_wait_for_vsync(ch);
1946 sh_mobile_lcdc_wait_for_vsync(ch);
8857b9aa
AC		 1947 }
1948 sh_mobile_lcdc_clk_off(p);
1949 }
1950
1951 ch->blank_status = blank;
1952 return 0;
1953}
1954
bf10a537
HE		 1955static int
1956sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
1957{
1958 struct sh_mobile_lcdc_chan *ch = info->par;
1959
1960 return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
1961 ch->dma_handle, ch->fb_size);
1962}
1963
8a48ac33 1964static const struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1965 .owner = THIS_MODULE,
cfb4f5d1 1966 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1967 .fb_read = fb_sys_read,
1968 .fb_write = fb_sys_write,
8564557a
MD		 1969 .fb_fillrect = sh_mobile_lcdc_fillrect,
1970 .fb_copyarea = sh_mobile_lcdc_copyarea,
1971 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1972 .fb_blank = sh_mobile_lcdc_blank,
d7ad3342
LP		 1973 .fb_pan_display = sh_mobile_lcdc_pan,
1974 .fb_ioctl = sh_mobile_lcdc_ioctl,
1975 .fb_open = sh_mobile_lcdc_open,
1976 .fb_release = sh_mobile_lcdc_release,
1977 .fb_check_var = sh_mobile_lcdc_check_var,
1978 .fb_set_par = sh_mobile_lcdc_set_par,
bf10a537 1979 .fb_mmap = sh_mobile_lcdc_mmap,
cfb4f5d1
MD		 1980};
1981
a67f379d
LP		 1982static void
1983sh_mobile_lcdc_channel_fb_unregister(struct sh_mobile_lcdc_chan *ch)
1984{
1985 if (ch->info && ch->info->dev)
1986 unregister_framebuffer(ch->info);
1987}
1988
48c68c4f 1989static int
a67f379d
LP		 1990sh_mobile_lcdc_channel_fb_register(struct sh_mobile_lcdc_chan *ch)
1991{
1992 struct fb_info *info = ch->info;
1993 int ret;
1994
1995 if (info->fbdefio) {
1996 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1997 ch->fb_size >> PAGE_SHIFT);
e281018b 1998 if (!ch->sglist)
a67f379d 1999 return -ENOMEM;
a67f379d
LP		 2000 }
2001
2002 info->bl_dev = ch->bl;
2003
2004 ret = register_framebuffer(info);
2005 if (ret < 0)
2006 return ret;
2007
2008 dev_info(ch->lcdc->dev, "registered %s/%s as %dx%d %dbpp.\n",
b5ef967d 2009 dev_name(ch->lcdc->dev), (ch->cfg->chan == LCDC_CHAN_MAINLCD) ?
a67f379d
LP		 2010 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
2011 info->var.bits_per_pixel);
2012
2013 /* deferred io mode: disable clock to save power */
2014 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
2015 sh_mobile_lcdc_clk_off(ch->lcdc);
2016
2017 return ret;
2018}
2019
2020static void
2021sh_mobile_lcdc_channel_fb_cleanup(struct sh_mobile_lcdc_chan *ch)
2022{
2023 struct fb_info *info = ch->info;
2024
2025 if (!info || !info->device)
2026 return;
2027
f8582758 2028 vfree(ch->sglist);
a67f379d
LP		 2029
2030 fb_dealloc_cmap(&info->cmap);
2031 framebuffer_release(info);
2032}
2033
48c68c4f 2034static int
a67f379d 2035sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
352d6138 2036 const struct fb_videomode *modes,
a67f379d
LP		 2037 unsigned int num_modes)
2038{
2039 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
2040 struct fb_var_screeninfo *var;
2041 struct fb_info *info;
2042 int ret;
2043
2044 /* Allocate and initialize the frame buffer device. Create the modes
2045 * list and allocate the color map.
2046 */
2047 info = framebuffer_alloc(0, priv->dev);
0adcdbcb 2048 if (!info)
a67f379d 2049 return -ENOMEM;
a67f379d
LP		 2050
2051 ch->info = info;
2052
2053 info->flags = FBINFO_FLAG_DEFAULT;
2054 info->fbops = &sh_mobile_lcdc_ops;
2055 info->device = priv->dev;
5d30146f 2056 info->screen_buffer = ch->fb_mem;
a67f379d
LP		 2057 info->pseudo_palette = &ch->pseudo_palette;
2058 info->par = ch;
2059
352d6138 2060 fb_videomode_to_modelist(modes, num_modes, &info->modelist);
a67f379d
LP		 2061
2062 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
2063 if (ret < 0) {
2064 dev_err(priv->dev, "unable to allocate cmap\n");
2065 return ret;
2066 }
2067
2068 /* Initialize fixed screen information. Restrict pan to 2 lines steps
2069 * for NV12 and NV21.
2070 */
2071 info->fix = sh_mobile_lcdc_fix;
2072 info->fix.smem_start = ch->dma_handle;
2073 info->fix.smem_len = ch->fb_size;
58f03d99
LP		 2074 info->fix.line_length = ch->pitch;
2075
2076 if (ch->format->yuv)
2077 info->fix.visual = FB_VISUAL_FOURCC;
2078 else
2079 info->fix.visual = FB_VISUAL_TRUECOLOR;
2080
15dede88 2081 switch (ch->format->fourcc) {
15dede88
LP		 2082 case V4L2_PIX_FMT_NV12:
2083 case V4L2_PIX_FMT_NV21:
ac33a207 2084 info->fix.ypanstep = 2;
ad04fae0 2085 fallthrough;
ac33a207
LP		 2086 case V4L2_PIX_FMT_NV16:
2087 case V4L2_PIX_FMT_NV61:
15dede88
LP		 2088 info->fix.xpanstep = 2;
2089 }
a67f379d
LP		 2090
2091 /* Initialize variable screen information using the first mode as
bd5f2c69 2092 * default.
a67f379d
LP		 2093 */
2094 var = &info->var;
352d6138 2095 fb_videomode_to_var(var, modes);
856e8dfe
LP		 2096 var->width = ch->display.width;
2097 var->height = ch->display.height;
bd5f2c69
LP		 2098 var->xres_virtual = ch->xres_virtual;
2099 var->yres_virtual = ch->yres_virtual;
a67f379d
LP		 2100 var->activate = FB_ACTIVATE_NOW;
2101
2102 /* Use the legacy API by default for RGB formats, and the FOURCC API
2103 * for YUV formats.
2104 */
2105 if (!ch->format->yuv)
2106 var->bits_per_pixel = ch->format->bpp;
2107 else
2108 var->grayscale = ch->format->fourcc;
2109
d7ad3342 2110 ret = sh_mobile_lcdc_check_var(var, info);
a67f379d
LP		 2111 if (ret)
2112 return ret;
2113
a67f379d
LP		 2114 return 0;
2115}
2116
f1f60b5f
LP		 2117/* -----------------------------------------------------------------------------
2118 * Backlight
2119 */
2120
3b0fd9d7
AC		 2121static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
2122{
2123 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7
AC		 2124 int brightness = bdev->props.brightness;
2125
2126 if (bdev->props.power != FB_BLANK_UNBLANK ||
2127 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
2128 brightness = 0;
2129
656d4f33 2130 ch->bl_brightness = brightness;
b5ef967d 2131 return ch->cfg->bl_info.set_brightness(brightness);
3b0fd9d7
AC		 2132}
2133
2134static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
2135{
2136 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7 2137
656d4f33 2138 return ch->bl_brightness;
3b0fd9d7
AC		 2139}
2140
2141static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
2142 struct fb_info *info)
2143{
2144 return (info->bl_dev == bdev);
2145}
2146
0e25884b 2147static const struct backlight_ops sh_mobile_lcdc_bl_ops = {
3b0fd9d7
AC		 2148 .options = BL_CORE_SUSPENDRESUME,
2149 .update_status = sh_mobile_lcdc_update_bl,
2150 .get_brightness = sh_mobile_lcdc_get_brightness,
2151 .check_fb = sh_mobile_lcdc_check_fb,
2152};
2153
2154static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
2155 struct sh_mobile_lcdc_chan *ch)
2156{
2157 struct backlight_device *bl;
2158
b5ef967d 2159 bl = backlight_device_register(ch->cfg->bl_info.name, parent, ch,
3b0fd9d7 2160 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 2161 if (IS_ERR(bl)) {
2162 dev_err(parent, "unable to register backlight device: %ld\n",
2163 PTR_ERR(bl));
3b0fd9d7
AC		 2164 return NULL;
2165 }
2166
b5ef967d 2167 bl->props.max_brightness = ch->cfg->bl_info.max_brightness;
3b0fd9d7
AC		 2168 bl->props.brightness = bl->props.max_brightness;
2169 backlight_update_status(bl);
2170
2171 return bl;
2172}
2173
2174static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
2175{
2176 backlight_device_unregister(bdev);
2177}
2178
f1f60b5f
LP		 2179/* -----------------------------------------------------------------------------
2180 * Power management
2181 */
2182
2feb075a
MD		 2183static int sh_mobile_lcdc_suspend(struct device *dev)
2184{
2185 struct platform_device *pdev = to_platform_device(dev);
2186
2187 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
2188 return 0;
2189}
2190
2191static int sh_mobile_lcdc_resume(struct device *dev)
2192{
2193 struct platform_device *pdev = to_platform_device(dev);
2194
2195 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
2196}
2197
0246c471
MD		 2198static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
2199{
b2faabc8 2200 struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
0246c471
MD		 2201
2202 /* turn off LCDC hardware */
2427bb24
LP		 2203 lcdc_write(priv, _LDCNT1R, 0);
2204
0246c471
MD		 2205 return 0;
2206}
2207
2208static int sh_mobile_lcdc_runtime_resume(struct device *dev)
2209{
b2faabc8 2210 struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
0246c471 2211
2427bb24 2212 __sh_mobile_lcdc_start(priv);
0246c471
MD		 2213
2214 return 0;
2215}
2216
47145210 2217static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 2218 .suspend = sh_mobile_lcdc_suspend,
2219 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 2220 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
2221 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 2222};
2223
f1f60b5f
LP		 2224/* -----------------------------------------------------------------------------
2225 * Framebuffer notifier
2226 */
2227
f1f60b5f
LP		 2228/* -----------------------------------------------------------------------------
2229 * Probe/remove and driver init/exit
2230 */
2231
48c68c4f 2232static const struct fb_videomode default_720p = {
f1f60b5f
LP		 2233 .name = "HDMI 720p",
2234 .xres = 1280,
2235 .yres = 720,
2236
2237 .left_margin = 220,
2238 .right_margin = 110,
2239 .hsync_len = 40,
2240
2241 .upper_margin = 20,
2242 .lower_margin = 5,
2243 .vsync_len = 5,
2244
2245 .pixclock = 13468,
2246 .refresh = 60,
2247 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
2248};
2249
b4bee692
LP		 2250static int sh_mobile_lcdc_remove(struct platform_device *pdev)
2251{
2252 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
c5deac3c 2253 unsigned int i;
b4bee692 2254
c5deac3c
LP		 2255 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++)
2256 sh_mobile_lcdc_overlay_fb_unregister(&priv->overlays[i]);
b4bee692 2257 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
a67f379d 2258 sh_mobile_lcdc_channel_fb_unregister(&priv->ch[i]);
b4bee692
LP		 2259
2260 sh_mobile_lcdc_stop(priv);
2261
c5deac3c
LP		 2262 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++) {
2263 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2264
2265 sh_mobile_lcdc_overlay_fb_cleanup(ovl);
2266
2267 if (ovl->fb_mem)
2268 dma_free_coherent(&pdev->dev, ovl->fb_size,
2269 ovl->fb_mem, ovl->dma_handle);
2270 }
2271
b4bee692 2272 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
9a2985e7 2273 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
b4bee692 2274
e34d0bbb
LP		 2275 if (ch->tx_dev) {
2276 ch->tx_dev->lcdc = NULL;
b5ef967d 2277 module_put(ch->cfg->tx_dev->dev.driver->owner);
e34d0bbb 2278 }
9a2985e7 2279
a67f379d 2280 sh_mobile_lcdc_channel_fb_cleanup(ch);
b4bee692 2281
a67f379d
LP		 2282 if (ch->fb_mem)
2283 dma_free_coherent(&pdev->dev, ch->fb_size,
2284 ch->fb_mem, ch->dma_handle);
b4bee692
LP		 2285 }
2286
2287 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
0c75c4e0
LP		 2288 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
2289
2290 if (ch->bl)
2291 sh_mobile_lcdc_bl_remove(ch->bl);
2292 mutex_destroy(&ch->open_lock);
b4bee692
LP		 2293 }
2294
4774c12a
LP		 2295 if (priv->dot_clk) {
2296 pm_runtime_disable(&pdev->dev);
b4bee692 2297 clk_put(priv->dot_clk);
4774c12a 2298 }
b4bee692
LP		 2299
2300 if (priv->base)
2301 iounmap(priv->base);
2302
2303 if (priv->irq)
2304 free_irq(priv->irq, priv);
2305 kfree(priv);
2306 return 0;
2307}
cfb4f5d1 2308
48c68c4f 2309static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f 2310{
b5ef967d 2311 int interface_type = ch->cfg->interface_type;
f1f60b5f
LP		 2312
2313 switch (interface_type) {
2314 case RGB8:
2315 case RGB9:
2316 case RGB12A:
2317 case RGB12B:
2318 case RGB16:
2319 case RGB18:
2320 case RGB24:
2321 case SYS8A:
2322 case SYS8B:
2323 case SYS8C:
2324 case SYS8D:
2325 case SYS9:
2326 case SYS12:
2327 case SYS16A:
2328 case SYS16B:
2329 case SYS16C:
2330 case SYS18:
2331 case SYS24:
2332 break;
2333 default:
2334 return -EINVAL;
2335 }
2336
2337 /* SUBLCD only supports SYS interface */
2338 if (lcdc_chan_is_sublcd(ch)) {
2339 if (!(interface_type & LDMT1R_IFM))
2340 return -EINVAL;
2341
2342 interface_type &= ~LDMT1R_IFM;
2343 }
2344
2345 ch->ldmt1r_value = interface_type;
2346 return 0;
2347}
2348
48c68c4f 2349static int
0707330b 2350sh_mobile_lcdc_overlay_init(struct sh_mobile_lcdc_overlay *ovl)
c5deac3c
LP		 2351{
2352 const struct sh_mobile_lcdc_format_info *format;
0707330b 2353 struct device *dev = ovl->channel->lcdc->dev;
c5deac3c
LP		 2354 int ret;
2355
2356 if (ovl->cfg->fourcc == 0)
2357 return 0;
2358
2359 /* Validate the format. */
2360 format = sh_mobile_format_info(ovl->cfg->fourcc);
2361 if (format == NULL) {
0707330b 2362 dev_err(dev, "Invalid FOURCC %08x\n", ovl->cfg->fourcc);
c5deac3c
LP		 2363 return -EINVAL;
2364 }
2365
2366 ovl->enabled = false;
2367 ovl->mode = LCDC_OVERLAY_BLEND;
2368 ovl->alpha = 255;
2369 ovl->rop3 = 0;
2370 ovl->pos_x = 0;
2371 ovl->pos_y = 0;
2372
2373 /* The default Y virtual resolution is twice the panel size to allow for
2374 * double-buffering.
2375 */
2376 ovl->format = format;
2377 ovl->xres = ovl->cfg->max_xres;
2378 ovl->xres_virtual = ovl->xres;
2379 ovl->yres = ovl->cfg->max_yres;
2380 ovl->yres_virtual = ovl->yres * 2;
2381
2382 if (!format->yuv)
16ca21c9 2383 ovl->pitch = ovl->xres_virtual * format->bpp / 8;
c5deac3c 2384 else
16ca21c9 2385 ovl->pitch = ovl->xres_virtual;
c5deac3c
LP		 2386
2387 /* Allocate frame buffer memory. */
2388 ovl->fb_size = ovl->cfg->max_xres * ovl->cfg->max_yres
2389 * format->bpp / 8 * 2;
0707330b
LP		 2390 ovl->fb_mem = dma_alloc_coherent(dev, ovl->fb_size, &ovl->dma_handle,
2391 GFP_KERNEL);
c5deac3c 2392 if (!ovl->fb_mem) {
0707330b 2393 dev_err(dev, "unable to allocate buffer\n");
c5deac3c
LP		 2394 return -ENOMEM;
2395 }
2396
2397 ret = sh_mobile_lcdc_overlay_fb_init(ovl);
2398 if (ret < 0)
2399 return ret;
2400
2401 return 0;
2402}
2403
48c68c4f 2404static int
0707330b 2405sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_chan *ch)
cfb4f5d1 2406{
105784bb 2407 const struct sh_mobile_lcdc_format_info *format;
b5ef967d 2408 const struct sh_mobile_lcdc_chan_cfg *cfg = ch->cfg;
0707330b 2409 struct device *dev = ch->lcdc->dev;
3ce05599
LP		 2410 const struct fb_videomode *max_mode;
2411 const struct fb_videomode *mode;
a67f379d 2412 unsigned int num_modes;
3ce05599 2413 unsigned int max_size;
a67f379d 2414 unsigned int i;
3ce05599 2415
105784bb
LP		 2416 /* Validate the format. */
2417 format = sh_mobile_format_info(cfg->fourcc);
2418 if (format == NULL) {
0707330b 2419 dev_err(dev, "Invalid FOURCC %08x.\n", cfg->fourcc);
105784bb
LP		 2420 return -EINVAL;
2421 }
2422
3ce05599
LP		 2423 /* Iterate through the modes to validate them and find the highest
2424 * resolution.
2425 */
2426 max_mode = NULL;
2427 max_size = 0;
2428
93ff2598 2429 for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
3ce05599
LP		 2430 unsigned int size = mode->yres * mode->xres;
2431
edd153a3
LP		 2432 /* NV12/NV21 buffers must have even number of lines */
2433 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
2434 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
0707330b 2435 dev_err(dev, "yres must be multiple of 2 for "
0a7f17aa 2436 "YCbCr420 mode.\n");
3ce05599
LP		 2437 return -EINVAL;
2438 }
2439
2440 if (size > max_size) {
2441 max_mode = mode;
2442 max_size = size;
2443 }
2444 }
2445
2446 if (!max_size)
2447 max_size = MAX_XRES * MAX_YRES;
2448 else
0707330b 2449 dev_dbg(dev, "Found largest videomode %ux%u\n",
3ce05599
LP		 2450 max_mode->xres, max_mode->yres);
2451
93ff2598 2452 if (cfg->lcd_modes == NULL) {
3ce05599 2453 mode = &default_720p;
93ff2598 2454 num_modes = 1;
3ce05599 2455 } else {
93ff2598
LP		 2456 mode = cfg->lcd_modes;
2457 num_modes = cfg->num_modes;
3ce05599
LP		 2458 }
2459
bd5f2c69
LP		 2460 /* Use the first mode as default. The default Y virtual resolution is
2461 * twice the panel size to allow for double-buffering.
2462 */
58f03d99
LP		 2463 ch->format = format;
2464 ch->xres = mode->xres;
2465 ch->xres_virtual = mode->xres;
2466 ch->yres = mode->yres;
2467 ch->yres_virtual = mode->yres * 2;
2468
2469 if (!format->yuv) {
2470 ch->colorspace = V4L2_COLORSPACE_SRGB;
16ca21c9 2471 ch->pitch = ch->xres_virtual * format->bpp / 8;
58f03d99
LP		 2472 } else {
2473 ch->colorspace = V4L2_COLORSPACE_REC709;
16ca21c9 2474 ch->pitch = ch->xres_virtual;
58f03d99
LP		 2475 }
2476
a67f379d
LP		 2477 ch->display.width = cfg->panel_cfg.width;
2478 ch->display.height = cfg->panel_cfg.height;
2479 ch->display.mode = *mode;
2480
2481 /* Allocate frame buffer memory. */
2482 ch->fb_size = max_size * format->bpp / 8 * 2;
0707330b 2483 ch->fb_mem = dma_alloc_coherent(dev, ch->fb_size, &ch->dma_handle,
a67f379d
LP		 2484 GFP_KERNEL);
2485 if (ch->fb_mem == NULL) {
0707330b 2486 dev_err(dev, "unable to allocate buffer\n");
a67f379d
LP		 2487 return -ENOMEM;
2488 }
3ce05599 2489
13f80eea
LP		 2490 /* Initialize the transmitter device if present. */
2491 if (cfg->tx_dev) {
2492 if (!cfg->tx_dev->dev.driver ||
2493 !try_module_get(cfg->tx_dev->dev.driver->owner)) {
0707330b 2494 dev_warn(dev, "unable to get transmitter device\n");
13f80eea
LP		 2495 return -EINVAL;
2496 }
2497 ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
2498 ch->tx_dev->lcdc = ch;
2499 ch->tx_dev->def_mode = *mode;
2500 }
2501
a67f379d 2502 return sh_mobile_lcdc_channel_fb_init(ch, mode, num_modes);
3ce05599
LP		 2503}
2504
48c68c4f 2505static int sh_mobile_lcdc_probe(struct platform_device *pdev)
3ce05599 2506{
01ac25b5 2507 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 2508 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 2509 struct resource *res;
3ce05599 2510 int num_channels;
cfb4f5d1 2511 int error;
7374ccc0 2512 int irq, i;
cfb4f5d1 2513
01ac25b5 2514 if (!pdata) {
cfb4f5d1 2515 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 2516 return -EINVAL;
cfb4f5d1
MD		 2517 }
2518
2519 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7374ccc0
GU		 2520 irq = platform_get_irq(pdev, 0);
2521 if (!res || irq < 0) {
8564557a 2522 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 2523 return -ENOENT;
cfb4f5d1
MD		 2524 }
2525
2526 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
e281018b 2527 if (!priv)
8bed9055 2528 return -ENOMEM;
cfb4f5d1 2529
4774c12a 2530 priv->dev = &pdev->dev;
9076aa99 2531
7374ccc0
GU		 2532 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
2533 mutex_init(&priv->ch[i].open_lock);
8bed9055
GL		 2534 platform_set_drvdata(pdev, priv);
2535
7374ccc0 2536 error = request_irq(irq, sh_mobile_lcdc_irq, 0,
7ad33e74 2537 dev_name(&pdev->dev), priv);
8564557a
MD		 2538 if (error) {
2539 dev_err(&pdev->dev, "unable to request irq\n");
2540 goto err1;
2541 }
2542
7374ccc0 2543 priv->irq = irq;
5ef6b505 2544 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 2545
3ce05599
LP		 2546 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
2547 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 2548
01ac25b5 2549 ch->lcdc = priv;
b5ef967d 2550 ch->cfg = &pdata->ch[i];
cfb4f5d1 2551
01ac25b5 2552 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 2553 if (error) {
2554 dev_err(&pdev->dev, "unsupported interface type\n");
2555 goto err1;
2556 }
01ac25b5
GL		 2557 init_waitqueue_head(&ch->frame_end_wait);
2558 init_completion(&ch->vsync_completion);
cfb4f5d1 2559
3b0fd9d7 2560 /* probe the backlight is there is one defined */
b5ef967d 2561 if (ch->cfg->bl_info.max_brightness)
3b0fd9d7
AC		 2562 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
2563
cfb4f5d1
MD		 2564 switch (pdata->ch[i].chan) {
2565 case LCDC_CHAN_MAINLCD:
ce1c0b08 2566 ch->enabled = LDCNT2R_ME;
01ac25b5 2567 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 2568 num_channels++;
cfb4f5d1
MD		 2569 break;
2570 case LCDC_CHAN_SUBLCD:
ce1c0b08 2571 ch->enabled = LDCNT2R_SE;
01ac25b5 2572 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 2573 num_channels++;
cfb4f5d1
MD		 2574 break;
2575 }
2576 }
2577
3ce05599 2578 if (!num_channels) {
cfb4f5d1
MD		 2579 dev_err(&pdev->dev, "no channels defined\n");
2580 error = -EINVAL;
2581 goto err1;
2582 }
2583
edd153a3 2584 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 2585 if (num_channels == 2)
edd153a3 2586 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 2587
4bdc0d67 2588 priv->base = ioremap(res->start, resource_size(res));
b49898ce
WY		 2589 if (!priv->base) {
2590 error = -ENOMEM;
dba6f385 2591 goto err1;
b49898ce 2592 }
dba6f385 2593
0a7f17aa 2594 error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
cfb4f5d1
MD		 2595 if (error) {
2596 dev_err(&pdev->dev, "unable to setup clocks\n");
2597 goto err1;
2598 }
2599
4774c12a
LP		 2600 /* Enable runtime PM. */
2601 pm_runtime_enable(&pdev->dev);
7caa4342 2602
3ce05599 2603 for (i = 0; i < num_channels; i++) {
0707330b 2604 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
c44f9f76 2605
0707330b 2606 error = sh_mobile_lcdc_channel_init(ch);
cfb4f5d1 2607 if (error)
3ce05599 2608 goto err1;
cfb4f5d1
MD		 2609 }
2610
c5deac3c
LP		 2611 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2612 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2613
2614 ovl->cfg = &pdata->overlays[i];
2615 ovl->channel = &priv->ch[0];
2616
0707330b 2617 error = sh_mobile_lcdc_overlay_init(ovl);
c5deac3c
LP		 2618 if (error)
2619 goto err1;
2620 }
2621
cfb4f5d1
MD		 2622 error = sh_mobile_lcdc_start(priv);
2623 if (error) {
2624 dev_err(&pdev->dev, "unable to start hardware\n");
2625 goto err1;
2626 }
2627
3ce05599 2628 for (i = 0; i < num_channels; i++) {
1c6a307a 2629 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1c6a307a 2630
a67f379d
LP		 2631 error = sh_mobile_lcdc_channel_fb_register(ch);
2632 if (error)
cfb4f5d1 2633 goto err1;
cfb4f5d1
MD		 2634 }
2635
c5deac3c
LP		 2636 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2637 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2638
2639 error = sh_mobile_lcdc_overlay_fb_register(ovl);
2640 if (error)
2641 goto err1;
2642 }
2643
cfb4f5d1 2644 return 0;
8bed9055 2645err1:
cfb4f5d1 2646 sh_mobile_lcdc_remove(pdev);
8bed9055 2647
cfb4f5d1
MD		 2648 return error;
2649}
2650
cfb4f5d1
MD		 2651static struct platform_driver sh_mobile_lcdc_driver = {
2652 .driver = {
2653 .name = "sh_mobile_lcdc_fb",
2feb075a 2654 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 2655 },
2656 .probe = sh_mobile_lcdc_probe,
2657 .remove = sh_mobile_lcdc_remove,
2658};
2659
4277f2c4 2660module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 2661
2662MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
2663MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
2664MODULE_LICENSE("GPL v2");
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