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Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | /* |
3 | * linux/drivers/video/w100fb.h | |
4 | * | |
5 | * Frame Buffer Device for ATI w100 (Wallaby) | |
6 | * | |
7 | * Copyright (C) 2002, ATI Corp. | |
8 | * Copyright (C) 2004-2005 Richard Purdie | |
aac51f09 | 9 | * Copyright (c) 2005 Ian Molton <spyro@f2s.com> |
1da177e4 LT |
10 | * |
11 | * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net> | |
12 | * | |
aac51f09 | 13 | * w32xx support by Ian Molton |
1da177e4 LT |
14 | */ |
15 | ||
16 | #if !defined (_W100FB_H) | |
17 | #define _W100FB_H | |
18 | ||
19 | /* Block CIF Start: */ | |
20 | #define mmCHIP_ID 0x0000 | |
aac51f09 | 21 | #define mmREVISION_ID 0x0004 |
1da177e4 LT |
22 | #define mmWRAP_BUF_A 0x0008 |
23 | #define mmWRAP_BUF_B 0x000C | |
24 | #define mmWRAP_TOP_DIR 0x0010 | |
25 | #define mmWRAP_START_DIR 0x0014 | |
26 | #define mmCIF_CNTL 0x0018 | |
27 | #define mmCFGREG_BASE 0x001C | |
28 | #define mmCIF_IO 0x0020 | |
29 | #define mmCIF_READ_DBG 0x0024 | |
30 | #define mmCIF_WRITE_DBG 0x0028 | |
31 | #define cfgIND_ADDR_A_0 0x0000 | |
32 | #define cfgIND_ADDR_A_1 0x0001 | |
33 | #define cfgIND_ADDR_A_2 0x0002 | |
34 | #define cfgIND_DATA_A 0x0003 | |
35 | #define cfgREG_BASE 0x0004 | |
36 | #define cfgINTF_CNTL 0x0005 | |
37 | #define cfgSTATUS 0x0006 | |
38 | #define cfgCPU_DEFAULTS 0x0007 | |
39 | #define cfgIND_ADDR_B_0 0x0008 | |
40 | #define cfgIND_ADDR_B_1 0x0009 | |
41 | #define cfgIND_ADDR_B_2 0x000A | |
42 | #define cfgIND_DATA_B 0x000B | |
43 | #define cfgPM4_RPTR 0x000C | |
44 | #define cfgSCRATCH 0x000D | |
45 | #define cfgPM4_WRPTR_0 0x000E | |
46 | #define cfgPM4_WRPTR_1 0x000F | |
47 | /* Block CIF End: */ | |
48 | ||
49 | /* Block CP Start: */ | |
50 | #define mmSCRATCH_UMSK 0x0280 | |
51 | #define mmSCRATCH_ADDR 0x0284 | |
52 | #define mmGEN_INT_CNTL 0x0200 | |
53 | #define mmGEN_INT_STATUS 0x0204 | |
54 | /* Block CP End: */ | |
55 | ||
56 | /* Block DISPLAY Start: */ | |
57 | #define mmLCD_FORMAT 0x0410 | |
58 | #define mmGRAPHIC_CTRL 0x0414 | |
59 | #define mmGRAPHIC_OFFSET 0x0418 | |
60 | #define mmGRAPHIC_PITCH 0x041C | |
61 | #define mmCRTC_TOTAL 0x0420 | |
62 | #define mmACTIVE_H_DISP 0x0424 | |
63 | #define mmACTIVE_V_DISP 0x0428 | |
64 | #define mmGRAPHIC_H_DISP 0x042C | |
65 | #define mmGRAPHIC_V_DISP 0x0430 | |
66 | #define mmVIDEO_CTRL 0x0434 | |
67 | #define mmGRAPHIC_KEY 0x0438 | |
68 | #define mmBRIGHTNESS_CNTL 0x045C | |
69 | #define mmDISP_INT_CNTL 0x0488 | |
70 | #define mmCRTC_SS 0x048C | |
71 | #define mmCRTC_LS 0x0490 | |
72 | #define mmCRTC_REV 0x0494 | |
73 | #define mmCRTC_DCLK 0x049C | |
74 | #define mmCRTC_GS 0x04A0 | |
75 | #define mmCRTC_VPOS_GS 0x04A4 | |
76 | #define mmCRTC_GCLK 0x04A8 | |
77 | #define mmCRTC_GOE 0x04AC | |
78 | #define mmCRTC_FRAME 0x04B0 | |
79 | #define mmCRTC_FRAME_VPOS 0x04B4 | |
80 | #define mmGPIO_DATA 0x04B8 | |
81 | #define mmGPIO_CNTL1 0x04BC | |
82 | #define mmGPIO_CNTL2 0x04C0 | |
83 | #define mmLCDD_CNTL1 0x04C4 | |
84 | #define mmLCDD_CNTL2 0x04C8 | |
85 | #define mmGENLCD_CNTL1 0x04CC | |
86 | #define mmGENLCD_CNTL2 0x04D0 | |
87 | #define mmDISP_DEBUG 0x04D4 | |
88 | #define mmDISP_DB_BUF_CNTL 0x04D8 | |
89 | #define mmDISP_CRC_SIG 0x04DC | |
aac51f09 | 90 | #define mmCRTC_DEFAULT_COUNT 0x04E0 |
1da177e4 LT |
91 | #define mmLCD_BACKGROUND_COLOR 0x04E4 |
92 | #define mmCRTC_PS2 0x04E8 | |
93 | #define mmCRTC_PS2_VPOS 0x04EC | |
94 | #define mmCRTC_PS1_ACTIVE 0x04F0 | |
95 | #define mmCRTC_PS1_NACTIVE 0x04F4 | |
96 | #define mmCRTC_GCLK_EXT 0x04F8 | |
97 | #define mmCRTC_ALW 0x04FC | |
98 | #define mmCRTC_ALW_VPOS 0x0500 | |
99 | #define mmCRTC_PSK 0x0504 | |
100 | #define mmCRTC_PSK_HPOS 0x0508 | |
101 | #define mmCRTC_CV4_START 0x050C | |
102 | #define mmCRTC_CV4_END 0x0510 | |
103 | #define mmCRTC_CV4_HPOS 0x0514 | |
104 | #define mmCRTC_ECK 0x051C | |
105 | #define mmREFRESH_CNTL 0x0520 | |
106 | #define mmGENLCD_CNTL3 0x0524 | |
107 | #define mmGPIO_DATA2 0x0528 | |
108 | #define mmGPIO_CNTL3 0x052C | |
109 | #define mmGPIO_CNTL4 0x0530 | |
110 | #define mmCHIP_STRAP 0x0534 | |
111 | #define mmDISP_DEBUG2 0x0538 | |
112 | #define mmDEBUG_BUS_CNTL 0x053C | |
113 | #define mmGAMMA_VALUE1 0x0540 | |
114 | #define mmGAMMA_VALUE2 0x0544 | |
115 | #define mmGAMMA_SLOPE 0x0548 | |
116 | #define mmGEN_STATUS 0x054C | |
117 | #define mmHW_INT 0x0550 | |
118 | /* Block DISPLAY End: */ | |
119 | ||
120 | /* Block GFX Start: */ | |
9b0e1c5d AM |
121 | #define mmDST_OFFSET 0x1004 |
122 | #define mmDST_PITCH 0x1008 | |
123 | #define mmDST_Y_X 0x1038 | |
124 | #define mmDST_WIDTH_HEIGHT 0x1198 | |
125 | #define mmDP_GUI_MASTER_CNTL 0x106C | |
aac51f09 RP |
126 | #define mmBRUSH_OFFSET 0x108C |
127 | #define mmBRUSH_Y_X 0x1074 | |
9b0e1c5d AM |
128 | #define mmDP_BRUSH_FRGD_CLR 0x107C |
129 | #define mmSRC_OFFSET 0x11AC | |
130 | #define mmSRC_PITCH 0x11B0 | |
131 | #define mmSRC_Y_X 0x1034 | |
aac51f09 RP |
132 | #define mmDEFAULT_PITCH_OFFSET 0x10A0 |
133 | #define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8 | |
134 | #define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC | |
9b0e1c5d AM |
135 | #define mmSC_TOP_LEFT 0x11BC |
136 | #define mmSC_BOTTOM_RIGHT 0x11C0 | |
137 | #define mmSRC_SC_BOTTOM_RIGHT 0x11C4 | |
aac51f09 RP |
138 | #define mmGLOBAL_ALPHA 0x1210 |
139 | #define mmFILTER_COEF 0x1214 | |
140 | #define mmMVC_CNTL_START 0x11E0 | |
141 | #define mmE2_ARITHMETIC_CNTL 0x1220 | |
9b0e1c5d AM |
142 | #define mmDP_CNTL 0x11C8 |
143 | #define mmDP_CNTL_DST_DIR 0x11CC | |
144 | #define mmDP_DATATYPE 0x12C4 | |
145 | #define mmDP_MIX 0x12C8 | |
146 | #define mmDP_WRITE_MSK 0x12CC | |
aac51f09 RP |
147 | #define mmENG_CNTL 0x13E8 |
148 | #define mmENG_PERF_CNT 0x13F0 | |
1da177e4 LT |
149 | /* Block GFX End: */ |
150 | ||
151 | /* Block IDCT Start: */ | |
152 | #define mmIDCT_RUNS 0x0C00 | |
153 | #define mmIDCT_LEVELS 0x0C04 | |
154 | #define mmIDCT_CONTROL 0x0C3C | |
155 | #define mmIDCT_AUTH_CONTROL 0x0C08 | |
156 | #define mmIDCT_AUTH 0x0C0C | |
157 | /* Block IDCT End: */ | |
158 | ||
159 | /* Block MC Start: */ | |
aac51f09 RP |
160 | #define mmMEM_CNTL 0x0180 |
161 | #define mmMEM_ARB 0x0184 | |
162 | #define mmMC_FB_LOCATION 0x0188 | |
163 | #define mmMEM_EXT_CNTL 0x018C | |
164 | #define mmMC_EXT_MEM_LOCATION 0x0190 | |
165 | #define mmMEM_EXT_TIMING_CNTL 0x0194 | |
166 | #define mmMEM_SDRAM_MODE_REG 0x0198 | |
167 | #define mmMEM_IO_CNTL 0x019C | |
168 | #define mmMC_DEBUG 0x01A0 | |
169 | #define mmMC_BIST_CTRL 0x01A4 | |
170 | #define mmMC_BIST_COLLAR_READ 0x01A8 | |
171 | #define mmTC_MISMATCH 0x01AC | |
172 | #define mmMC_PERF_MON_CNTL 0x01B0 | |
173 | #define mmMC_PERF_COUNTERS 0x01B4 | |
1da177e4 LT |
174 | /* Block MC End: */ |
175 | ||
aac51f09 RP |
176 | /* Block BM Start: */ |
177 | #define mmBM_EXT_MEM_BANDWIDTH 0x0A00 | |
178 | #define mmBM_OFFSET 0x0A04 | |
179 | #define mmBM_MEM_EXT_TIMING_CNTL 0x0A08 | |
180 | #define mmBM_MEM_EXT_CNTL 0x0A0C | |
181 | #define mmBM_MEM_MODE_REG 0x0A10 | |
182 | #define mmBM_MEM_IO_CNTL 0x0A18 | |
183 | #define mmBM_CONFIG 0x0A1C | |
184 | #define mmBM_STATUS 0x0A20 | |
185 | #define mmBM_DEBUG 0x0A24 | |
186 | #define mmBM_PERF_MON_CNTL 0x0A28 | |
187 | #define mmBM_PERF_COUNTERS 0x0A2C | |
188 | #define mmBM_PERF2_MON_CNTL 0x0A30 | |
189 | #define mmBM_PERF2_COUNTERS 0x0A34 | |
190 | /* Block BM End: */ | |
191 | ||
1da177e4 LT |
192 | /* Block RBBM Start: */ |
193 | #define mmWAIT_UNTIL 0x1400 | |
194 | #define mmISYNC_CNTL 0x1404 | |
9b0e1c5d | 195 | #define mmRBBM_STATUS 0x0140 |
1da177e4 LT |
196 | #define mmRBBM_CNTL 0x0144 |
197 | #define mmNQWAIT_UNTIL 0x0150 | |
198 | /* Block RBBM End: */ | |
199 | ||
200 | /* Block CG Start: */ | |
201 | #define mmCLK_PIN_CNTL 0x0080 | |
202 | #define mmPLL_REF_FB_DIV 0x0084 | |
203 | #define mmPLL_CNTL 0x0088 | |
204 | #define mmSCLK_CNTL 0x008C | |
205 | #define mmPCLK_CNTL 0x0090 | |
206 | #define mmCLK_TEST_CNTL 0x0094 | |
207 | #define mmPWRMGT_CNTL 0x0098 | |
208 | #define mmPWRMGT_STATUS 0x009C | |
209 | /* Block CG End: */ | |
210 | ||
211 | /* default value definitions */ | |
aac51f09 RP |
212 | #define defWRAP_TOP_DIR 0x00000000 |
213 | #define defWRAP_START_DIR 0x00000000 | |
214 | #define defCFGREG_BASE 0x00000000 | |
215 | #define defCIF_IO 0x000C0902 | |
216 | #define defINTF_CNTL 0x00000011 | |
217 | #define defCPU_DEFAULTS 0x00000006 | |
218 | #define defHW_INT 0x00000000 | |
219 | #define defMC_EXT_MEM_LOCATION 0x07ff0000 | |
220 | #define defTC_MISMATCH 0x00000000 | |
1da177e4 LT |
221 | |
222 | #define W100_CFG_BASE 0x0 | |
223 | #define W100_CFG_LEN 0x10 | |
224 | #define W100_REG_BASE 0x10000 | |
225 | #define W100_REG_LEN 0x2000 | |
226 | #define MEM_INT_BASE_VALUE 0x100000 | |
1da177e4 | 227 | #define MEM_EXT_BASE_VALUE 0x800000 |
aac51f09 RP |
228 | #define MEM_INT_SIZE 0x05ffff |
229 | #define MEM_WINDOW_BASE 0x100000 | |
230 | #define MEM_WINDOW_SIZE 0xf00000 | |
231 | ||
1da177e4 LT |
232 | #define WRAP_BUF_BASE_VALUE 0x80000 |
233 | #define WRAP_BUF_TOP_VALUE 0xbffff | |
234 | ||
aac51f09 RP |
235 | #define CHIP_ID_W100 0x57411002 |
236 | #define CHIP_ID_W3200 0x56441002 | |
237 | #define CHIP_ID_W3220 0x57441002 | |
1da177e4 | 238 | |
aac51f09 | 239 | /* Register structure definitions */ |
1da177e4 LT |
240 | |
241 | struct wrap_top_dir_t { | |
9b0e1c5d AM |
242 | u32 top_addr : 23; |
243 | u32 : 9; | |
1da177e4 LT |
244 | } __attribute__((packed)); |
245 | ||
246 | union wrap_top_dir_u { | |
9b0e1c5d | 247 | u32 val : 32; |
aac51f09 | 248 | struct wrap_top_dir_t f; |
1da177e4 LT |
249 | } __attribute__((packed)); |
250 | ||
251 | struct wrap_start_dir_t { | |
9b0e1c5d AM |
252 | u32 start_addr : 23; |
253 | u32 : 9; | |
1da177e4 LT |
254 | } __attribute__((packed)); |
255 | ||
256 | union wrap_start_dir_u { | |
9b0e1c5d | 257 | u32 val : 32; |
aac51f09 | 258 | struct wrap_start_dir_t f; |
1da177e4 LT |
259 | } __attribute__((packed)); |
260 | ||
261 | struct cif_cntl_t { | |
9b0e1c5d AM |
262 | u32 swap_reg : 2; |
263 | u32 swap_fbuf_1 : 2; | |
264 | u32 swap_fbuf_2 : 2; | |
265 | u32 swap_fbuf_3 : 2; | |
266 | u32 pmi_int_disable : 1; | |
267 | u32 pmi_schmen_disable : 1; | |
268 | u32 intb_oe : 1; | |
269 | u32 en_wait_to_compensate_dq_prop_dly : 1; | |
270 | u32 compensate_wait_rd_size : 2; | |
271 | u32 wait_asserted_timeout_val : 2; | |
272 | u32 wait_masked_val : 2; | |
273 | u32 en_wait_timeout : 1; | |
274 | u32 en_one_clk_setup_before_wait : 1; | |
275 | u32 interrupt_active_high : 1; | |
276 | u32 en_overwrite_straps : 1; | |
277 | u32 strap_wait_active_hi : 1; | |
278 | u32 lat_busy_count : 2; | |
279 | u32 lat_rd_pm4_sclk_busy : 1; | |
280 | u32 dis_system_bits : 1; | |
281 | u32 dis_mr : 1; | |
282 | u32 cif_spare_1 : 4; | |
1da177e4 LT |
283 | } __attribute__((packed)); |
284 | ||
285 | union cif_cntl_u { | |
9b0e1c5d | 286 | u32 val : 32; |
aac51f09 | 287 | struct cif_cntl_t f; |
1da177e4 LT |
288 | } __attribute__((packed)); |
289 | ||
290 | struct cfgreg_base_t { | |
9b0e1c5d AM |
291 | u32 cfgreg_base : 24; |
292 | u32 : 8; | |
1da177e4 LT |
293 | } __attribute__((packed)); |
294 | ||
295 | union cfgreg_base_u { | |
9b0e1c5d | 296 | u32 val : 32; |
aac51f09 | 297 | struct cfgreg_base_t f; |
1da177e4 LT |
298 | } __attribute__((packed)); |
299 | ||
300 | struct cif_io_t { | |
9b0e1c5d AM |
301 | u32 dq_srp : 1; |
302 | u32 dq_srn : 1; | |
303 | u32 dq_sp : 4; | |
304 | u32 dq_sn : 4; | |
305 | u32 waitb_srp : 1; | |
306 | u32 waitb_srn : 1; | |
307 | u32 waitb_sp : 4; | |
308 | u32 waitb_sn : 4; | |
309 | u32 intb_srp : 1; | |
310 | u32 intb_srn : 1; | |
311 | u32 intb_sp : 4; | |
312 | u32 intb_sn : 4; | |
313 | u32 : 2; | |
1da177e4 LT |
314 | } __attribute__((packed)); |
315 | ||
316 | union cif_io_u { | |
9b0e1c5d | 317 | u32 val : 32; |
aac51f09 | 318 | struct cif_io_t f; |
1da177e4 LT |
319 | } __attribute__((packed)); |
320 | ||
321 | struct cif_read_dbg_t { | |
9b0e1c5d AM |
322 | u32 unpacker_pre_fetch_trig_gen : 2; |
323 | u32 dly_second_rd_fetch_trig : 1; | |
324 | u32 rst_rd_burst_id : 1; | |
325 | u32 dis_rd_burst_id : 1; | |
326 | u32 en_block_rd_when_packer_is_not_emp : 1; | |
327 | u32 dis_pre_fetch_cntl_sm : 1; | |
328 | u32 rbbm_chrncy_dis : 1; | |
329 | u32 rbbm_rd_after_wr_lat : 2; | |
330 | u32 dis_be_during_rd : 1; | |
331 | u32 one_clk_invalidate_pulse : 1; | |
332 | u32 dis_chnl_priority : 1; | |
333 | u32 rst_read_path_a_pls : 1; | |
334 | u32 rst_read_path_b_pls : 1; | |
335 | u32 dis_reg_rd_fetch_trig : 1; | |
336 | u32 dis_rd_fetch_trig_from_ind_addr : 1; | |
337 | u32 dis_rd_same_byte_to_trig_fetch : 1; | |
338 | u32 dis_dir_wrap : 1; | |
339 | u32 dis_ring_buf_to_force_dec : 1; | |
340 | u32 dis_addr_comp_in_16bit : 1; | |
341 | u32 clr_w : 1; | |
342 | u32 err_rd_tag_is_3 : 1; | |
343 | u32 err_load_when_ful_a : 1; | |
344 | u32 err_load_when_ful_b : 1; | |
345 | u32 : 7; | |
1da177e4 LT |
346 | } __attribute__((packed)); |
347 | ||
348 | union cif_read_dbg_u { | |
9b0e1c5d | 349 | u32 val : 32; |
aac51f09 | 350 | struct cif_read_dbg_t f; |
1da177e4 LT |
351 | } __attribute__((packed)); |
352 | ||
353 | struct cif_write_dbg_t { | |
9b0e1c5d AM |
354 | u32 packer_timeout_count : 2; |
355 | u32 en_upper_load_cond : 1; | |
356 | u32 en_chnl_change_cond : 1; | |
357 | u32 dis_addr_comp_cond : 1; | |
358 | u32 dis_load_same_byte_addr_cond : 1; | |
359 | u32 dis_timeout_cond : 1; | |
360 | u32 dis_timeout_during_rbbm : 1; | |
361 | u32 dis_packer_ful_during_rbbm_timeout : 1; | |
362 | u32 en_dword_split_to_rbbm : 1; | |
363 | u32 en_dummy_val : 1; | |
364 | u32 dummy_val_sel : 1; | |
365 | u32 mask_pm4_wrptr_dec : 1; | |
366 | u32 dis_mc_clean_cond : 1; | |
367 | u32 err_two_reqi_during_ful : 1; | |
368 | u32 err_reqi_during_idle_clk : 1; | |
369 | u32 err_global : 1; | |
370 | u32 en_wr_buf_dbg_load : 1; | |
371 | u32 en_wr_buf_dbg_path : 1; | |
372 | u32 sel_wr_buf_byte : 3; | |
373 | u32 dis_rd_flush_wr : 1; | |
374 | u32 dis_packer_ful_cond : 1; | |
375 | u32 dis_invalidate_by_ops_chnl : 1; | |
376 | u32 en_halt_when_reqi_err : 1; | |
377 | u32 cif_spare_2 : 5; | |
378 | u32 : 1; | |
1da177e4 LT |
379 | } __attribute__((packed)); |
380 | ||
381 | union cif_write_dbg_u { | |
9b0e1c5d | 382 | u32 val : 32; |
aac51f09 | 383 | struct cif_write_dbg_t f; |
1da177e4 LT |
384 | } __attribute__((packed)); |
385 | ||
386 | ||
387 | struct intf_cntl_t { | |
aac51f09 RP |
388 | unsigned char ad_inc_a : 1; |
389 | unsigned char ring_buf_a : 1; | |
390 | unsigned char rd_fetch_trigger_a : 1; | |
391 | unsigned char rd_data_rdy_a : 1; | |
392 | unsigned char ad_inc_b : 1; | |
393 | unsigned char ring_buf_b : 1; | |
394 | unsigned char rd_fetch_trigger_b : 1; | |
395 | unsigned char rd_data_rdy_b : 1; | |
1da177e4 LT |
396 | } __attribute__((packed)); |
397 | ||
398 | union intf_cntl_u { | |
aac51f09 RP |
399 | unsigned char val : 8; |
400 | struct intf_cntl_t f; | |
1da177e4 LT |
401 | } __attribute__((packed)); |
402 | ||
403 | struct cpu_defaults_t { | |
aac51f09 RP |
404 | unsigned char unpack_rd_data : 1; |
405 | unsigned char access_ind_addr_a : 1; | |
406 | unsigned char access_ind_addr_b : 1; | |
407 | unsigned char access_scratch_reg : 1; | |
408 | unsigned char pack_wr_data : 1; | |
409 | unsigned char transition_size : 1; | |
410 | unsigned char en_read_buf_mode : 1; | |
411 | unsigned char rd_fetch_scratch : 1; | |
1da177e4 LT |
412 | } __attribute__((packed)); |
413 | ||
414 | union cpu_defaults_u { | |
aac51f09 RP |
415 | unsigned char val : 8; |
416 | struct cpu_defaults_t f; | |
417 | } __attribute__((packed)); | |
418 | ||
419 | struct crtc_total_t { | |
9b0e1c5d AM |
420 | u32 crtc_h_total : 10; |
421 | u32 : 6; | |
422 | u32 crtc_v_total : 10; | |
423 | u32 : 6; | |
aac51f09 RP |
424 | } __attribute__((packed)); |
425 | ||
426 | union crtc_total_u { | |
9b0e1c5d | 427 | u32 val : 32; |
aac51f09 RP |
428 | struct crtc_total_t f; |
429 | } __attribute__((packed)); | |
430 | ||
431 | struct crtc_ss_t { | |
9b0e1c5d AM |
432 | u32 ss_start : 10; |
433 | u32 : 6; | |
434 | u32 ss_end : 10; | |
435 | u32 : 2; | |
436 | u32 ss_align : 1; | |
437 | u32 ss_pol : 1; | |
438 | u32 ss_run_mode : 1; | |
439 | u32 ss_en : 1; | |
aac51f09 RP |
440 | } __attribute__((packed)); |
441 | ||
442 | union crtc_ss_u { | |
9b0e1c5d | 443 | u32 val : 32; |
aac51f09 RP |
444 | struct crtc_ss_t f; |
445 | } __attribute__((packed)); | |
446 | ||
447 | struct active_h_disp_t { | |
9b0e1c5d AM |
448 | u32 active_h_start : 10; |
449 | u32 : 6; | |
450 | u32 active_h_end : 10; | |
451 | u32 : 6; | |
aac51f09 RP |
452 | } __attribute__((packed)); |
453 | ||
454 | union active_h_disp_u { | |
9b0e1c5d | 455 | u32 val : 32; |
aac51f09 RP |
456 | struct active_h_disp_t f; |
457 | } __attribute__((packed)); | |
458 | ||
459 | struct active_v_disp_t { | |
9b0e1c5d AM |
460 | u32 active_v_start : 10; |
461 | u32 : 6; | |
462 | u32 active_v_end : 10; | |
463 | u32 : 6; | |
aac51f09 RP |
464 | } __attribute__((packed)); |
465 | ||
466 | union active_v_disp_u { | |
9b0e1c5d | 467 | u32 val : 32; |
aac51f09 RP |
468 | struct active_v_disp_t f; |
469 | } __attribute__((packed)); | |
470 | ||
471 | struct graphic_h_disp_t { | |
9b0e1c5d AM |
472 | u32 graphic_h_start : 10; |
473 | u32 : 6; | |
474 | u32 graphic_h_end : 10; | |
475 | u32 : 6; | |
aac51f09 RP |
476 | } __attribute__((packed)); |
477 | ||
478 | union graphic_h_disp_u { | |
9b0e1c5d | 479 | u32 val : 32; |
aac51f09 RP |
480 | struct graphic_h_disp_t f; |
481 | } __attribute__((packed)); | |
482 | ||
483 | struct graphic_v_disp_t { | |
9b0e1c5d AM |
484 | u32 graphic_v_start : 10; |
485 | u32 : 6; | |
486 | u32 graphic_v_end : 10; | |
487 | u32 : 6; | |
aac51f09 RP |
488 | } __attribute__((packed)); |
489 | ||
490 | union graphic_v_disp_u{ | |
9b0e1c5d | 491 | u32 val : 32; |
aac51f09 RP |
492 | struct graphic_v_disp_t f; |
493 | } __attribute__((packed)); | |
494 | ||
495 | struct graphic_ctrl_t_w100 { | |
9b0e1c5d AM |
496 | u32 color_depth : 3; |
497 | u32 portrait_mode : 2; | |
498 | u32 low_power_on : 1; | |
499 | u32 req_freq : 4; | |
500 | u32 en_crtc : 1; | |
501 | u32 en_graphic_req : 1; | |
502 | u32 en_graphic_crtc : 1; | |
503 | u32 total_req_graphic : 9; | |
504 | u32 lcd_pclk_on : 1; | |
505 | u32 lcd_sclk_on : 1; | |
506 | u32 pclk_running : 1; | |
507 | u32 sclk_running : 1; | |
508 | u32 : 6; | |
aac51f09 RP |
509 | } __attribute__((packed)); |
510 | ||
511 | struct graphic_ctrl_t_w32xx { | |
9b0e1c5d AM |
512 | u32 color_depth : 3; |
513 | u32 portrait_mode : 2; | |
514 | u32 low_power_on : 1; | |
515 | u32 req_freq : 4; | |
516 | u32 en_crtc : 1; | |
517 | u32 en_graphic_req : 1; | |
518 | u32 en_graphic_crtc : 1; | |
519 | u32 total_req_graphic : 10; | |
520 | u32 lcd_pclk_on : 1; | |
521 | u32 lcd_sclk_on : 1; | |
522 | u32 pclk_running : 1; | |
523 | u32 sclk_running : 1; | |
524 | u32 : 5; | |
aac51f09 RP |
525 | } __attribute__((packed)); |
526 | ||
527 | union graphic_ctrl_u { | |
9b0e1c5d | 528 | u32 val : 32; |
aac51f09 RP |
529 | struct graphic_ctrl_t_w100 f_w100; |
530 | struct graphic_ctrl_t_w32xx f_w32xx; | |
1da177e4 LT |
531 | } __attribute__((packed)); |
532 | ||
533 | struct video_ctrl_t { | |
9b0e1c5d AM |
534 | u32 video_mode : 1; |
535 | u32 keyer_en : 1; | |
536 | u32 en_video_req : 1; | |
537 | u32 en_graphic_req_video : 1; | |
538 | u32 en_video_crtc : 1; | |
539 | u32 video_hor_exp : 2; | |
540 | u32 video_ver_exp : 2; | |
541 | u32 uv_combine : 1; | |
542 | u32 total_req_video : 9; | |
543 | u32 video_ch_sel : 1; | |
544 | u32 video_portrait : 2; | |
545 | u32 yuv2rgb_en : 1; | |
546 | u32 yuv2rgb_option : 1; | |
547 | u32 video_inv_hor : 1; | |
548 | u32 video_inv_ver : 1; | |
549 | u32 gamma_sel : 2; | |
550 | u32 dis_limit : 1; | |
551 | u32 en_uv_hblend : 1; | |
552 | u32 rgb_gamma_sel : 2; | |
1da177e4 LT |
553 | } __attribute__((packed)); |
554 | ||
555 | union video_ctrl_u { | |
9b0e1c5d | 556 | u32 val : 32; |
aac51f09 | 557 | struct video_ctrl_t f; |
1da177e4 LT |
558 | } __attribute__((packed)); |
559 | ||
560 | struct disp_db_buf_cntl_rd_t { | |
9b0e1c5d AM |
561 | u32 en_db_buf : 1; |
562 | u32 update_db_buf_done : 1; | |
563 | u32 db_buf_cntl : 6; | |
564 | u32 : 24; | |
1da177e4 LT |
565 | } __attribute__((packed)); |
566 | ||
567 | union disp_db_buf_cntl_rd_u { | |
9b0e1c5d | 568 | u32 val : 32; |
aac51f09 | 569 | struct disp_db_buf_cntl_rd_t f; |
1da177e4 LT |
570 | } __attribute__((packed)); |
571 | ||
572 | struct disp_db_buf_cntl_wr_t { | |
9b0e1c5d AM |
573 | u32 en_db_buf : 1; |
574 | u32 update_db_buf : 1; | |
575 | u32 db_buf_cntl : 6; | |
576 | u32 : 24; | |
1da177e4 LT |
577 | } __attribute__((packed)); |
578 | ||
579 | union disp_db_buf_cntl_wr_u { | |
9b0e1c5d | 580 | u32 val : 32; |
aac51f09 | 581 | struct disp_db_buf_cntl_wr_t f; |
1da177e4 LT |
582 | } __attribute__((packed)); |
583 | ||
584 | struct gamma_value1_t { | |
9b0e1c5d AM |
585 | u32 gamma1 : 8; |
586 | u32 gamma2 : 8; | |
587 | u32 gamma3 : 8; | |
588 | u32 gamma4 : 8; | |
1da177e4 LT |
589 | } __attribute__((packed)); |
590 | ||
591 | union gamma_value1_u { | |
9b0e1c5d | 592 | u32 val : 32; |
aac51f09 | 593 | struct gamma_value1_t f; |
1da177e4 LT |
594 | } __attribute__((packed)); |
595 | ||
596 | struct gamma_value2_t { | |
9b0e1c5d AM |
597 | u32 gamma5 : 8; |
598 | u32 gamma6 : 8; | |
599 | u32 gamma7 : 8; | |
600 | u32 gamma8 : 8; | |
1da177e4 LT |
601 | } __attribute__((packed)); |
602 | ||
603 | union gamma_value2_u { | |
9b0e1c5d | 604 | u32 val : 32; |
aac51f09 | 605 | struct gamma_value2_t f; |
1da177e4 LT |
606 | } __attribute__((packed)); |
607 | ||
608 | struct gamma_slope_t { | |
9b0e1c5d AM |
609 | u32 slope1 : 3; |
610 | u32 slope2 : 3; | |
611 | u32 slope3 : 3; | |
612 | u32 slope4 : 3; | |
613 | u32 slope5 : 3; | |
614 | u32 slope6 : 3; | |
615 | u32 slope7 : 3; | |
616 | u32 slope8 : 3; | |
617 | u32 : 8; | |
1da177e4 LT |
618 | } __attribute__((packed)); |
619 | ||
620 | union gamma_slope_u { | |
9b0e1c5d | 621 | u32 val : 32; |
aac51f09 | 622 | struct gamma_slope_t f; |
1da177e4 LT |
623 | } __attribute__((packed)); |
624 | ||
625 | struct mc_ext_mem_location_t { | |
9b0e1c5d AM |
626 | u32 mc_ext_mem_start : 16; |
627 | u32 mc_ext_mem_top : 16; | |
1da177e4 LT |
628 | } __attribute__((packed)); |
629 | ||
630 | union mc_ext_mem_location_u { | |
9b0e1c5d | 631 | u32 val : 32; |
aac51f09 RP |
632 | struct mc_ext_mem_location_t f; |
633 | } __attribute__((packed)); | |
634 | ||
635 | struct mc_fb_location_t { | |
9b0e1c5d AM |
636 | u32 mc_fb_start : 16; |
637 | u32 mc_fb_top : 16; | |
aac51f09 RP |
638 | } __attribute__((packed)); |
639 | ||
640 | union mc_fb_location_u { | |
9b0e1c5d | 641 | u32 val : 32; |
aac51f09 | 642 | struct mc_fb_location_t f; |
1da177e4 LT |
643 | } __attribute__((packed)); |
644 | ||
645 | struct clk_pin_cntl_t { | |
9b0e1c5d AM |
646 | u32 osc_en : 1; |
647 | u32 osc_gain : 5; | |
648 | u32 dont_use_xtalin : 1; | |
649 | u32 xtalin_pm_en : 1; | |
650 | u32 xtalin_dbl_en : 1; | |
651 | u32 : 7; | |
652 | u32 cg_debug : 16; | |
1da177e4 LT |
653 | } __attribute__((packed)); |
654 | ||
655 | union clk_pin_cntl_u { | |
9b0e1c5d | 656 | u32 val : 32; |
aac51f09 | 657 | struct clk_pin_cntl_t f; |
1da177e4 LT |
658 | } __attribute__((packed)); |
659 | ||
660 | struct pll_ref_fb_div_t { | |
9b0e1c5d AM |
661 | u32 pll_ref_div : 4; |
662 | u32 : 4; | |
663 | u32 pll_fb_div_int : 6; | |
664 | u32 : 2; | |
665 | u32 pll_fb_div_frac : 3; | |
666 | u32 : 1; | |
667 | u32 pll_reset_time : 4; | |
668 | u32 pll_lock_time : 8; | |
1da177e4 LT |
669 | } __attribute__((packed)); |
670 | ||
671 | union pll_ref_fb_div_u { | |
9b0e1c5d | 672 | u32 val : 32; |
aac51f09 | 673 | struct pll_ref_fb_div_t f; |
1da177e4 LT |
674 | } __attribute__((packed)); |
675 | ||
676 | struct pll_cntl_t { | |
9b0e1c5d AM |
677 | u32 pll_pwdn : 1; |
678 | u32 pll_reset : 1; | |
679 | u32 pll_pm_en : 1; | |
680 | u32 pll_mode : 1; | |
681 | u32 pll_refclk_sel : 1; | |
682 | u32 pll_fbclk_sel : 1; | |
683 | u32 pll_tcpoff : 1; | |
684 | u32 pll_pcp : 3; | |
685 | u32 pll_pvg : 3; | |
686 | u32 pll_vcofr : 1; | |
687 | u32 pll_ioffset : 2; | |
688 | u32 pll_pecc_mode : 2; | |
689 | u32 pll_pecc_scon : 2; | |
690 | u32 pll_dactal : 4; | |
691 | u32 pll_cp_clip : 2; | |
692 | u32 pll_conf : 3; | |
693 | u32 pll_mbctrl : 2; | |
694 | u32 pll_ring_off : 1; | |
1da177e4 LT |
695 | } __attribute__((packed)); |
696 | ||
697 | union pll_cntl_u { | |
9b0e1c5d | 698 | u32 val : 32; |
aac51f09 | 699 | struct pll_cntl_t f; |
1da177e4 LT |
700 | } __attribute__((packed)); |
701 | ||
702 | struct sclk_cntl_t { | |
9b0e1c5d AM |
703 | u32 sclk_src_sel : 2; |
704 | u32 : 2; | |
705 | u32 sclk_post_div_fast : 4; | |
706 | u32 sclk_clkon_hys : 3; | |
707 | u32 sclk_post_div_slow : 4; | |
708 | u32 disp_cg_ok2switch_en : 1; | |
709 | u32 sclk_force_reg : 1; | |
710 | u32 sclk_force_disp : 1; | |
711 | u32 sclk_force_mc : 1; | |
712 | u32 sclk_force_extmc : 1; | |
713 | u32 sclk_force_cp : 1; | |
714 | u32 sclk_force_e2 : 1; | |
715 | u32 sclk_force_e3 : 1; | |
716 | u32 sclk_force_idct : 1; | |
717 | u32 sclk_force_bist : 1; | |
718 | u32 busy_extend_cp : 1; | |
719 | u32 busy_extend_e2 : 1; | |
720 | u32 busy_extend_e3 : 1; | |
721 | u32 busy_extend_idct : 1; | |
722 | u32 : 3; | |
1da177e4 LT |
723 | } __attribute__((packed)); |
724 | ||
725 | union sclk_cntl_u { | |
9b0e1c5d | 726 | u32 val : 32; |
aac51f09 | 727 | struct sclk_cntl_t f; |
1da177e4 LT |
728 | } __attribute__((packed)); |
729 | ||
730 | struct pclk_cntl_t { | |
9b0e1c5d AM |
731 | u32 pclk_src_sel : 2; |
732 | u32 : 2; | |
733 | u32 pclk_post_div : 4; | |
734 | u32 : 8; | |
735 | u32 pclk_force_disp : 1; | |
736 | u32 : 15; | |
1da177e4 LT |
737 | } __attribute__((packed)); |
738 | ||
739 | union pclk_cntl_u { | |
9b0e1c5d | 740 | u32 val : 32; |
aac51f09 | 741 | struct pclk_cntl_t f; |
1da177e4 LT |
742 | } __attribute__((packed)); |
743 | ||
aac51f09 RP |
744 | |
745 | #define TESTCLK_SRC_PLL 0x01 | |
746 | #define TESTCLK_SRC_SCLK 0x02 | |
747 | #define TESTCLK_SRC_PCLK 0x03 | |
748 | /* 4 and 5 seem to by XTAL/M */ | |
749 | #define TESTCLK_SRC_XTAL 0x06 | |
750 | ||
1da177e4 | 751 | struct clk_test_cntl_t { |
9b0e1c5d AM |
752 | u32 testclk_sel : 4; |
753 | u32 : 3; | |
754 | u32 start_check_freq : 1; | |
755 | u32 tstcount_rst : 1; | |
756 | u32 : 15; | |
757 | u32 test_count : 8; | |
1da177e4 LT |
758 | } __attribute__((packed)); |
759 | ||
760 | union clk_test_cntl_u { | |
9b0e1c5d | 761 | u32 val : 32; |
aac51f09 | 762 | struct clk_test_cntl_t f; |
1da177e4 LT |
763 | } __attribute__((packed)); |
764 | ||
765 | struct pwrmgt_cntl_t { | |
9b0e1c5d AM |
766 | u32 pwm_enable : 1; |
767 | u32 : 1; | |
768 | u32 pwm_mode_req : 2; | |
769 | u32 pwm_wakeup_cond : 2; | |
770 | u32 pwm_fast_noml_hw_en : 1; | |
771 | u32 pwm_noml_fast_hw_en : 1; | |
772 | u32 pwm_fast_noml_cond : 4; | |
773 | u32 pwm_noml_fast_cond : 4; | |
774 | u32 pwm_idle_timer : 8; | |
775 | u32 pwm_busy_timer : 8; | |
1da177e4 LT |
776 | } __attribute__((packed)); |
777 | ||
778 | union pwrmgt_cntl_u { | |
9b0e1c5d | 779 | u32 val : 32; |
aac51f09 | 780 | struct pwrmgt_cntl_t f; |
1da177e4 LT |
781 | } __attribute__((packed)); |
782 | ||
9b0e1c5d AM |
783 | #define SRC_DATATYPE_EQU_DST 3 |
784 | ||
785 | #define ROP3_SRCCOPY 0xcc | |
786 | #define ROP3_PATCOPY 0xf0 | |
787 | ||
788 | #define GMC_BRUSH_SOLID_COLOR 13 | |
789 | #define GMC_BRUSH_NONE 15 | |
790 | ||
791 | #define DP_SRC_MEM_RECTANGULAR 2 | |
792 | ||
793 | #define DP_OP_ROP 0 | |
794 | ||
795 | struct dp_gui_master_cntl_t { | |
796 | u32 gmc_src_pitch_offset_cntl : 1; | |
797 | u32 gmc_dst_pitch_offset_cntl : 1; | |
798 | u32 gmc_src_clipping : 1; | |
799 | u32 gmc_dst_clipping : 1; | |
800 | u32 gmc_brush_datatype : 4; | |
801 | u32 gmc_dst_datatype : 4; | |
802 | u32 gmc_src_datatype : 3; | |
803 | u32 gmc_byte_pix_order : 1; | |
804 | u32 gmc_default_sel : 1; | |
805 | u32 gmc_rop3 : 8; | |
806 | u32 gmc_dp_src_source : 3; | |
807 | u32 gmc_clr_cmp_fcn_dis : 1; | |
808 | u32 : 1; | |
809 | u32 gmc_wr_msk_dis : 1; | |
810 | u32 gmc_dp_op : 1; | |
811 | } __attribute__((packed)); | |
812 | ||
813 | union dp_gui_master_cntl_u { | |
814 | u32 val : 32; | |
815 | struct dp_gui_master_cntl_t f; | |
816 | } __attribute__((packed)); | |
817 | ||
818 | struct rbbm_status_t { | |
819 | u32 cmdfifo_avail : 7; | |
820 | u32 : 1; | |
821 | u32 hirq_on_rbb : 1; | |
822 | u32 cprq_on_rbb : 1; | |
823 | u32 cfrq_on_rbb : 1; | |
824 | u32 hirq_in_rtbuf : 1; | |
825 | u32 cprq_in_rtbuf : 1; | |
826 | u32 cfrq_in_rtbuf : 1; | |
827 | u32 cf_pipe_busy : 1; | |
828 | u32 eng_ev_busy : 1; | |
829 | u32 cp_cmdstrm_busy : 1; | |
830 | u32 e2_busy : 1; | |
831 | u32 rb2d_busy : 1; | |
832 | u32 rb3d_busy : 1; | |
833 | u32 se_busy : 1; | |
834 | u32 re_busy : 1; | |
835 | u32 tam_busy : 1; | |
836 | u32 tdm_busy : 1; | |
837 | u32 pb_busy : 1; | |
838 | u32 : 6; | |
839 | u32 gui_active : 1; | |
840 | } __attribute__((packed)); | |
841 | ||
842 | union rbbm_status_u { | |
843 | u32 val : 32; | |
844 | struct rbbm_status_t f; | |
845 | } __attribute__((packed)); | |
846 | ||
847 | struct dp_datatype_t { | |
848 | u32 dp_dst_datatype : 4; | |
849 | u32 : 4; | |
850 | u32 dp_brush_datatype : 4; | |
851 | u32 dp_src2_type : 1; | |
852 | u32 dp_src2_datatype : 3; | |
853 | u32 dp_src_datatype : 3; | |
854 | u32 : 11; | |
855 | u32 dp_byte_pix_order : 1; | |
856 | u32 : 1; | |
857 | } __attribute__((packed)); | |
858 | ||
859 | union dp_datatype_u { | |
860 | u32 val : 32; | |
861 | struct dp_datatype_t f; | |
862 | } __attribute__((packed)); | |
863 | ||
864 | struct dp_mix_t { | |
865 | u32 : 8; | |
866 | u32 dp_src_source : 3; | |
867 | u32 dp_src2_source : 3; | |
868 | u32 : 2; | |
869 | u32 dp_rop3 : 8; | |
870 | u32 dp_op : 1; | |
871 | u32 : 7; | |
872 | } __attribute__((packed)); | |
873 | ||
874 | union dp_mix_u { | |
875 | u32 val : 32; | |
876 | struct dp_mix_t f; | |
877 | } __attribute__((packed)); | |
878 | ||
879 | struct eng_cntl_t { | |
880 | u32 erc_reg_rd_ws : 1; | |
881 | u32 erc_reg_wr_ws : 1; | |
882 | u32 erc_idle_reg_wr : 1; | |
883 | u32 dis_engine_triggers : 1; | |
884 | u32 dis_rop_src_uses_dst_w_h : 1; | |
885 | u32 dis_src_uses_dst_dirmaj : 1; | |
886 | u32 : 6; | |
887 | u32 force_3dclk_when_2dclk : 1; | |
888 | u32 : 19; | |
889 | } __attribute__((packed)); | |
890 | ||
891 | union eng_cntl_u { | |
892 | u32 val : 32; | |
893 | struct eng_cntl_t f; | |
894 | } __attribute__((packed)); | |
895 | ||
896 | struct dp_cntl_t { | |
897 | u32 dst_x_dir : 1; | |
898 | u32 dst_y_dir : 1; | |
899 | u32 src_x_dir : 1; | |
900 | u32 src_y_dir : 1; | |
901 | u32 dst_major_x : 1; | |
902 | u32 src_major_x : 1; | |
903 | u32 : 26; | |
904 | } __attribute__((packed)); | |
905 | ||
906 | union dp_cntl_u { | |
907 | u32 val : 32; | |
908 | struct dp_cntl_t f; | |
909 | } __attribute__((packed)); | |
910 | ||
911 | struct dp_cntl_dst_dir_t { | |
912 | u32 : 15; | |
913 | u32 dst_y_dir : 1; | |
914 | u32 : 15; | |
915 | u32 dst_x_dir : 1; | |
916 | } __attribute__((packed)); | |
917 | ||
918 | union dp_cntl_dst_dir_u { | |
919 | u32 val : 32; | |
920 | struct dp_cntl_dst_dir_t f; | |
921 | } __attribute__((packed)); | |
922 | ||
1da177e4 LT |
923 | #endif |
924 |