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1 | /*-*- linux-c -*- |
2 | * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device | |
3 | * | |
4 | * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> | |
5 | * All Rights Reserved | |
6 | * | |
7 | * Contributors: | |
8 | * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets | |
9 | * and enabling the power-on state of | |
10 | * external VGA connectors for | |
11 | * secondary displays | |
12 | * | |
13 | * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of | |
14 | * the VESA GTF | |
15 | * | |
16 | * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized | |
17 | * timings support | |
18 | * | |
19 | * The code framework is a modification of vfb.c by Geert Uytterhoeven. | |
20 | * DotClock and PLL calculations are partly based on i810_driver.c | |
21 | * in xfree86 v4.0.3 by Precision Insight. | |
22 | * Watermark calculation and tables are based on i810_wmark.c | |
23 | * in xfre86 v4.0.3 by Precision Insight. Slight modifications | |
24 | * only to allow for integer operations instead of floating point. | |
25 | * | |
26 | * This file is subject to the terms and conditions of the GNU General Public | |
27 | * License. See the file COPYING in the main directory of this archive for | |
28 | * more details. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/config.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/mm.h> | |
37 | #include <linux/tty.h> | |
38 | #include <linux/slab.h> | |
39 | #include <linux/fb.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/pci_ids.h> | |
43 | #include <linux/resource.h> | |
44 | #include <linux/unistd.h> | |
45 | ||
46 | #include <asm/io.h> | |
47 | #include <asm/div64.h> | |
48 | ||
49 | #ifdef CONFIG_MTRR | |
50 | #include <asm/mtrr.h> | |
51 | #endif | |
52 | ||
53 | #include <asm/page.h> | |
54 | ||
55 | #include "i810_regs.h" | |
56 | #include "i810.h" | |
57 | #include "i810_main.h" | |
58 | ||
59 | /* PCI */ | |
60 | static const char *i810_pci_list[] __devinitdata = { | |
61 | "Intel(R) 810 Framebuffer Device" , | |
62 | "Intel(R) 810-DC100 Framebuffer Device" , | |
63 | "Intel(R) 810E Framebuffer Device" , | |
64 | "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" , | |
65 | "Intel(R) 815 (Internal Graphics only) Framebuffer Device" , | |
66 | "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device" | |
67 | }; | |
68 | ||
69 | static struct pci_device_id i810fb_pci_tbl[] = { | |
70 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1, | |
71 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
72 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, | |
73 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
74 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG, | |
75 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
76 | /* mvo: added i815 PCI-ID */ | |
77 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100, | |
78 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, | |
79 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP, | |
80 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
81 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, | |
82 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, | |
83 | { 0 }, | |
84 | }; | |
85 | ||
86 | static struct pci_driver i810fb_driver = { | |
87 | .name = "i810fb", | |
88 | .id_table = i810fb_pci_tbl, | |
89 | .probe = i810fb_init_pci, | |
90 | .remove = __exit_p(i810fb_remove_pci), | |
91 | .suspend = i810fb_suspend, | |
92 | .resume = i810fb_resume, | |
93 | }; | |
94 | ||
95 | static int vram __initdata = 4; | |
96 | static int bpp __initdata = 8; | |
97 | static int mtrr __initdata = 0; | |
98 | static int accel __initdata = 0; | |
99 | static int hsync1 __initdata = 0; | |
100 | static int hsync2 __initdata = 0; | |
101 | static int vsync1 __initdata = 0; | |
102 | static int vsync2 __initdata = 0; | |
103 | static int xres __initdata = 640; | |
104 | static int yres __initdata = 480; | |
105 | static int vyres __initdata = 0; | |
106 | static int sync __initdata = 0; | |
107 | static int ext_vga __initdata = 0; | |
108 | static int dcolor __initdata = 0; | |
109 | ||
110 | /*------------------------------------------------------------*/ | |
111 | ||
112 | /************************************************************** | |
113 | * Hardware Low Level Routines * | |
114 | **************************************************************/ | |
115 | ||
116 | /** | |
117 | * i810_screen_off - turns off/on display | |
118 | * @mmio: address of register space | |
119 | * @mode: on or off | |
120 | * | |
121 | * DESCRIPTION: | |
122 | * Blanks/unblanks the display | |
123 | */ | |
124 | static void i810_screen_off(u8 __iomem *mmio, u8 mode) | |
125 | { | |
126 | u32 count = WAIT_COUNT; | |
127 | u8 val; | |
128 | ||
129 | i810_writeb(SR_INDEX, mmio, SR01); | |
130 | val = i810_readb(SR_DATA, mmio); | |
131 | val = (mode == OFF) ? val | SCR_OFF : | |
132 | val & ~SCR_OFF; | |
133 | ||
134 | while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); | |
135 | i810_writeb(SR_INDEX, mmio, SR01); | |
136 | i810_writeb(SR_DATA, mmio, val); | |
137 | } | |
138 | ||
139 | /** | |
140 | * i810_dram_off - turns off/on dram refresh | |
141 | * @mmio: address of register space | |
142 | * @mode: on or off | |
143 | * | |
144 | * DESCRIPTION: | |
145 | * Turns off DRAM refresh. Must be off for only 2 vsyncs | |
146 | * before data becomes corrupt | |
147 | */ | |
148 | static void i810_dram_off(u8 __iomem *mmio, u8 mode) | |
149 | { | |
150 | u8 val; | |
151 | ||
152 | val = i810_readb(DRAMCH, mmio); | |
153 | val &= DRAM_OFF; | |
154 | val = (mode == OFF) ? val : val | DRAM_ON; | |
155 | i810_writeb(DRAMCH, mmio, val); | |
156 | } | |
157 | ||
158 | /** | |
159 | * i810_protect_regs - allows rw/ro mode of certain VGA registers | |
160 | * @mmio: address of register space | |
161 | * @mode: protect/unprotect | |
162 | * | |
163 | * DESCRIPTION: | |
164 | * The IBM VGA standard allows protection of certain VGA registers. | |
165 | * This will protect or unprotect them. | |
166 | */ | |
167 | static void i810_protect_regs(u8 __iomem *mmio, int mode) | |
168 | { | |
169 | u8 reg; | |
170 | ||
171 | i810_writeb(CR_INDEX_CGA, mmio, CR11); | |
172 | reg = i810_readb(CR_DATA_CGA, mmio); | |
173 | reg = (mode == OFF) ? reg & ~0x80 : | |
174 | reg | 0x80; | |
175 | ||
176 | i810_writeb(CR_INDEX_CGA, mmio, CR11); | |
177 | i810_writeb(CR_DATA_CGA, mmio, reg); | |
178 | } | |
179 | ||
180 | /** | |
181 | * i810_load_pll - loads values for the hardware PLL clock | |
182 | * @par: pointer to i810fb_par structure | |
183 | * | |
184 | * DESCRIPTION: | |
185 | * Loads the P, M, and N registers. | |
186 | */ | |
187 | static void i810_load_pll(struct i810fb_par *par) | |
188 | { | |
189 | u32 tmp1, tmp2; | |
190 | u8 __iomem *mmio = par->mmio_start_virtual; | |
191 | ||
192 | tmp1 = par->regs.M | par->regs.N << 16; | |
193 | tmp2 = i810_readl(DCLK_2D, mmio); | |
194 | tmp2 &= ~MN_MASK; | |
195 | i810_writel(DCLK_2D, mmio, tmp1 | tmp2); | |
196 | ||
197 | tmp1 = par->regs.P; | |
198 | tmp2 = i810_readl(DCLK_0DS, mmio); | |
199 | tmp2 &= ~(P_OR << 16); | |
200 | i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2); | |
201 | ||
202 | i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1); | |
203 | ||
204 | } | |
205 | ||
206 | /** | |
207 | * i810_load_vga - load standard VGA registers | |
208 | * @par: pointer to i810fb_par structure | |
209 | * | |
210 | * DESCRIPTION: | |
211 | * Load values to VGA registers | |
212 | */ | |
213 | static void i810_load_vga(struct i810fb_par *par) | |
214 | { | |
215 | u8 __iomem *mmio = par->mmio_start_virtual; | |
216 | ||
217 | /* interlace */ | |
218 | i810_writeb(CR_INDEX_CGA, mmio, CR70); | |
219 | i810_writeb(CR_DATA_CGA, mmio, par->interlace); | |
220 | ||
221 | i810_writeb(CR_INDEX_CGA, mmio, CR00); | |
222 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00); | |
223 | i810_writeb(CR_INDEX_CGA, mmio, CR01); | |
224 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01); | |
225 | i810_writeb(CR_INDEX_CGA, mmio, CR02); | |
226 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02); | |
227 | i810_writeb(CR_INDEX_CGA, mmio, CR03); | |
228 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03); | |
229 | i810_writeb(CR_INDEX_CGA, mmio, CR04); | |
230 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04); | |
231 | i810_writeb(CR_INDEX_CGA, mmio, CR05); | |
232 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05); | |
233 | i810_writeb(CR_INDEX_CGA, mmio, CR06); | |
234 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06); | |
235 | i810_writeb(CR_INDEX_CGA, mmio, CR09); | |
236 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09); | |
237 | i810_writeb(CR_INDEX_CGA, mmio, CR10); | |
238 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10); | |
239 | i810_writeb(CR_INDEX_CGA, mmio, CR11); | |
240 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11); | |
241 | i810_writeb(CR_INDEX_CGA, mmio, CR12); | |
242 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12); | |
243 | i810_writeb(CR_INDEX_CGA, mmio, CR15); | |
244 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15); | |
245 | i810_writeb(CR_INDEX_CGA, mmio, CR16); | |
246 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16); | |
247 | } | |
248 | ||
249 | /** | |
250 | * i810_load_vgax - load extended VGA registers | |
251 | * @par: pointer to i810fb_par structure | |
252 | * | |
253 | * DESCRIPTION: | |
254 | * Load values to extended VGA registers | |
255 | */ | |
256 | static void i810_load_vgax(struct i810fb_par *par) | |
257 | { | |
258 | u8 __iomem *mmio = par->mmio_start_virtual; | |
259 | ||
260 | i810_writeb(CR_INDEX_CGA, mmio, CR30); | |
261 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30); | |
262 | i810_writeb(CR_INDEX_CGA, mmio, CR31); | |
263 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31); | |
264 | i810_writeb(CR_INDEX_CGA, mmio, CR32); | |
265 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32); | |
266 | i810_writeb(CR_INDEX_CGA, mmio, CR33); | |
267 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33); | |
268 | i810_writeb(CR_INDEX_CGA, mmio, CR35); | |
269 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35); | |
270 | i810_writeb(CR_INDEX_CGA, mmio, CR39); | |
271 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39); | |
272 | } | |
273 | ||
274 | /** | |
275 | * i810_load_2d - load grahics registers | |
276 | * @par: pointer to i810fb_par structure | |
277 | * | |
278 | * DESCRIPTION: | |
279 | * Load values to graphics registers | |
280 | */ | |
281 | static void i810_load_2d(struct i810fb_par *par) | |
282 | { | |
283 | u32 tmp; | |
284 | u8 tmp8; | |
285 | u8 __iomem *mmio = par->mmio_start_virtual; | |
286 | ||
287 | i810_writel(FW_BLC, mmio, par->watermark); | |
288 | tmp = i810_readl(PIXCONF, mmio); | |
289 | tmp |= 1 | 1 << 20; | |
290 | i810_writel(PIXCONF, mmio, tmp); | |
291 | ||
292 | i810_writel(OVRACT, mmio, par->ovract); | |
293 | ||
294 | i810_writeb(GR_INDEX, mmio, GR10); | |
295 | tmp8 = i810_readb(GR_DATA, mmio); | |
296 | tmp8 |= 2; | |
297 | i810_writeb(GR_INDEX, mmio, GR10); | |
298 | i810_writeb(GR_DATA, mmio, tmp8); | |
299 | } | |
300 | ||
301 | /** | |
302 | * i810_hires - enables high resolution mode | |
303 | * @mmio: address of register space | |
304 | */ | |
305 | static void i810_hires(u8 __iomem *mmio) | |
306 | { | |
307 | u8 val; | |
308 | ||
309 | i810_writeb(CR_INDEX_CGA, mmio, CR80); | |
310 | val = i810_readb(CR_DATA_CGA, mmio); | |
311 | i810_writeb(CR_INDEX_CGA, mmio, CR80); | |
312 | i810_writeb(CR_DATA_CGA, mmio, val | 1); | |
313 | } | |
314 | ||
315 | /** | |
316 | * i810_load_pitch - loads the characters per line of the display | |
317 | * @par: pointer to i810fb_par structure | |
318 | * | |
319 | * DESCRIPTION: | |
320 | * Loads the characters per line | |
321 | */ | |
322 | static void i810_load_pitch(struct i810fb_par *par) | |
323 | { | |
324 | u32 tmp, pitch; | |
325 | u8 val; | |
326 | u8 __iomem *mmio = par->mmio_start_virtual; | |
327 | ||
328 | pitch = par->pitch >> 3; | |
329 | i810_writeb(SR_INDEX, mmio, SR01); | |
330 | val = i810_readb(SR_DATA, mmio); | |
331 | val &= 0xE0; | |
332 | val |= 1 | 1 << 2; | |
333 | i810_writeb(SR_INDEX, mmio, SR01); | |
334 | i810_writeb(SR_DATA, mmio, val); | |
335 | ||
336 | tmp = pitch & 0xFF; | |
337 | i810_writeb(CR_INDEX_CGA, mmio, CR13); | |
338 | i810_writeb(CR_DATA_CGA, mmio, (u8) tmp); | |
339 | ||
340 | tmp = pitch >> 8; | |
341 | i810_writeb(CR_INDEX_CGA, mmio, CR41); | |
342 | val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F; | |
343 | i810_writeb(CR_INDEX_CGA, mmio, CR41); | |
344 | i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val); | |
345 | } | |
346 | ||
347 | /** | |
348 | * i810_load_color - loads the color depth of the display | |
349 | * @par: pointer to i810fb_par structure | |
350 | * | |
351 | * DESCRIPTION: | |
352 | * Loads the color depth of the display and the graphics engine | |
353 | */ | |
354 | static void i810_load_color(struct i810fb_par *par) | |
355 | { | |
356 | u8 __iomem *mmio = par->mmio_start_virtual; | |
357 | u32 reg1; | |
358 | u16 reg2; | |
359 | ||
360 | reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27); | |
361 | reg2 = i810_readw(BLTCNTL, mmio) & ~0x30; | |
362 | ||
363 | reg1 |= 0x8000 | par->pixconf; | |
364 | reg2 |= par->bltcntl; | |
365 | i810_writel(PIXCONF, mmio, reg1); | |
366 | i810_writew(BLTCNTL, mmio, reg2); | |
367 | } | |
368 | ||
369 | /** | |
370 | * i810_load_regs - loads all registers for the mode | |
371 | * @par: pointer to i810fb_par structure | |
372 | * | |
373 | * DESCRIPTION: | |
374 | * Loads registers | |
375 | */ | |
376 | static void i810_load_regs(struct i810fb_par *par) | |
377 | { | |
378 | u8 __iomem *mmio = par->mmio_start_virtual; | |
379 | ||
380 | i810_screen_off(mmio, OFF); | |
381 | i810_protect_regs(mmio, OFF); | |
382 | i810_dram_off(mmio, OFF); | |
383 | i810_load_pll(par); | |
384 | i810_load_vga(par); | |
385 | i810_load_vgax(par); | |
386 | i810_dram_off(mmio, ON); | |
387 | i810_load_2d(par); | |
388 | i810_hires(mmio); | |
389 | i810_screen_off(mmio, ON); | |
390 | i810_protect_regs(mmio, ON); | |
391 | i810_load_color(par); | |
392 | i810_load_pitch(par); | |
393 | } | |
394 | ||
395 | static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue, | |
396 | u8 __iomem *mmio) | |
397 | { | |
398 | i810_writeb(CLUT_INDEX_WRITE, mmio, regno); | |
399 | i810_writeb(CLUT_DATA, mmio, red); | |
400 | i810_writeb(CLUT_DATA, mmio, green); | |
401 | i810_writeb(CLUT_DATA, mmio, blue); | |
402 | } | |
403 | ||
404 | static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue, | |
405 | u8 __iomem *mmio) | |
406 | { | |
407 | i810_writeb(CLUT_INDEX_READ, mmio, regno); | |
408 | *red = i810_readb(CLUT_DATA, mmio); | |
409 | *green = i810_readb(CLUT_DATA, mmio); | |
410 | *blue = i810_readb(CLUT_DATA, mmio); | |
411 | } | |
412 | ||
413 | /************************************************************ | |
414 | * VGA State Restore * | |
415 | ************************************************************/ | |
416 | static void i810_restore_pll(struct i810fb_par *par) | |
417 | { | |
418 | u32 tmp1, tmp2; | |
419 | u8 __iomem *mmio = par->mmio_start_virtual; | |
420 | ||
421 | tmp1 = par->hw_state.dclk_2d; | |
422 | tmp2 = i810_readl(DCLK_2D, mmio); | |
423 | tmp1 &= ~MN_MASK; | |
424 | tmp2 &= MN_MASK; | |
425 | i810_writel(DCLK_2D, mmio, tmp1 | tmp2); | |
426 | ||
427 | tmp1 = par->hw_state.dclk_1d; | |
428 | tmp2 = i810_readl(DCLK_1D, mmio); | |
429 | tmp1 &= ~MN_MASK; | |
430 | tmp2 &= MN_MASK; | |
431 | i810_writel(DCLK_1D, mmio, tmp1 | tmp2); | |
432 | ||
433 | i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds); | |
434 | } | |
435 | ||
436 | static void i810_restore_dac(struct i810fb_par *par) | |
437 | { | |
438 | u32 tmp1, tmp2; | |
439 | u8 __iomem *mmio = par->mmio_start_virtual; | |
440 | ||
441 | tmp1 = par->hw_state.pixconf; | |
442 | tmp2 = i810_readl(PIXCONF, mmio); | |
443 | tmp1 &= DAC_BIT; | |
444 | tmp2 &= ~DAC_BIT; | |
445 | i810_writel(PIXCONF, mmio, tmp1 | tmp2); | |
446 | } | |
447 | ||
448 | static void i810_restore_vgax(struct i810fb_par *par) | |
449 | { | |
450 | u8 i, j; | |
451 | u8 __iomem *mmio = par->mmio_start_virtual; | |
452 | ||
453 | for (i = 0; i < 4; i++) { | |
454 | i810_writeb(CR_INDEX_CGA, mmio, CR30+i); | |
455 | i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i)); | |
456 | } | |
457 | i810_writeb(CR_INDEX_CGA, mmio, CR35); | |
458 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35); | |
459 | i810_writeb(CR_INDEX_CGA, mmio, CR39); | |
460 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); | |
461 | i810_writeb(CR_INDEX_CGA, mmio, CR41); | |
462 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); | |
463 | ||
464 | /*restore interlace*/ | |
465 | i810_writeb(CR_INDEX_CGA, mmio, CR70); | |
466 | i = par->hw_state.cr70; | |
467 | i &= INTERLACE_BIT; | |
468 | j = i810_readb(CR_DATA_CGA, mmio); | |
469 | i810_writeb(CR_INDEX_CGA, mmio, CR70); | |
470 | i810_writeb(CR_DATA_CGA, mmio, j | i); | |
471 | ||
472 | i810_writeb(CR_INDEX_CGA, mmio, CR80); | |
473 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80); | |
474 | i810_writeb(MSR_WRITE, mmio, par->hw_state.msr); | |
475 | i810_writeb(SR_INDEX, mmio, SR01); | |
476 | i = (par->hw_state.sr01) & ~0xE0 ; | |
477 | j = i810_readb(SR_DATA, mmio) & 0xE0; | |
478 | i810_writeb(SR_INDEX, mmio, SR01); | |
479 | i810_writeb(SR_DATA, mmio, i | j); | |
480 | } | |
481 | ||
482 | static void i810_restore_vga(struct i810fb_par *par) | |
483 | { | |
484 | u8 i; | |
485 | u8 __iomem *mmio = par->mmio_start_virtual; | |
486 | ||
487 | for (i = 0; i < 10; i++) { | |
488 | i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); | |
489 | i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i)); | |
490 | } | |
491 | for (i = 0; i < 8; i++) { | |
492 | i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); | |
493 | i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i)); | |
494 | } | |
495 | } | |
496 | ||
497 | static void i810_restore_addr_map(struct i810fb_par *par) | |
498 | { | |
499 | u8 tmp; | |
500 | u8 __iomem *mmio = par->mmio_start_virtual; | |
501 | ||
502 | i810_writeb(GR_INDEX, mmio, GR10); | |
503 | tmp = i810_readb(GR_DATA, mmio); | |
504 | tmp &= ADDR_MAP_MASK; | |
505 | tmp |= par->hw_state.gr10; | |
506 | i810_writeb(GR_INDEX, mmio, GR10); | |
507 | i810_writeb(GR_DATA, mmio, tmp); | |
508 | } | |
509 | ||
510 | static void i810_restore_2d(struct i810fb_par *par) | |
511 | { | |
512 | u32 tmp_long; | |
513 | u16 tmp_word; | |
514 | u8 __iomem *mmio = par->mmio_start_virtual; | |
515 | ||
516 | tmp_word = i810_readw(BLTCNTL, mmio); | |
517 | tmp_word &= ~(3 << 4); | |
518 | tmp_word |= par->hw_state.bltcntl; | |
519 | i810_writew(BLTCNTL, mmio, tmp_word); | |
520 | ||
521 | i810_dram_off(mmio, OFF); | |
522 | i810_writel(PIXCONF, mmio, par->hw_state.pixconf); | |
523 | i810_dram_off(mmio, ON); | |
524 | ||
525 | tmp_word = i810_readw(HWSTAM, mmio); | |
526 | tmp_word &= 3 << 13; | |
527 | tmp_word |= par->hw_state.hwstam; | |
528 | i810_writew(HWSTAM, mmio, tmp_word); | |
529 | ||
530 | tmp_long = i810_readl(FW_BLC, mmio); | |
531 | tmp_long &= FW_BLC_MASK; | |
532 | tmp_long |= par->hw_state.fw_blc; | |
533 | i810_writel(FW_BLC, mmio, tmp_long); | |
534 | ||
535 | i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga); | |
536 | i810_writew(IER, mmio, par->hw_state.ier); | |
537 | i810_writew(IMR, mmio, par->hw_state.imr); | |
538 | i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas); | |
539 | } | |
540 | ||
541 | static void i810_restore_vga_state(struct i810fb_par *par) | |
542 | { | |
543 | u8 __iomem *mmio = par->mmio_start_virtual; | |
544 | ||
545 | i810_screen_off(mmio, OFF); | |
546 | i810_protect_regs(mmio, OFF); | |
547 | i810_dram_off(mmio, OFF); | |
548 | i810_restore_pll(par); | |
549 | i810_restore_dac(par); | |
550 | i810_restore_vga(par); | |
551 | i810_restore_vgax(par); | |
552 | i810_restore_addr_map(par); | |
553 | i810_dram_off(mmio, ON); | |
554 | i810_restore_2d(par); | |
555 | i810_screen_off(mmio, ON); | |
556 | i810_protect_regs(mmio, ON); | |
557 | } | |
558 | ||
559 | /*********************************************************************** | |
560 | * VGA State Save * | |
561 | ***********************************************************************/ | |
562 | ||
563 | static void i810_save_vgax(struct i810fb_par *par) | |
564 | { | |
565 | u8 i; | |
566 | u8 __iomem *mmio = par->mmio_start_virtual; | |
567 | ||
568 | for (i = 0; i < 4; i++) { | |
569 | i810_writeb(CR_INDEX_CGA, mmio, CR30 + i); | |
570 | *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio); | |
571 | } | |
572 | i810_writeb(CR_INDEX_CGA, mmio, CR35); | |
573 | par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio); | |
574 | i810_writeb(CR_INDEX_CGA, mmio, CR39); | |
575 | par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio); | |
576 | i810_writeb(CR_INDEX_CGA, mmio, CR41); | |
577 | par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio); | |
578 | i810_writeb(CR_INDEX_CGA, mmio, CR70); | |
579 | par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio); | |
580 | par->hw_state.msr = i810_readb(MSR_READ, mmio); | |
581 | i810_writeb(CR_INDEX_CGA, mmio, CR80); | |
582 | par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio); | |
583 | i810_writeb(SR_INDEX, mmio, SR01); | |
584 | par->hw_state.sr01 = i810_readb(SR_DATA, mmio); | |
585 | } | |
586 | ||
587 | static void i810_save_vga(struct i810fb_par *par) | |
588 | { | |
589 | u8 i; | |
590 | u8 __iomem *mmio = par->mmio_start_virtual; | |
591 | ||
592 | for (i = 0; i < 10; i++) { | |
593 | i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); | |
594 | *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio); | |
595 | } | |
596 | for (i = 0; i < 8; i++) { | |
597 | i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); | |
598 | *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio); | |
599 | } | |
600 | } | |
601 | ||
602 | static void i810_save_2d(struct i810fb_par *par) | |
603 | { | |
604 | u8 __iomem *mmio = par->mmio_start_virtual; | |
605 | ||
606 | par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio); | |
607 | par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio); | |
608 | par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio); | |
609 | par->hw_state.pixconf = i810_readl(PIXCONF, mmio); | |
610 | par->hw_state.fw_blc = i810_readl(FW_BLC, mmio); | |
611 | par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio); | |
612 | par->hw_state.hwstam = i810_readw(HWSTAM, mmio); | |
613 | par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio); | |
614 | par->hw_state.ier = i810_readw(IER, mmio); | |
615 | par->hw_state.imr = i810_readw(IMR, mmio); | |
616 | par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio); | |
617 | } | |
618 | ||
619 | static void i810_save_vga_state(struct i810fb_par *par) | |
620 | { | |
621 | i810_save_vga(par); | |
622 | i810_save_vgax(par); | |
623 | i810_save_2d(par); | |
624 | } | |
625 | ||
626 | /************************************************************ | |
627 | * Helpers * | |
628 | ************************************************************/ | |
629 | /** | |
630 | * get_line_length - calculates buffer pitch in bytes | |
631 | * @par: pointer to i810fb_par structure | |
632 | * @xres_virtual: virtual resolution of the frame | |
633 | * @bpp: bits per pixel | |
634 | * | |
635 | * DESCRIPTION: | |
636 | * Calculates buffer pitch in bytes. | |
637 | */ | |
638 | static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp) | |
639 | { | |
640 | u32 length; | |
641 | ||
642 | length = xres_virtual*bpp; | |
643 | length = (length+31)&-32; | |
644 | length >>= 3; | |
645 | return length; | |
646 | } | |
647 | ||
648 | /** | |
649 | * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value | |
650 | * @freq: target pixelclock in picoseconds | |
651 | * @m: where to write M register | |
652 | * @n: where to write N register | |
653 | * @p: where to write P register | |
654 | * | |
655 | * DESCRIPTION: | |
656 | * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P) | |
657 | * Repeatedly computes the Freq until the actual Freq is equal to | |
658 | * the target Freq or until the loop count is zero. In the latter | |
659 | * case, the actual frequency nearest the target will be used. | |
660 | */ | |
661 | static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p) | |
662 | { | |
663 | u32 m_reg, n_reg, p_divisor, n_target_max; | |
664 | u32 m_target, n_target, p_target, n_best, m_best, mod; | |
665 | u32 f_out, target_freq, diff = 0, mod_min, diff_min; | |
666 | ||
667 | diff_min = mod_min = 0xFFFFFFFF; | |
668 | n_best = m_best = m_target = f_out = 0; | |
669 | ||
670 | target_freq = freq; | |
671 | n_target_max = 30; | |
672 | ||
673 | /* | |
674 | * find P such that target freq is 16x reference freq (Hz). | |
675 | */ | |
676 | p_divisor = 1; | |
677 | p_target = 0; | |
678 | while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) && | |
679 | p_divisor <= 32) { | |
680 | p_divisor <<= 1; | |
681 | p_target++; | |
682 | } | |
683 | ||
684 | n_reg = m_reg = n_target = 3; | |
685 | while (diff_min && mod_min && (n_target < n_target_max)) { | |
686 | f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg); | |
687 | mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg); | |
688 | m_target = m_reg; | |
689 | n_target = n_reg; | |
690 | if (f_out <= target_freq) { | |
691 | n_reg++; | |
692 | diff = target_freq - f_out; | |
693 | } else { | |
694 | m_reg++; | |
695 | diff = f_out - target_freq; | |
696 | } | |
697 | ||
698 | if (diff_min > diff) { | |
699 | diff_min = diff; | |
700 | n_best = n_target; | |
701 | m_best = m_target; | |
702 | } | |
703 | ||
704 | if (!diff && mod_min > mod) { | |
705 | mod_min = mod; | |
706 | n_best = n_target; | |
707 | m_best = m_target; | |
708 | } | |
709 | } | |
710 | if (m) *m = (m_best - 2) & 0x3FF; | |
711 | if (n) *n = (n_best - 2) & 0x3FF; | |
712 | if (p) *p = (p_target << 4); | |
713 | } | |
714 | ||
715 | /************************************************************* | |
716 | * Hardware Cursor Routines * | |
717 | *************************************************************/ | |
718 | ||
719 | /** | |
720 | * i810_enable_cursor - show or hide the hardware cursor | |
721 | * @mmio: address of register space | |
722 | * @mode: show (1) or hide (0) | |
723 | * | |
724 | * Description: | |
725 | * Shows or hides the hardware cursor | |
726 | */ | |
727 | static void i810_enable_cursor(u8 __iomem *mmio, int mode) | |
728 | { | |
729 | u32 temp; | |
730 | ||
731 | temp = i810_readl(PIXCONF, mmio); | |
732 | temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK : | |
733 | temp & ~CURSOR_ENABLE_MASK; | |
734 | ||
735 | i810_writel(PIXCONF, mmio, temp); | |
736 | } | |
737 | ||
738 | static void i810_reset_cursor_image(struct i810fb_par *par) | |
739 | { | |
740 | u8 __iomem *addr = par->cursor_heap.virtual; | |
741 | int i, j; | |
742 | ||
743 | for (i = 64; i--; ) { | |
744 | for (j = 0; j < 8; j++) { | |
745 | i810_writeb(j, addr, 0xff); | |
746 | i810_writeb(j+8, addr, 0x00); | |
747 | } | |
748 | addr +=16; | |
749 | } | |
750 | } | |
751 | ||
752 | static void i810_load_cursor_image(int width, int height, u8 *data, | |
753 | struct i810fb_par *par) | |
754 | { | |
755 | u8 __iomem *addr = par->cursor_heap.virtual; | |
756 | int i, j, w = width/8; | |
757 | int mod = width % 8, t_mask, d_mask; | |
758 | ||
759 | t_mask = 0xff >> mod; | |
760 | d_mask = ~(0xff >> mod); | |
761 | for (i = height; i--; ) { | |
762 | for (j = 0; j < w; j++) { | |
763 | i810_writeb(j+0, addr, 0x00); | |
764 | i810_writeb(j+8, addr, *data++); | |
765 | } | |
766 | if (mod) { | |
767 | i810_writeb(j+0, addr, t_mask); | |
768 | i810_writeb(j+8, addr, *data++ & d_mask); | |
769 | } | |
770 | addr += 16; | |
771 | } | |
772 | } | |
773 | ||
774 | static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info) | |
775 | { | |
776 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
777 | u8 __iomem *mmio = par->mmio_start_virtual; | |
778 | u8 red, green, blue, trans, temp; | |
779 | ||
780 | i810fb_getcolreg(bg, &red, &green, &blue, &trans, info); | |
781 | ||
782 | temp = i810_readb(PIXCONF1, mmio); | |
783 | i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); | |
784 | ||
785 | i810_write_dac(4, red, green, blue, mmio); | |
786 | ||
787 | i810_writeb(PIXCONF1, mmio, temp); | |
788 | ||
789 | i810fb_getcolreg(fg, &red, &green, &blue, &trans, info); | |
790 | temp = i810_readb(PIXCONF1, mmio); | |
791 | i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); | |
792 | ||
793 | i810_write_dac(5, red, green, blue, mmio); | |
794 | ||
795 | i810_writeb(PIXCONF1, mmio, temp); | |
796 | } | |
797 | ||
798 | /** | |
799 | * i810_init_cursor - initializes the cursor | |
800 | * @par: pointer to i810fb_par structure | |
801 | * | |
802 | * DESCRIPTION: | |
803 | * Initializes the cursor registers | |
804 | */ | |
805 | static void i810_init_cursor(struct i810fb_par *par) | |
806 | { | |
807 | u8 __iomem *mmio = par->mmio_start_virtual; | |
808 | ||
809 | i810_enable_cursor(mmio, OFF); | |
810 | i810_writel(CURBASE, mmio, par->cursor_heap.physical); | |
811 | i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR); | |
812 | } | |
813 | ||
814 | /********************************************************************* | |
815 | * Framebuffer hook helpers * | |
816 | *********************************************************************/ | |
817 | /** | |
818 | * i810_round_off - Round off values to capability of hardware | |
819 | * @var: pointer to fb_var_screeninfo structure | |
820 | * | |
821 | * DESCRIPTION: | |
822 | * @var contains user-defined information for the mode to be set. | |
823 | * This will try modify those values to ones nearest the | |
824 | * capability of the hardware | |
825 | */ | |
826 | static void i810_round_off(struct fb_var_screeninfo *var) | |
827 | { | |
828 | u32 xres, yres, vxres, vyres; | |
829 | ||
830 | /* | |
831 | * Presently supports only these configurations | |
832 | */ | |
833 | ||
834 | xres = var->xres; | |
835 | yres = var->yres; | |
836 | vxres = var->xres_virtual; | |
837 | vyres = var->yres_virtual; | |
838 | ||
839 | var->bits_per_pixel += 7; | |
840 | var->bits_per_pixel &= ~7; | |
841 | ||
842 | if (var->bits_per_pixel < 8) | |
843 | var->bits_per_pixel = 8; | |
844 | if (var->bits_per_pixel > 32) | |
845 | var->bits_per_pixel = 32; | |
846 | ||
847 | round_off_xres(&xres); | |
848 | if (xres < 40) | |
849 | xres = 40; | |
850 | if (xres > 2048) | |
851 | xres = 2048; | |
852 | xres = (xres + 7) & ~7; | |
853 | ||
854 | if (vxres < xres) | |
855 | vxres = xres; | |
856 | ||
857 | round_off_yres(&xres, &yres); | |
858 | if (yres < 1) | |
859 | yres = 1; | |
860 | if (yres >= 2048) | |
861 | yres = 2048; | |
862 | ||
863 | if (vyres < yres) | |
864 | vyres = yres; | |
865 | ||
866 | if (var->bits_per_pixel == 32) | |
867 | var->accel_flags = 0; | |
868 | ||
869 | /* round of horizontal timings to nearest 8 pixels */ | |
870 | var->left_margin = (var->left_margin + 4) & ~7; | |
871 | var->right_margin = (var->right_margin + 4) & ~7; | |
872 | var->hsync_len = (var->hsync_len + 4) & ~7; | |
873 | ||
874 | if (var->vmode & FB_VMODE_INTERLACED) { | |
875 | if (!((yres + var->upper_margin + var->vsync_len + | |
876 | var->lower_margin) & 1)) | |
877 | var->upper_margin++; | |
878 | } | |
879 | ||
880 | var->xres = xres; | |
881 | var->yres = yres; | |
882 | var->xres_virtual = vxres; | |
883 | var->yres_virtual = vyres; | |
884 | } | |
885 | ||
886 | /** | |
887 | * set_color_bitfields - sets rgba fields | |
888 | * @var: pointer to fb_var_screeninfo | |
889 | * | |
890 | * DESCRIPTION: | |
891 | * The length, offset and ordering for each color field | |
892 | * (red, green, blue) will be set as specified | |
893 | * by the hardware | |
894 | */ | |
895 | static void set_color_bitfields(struct fb_var_screeninfo *var) | |
896 | { | |
897 | switch (var->bits_per_pixel) { | |
898 | case 8: | |
899 | var->red.offset = 0; | |
900 | var->red.length = 8; | |
901 | var->green.offset = 0; | |
902 | var->green.length = 8; | |
903 | var->blue.offset = 0; | |
904 | var->blue.length = 8; | |
905 | var->transp.offset = 0; | |
906 | var->transp.length = 0; | |
907 | break; | |
908 | case 16: | |
909 | var->green.length = (var->green.length == 5) ? 5 : 6; | |
910 | var->red.length = 5; | |
911 | var->blue.length = 5; | |
912 | var->transp.length = 6 - var->green.length; | |
913 | var->blue.offset = 0; | |
914 | var->green.offset = 5; | |
915 | var->red.offset = 5 + var->green.length; | |
916 | var->transp.offset = (5 + var->red.offset) & 15; | |
917 | break; | |
918 | case 24: /* RGB 888 */ | |
919 | case 32: /* RGBA 8888 */ | |
920 | var->red.offset = 16; | |
921 | var->red.length = 8; | |
922 | var->green.offset = 8; | |
923 | var->green.length = 8; | |
924 | var->blue.offset = 0; | |
925 | var->blue.length = 8; | |
926 | var->transp.length = var->bits_per_pixel - 24; | |
927 | var->transp.offset = (var->transp.length) ? 24 : 0; | |
928 | break; | |
929 | } | |
930 | var->red.msb_right = 0; | |
931 | var->green.msb_right = 0; | |
932 | var->blue.msb_right = 0; | |
933 | var->transp.msb_right = 0; | |
934 | } | |
935 | ||
936 | /** | |
937 | * i810_check_params - check if contents in var are valid | |
938 | * @var: pointer to fb_var_screeninfo | |
939 | * @info: pointer to fb_info | |
940 | * | |
941 | * DESCRIPTION: | |
942 | * This will check if the framebuffer size is sufficient | |
943 | * for the current mode and if the user's monitor has the | |
944 | * required specifications to display the current mode. | |
945 | */ | |
946 | static int i810_check_params(struct fb_var_screeninfo *var, | |
947 | struct fb_info *info) | |
948 | { | |
949 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
950 | int line_length, vidmem; | |
951 | u32 xres, yres, vxres, vyres; | |
952 | ||
953 | xres = var->xres; | |
954 | yres = var->yres; | |
955 | vxres = var->xres_virtual; | |
956 | vyres = var->yres_virtual; | |
957 | ||
958 | /* | |
959 | * Memory limit | |
960 | */ | |
961 | line_length = get_line_length(par, vxres, | |
962 | var->bits_per_pixel); | |
963 | ||
964 | vidmem = line_length*vyres; | |
965 | if (vidmem > par->fb.size) { | |
966 | vyres = par->fb.size/line_length; | |
967 | if (vyres < yres) { | |
968 | vyres = yres; | |
969 | vxres = par->fb.size/vyres; | |
970 | vxres /= var->bits_per_pixel >> 3; | |
971 | line_length = get_line_length(par, vxres, | |
972 | var->bits_per_pixel); | |
973 | vidmem = line_length * yres; | |
974 | if (vxres < xres) { | |
975 | printk("i810fb: required video memory, " | |
976 | "%d bytes, for %dx%d-%d (virtual) " | |
977 | "is out of range\n", | |
978 | vidmem, vxres, vyres, | |
979 | var->bits_per_pixel); | |
980 | return -ENOMEM; | |
981 | } | |
982 | } | |
983 | } | |
984 | /* | |
985 | * Monitor limit | |
986 | */ | |
987 | switch (var->bits_per_pixel) { | |
988 | case 8: | |
989 | info->monspecs.dclkmax = 234000000; | |
990 | break; | |
991 | case 16: | |
992 | info->monspecs.dclkmax = 229000000; | |
993 | break; | |
994 | case 24: | |
995 | case 32: | |
996 | info->monspecs.dclkmax = 204000000; | |
997 | break; | |
998 | } | |
999 | info->monspecs.dclkmin = 15000000; | |
1000 | ||
1001 | if (fb_validate_mode(var, info)) { | |
1002 | if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
1006 | var->xres = xres; | |
1007 | var->yres = yres; | |
1008 | var->xres_virtual = vxres; | |
1009 | var->yres_virtual = vyres; | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | /** | |
1014 | * encode_fix - fill up fb_fix_screeninfo structure | |
1015 | * @fix: pointer to fb_fix_screeninfo | |
1016 | * @info: pointer to fb_info | |
1017 | * | |
1018 | * DESCRIPTION: | |
1019 | * This will set up parameters that are unmodifiable by the user. | |
1020 | */ | |
1021 | static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info) | |
1022 | { | |
1023 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1024 | ||
1025 | memset(fix, 0, sizeof(struct fb_fix_screeninfo)); | |
1026 | ||
1027 | strcpy(fix->id, "I810"); | |
1028 | fix->smem_start = par->fb.physical; | |
1029 | fix->smem_len = par->fb.size; | |
1030 | fix->type = FB_TYPE_PACKED_PIXELS; | |
1031 | fix->type_aux = 0; | |
1032 | fix->xpanstep = 8; | |
1033 | fix->ypanstep = 1; | |
1034 | ||
1035 | switch (info->var.bits_per_pixel) { | |
1036 | case 8: | |
1037 | fix->visual = FB_VISUAL_PSEUDOCOLOR; | |
1038 | break; | |
1039 | case 16: | |
1040 | case 24: | |
1041 | case 32: | |
1042 | if (info->var.nonstd) | |
1043 | fix->visual = FB_VISUAL_DIRECTCOLOR; | |
1044 | else | |
1045 | fix->visual = FB_VISUAL_TRUECOLOR; | |
1046 | break; | |
1047 | default: | |
1048 | return -EINVAL; | |
1049 | } | |
1050 | fix->ywrapstep = 0; | |
1051 | fix->line_length = par->pitch; | |
1052 | fix->mmio_start = par->mmio_start_phys; | |
1053 | fix->mmio_len = MMIO_SIZE; | |
1054 | fix->accel = FB_ACCEL_I810; | |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * decode_var - modify par according to contents of var | |
1061 | * @var: pointer to fb_var_screeninfo | |
1062 | * @par: pointer to i810fb_par | |
1063 | * | |
1064 | * DESCRIPTION: | |
1065 | * Based on the contents of @var, @par will be dynamically filled up. | |
1066 | * @par contains all information necessary to modify the hardware. | |
1067 | */ | |
1068 | static void decode_var(const struct fb_var_screeninfo *var, | |
1069 | struct i810fb_par *par) | |
1070 | { | |
1071 | u32 xres, yres, vxres, vyres; | |
1072 | ||
1073 | xres = var->xres; | |
1074 | yres = var->yres; | |
1075 | vxres = var->xres_virtual; | |
1076 | vyres = var->yres_virtual; | |
1077 | ||
1078 | switch (var->bits_per_pixel) { | |
1079 | case 8: | |
1080 | par->pixconf = PIXCONF8; | |
1081 | par->bltcntl = 0; | |
1082 | par->depth = 1; | |
1083 | par->blit_bpp = BPP8; | |
1084 | break; | |
1085 | case 16: | |
1086 | if (var->green.length == 5) | |
1087 | par->pixconf = PIXCONF15; | |
1088 | else | |
1089 | par->pixconf = PIXCONF16; | |
1090 | par->bltcntl = 16; | |
1091 | par->depth = 2; | |
1092 | par->blit_bpp = BPP16; | |
1093 | break; | |
1094 | case 24: | |
1095 | par->pixconf = PIXCONF24; | |
1096 | par->bltcntl = 32; | |
1097 | par->depth = 3; | |
1098 | par->blit_bpp = BPP24; | |
1099 | break; | |
1100 | case 32: | |
1101 | par->pixconf = PIXCONF32; | |
1102 | par->bltcntl = 0; | |
1103 | par->depth = 4; | |
1104 | par->blit_bpp = 3 << 24; | |
1105 | break; | |
1106 | } | |
1107 | if (var->nonstd && var->bits_per_pixel != 8) | |
1108 | par->pixconf |= 1 << 27; | |
1109 | ||
1110 | i810_calc_dclk(var->pixclock, &par->regs.M, | |
1111 | &par->regs.N, &par->regs.P); | |
1112 | i810fb_encode_registers(var, par, xres, yres); | |
1113 | ||
1114 | par->watermark = i810_get_watermark(var, par); | |
1115 | par->pitch = get_line_length(par, vxres, var->bits_per_pixel); | |
1116 | } | |
1117 | ||
1118 | /** | |
1119 | * i810fb_getcolreg - gets red, green and blue values of the hardware DAC | |
1120 | * @regno: DAC index | |
1121 | * @red: red | |
1122 | * @green: green | |
1123 | * @blue: blue | |
1124 | * @transp: transparency (alpha) | |
1125 | * @info: pointer to fb_info | |
1126 | * | |
1127 | * DESCRIPTION: | |
1128 | * Gets the red, green and blue values of the hardware DAC as pointed by @regno | |
1129 | * and writes them to @red, @green and @blue respectively | |
1130 | */ | |
1131 | static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue, | |
1132 | u8 *transp, struct fb_info *info) | |
1133 | { | |
1134 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1135 | u8 __iomem *mmio = par->mmio_start_virtual; | |
1136 | u8 temp; | |
1137 | ||
1138 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
1139 | if ((info->var.green.length == 5 && regno > 31) || | |
1140 | (info->var.green.length == 6 && regno > 63)) | |
1141 | return 1; | |
1142 | } | |
1143 | ||
1144 | temp = i810_readb(PIXCONF1, mmio); | |
1145 | i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); | |
1146 | ||
1147 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && | |
1148 | info->var.green.length == 5) | |
1149 | i810_read_dac(regno * 8, red, green, blue, mmio); | |
1150 | ||
1151 | else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && | |
1152 | info->var.green.length == 6) { | |
1153 | u8 tmp; | |
1154 | ||
1155 | i810_read_dac(regno * 8, red, &tmp, blue, mmio); | |
1156 | i810_read_dac(regno * 4, &tmp, green, &tmp, mmio); | |
1157 | } | |
1158 | else | |
1159 | i810_read_dac(regno, red, green, blue, mmio); | |
1160 | ||
1161 | *transp = 0; | |
1162 | i810_writeb(PIXCONF1, mmio, temp); | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /****************************************************************** | |
1168 | * Framebuffer device-specific hooks * | |
1169 | ******************************************************************/ | |
1170 | ||
1171 | static int i810fb_open(struct fb_info *info, int user) | |
1172 | { | |
1173 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1174 | u32 count = atomic_read(&par->use_count); | |
1175 | ||
1176 | if (count == 0) { | |
1177 | memset(&par->state, 0, sizeof(struct vgastate)); | |
1178 | par->state.flags = VGA_SAVE_CMAP; | |
1179 | par->state.vgabase = par->mmio_start_virtual; | |
1180 | save_vga(&par->state); | |
1181 | ||
1182 | i810_save_vga_state(par); | |
1183 | } | |
1184 | ||
1185 | atomic_inc(&par->use_count); | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static int i810fb_release(struct fb_info *info, int user) | |
1191 | { | |
1192 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1193 | u32 count; | |
1194 | ||
1195 | count = atomic_read(&par->use_count); | |
1196 | if (count == 0) | |
1197 | return -EINVAL; | |
1198 | ||
1199 | if (count == 1) { | |
1200 | i810_restore_vga_state(par); | |
1201 | restore_vga(&par->state); | |
1202 | } | |
1203 | ||
1204 | atomic_dec(&par->use_count); | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | ||
1210 | static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
1211 | unsigned blue, unsigned transp, | |
1212 | struct fb_info *info) | |
1213 | { | |
1214 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1215 | u8 __iomem *mmio = par->mmio_start_virtual; | |
1216 | u8 temp; | |
1217 | int i; | |
1218 | ||
1219 | if (regno > 255) return 1; | |
1220 | ||
1221 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
1222 | if ((info->var.green.length == 5 && regno > 31) || | |
1223 | (info->var.green.length == 6 && regno > 63)) | |
1224 | return 1; | |
1225 | } | |
1226 | ||
1227 | if (info->var.grayscale) | |
1228 | red = green = blue = (19595 * red + 38470 * green + | |
1229 | 7471 * blue) >> 16; | |
1230 | ||
1231 | temp = i810_readb(PIXCONF1, mmio); | |
1232 | i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); | |
1233 | ||
1234 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && | |
1235 | info->var.green.length == 5) { | |
1236 | for (i = 0; i < 8; i++) | |
1237 | i810_write_dac((u8) (regno * 8) + i, (u8) red, | |
1238 | (u8) green, (u8) blue, mmio); | |
1239 | } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && | |
1240 | info->var.green.length == 6) { | |
1241 | u8 r, g, b; | |
1242 | ||
1243 | if (regno < 32) { | |
1244 | for (i = 0; i < 8; i++) | |
1245 | i810_write_dac((u8) (regno * 8) + i, | |
1246 | (u8) red, (u8) green, | |
1247 | (u8) blue, mmio); | |
1248 | } | |
1249 | i810_read_dac((u8) (regno*4), &r, &g, &b, mmio); | |
1250 | for (i = 0; i < 4; i++) | |
1251 | i810_write_dac((u8) (regno*4) + i, r, (u8) green, | |
1252 | b, mmio); | |
1253 | } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { | |
1254 | i810_write_dac((u8) regno, (u8) red, (u8) green, | |
1255 | (u8) blue, mmio); | |
1256 | } | |
1257 | ||
1258 | i810_writeb(PIXCONF1, mmio, temp); | |
1259 | ||
1260 | if (regno < 16) { | |
1261 | switch (info->var.bits_per_pixel) { | |
1262 | case 16: | |
1263 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
1264 | if (info->var.green.length == 5) | |
1265 | ((u32 *)info->pseudo_palette)[regno] = | |
1266 | (regno << 10) | (regno << 5) | | |
1267 | regno; | |
1268 | else | |
1269 | ((u32 *)info->pseudo_palette)[regno] = | |
1270 | (regno << 11) | (regno << 5) | | |
1271 | regno; | |
1272 | } else { | |
1273 | if (info->var.green.length == 5) { | |
1274 | /* RGB 555 */ | |
1275 | ((u32 *)info->pseudo_palette)[regno] = | |
1276 | ((red & 0xf800) >> 1) | | |
1277 | ((green & 0xf800) >> 6) | | |
1278 | ((blue & 0xf800) >> 11); | |
1279 | } else { | |
1280 | /* RGB 565 */ | |
1281 | ((u32 *)info->pseudo_palette)[regno] = | |
1282 | (red & 0xf800) | | |
1283 | ((green & 0xf800) >> 5) | | |
1284 | ((blue & 0xf800) >> 11); | |
1285 | } | |
1286 | } | |
1287 | break; | |
1288 | case 24: /* RGB 888 */ | |
1289 | case 32: /* RGBA 8888 */ | |
1290 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
1291 | ((u32 *)info->pseudo_palette)[regno] = | |
1292 | (regno << 16) | (regno << 8) | | |
1293 | regno; | |
1294 | else | |
1295 | ((u32 *)info->pseudo_palette)[regno] = | |
1296 | ((red & 0xff00) << 8) | | |
1297 | (green & 0xff00) | | |
1298 | ((blue & 0xff00) >> 8); | |
1299 | break; | |
1300 | } | |
1301 | } | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | static int i810fb_pan_display(struct fb_var_screeninfo *var, | |
1306 | struct fb_info *info) | |
1307 | { | |
1308 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1309 | u32 total; | |
1310 | ||
1311 | total = var->xoffset * par->depth + | |
1312 | var->yoffset * info->fix.line_length; | |
1313 | i810fb_load_front(total, info); | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | static int i810fb_blank (int blank_mode, struct fb_info *info) | |
1319 | { | |
1320 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1321 | u8 __iomem *mmio = par->mmio_start_virtual; | |
1322 | int mode = 0, pwr, scr_off = 0; | |
1323 | ||
1324 | pwr = i810_readl(PWR_CLKC, mmio); | |
1325 | ||
1326 | switch (blank_mode) { | |
1327 | case FB_BLANK_UNBLANK: | |
1328 | mode = POWERON; | |
1329 | pwr |= 1; | |
1330 | scr_off = ON; | |
1331 | break; | |
1332 | case FB_BLANK_NORMAL: | |
1333 | mode = POWERON; | |
1334 | pwr |= 1; | |
1335 | scr_off = OFF; | |
1336 | break; | |
1337 | case FB_BLANK_VSYNC_SUSPEND: | |
1338 | mode = STANDBY; | |
1339 | pwr |= 1; | |
1340 | scr_off = OFF; | |
1341 | break; | |
1342 | case FB_BLANK_HSYNC_SUSPEND: | |
1343 | mode = SUSPEND; | |
1344 | pwr |= 1; | |
1345 | scr_off = OFF; | |
1346 | break; | |
1347 | case FB_BLANK_POWERDOWN: | |
1348 | mode = POWERDOWN; | |
1349 | pwr &= ~1; | |
1350 | scr_off = OFF; | |
1351 | break; | |
1352 | default: | |
1353 | return -EINVAL; | |
1354 | } | |
1355 | ||
1356 | i810_screen_off(mmio, scr_off); | |
1357 | i810_writel(HVSYNC, mmio, mode); | |
1358 | i810_writel(PWR_CLKC, mmio, pwr); | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int i810fb_set_par(struct fb_info *info) | |
1364 | { | |
1365 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1366 | ||
1367 | decode_var(&info->var, par); | |
1368 | i810_load_regs(par); | |
1369 | i810_init_cursor(par); | |
1370 | ||
1371 | encode_fix(&info->fix, info); | |
1372 | ||
1373 | if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) { | |
1374 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN | | |
1375 | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | | |
1376 | FBINFO_HWACCEL_IMAGEBLIT; | |
1377 | info->pixmap.scan_align = 2; | |
1378 | } else { | |
1379 | info->pixmap.scan_align = 1; | |
1380 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | |
1381 | } | |
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | static int i810fb_check_var(struct fb_var_screeninfo *var, | |
1386 | struct fb_info *info) | |
1387 | { | |
1388 | int err; | |
1389 | ||
1390 | if (IS_DVT) { | |
1391 | var->vmode &= ~FB_VMODE_MASK; | |
1392 | var->vmode |= FB_VMODE_NONINTERLACED; | |
1393 | } | |
1394 | if (var->vmode & FB_VMODE_DOUBLE) { | |
1395 | var->vmode &= ~FB_VMODE_MASK; | |
1396 | var->vmode |= FB_VMODE_NONINTERLACED; | |
1397 | } | |
1398 | ||
1399 | i810_round_off(var); | |
1400 | if ((err = i810_check_params(var, info))) | |
1401 | return err; | |
1402 | ||
1403 | i810fb_fill_var_timings(var); | |
1404 | set_color_bitfields(var); | |
1405 | return 0; | |
1406 | } | |
1407 | ||
1408 | static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
1409 | { | |
1410 | struct i810fb_par *par = (struct i810fb_par *)info->par; | |
1411 | u8 __iomem *mmio = par->mmio_start_virtual; | |
1412 | ||
1413 | if (!(par->dev_flags & USE_HWCUR) || !info->var.accel_flags || | |
1414 | par->dev_flags & LOCKUP) | |
1415 | return soft_cursor(info, cursor); | |
1416 | ||
1417 | if (cursor->image.width > 64 || cursor->image.height > 64) | |
1418 | return -ENXIO; | |
1419 | ||
1420 | if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) { | |
1421 | i810_init_cursor(par); | |
1422 | cursor->set |= FB_CUR_SETALL; | |
1423 | } | |
1424 | ||
1425 | i810_enable_cursor(mmio, OFF); | |
1426 | ||
1427 | if (cursor->set & FB_CUR_SETPOS) { | |
1428 | u32 tmp; | |
1429 | ||
1430 | tmp = (cursor->image.dx - info->var.xoffset) & 0xffff; | |
1431 | tmp |= (cursor->image.dy - info->var.yoffset) << 16; | |
1432 | i810_writel(CURPOS, mmio, tmp); | |
1433 | } | |
1434 | ||
1435 | if (cursor->set & FB_CUR_SETSIZE) | |
1436 | i810_reset_cursor_image(par); | |
1437 | ||
1438 | if (cursor->set & FB_CUR_SETCMAP) | |
1439 | i810_load_cursor_colors(cursor->image.fg_color, | |
1440 | cursor->image.bg_color, | |
1441 | info); | |
1442 | ||
1443 | if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { | |
1444 | int size = ((cursor->image.width + 7) >> 3) * | |
1445 | cursor->image.height; | |
1446 | int i; | |
1447 | u8 *data = kmalloc(64 * 8, GFP_KERNEL); | |
1448 | ||
1449 | if (data == NULL) | |
1450 | return -ENOMEM; | |
1451 | ||
1452 | switch (cursor->rop) { | |
1453 | case ROP_XOR: | |
1454 | for (i = 0; i < size; i++) | |
1455 | data[i] = cursor->image.data[i] ^ cursor->mask[i]; | |
1456 | break; | |
1457 | case ROP_COPY: | |
1458 | default: | |
1459 | for (i = 0; i < size; i++) | |
1460 | data[i] = cursor->image.data[i] & cursor->mask[i]; | |
1461 | break; | |
1462 | } | |
1463 | ||
1464 | i810_load_cursor_image(cursor->image.width, | |
1465 | cursor->image.height, data, | |
1466 | par); | |
1467 | kfree(data); | |
1468 | } | |
1469 | ||
1470 | if (cursor->enable) | |
1471 | i810_enable_cursor(mmio, ON); | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static struct fb_ops i810fb_ops __devinitdata = { | |
1477 | .owner = THIS_MODULE, | |
1478 | .fb_open = i810fb_open, | |
1479 | .fb_release = i810fb_release, | |
1480 | .fb_check_var = i810fb_check_var, | |
1481 | .fb_set_par = i810fb_set_par, | |
1482 | .fb_setcolreg = i810fb_setcolreg, | |
1483 | .fb_blank = i810fb_blank, | |
1484 | .fb_pan_display = i810fb_pan_display, | |
1485 | .fb_fillrect = i810fb_fillrect, | |
1486 | .fb_copyarea = i810fb_copyarea, | |
1487 | .fb_imageblit = i810fb_imageblit, | |
1488 | .fb_cursor = i810fb_cursor, | |
1489 | .fb_sync = i810fb_sync, | |
1490 | }; | |
1491 | ||
1492 | /*********************************************************************** | |
1493 | * Power Management * | |
1494 | ***********************************************************************/ | |
1495 | static int i810fb_suspend(struct pci_dev *dev, pm_message_t state) | |
1496 | { | |
1497 | struct fb_info *info = pci_get_drvdata(dev); | |
1498 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1499 | int blank = 0, prev_state = par->cur_state; | |
1500 | ||
1501 | if (state == prev_state) | |
1502 | return 0; | |
1503 | ||
1504 | par->cur_state = state; | |
1505 | ||
1506 | switch (state) { | |
1507 | case 1: | |
1508 | blank = VESA_VSYNC_SUSPEND; | |
1509 | break; | |
1510 | case 2: | |
1511 | blank = VESA_HSYNC_SUSPEND; | |
1512 | break; | |
1513 | case 3: | |
1514 | blank = VESA_POWERDOWN; | |
1515 | break; | |
1516 | default: | |
1517 | return -EINVAL; | |
1518 | } | |
1519 | info->fbops->fb_blank(blank, info); | |
1520 | ||
1521 | if (!prev_state) { | |
1522 | agp_unbind_memory(par->i810_gtt.i810_fb_memory); | |
1523 | agp_unbind_memory(par->i810_gtt.i810_cursor_memory); | |
1524 | pci_disable_device(dev); | |
1525 | } | |
1526 | pci_save_state(dev); | |
1527 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static int i810fb_resume(struct pci_dev *dev) | |
1533 | { | |
1534 | struct fb_info *info = pci_get_drvdata(dev); | |
1535 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1536 | ||
1537 | if (par->cur_state == 0) | |
1538 | return 0; | |
1539 | ||
1540 | pci_restore_state(dev); | |
1541 | pci_set_power_state(dev, PCI_D0); | |
1542 | pci_enable_device(dev); | |
1543 | agp_bind_memory(par->i810_gtt.i810_fb_memory, | |
1544 | par->fb.offset); | |
1545 | agp_bind_memory(par->i810_gtt.i810_cursor_memory, | |
1546 | par->cursor_heap.offset); | |
1547 | ||
1548 | info->fbops->fb_blank(VESA_NO_BLANKING, info); | |
1549 | ||
1550 | par->cur_state = 0; | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | /*********************************************************************** | |
1555 | * AGP resource allocation * | |
1556 | ***********************************************************************/ | |
1557 | ||
1558 | static void __devinit i810_fix_pointers(struct i810fb_par *par) | |
1559 | { | |
1560 | par->fb.physical = par->aperture.physical+(par->fb.offset << 12); | |
1561 | par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12); | |
1562 | par->iring.physical = par->aperture.physical + | |
1563 | (par->iring.offset << 12); | |
1564 | par->iring.virtual = par->aperture.virtual + | |
1565 | (par->iring.offset << 12); | |
1566 | par->cursor_heap.virtual = par->aperture.virtual+ | |
1567 | (par->cursor_heap.offset << 12); | |
1568 | } | |
1569 | ||
1570 | static void __devinit i810_fix_offsets(struct i810fb_par *par) | |
1571 | { | |
1572 | if (vram + 1 > par->aperture.size >> 20) | |
1573 | vram = (par->aperture.size >> 20) - 1; | |
1574 | if (v_offset_default > (par->aperture.size >> 20)) | |
1575 | v_offset_default = (par->aperture.size >> 20); | |
1576 | if (vram + v_offset_default + 1 > par->aperture.size >> 20) | |
1577 | v_offset_default = (par->aperture.size >> 20) - (vram + 1); | |
1578 | ||
1579 | par->fb.size = vram << 20; | |
1580 | par->fb.offset = v_offset_default << 20; | |
1581 | par->fb.offset >>= 12; | |
1582 | ||
1583 | par->iring.offset = par->fb.offset + (par->fb.size >> 12); | |
1584 | par->iring.size = RINGBUFFER_SIZE; | |
1585 | ||
1586 | par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12); | |
1587 | par->cursor_heap.size = 4096; | |
1588 | } | |
1589 | ||
1590 | static int __devinit i810_alloc_agp_mem(struct fb_info *info) | |
1591 | { | |
1592 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1593 | int size; | |
1594 | struct agp_bridge_data *bridge; | |
1595 | ||
1596 | i810_fix_offsets(par); | |
1597 | size = par->fb.size + par->iring.size; | |
1598 | ||
1599 | if (!(bridge = agp_backend_acquire(par->dev))) { | |
1600 | printk("i810fb_alloc_fbmem: cannot acquire agpgart\n"); | |
1601 | return -ENODEV; | |
1602 | } | |
1603 | if (!(par->i810_gtt.i810_fb_memory = | |
1604 | agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) { | |
1605 | printk("i810fb_alloc_fbmem: can't allocate framebuffer " | |
1606 | "memory\n"); | |
1607 | agp_backend_release(bridge); | |
1608 | return -ENOMEM; | |
1609 | } | |
1610 | if (agp_bind_memory(par->i810_gtt.i810_fb_memory, | |
1611 | par->fb.offset)) { | |
1612 | printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n"); | |
1613 | agp_backend_release(bridge); | |
1614 | return -EBUSY; | |
1615 | } | |
1616 | ||
1617 | if (!(par->i810_gtt.i810_cursor_memory = | |
1618 | agp_allocate_memory(bridge, par->cursor_heap.size >> 12, | |
1619 | AGP_PHYSICAL_MEMORY))) { | |
1620 | printk("i810fb_alloc_cursormem: can't allocate" | |
1621 | "cursor memory\n"); | |
1622 | agp_backend_release(bridge); | |
1623 | return -ENOMEM; | |
1624 | } | |
1625 | if (agp_bind_memory(par->i810_gtt.i810_cursor_memory, | |
1626 | par->cursor_heap.offset)) { | |
1627 | printk("i810fb_alloc_cursormem: cannot bind cursor memory\n"); | |
1628 | agp_backend_release(bridge); | |
1629 | return -EBUSY; | |
1630 | } | |
1631 | ||
1632 | par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical; | |
1633 | ||
1634 | i810_fix_pointers(par); | |
1635 | ||
1636 | agp_backend_release(bridge); | |
1637 | ||
1638 | return 0; | |
1639 | } | |
1640 | ||
1641 | /*************************************************************** | |
1642 | * Initialization * | |
1643 | ***************************************************************/ | |
1644 | ||
1645 | /** | |
1646 | * i810_init_monspecs | |
1647 | * @info: pointer to device specific info structure | |
1648 | * | |
1649 | * DESCRIPTION: | |
1650 | * Sets the the user monitor's horizontal and vertical | |
1651 | * frequency limits | |
1652 | */ | |
1653 | static void __devinit i810_init_monspecs(struct fb_info *info) | |
1654 | { | |
1655 | if (!hsync1) | |
1656 | hsync1 = HFMIN; | |
1657 | if (!hsync2) | |
1658 | hsync2 = HFMAX; | |
1659 | if (!info->monspecs.hfmax) | |
1660 | info->monspecs.hfmax = hsync2; | |
1661 | if (!info->monspecs.hfmin) | |
1662 | info->monspecs.hfmin = hsync1; | |
1663 | if (hsync2 < hsync1) | |
1664 | info->monspecs.hfmin = hsync2; | |
1665 | ||
1666 | if (!vsync1) | |
1667 | vsync1 = VFMIN; | |
1668 | if (!vsync2) | |
1669 | vsync2 = VFMAX; | |
1670 | if (IS_DVT && vsync1 < 60) | |
1671 | vsync1 = 60; | |
1672 | if (!info->monspecs.vfmax) | |
1673 | info->monspecs.vfmax = vsync2; | |
1674 | if (!info->monspecs.vfmin) | |
1675 | info->monspecs.vfmin = vsync1; | |
1676 | if (vsync2 < vsync1) | |
1677 | info->monspecs.vfmin = vsync2; | |
1678 | } | |
1679 | ||
1680 | /** | |
1681 | * i810_init_defaults - initializes default values to use | |
1682 | * @par: pointer to i810fb_par structure | |
1683 | * @info: pointer to current fb_info structure | |
1684 | */ | |
1685 | static void __devinit i810_init_defaults(struct i810fb_par *par, | |
1686 | struct fb_info *info) | |
1687 | { | |
1688 | if (voffset) | |
1689 | v_offset_default = voffset; | |
1690 | else if (par->aperture.size > 32 * 1024 * 1024) | |
1691 | v_offset_default = 16; | |
1692 | else | |
1693 | v_offset_default = 8; | |
1694 | ||
1695 | if (!vram) | |
1696 | vram = 1; | |
1697 | ||
1698 | if (accel) | |
1699 | par->dev_flags |= HAS_ACCELERATION; | |
1700 | ||
1701 | if (sync) | |
1702 | par->dev_flags |= ALWAYS_SYNC; | |
1703 | ||
1704 | if (bpp < 8) | |
1705 | bpp = 8; | |
1706 | ||
1707 | if (!vyres) | |
1708 | vyres = (vram << 20)/(xres*bpp >> 3); | |
1709 | ||
1710 | par->i810fb_ops = i810fb_ops; | |
1711 | info->var.xres = xres; | |
1712 | info->var.yres = yres; | |
1713 | info->var.yres_virtual = vyres; | |
1714 | info->var.bits_per_pixel = bpp; | |
1715 | ||
1716 | if (dcolor) | |
1717 | info->var.nonstd = 1; | |
1718 | ||
1719 | if (par->dev_flags & HAS_ACCELERATION) | |
1720 | info->var.accel_flags = 1; | |
1721 | ||
1722 | i810_init_monspecs(info); | |
1723 | } | |
1724 | ||
1725 | /** | |
1726 | * i810_init_device - initialize device | |
1727 | * @par: pointer to i810fb_par structure | |
1728 | */ | |
1729 | static void __devinit i810_init_device(struct i810fb_par *par) | |
1730 | { | |
1731 | u8 reg; | |
1732 | u8 __iomem *mmio = par->mmio_start_virtual; | |
1733 | ||
1734 | if (mtrr) set_mtrr(par); | |
1735 | ||
1736 | i810_init_cursor(par); | |
1737 | ||
1738 | /* mvo: enable external vga-connector (for laptops) */ | |
1739 | if (ext_vga) { | |
1740 | i810_writel(HVSYNC, mmio, 0); | |
1741 | i810_writel(PWR_CLKC, mmio, 3); | |
1742 | } | |
1743 | ||
1744 | pci_read_config_byte(par->dev, 0x50, ®); | |
1745 | reg &= FREQ_MASK; | |
1746 | par->mem_freq = (reg) ? 133 : 100; | |
1747 | ||
1748 | } | |
1749 | ||
1750 | static int __devinit | |
1751 | i810_allocate_pci_resource(struct i810fb_par *par, | |
1752 | const struct pci_device_id *entry) | |
1753 | { | |
1754 | int err; | |
1755 | ||
1756 | if ((err = pci_enable_device(par->dev))) { | |
1757 | printk("i810fb_init: cannot enable device\n"); | |
1758 | return err; | |
1759 | } | |
1760 | par->res_flags |= PCI_DEVICE_ENABLED; | |
1761 | ||
1762 | if (pci_resource_len(par->dev, 0) > 512 * 1024) { | |
1763 | par->aperture.physical = pci_resource_start(par->dev, 0); | |
1764 | par->aperture.size = pci_resource_len(par->dev, 0); | |
1765 | par->mmio_start_phys = pci_resource_start(par->dev, 1); | |
1766 | } else { | |
1767 | par->aperture.physical = pci_resource_start(par->dev, 1); | |
1768 | par->aperture.size = pci_resource_len(par->dev, 1); | |
1769 | par->mmio_start_phys = pci_resource_start(par->dev, 0); | |
1770 | } | |
1771 | if (!par->aperture.size) { | |
1772 | printk("i810fb_init: device is disabled\n"); | |
1773 | return -ENOMEM; | |
1774 | } | |
1775 | ||
1776 | if (!request_mem_region(par->aperture.physical, | |
1777 | par->aperture.size, | |
1778 | i810_pci_list[entry->driver_data])) { | |
1779 | printk("i810fb_init: cannot request framebuffer region\n"); | |
1780 | return -ENODEV; | |
1781 | } | |
1782 | par->res_flags |= FRAMEBUFFER_REQ; | |
1783 | ||
1784 | par->aperture.virtual = ioremap_nocache(par->aperture.physical, | |
1785 | par->aperture.size); | |
1786 | if (!par->aperture.virtual) { | |
1787 | printk("i810fb_init: cannot remap framebuffer region\n"); | |
1788 | return -ENODEV; | |
1789 | } | |
1790 | ||
1791 | if (!request_mem_region(par->mmio_start_phys, | |
1792 | MMIO_SIZE, | |
1793 | i810_pci_list[entry->driver_data])) { | |
1794 | printk("i810fb_init: cannot request mmio region\n"); | |
1795 | return -ENODEV; | |
1796 | } | |
1797 | par->res_flags |= MMIO_REQ; | |
1798 | ||
1799 | par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys, | |
1800 | MMIO_SIZE); | |
1801 | if (!par->mmio_start_virtual) { | |
1802 | printk("i810fb_init: cannot remap mmio region\n"); | |
1803 | return -ENODEV; | |
1804 | } | |
1805 | ||
1806 | return 0; | |
1807 | } | |
1808 | ||
1809 | #ifndef MODULE | |
1810 | static int __init i810fb_setup(char *options) | |
1811 | { | |
1812 | char *this_opt, *suffix = NULL; | |
1813 | ||
1814 | if (!options || !*options) | |
1815 | return 0; | |
1816 | ||
1817 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1818 | if (!strncmp(this_opt, "mtrr", 4)) | |
1819 | mtrr = 1; | |
1820 | else if (!strncmp(this_opt, "accel", 5)) | |
1821 | accel = 1; | |
1822 | else if (!strncmp(this_opt, "ext_vga", 7)) | |
1823 | ext_vga = 1; | |
1824 | else if (!strncmp(this_opt, "sync", 4)) | |
1825 | sync = 1; | |
1826 | else if (!strncmp(this_opt, "vram:", 5)) | |
1827 | vram = (simple_strtoul(this_opt+5, NULL, 0)); | |
1828 | else if (!strncmp(this_opt, "voffset:", 8)) | |
1829 | voffset = (simple_strtoul(this_opt+8, NULL, 0)); | |
1830 | else if (!strncmp(this_opt, "xres:", 5)) | |
1831 | xres = simple_strtoul(this_opt+5, NULL, 0); | |
1832 | else if (!strncmp(this_opt, "yres:", 5)) | |
1833 | yres = simple_strtoul(this_opt+5, NULL, 0); | |
1834 | else if (!strncmp(this_opt, "vyres:", 6)) | |
1835 | vyres = simple_strtoul(this_opt+6, NULL, 0); | |
1836 | else if (!strncmp(this_opt, "bpp:", 4)) | |
1837 | bpp = simple_strtoul(this_opt+4, NULL, 0); | |
1838 | else if (!strncmp(this_opt, "hsync1:", 7)) { | |
1839 | hsync1 = simple_strtoul(this_opt+7, &suffix, 0); | |
1840 | if (strncmp(suffix, "H", 1)) | |
1841 | hsync1 *= 1000; | |
1842 | } else if (!strncmp(this_opt, "hsync2:", 7)) { | |
1843 | hsync2 = simple_strtoul(this_opt+7, &suffix, 0); | |
1844 | if (strncmp(suffix, "H", 1)) | |
1845 | hsync2 *= 1000; | |
1846 | } else if (!strncmp(this_opt, "vsync1:", 7)) | |
1847 | vsync1 = simple_strtoul(this_opt+7, NULL, 0); | |
1848 | else if (!strncmp(this_opt, "vsync2:", 7)) | |
1849 | vsync2 = simple_strtoul(this_opt+7, NULL, 0); | |
1850 | else if (!strncmp(this_opt, "dcolor", 6)) | |
1851 | dcolor = 1; | |
1852 | } | |
1853 | return 0; | |
1854 | } | |
1855 | #endif | |
1856 | ||
1857 | static int __devinit i810fb_init_pci (struct pci_dev *dev, | |
1858 | const struct pci_device_id *entry) | |
1859 | { | |
1860 | struct fb_info *info; | |
1861 | struct i810fb_par *par = NULL; | |
1862 | int i, err = -1, vfreq, hfreq, pixclock; | |
1863 | ||
1864 | i = 0; | |
1865 | ||
1866 | info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev); | |
1867 | if (!info) | |
1868 | return -ENOMEM; | |
1869 | ||
1870 | par = (struct i810fb_par *) info->par; | |
1871 | par->dev = dev; | |
1872 | ||
1873 | if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) { | |
1874 | i810fb_release_resource(info, par); | |
1875 | return -ENOMEM; | |
1876 | } | |
1877 | memset(info->pixmap.addr, 0, 8*1024); | |
1878 | info->pixmap.size = 8*1024; | |
1879 | info->pixmap.buf_align = 8; | |
1880 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
1881 | ||
1882 | if ((err = i810_allocate_pci_resource(par, entry))) { | |
1883 | i810fb_release_resource(info, par); | |
1884 | return err; | |
1885 | } | |
1886 | ||
1887 | i810_init_defaults(par, info); | |
1888 | ||
1889 | if ((err = i810_alloc_agp_mem(info))) { | |
1890 | i810fb_release_resource(info, par); | |
1891 | return err; | |
1892 | } | |
1893 | ||
1894 | i810_init_device(par); | |
1895 | ||
1896 | info->screen_base = par->fb.virtual; | |
1897 | info->fbops = &par->i810fb_ops; | |
1898 | info->pseudo_palette = par->pseudo_palette; | |
1899 | fb_alloc_cmap(&info->cmap, 256, 0); | |
1900 | ||
1901 | if ((err = info->fbops->fb_check_var(&info->var, info))) { | |
1902 | i810fb_release_resource(info, par); | |
1903 | return err; | |
1904 | } | |
1905 | encode_fix(&info->fix, info); | |
1906 | ||
1907 | i810fb_init_ringbuffer(info); | |
1908 | err = register_framebuffer(info); | |
1909 | if (err < 0) { | |
1910 | i810fb_release_resource(info, par); | |
1911 | printk("i810fb_init: cannot register framebuffer device\n"); | |
1912 | return err; | |
1913 | } | |
1914 | ||
1915 | pci_set_drvdata(dev, info); | |
1916 | pixclock = 1000000000/(info->var.pixclock); | |
1917 | pixclock *= 1000; | |
1918 | hfreq = pixclock/(info->var.xres + info->var.left_margin + | |
1919 | info->var.hsync_len + info->var.right_margin); | |
1920 | vfreq = hfreq/(info->var.yres + info->var.upper_margin + | |
1921 | info->var.vsync_len + info->var.lower_margin); | |
1922 | ||
1923 | printk("I810FB: fb%d : %s v%d.%d.%d%s\n" | |
1924 | "I810FB: Video RAM : %dK\n" | |
1925 | "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n" | |
1926 | "I810FB: Mode : %dx%d-%dbpp@%dHz\n", | |
1927 | info->node, | |
1928 | i810_pci_list[entry->driver_data], | |
1929 | VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION, | |
1930 | (int) par->fb.size>>10, info->monspecs.hfmin/1000, | |
1931 | info->monspecs.hfmax/1000, info->monspecs.vfmin, | |
1932 | info->monspecs.vfmax, info->var.xres, | |
1933 | info->var.yres, info->var.bits_per_pixel, vfreq); | |
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | /*************************************************************** | |
1938 | * De-initialization * | |
1939 | ***************************************************************/ | |
1940 | ||
1941 | static void i810fb_release_resource(struct fb_info *info, | |
1942 | struct i810fb_par *par) | |
1943 | { | |
1944 | struct gtt_data *gtt = &par->i810_gtt; | |
1945 | unset_mtrr(par); | |
1946 | ||
1947 | if (par->i810_gtt.i810_cursor_memory) | |
1948 | agp_free_memory(gtt->i810_cursor_memory); | |
1949 | if (par->i810_gtt.i810_fb_memory) | |
1950 | agp_free_memory(gtt->i810_fb_memory); | |
1951 | ||
1952 | if (par->mmio_start_virtual) | |
1953 | iounmap(par->mmio_start_virtual); | |
1954 | if (par->aperture.virtual) | |
1955 | iounmap(par->aperture.virtual); | |
1956 | ||
1957 | if (par->res_flags & FRAMEBUFFER_REQ) | |
1958 | release_mem_region(par->aperture.physical, | |
1959 | par->aperture.size); | |
1960 | if (par->res_flags & MMIO_REQ) | |
1961 | release_mem_region(par->mmio_start_phys, MMIO_SIZE); | |
1962 | ||
1963 | if (par->res_flags & PCI_DEVICE_ENABLED) | |
1964 | pci_disable_device(par->dev); | |
1965 | ||
1966 | framebuffer_release(info); | |
1967 | ||
1968 | } | |
1969 | ||
1970 | static void __exit i810fb_remove_pci(struct pci_dev *dev) | |
1971 | { | |
1972 | struct fb_info *info = pci_get_drvdata(dev); | |
1973 | struct i810fb_par *par = (struct i810fb_par *) info->par; | |
1974 | ||
1975 | unregister_framebuffer(info); | |
1976 | i810fb_release_resource(info, par); | |
1977 | pci_set_drvdata(dev, NULL); | |
1978 | printk("cleanup_module: unloaded i810 framebuffer device\n"); | |
1979 | } | |
1980 | ||
1981 | #ifndef MODULE | |
1982 | static int __init i810fb_init(void) | |
1983 | { | |
1984 | char *option = NULL; | |
1985 | ||
1986 | if (fb_get_options("i810fb", &option)) | |
1987 | return -ENODEV; | |
1988 | i810fb_setup(option); | |
1989 | ||
1990 | return pci_register_driver(&i810fb_driver); | |
1991 | } | |
1992 | #endif | |
1993 | ||
1994 | /********************************************************************* | |
1995 | * Modularization * | |
1996 | *********************************************************************/ | |
1997 | ||
1998 | #ifdef MODULE | |
1999 | ||
2000 | static int __init i810fb_init(void) | |
2001 | { | |
2002 | hsync1 *= 1000; | |
2003 | hsync2 *= 1000; | |
2004 | ||
2005 | return pci_register_driver(&i810fb_driver); | |
2006 | } | |
2007 | ||
2008 | module_param(vram, int, 0); | |
2009 | MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB" | |
2010 | " (default=4)"); | |
2011 | module_param(voffset, int, 0); | |
2012 | MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer " | |
2013 | "memory (0 to maximum aperture size), in MiB (default = 48)"); | |
2014 | module_param(bpp, int, 0); | |
2015 | MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel" | |
2016 | " (default = 8)"); | |
2017 | module_param(xres, int, 0); | |
2018 | MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)"); | |
2019 | module_param(yres, int, 0); | |
2020 | MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)"); | |
2021 | module_param(vyres,int, 0); | |
2022 | MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines" | |
2023 | " (default = 480)"); | |
2024 | module_param(hsync1, int, 0); | |
2025 | MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz" | |
2026 | " (default = 31)"); | |
2027 | module_param(hsync2, int, 0); | |
2028 | MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz" | |
2029 | " (default = 31)"); | |
2030 | module_param(vsync1, int, 0); | |
2031 | MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz" | |
2032 | " (default = 50)"); | |
2033 | module_param(vsync2, int, 0); | |
2034 | MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz" | |
2035 | " (default = 60)"); | |
2036 | module_param(accel, bool, 0); | |
2037 | MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)"); | |
2038 | module_param(mtrr, bool, 0); | |
2039 | MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)"); | |
2040 | module_param(ext_vga, bool, 0); | |
2041 | MODULE_PARM_DESC(ext_vga, "Enable external VGA connector (default = 0)"); | |
2042 | module_param(sync, bool, 0); | |
2043 | MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing" | |
2044 | " (default = 0)"); | |
2045 | module_param(dcolor, bool, 0); | |
2046 | MODULE_PARM_DESC(dcolor, "use DirectColor visuals" | |
2047 | " (default = 0 = TrueColor)"); | |
2048 | ||
2049 | MODULE_AUTHOR("Tony A. Daplas"); | |
2050 | MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and" | |
2051 | " compatible cards"); | |
2052 | MODULE_LICENSE("GPL"); | |
2053 | ||
2054 | static void __exit i810fb_exit(void) | |
2055 | { | |
2056 | pci_unregister_driver(&i810fb_driver); | |
2057 | } | |
2058 | module_exit(i810fb_exit); | |
2059 | ||
2060 | #endif /* MODULE */ | |
2061 | ||
2062 | module_init(i810fb_init); |