[mirror_ubuntu-bionic-kernel.git] / drivers / video / nvidia / nv_accel.c

 /***************************************************************************\
|*                                                                           *|
|*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
|*                                                                           *|
|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
|*     international laws.  Users and possessors of this source code are     *|
|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
|*     use this code in individual and commercial software.                  *|
|*                                                                           *|
|*     Any use of this source code must include,  in the user documenta-     *|
|*     tion and  internal comments to the code,  notices to the end user     *|
|*     as follows:                                                           *|
|*                                                                           *|
|*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
|*                                                                           *|
|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
|*                                                                           *|
|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
|*     consisting  of "commercial  computer  software"  and  "commercial     *|
|*     computer  software  documentation,"  as such  terms  are  used in     *|
|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
|*     all U.S. Government End Users  acquire the source code  with only     *|
|*     those rights set forth herein.                                        *|
|*                                                                           *|
 \***************************************************************************/

/*
 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
 * where the source code is provided "as is" without warranty of any kind.
 * The only usage restriction is for the copyright notices to be retained
 * whenever code is used.
 *
 * Antonino Daplas <adaplas@pol.net> 2005-03-11
 */

#include <linux/fb.h>
#include "nv_type.h"
#include "nv_proto.h"
#include "nv_dma.h"
#include "nv_local.h"

/* There is a HW race condition with videoram command buffers.
   You can't jump to the location of your put offset.  We write put
   at the jump offset + SKIPS dwords with noop padding in between
   to solve this problem */
#define SKIPS  8

static const int NVCopyROP[16] = {
	0xCC,			/* copy   */
	0x55			/* invert */
};

static const int NVCopyROP_PM[16] = {
	0xCA,			/* copy  */
	0x5A,			/* invert */
};

static inline void nvidiafb_safe_mode(struct fb_info *info)
{
	struct nvidia_par *par = info->par;

	touch_softlockup_watchdog();
	info->pixmap.scan_align = 1;
	par->lockup = 1;
}

static inline void NVFlush(struct fb_info *info)
{
	struct nvidia_par *par = info->par;
	int count = 1000000000;

	while (--count && READ_GET(par) != par->dmaPut) ;

	if (!count) {
		printk("nvidiafb: DMA Flush lockup\n");
		nvidiafb_safe_mode(info);
	}
}

static inline void NVSync(struct fb_info *info)
{
	struct nvidia_par *par = info->par;
	int count = 1000000000;

	while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;

	if (!count) {
		printk("nvidiafb: DMA Sync lockup\n");
		nvidiafb_safe_mode(info);
	}
}

static void NVDmaKickoff(struct nvidia_par *par)
{
	if (par->dmaCurrent != par->dmaPut) {
		par->dmaPut = par->dmaCurrent;
		WRITE_PUT(par, par->dmaPut);
	}
}

static void NVDmaWait(struct fb_info *info, int size)
{
	struct nvidia_par *par = info->par;
	int dmaGet;
	int count = 1000000000, cnt;
	size++;

	while (par->dmaFree < size && --count && !par->lockup) {
		dmaGet = READ_GET(par);

		if (par->dmaPut >= dmaGet) {
			par->dmaFree = par->dmaMax - par->dmaCurrent;
			if (par->dmaFree < size) {
				NVDmaNext(par, 0x20000000);
				if (dmaGet <= SKIPS) {
					if (par->dmaPut <= SKIPS)
						WRITE_PUT(par, SKIPS + 1);
					cnt = 1000000000;
					do {
						dmaGet = READ_GET(par);
					} while (--cnt && dmaGet <= SKIPS);
					if (!cnt) {
						printk("DMA Get lockup\n");
						par->lockup = 1;
					}
				}
				WRITE_PUT(par, SKIPS);
				par->dmaCurrent = par->dmaPut = SKIPS;
				par->dmaFree = dmaGet - (SKIPS + 1);
			}
		} else
			par->dmaFree = dmaGet - par->dmaCurrent - 1;
	}

	if (!count) {
		printk("nvidiafb: DMA Wait Lockup\n");
		nvidiafb_safe_mode(info);
	}
}

static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
			 u32 pat0, u32 pat1)
{
	struct nvidia_par *par = info->par;

	NVDmaStart(info, par, PATTERN_COLOR_0, 4);
	NVDmaNext(par, clr0);
	NVDmaNext(par, clr1);
	NVDmaNext(par, pat0);
	NVDmaNext(par, pat1);
}

static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
{
	struct nvidia_par *par = info->par;

	if (planemask != ~0) {
		NVSetPattern(info, 0, planemask, ~0, ~0);
		if (par->currentRop != (rop + 32)) {
			NVDmaStart(info, par, ROP_SET, 1);
			NVDmaNext(par, NVCopyROP_PM[rop]);
			par->currentRop = rop + 32;
		}
	} else if (par->currentRop != rop) {
		if (par->currentRop >= 16)
			NVSetPattern(info, ~0, ~0, ~0, ~0);
		NVDmaStart(info, par, ROP_SET, 1);
		NVDmaNext(par, NVCopyROP[rop]);
		par->currentRop = rop;
	}
}

static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
				   int x2, int y2)
{
	struct nvidia_par *par = info->par;
	int h = y2 - y1 + 1;
	int w = x2 - x1 + 1;

	NVDmaStart(info, par, CLIP_POINT, 2);
	NVDmaNext(par, (y1 << 16) | x1);
	NVDmaNext(par, (h << 16) | w);
}

void NVResetGraphics(struct fb_info *info)
{
	struct nvidia_par *par = info->par;
	u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
	int pitch, i;

	pitch = info->fix.line_length;

	par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);

	for (i = 0; i < SKIPS; i++)
		NV_WR32(&par->dmaBase[i], 0, 0x00000000);

	NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
	NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
	NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
	NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
	NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
	NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
	NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
	NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
	NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
	NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
	NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
	NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
	NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
	NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
	NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
	NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);

	par->dmaPut = 0;
	par->dmaCurrent = 16 + SKIPS;
	par->dmaMax = 8191;
	par->dmaFree = par->dmaMax - par->dmaCurrent;

	switch (info->var.bits_per_pixel) {
	case 32:
	case 24:
		surfaceFormat = SURFACE_FORMAT_DEPTH24;
		patternFormat = PATTERN_FORMAT_DEPTH24;
		rectFormat = RECT_FORMAT_DEPTH24;
		lineFormat = LINE_FORMAT_DEPTH24;
		break;
	case 16:
		surfaceFormat = SURFACE_FORMAT_DEPTH16;
		patternFormat = PATTERN_FORMAT_DEPTH16;
		rectFormat = RECT_FORMAT_DEPTH16;
		lineFormat = LINE_FORMAT_DEPTH16;
		break;
	default:
		surfaceFormat = SURFACE_FORMAT_DEPTH8;
		patternFormat = PATTERN_FORMAT_DEPTH8;
		rectFormat = RECT_FORMAT_DEPTH8;
		lineFormat = LINE_FORMAT_DEPTH8;
		break;
	}

	NVDmaStart(info, par, SURFACE_FORMAT, 4);
	NVDmaNext(par, surfaceFormat);
	NVDmaNext(par, pitch | (pitch << 16));
	NVDmaNext(par, 0);
	NVDmaNext(par, 0);

	NVDmaStart(info, par, PATTERN_FORMAT, 1);
	NVDmaNext(par, patternFormat);

	NVDmaStart(info, par, RECT_FORMAT, 1);
	NVDmaNext(par, rectFormat);

	NVDmaStart(info, par, LINE_FORMAT, 1);
	NVDmaNext(par, lineFormat);

	par->currentRop = ~0;	/* set to something invalid */
	NVSetRopSolid(info, ROP_COPY, ~0);

	NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
			       info->var.yres_virtual);

	NVDmaKickoff(par);
}

int nvidiafb_sync(struct fb_info *info)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return 0;

	if (!par->lockup)
		NVFlush(info);

	if (!par->lockup)
		NVSync(info);

	return 0;
}

void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (par->lockup) {
		cfb_copyarea(info, region);
		return;
	}

	NVDmaStart(info, par, BLIT_POINT_SRC, 3);
	NVDmaNext(par, (region->sy << 16) | region->sx);
	NVDmaNext(par, (region->dy << 16) | region->dx);
	NVDmaNext(par, (region->height << 16) | region->width);

	NVDmaKickoff(par);
}

void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct nvidia_par *par = info->par;
	u32 color;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (par->lockup) {
		cfb_fillrect(info, rect);
		return;
	}

	if (info->var.bits_per_pixel == 8)
		color = rect->color;
	else
		color = ((u32 *) info->pseudo_palette)[rect->color];

	if (rect->rop != ROP_COPY)
		NVSetRopSolid(info, rect->rop, ~0);

	NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
	NVDmaNext(par, color);

	NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
	NVDmaNext(par, (rect->dx << 16) | rect->dy);
	NVDmaNext(par, (rect->width << 16) | rect->height);

	NVDmaKickoff(par);

	if (rect->rop != ROP_COPY)
		NVSetRopSolid(info, ROP_COPY, ~0);
}

static void nvidiafb_mono_color_expand(struct fb_info *info,
				       const struct fb_image *image)
{
	struct nvidia_par *par = info->par;
	u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
	u32 dsize, width, *data = (u32 *) image->data, tmp;
	int j, k = 0;

	width = (image->width + 31) & ~31;
	dsize = (width * image->height) >> 5;

	if (info->var.bits_per_pixel == 8) {
		fg = image->fg_color | mask;
		bg = image->bg_color | mask;
	} else {
		fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
		bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
	}

	NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
	NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
	NVDmaNext(par, ((image->dy + image->height) << 16) |
		  ((image->dx + image->width) & 0xffff));
	NVDmaNext(par, bg);
	NVDmaNext(par, fg);
	NVDmaNext(par, (image->height << 16) | width);
	NVDmaNext(par, (image->height << 16) | width);
	NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));

	while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
		NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
			   RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);

		for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
			tmp = data[k++];
			reverse_order(&tmp);
			NVDmaNext(par, tmp);
		}

		dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
	}

	if (dsize) {
		NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);

		for (j = dsize; j--;) {
			tmp = data[k++];
			reverse_order(&tmp);
			NVDmaNext(par, tmp);
		}
	}

	NVDmaKickoff(par);
}

void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (image->depth == 1 && !par->lockup)
		nvidiafb_mono_color_expand(info, image);
	else
		cfb_imageblit(info, image);
}
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************\
	2	\|* *\|
	3	\|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *\|
	4	\|* *\|
	5	\|* NOTICE TO USER: The source code is copyrighted under U.S. and *\|
	6	\|* international laws. Users and possessors of this source code are *\|
	7	\|* hereby granted a nonexclusive, royalty-free copyright license to *\|
	8	\|* use this code in individual and commercial software. *\|
	9	\|* *\|
	10	\|* Any use of this source code must include, in the user documenta- *\|
	11	\|* tion and internal comments to the code, notices to the end user *\|
	12	\|* as follows: *\|
	13	\|* *\|
	14	\|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *\|
	15	\|* *\|
	16	\|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *\|
	17	\|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *\|
	18	\|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *\|
	19	\|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *\|
	20	\|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *\|
	21	\|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *\|
	22	\|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *\|
	23	\|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *\|
	24	\|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *\|
	25	\|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *\|
	26	\|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *\|
	27	\|* *\|
	28	\|* U.S. Government End Users. This source code is a "commercial *\|
	29	\|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *\|
	30	\|* consisting of "commercial computer software" and "commercial *\|
	31	\|* computer software documentation," as such terms are used in *\|
	32	\|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *\|
	33	\|* ment only as a commercial end item. Consistent with 48 C.F.R. *\|
	34	\|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *\|
	35	\|* all U.S. Government End Users acquire the source code with only *\|
	36	\|* those rights set forth herein. *\|
	37	\|* *\|
	38	\***************************************************************************/
	39
	40	/*
	41	* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
	42	* XFree86 'nv' driver, this source code is provided under MIT-style licensing
	43	* where the source code is provided "as is" without warranty of any kind.
	44	* The only usage restriction is for the copyright notices to be retained
	45	* whenever code is used.
	46	*
	47	* Antonino Daplas <adaplas@pol.net> 2005-03-11
	48	*/
	49
	50	#include <linux/fb.h>
	51	#include "nv_type.h"
	52	#include "nv_proto.h"
	53	#include "nv_dma.h"
	54	#include "nv_local.h"
	55
	56	/* There is a HW race condition with videoram command buffers.
	57	You can't jump to the location of your put offset. We write put
	58	at the jump offset + SKIPS dwords with noop padding in between
	59	to solve this problem */
	60	#define SKIPS 8
	61
	62	static const int NVCopyROP[16] = {
	63	0xCC, /* copy */
	64	0x55 /* invert */
65	};
66
67	static const int NVCopyROP_PM[16] = {
68	0xCA, /* copy */
69	0x5A, /* invert */
70	};
71
e15de77e	72	static inline void nvidiafb_safe_mode(struct fb_info *info)
1da177e4	73	{
e15de77e DJ	74	struct nvidia_par *par = info->par;
	75
	76	touch_softlockup_watchdog();
	77	info->pixmap.scan_align = 1;
	78	par->lockup = 1;
	79	}
	80
	81	static inline void NVFlush(struct fb_info *info)
	82	{
	83	struct nvidia_par *par = info->par;
1da177e4 LT	84	int count = 1000000000;
	85
	86	while (--count && READ_GET(par) != par->dmaPut) ;
	87
	88	if (!count) {
	89	printk("nvidiafb: DMA Flush lockup\n");
e15de77e	90	nvidiafb_safe_mode(info);
1da177e4 LT	91	}
	92	}
	93
e15de77e	94	static inline void NVSync(struct fb_info *info)
1da177e4	95	{
e15de77e	96	struct nvidia_par *par = info->par;
1da177e4 LT	97	int count = 1000000000;
	98
	99	while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
	100
	101	if (!count) {
	102	printk("nvidiafb: DMA Sync lockup\n");
e15de77e	103	nvidiafb_safe_mode(info);
1da177e4 LT	104	}
	105	}
	106
	107	static void NVDmaKickoff(struct nvidia_par *par)
	108	{
	109	if (par->dmaCurrent != par->dmaPut) {
	110	par->dmaPut = par->dmaCurrent;
	111	WRITE_PUT(par, par->dmaPut);
	112	}
	113	}
	114
e15de77e	115	static void NVDmaWait(struct fb_info *info, int size)
1da177e4	116	{
e15de77e	117	struct nvidia_par *par = info->par;
1da177e4 LT	118	int dmaGet;
	119	int count = 1000000000, cnt;
	120	size++;
	121
	122	while (par->dmaFree < size && --count && !par->lockup) {
	123	dmaGet = READ_GET(par);
	124
	125	if (par->dmaPut >= dmaGet) {
	126	par->dmaFree = par->dmaMax - par->dmaCurrent;
	127	if (par->dmaFree < size) {
	128	NVDmaNext(par, 0x20000000);
	129	if (dmaGet <= SKIPS) {
	130	if (par->dmaPut <= SKIPS)
	131	WRITE_PUT(par, SKIPS + 1);
	132	cnt = 1000000000;
	133	do {
	134	dmaGet = READ_GET(par);
	135	} while (--cnt && dmaGet <= SKIPS);
	136	if (!cnt) {
	137	printk("DMA Get lockup\n");
	138	par->lockup = 1;
	139	}
	140	}
	141	WRITE_PUT(par, SKIPS);
	142	par->dmaCurrent = par->dmaPut = SKIPS;
	143	par->dmaFree = dmaGet - (SKIPS + 1);
	144	}
	145	} else
	146	par->dmaFree = dmaGet - par->dmaCurrent - 1;
	147	}
	148
	149	if (!count) {
e15de77e DJ	150	printk("nvidiafb: DMA Wait Lockup\n");
e15de77e DJ	151	nvidiafb_safe_mode(info);
1da177e4 LT	152	}
	153	}
	154
e15de77e	155	static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
1da177e4 LT	156	u32 pat0, u32 pat1)
1da177e4 LT	157	{
e15de77e DJ	158	struct nvidia_par *par = info->par;
	159
	160	NVDmaStart(info, par, PATTERN_COLOR_0, 4);
1da177e4 LT	161	NVDmaNext(par, clr0);
	162	NVDmaNext(par, clr1);
	163	NVDmaNext(par, pat0);
	164	NVDmaNext(par, pat1);
	165	}
	166
e15de77e	167	static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
1da177e4	168	{
e15de77e DJ	169	struct nvidia_par *par = info->par;
e15de77e DJ	170
1da177e4	171	if (planemask != ~0) {
e15de77e	172	NVSetPattern(info, 0, planemask, ~0, ~0);
1da177e4	173	if (par->currentRop != (rop + 32)) {
e15de77e	174	NVDmaStart(info, par, ROP_SET, 1);
1da177e4 LT	175	NVDmaNext(par, NVCopyROP_PM[rop]);
	176	par->currentRop = rop + 32;
	177	}
	178	} else if (par->currentRop != rop) {
	179	if (par->currentRop >= 16)
e15de77e DJ	180	NVSetPattern(info, ~0, ~0, ~0, ~0);
e15de77e DJ	181	NVDmaStart(info, par, ROP_SET, 1);
1da177e4 LT	182	NVDmaNext(par, NVCopyROP[rop]);
	183	par->currentRop = rop;
	184	}
	185	}
	186
	187	static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
	188	int x2, int y2)
	189	{
	190	struct nvidia_par *par = info->par;
	191	int h = y2 - y1 + 1;
	192	int w = x2 - x1 + 1;
	193
e15de77e	194	NVDmaStart(info, par, CLIP_POINT, 2);
1da177e4 LT	195	NVDmaNext(par, (y1 << 16) \| x1);
	196	NVDmaNext(par, (h << 16) \| w);
	197	}
	198
	199	void NVResetGraphics(struct fb_info *info)
	200	{
	201	struct nvidia_par *par = info->par;
	202	u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
	203	int pitch, i;
	204
	205	pitch = info->fix.line_length;
	206
	207	par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
	208
	209	for (i = 0; i < SKIPS; i++)
	210	NV_WR32(&par->dmaBase[i], 0, 0x00000000);
	211
	212	NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
	213	NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
	214	NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
	215	NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
	216	NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
	217	NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
	218	NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
	219	NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
	220	NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
	221	NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
	222	NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
	223	NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
	224	NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
	225	NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
	226	NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
	227	NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
	228
	229	par->dmaPut = 0;
	230	par->dmaCurrent = 16 + SKIPS;
	231	par->dmaMax = 8191;
	232	par->dmaFree = par->dmaMax - par->dmaCurrent;
	233
	234	switch (info->var.bits_per_pixel) {
	235	case 32:
	236	case 24:
	237	surfaceFormat = SURFACE_FORMAT_DEPTH24;
	238	patternFormat = PATTERN_FORMAT_DEPTH24;
	239	rectFormat = RECT_FORMAT_DEPTH24;
	240	lineFormat = LINE_FORMAT_DEPTH24;
	241	break;
	242	case 16:
	243	surfaceFormat = SURFACE_FORMAT_DEPTH16;
	244	patternFormat = PATTERN_FORMAT_DEPTH16;
	245	rectFormat = RECT_FORMAT_DEPTH16;
	246	lineFormat = LINE_FORMAT_DEPTH16;
	247	break;
	248	default:
	249	surfaceFormat = SURFACE_FORMAT_DEPTH8;
	250	patternFormat = PATTERN_FORMAT_DEPTH8;
	251	rectFormat = RECT_FORMAT_DEPTH8;
	252	lineFormat = LINE_FORMAT_DEPTH8;
	253	break;
	254	}
	255
e15de77e	256	NVDmaStart(info, par, SURFACE_FORMAT, 4);
1da177e4 LT	257	NVDmaNext(par, surfaceFormat);
	258	NVDmaNext(par, pitch \| (pitch << 16));
	259	NVDmaNext(par, 0);
	260	NVDmaNext(par, 0);
	261
e15de77e	262	NVDmaStart(info, par, PATTERN_FORMAT, 1);
1da177e4 LT	263	NVDmaNext(par, patternFormat);
1da177e4 LT	264
e15de77e	265	NVDmaStart(info, par, RECT_FORMAT, 1);
1da177e4 LT	266	NVDmaNext(par, rectFormat);
1da177e4 LT	267
e15de77e	268	NVDmaStart(info, par, LINE_FORMAT, 1);
1da177e4 LT	269	NVDmaNext(par, lineFormat);
	270
	271	par->currentRop = ~0; /* set to something invalid */
e15de77e	272	NVSetRopSolid(info, ROP_COPY, ~0);
1da177e4 LT	273
	274	NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
	275	info->var.yres_virtual);
	276
	277	NVDmaKickoff(par);
	278	}
	279
1da177e4 LT	280	int nvidiafb_sync(struct fb_info *info)
	281	{
	282	struct nvidia_par *par = info->par;
	283
7a07cd78 AD	284	if (info->state != FBINFO_STATE_RUNNING)
	285	return 0;
	286
1da177e4	287	if (!par->lockup)
e15de77e	288	NVFlush(info);
1da177e4 LT	289
1da177e4 LT	290	if (!par->lockup)
e15de77e	291	NVSync(info);
1da177e4 LT	292
	293	return 0;
	294	}
	295
	296	void nvidiafb_copyarea(struct fb_info info, const struct fb_copyarea region)
	297	{
	298	struct nvidia_par *par = info->par;
	299
7a07cd78 AD	300	if (info->state != FBINFO_STATE_RUNNING)
	301	return;
	302
68751459 HE	303	if (par->lockup) {
	304	cfb_copyarea(info, region);
	305	return;
	306	}
1da177e4	307
e15de77e	308	NVDmaStart(info, par, BLIT_POINT_SRC, 3);
1da177e4 LT	309	NVDmaNext(par, (region->sy << 16) \| region->sx);
	310	NVDmaNext(par, (region->dy << 16) \| region->dx);
	311	NVDmaNext(par, (region->height << 16) \| region->width);
	312
	313	NVDmaKickoff(par);
	314	}
	315
	316	void nvidiafb_fillrect(struct fb_info info, const struct fb_fillrect rect)
	317	{
	318	struct nvidia_par *par = info->par;
	319	u32 color;
	320
7a07cd78 AD	321	if (info->state != FBINFO_STATE_RUNNING)
	322	return;
	323
68751459 HE	324	if (par->lockup) {
	325	cfb_fillrect(info, rect);
	326	return;
	327	}
1da177e4 LT	328
	329	if (info->var.bits_per_pixel == 8)
	330	color = rect->color;
	331	else
	332	color = ((u32 *) info->pseudo_palette)[rect->color];
	333
	334	if (rect->rop != ROP_COPY)
e15de77e	335	NVSetRopSolid(info, rect->rop, ~0);
1da177e4	336
e15de77e	337	NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
1da177e4 LT	338	NVDmaNext(par, color);
1da177e4 LT	339
e15de77e	340	NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
1da177e4 LT	341	NVDmaNext(par, (rect->dx << 16) \| rect->dy);
	342	NVDmaNext(par, (rect->width << 16) \| rect->height);
	343
	344	NVDmaKickoff(par);
	345
	346	if (rect->rop != ROP_COPY)
e15de77e	347	NVSetRopSolid(info, ROP_COPY, ~0);
1da177e4 LT	348	}
	349
	350	static void nvidiafb_mono_color_expand(struct fb_info *info,
	351	const struct fb_image *image)
	352	{
	353	struct nvidia_par *par = info->par;
	354	u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
	355	u32 dsize, width, data = (u32 ) image->data, tmp;
	356	int j, k = 0;
	357
	358	width = (image->width + 31) & ~31;
	359	dsize = (width * image->height) >> 5;
	360
	361	if (info->var.bits_per_pixel == 8) {
	362	fg = image->fg_color \| mask;
	363	bg = image->bg_color \| mask;
	364	} else {
	365	fg = ((u32 *) info->pseudo_palette)[image->fg_color] \| mask;
	366	bg = ((u32 *) info->pseudo_palette)[image->bg_color] \| mask;
	367	}
	368
e15de77e	369	NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
1da177e4 LT	370	NVDmaNext(par, (image->dy << 16) \| (image->dx & 0xffff));
	371	NVDmaNext(par, ((image->dy + image->height) << 16) \|
	372	((image->dx + image->width) & 0xffff));
	373	NVDmaNext(par, bg);
	374	NVDmaNext(par, fg);
	375	NVDmaNext(par, (image->height << 16) \| width);
	376	NVDmaNext(par, (image->height << 16) \| width);
	377	NVDmaNext(par, (image->dy << 16) \| (image->dx & 0xffff));
	378
	379	while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
e15de77e	380	NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
1da177e4 LT	381	RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
	382
	383	for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
	384	tmp = data[k++];
	385	reverse_order(&tmp);
	386	NVDmaNext(par, tmp);
	387	}
	388
	389	dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
	390	}
	391
	392	if (dsize) {
e15de77e	393	NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
1da177e4 LT	394
	395	for (j = dsize; j--;) {
	396	tmp = data[k++];
	397	reverse_order(&tmp);
	398	NVDmaNext(par, tmp);
	399	}
	400	}
	401
	402	NVDmaKickoff(par);
	403	}
	404
	405	void nvidiafb_imageblit(struct fb_info info, const struct fb_image image)
	406	{
	407	struct nvidia_par *par = info->par;
	408
7a07cd78 AD	409	if (info->state != FBINFO_STATE_RUNNING)
	410	return;
	411
1da177e4 LT	412	if (image->depth == 1 && !par->lockup)
	413	nvidiafb_mono_color_expand(info, image);
	414	else
	415	cfb_imageblit(info, image);
	416	}