[mirror_ubuntu-bionic-kernel.git] / drivers / video / nvidia / nv_accel.c

 /***************************************************************************\
|*                                                                           *|
|*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
|*                                                                           *|
|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
|*     international laws.  Users and possessors of this source code are     *|
|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
|*     use this code in individual and commercial software.                  *|
|*                                                                           *|
|*     Any use of this source code must include,  in the user documenta-     *|
|*     tion and  internal comments to the code,  notices to the end user     *|
|*     as follows:                                                           *|
|*                                                                           *|
|*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
|*                                                                           *|
|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
|*                                                                           *|
|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
|*     consisting  of "commercial  computer  software"  and  "commercial     *|
|*     computer  software  documentation,"  as such  terms  are  used in     *|
|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
|*     all U.S. Government End Users  acquire the source code  with only     *|
|*     those rights set forth herein.                                        *|
|*                                                                           *|
 \***************************************************************************/

/*
 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
 * where the source code is provided "as is" without warranty of any kind.
 * The only usage restriction is for the copyright notices to be retained
 * whenever code is used.
 *
 * Antonino Daplas <adaplas@pol.net> 2005-03-11
 */

#include <linux/fb.h>
#include "nv_type.h"
#include "nv_proto.h"
#include "nv_dma.h"
#include "nv_local.h"

/* There is a HW race condition with videoram command buffers.
   You can't jump to the location of your put offset.  We write put
   at the jump offset + SKIPS dwords with noop padding in between
   to solve this problem */
#define SKIPS  8

static const int NVCopyROP[16] = {
	0xCC,			/* copy   */
	0x55			/* invert */
};

static const int NVCopyROP_PM[16] = {
	0xCA,			/* copy  */
	0x5A,			/* invert */
};

static inline void NVFlush(struct nvidia_par *par)
{
	int count = 1000000000;

	while (--count && READ_GET(par) != par->dmaPut) ;

	if (!count) {
		printk("nvidiafb: DMA Flush lockup\n");
		par->lockup = 1;
	}
}

static inline void NVSync(struct nvidia_par *par)
{
	int count = 1000000000;

	while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;

	if (!count) {
		printk("nvidiafb: DMA Sync lockup\n");
		par->lockup = 1;
	}
}

static void NVDmaKickoff(struct nvidia_par *par)
{
	if (par->dmaCurrent != par->dmaPut) {
		par->dmaPut = par->dmaCurrent;
		WRITE_PUT(par, par->dmaPut);
	}
}

static void NVDmaWait(struct nvidia_par *par, int size)
{
	int dmaGet;
	int count = 1000000000, cnt;
	size++;

	while (par->dmaFree < size && --count && !par->lockup) {
		dmaGet = READ_GET(par);

		if (par->dmaPut >= dmaGet) {
			par->dmaFree = par->dmaMax - par->dmaCurrent;
			if (par->dmaFree < size) {
				NVDmaNext(par, 0x20000000);
				if (dmaGet <= SKIPS) {
					if (par->dmaPut <= SKIPS)
						WRITE_PUT(par, SKIPS + 1);
					cnt = 1000000000;
					do {
						dmaGet = READ_GET(par);
					} while (--cnt && dmaGet <= SKIPS);
					if (!cnt) {
						printk("DMA Get lockup\n");
						par->lockup = 1;
					}
				}
				WRITE_PUT(par, SKIPS);
				par->dmaCurrent = par->dmaPut = SKIPS;
				par->dmaFree = dmaGet - (SKIPS + 1);
			}
		} else
			par->dmaFree = dmaGet - par->dmaCurrent - 1;
	}

	if (!count) {
		printk("DMA Wait Lockup\n");
		par->lockup = 1;
	}
}

static void NVSetPattern(struct nvidia_par *par, u32 clr0, u32 clr1,
			 u32 pat0, u32 pat1)
{
	NVDmaStart(par, PATTERN_COLOR_0, 4);
	NVDmaNext(par, clr0);
	NVDmaNext(par, clr1);
	NVDmaNext(par, pat0);
	NVDmaNext(par, pat1);
}

static void NVSetRopSolid(struct nvidia_par *par, u32 rop, u32 planemask)
{
	if (planemask != ~0) {
		NVSetPattern(par, 0, planemask, ~0, ~0);
		if (par->currentRop != (rop + 32)) {
			NVDmaStart(par, ROP_SET, 1);
			NVDmaNext(par, NVCopyROP_PM[rop]);
			par->currentRop = rop + 32;
		}
	} else if (par->currentRop != rop) {
		if (par->currentRop >= 16)
			NVSetPattern(par, ~0, ~0, ~0, ~0);
		NVDmaStart(par, ROP_SET, 1);
		NVDmaNext(par, NVCopyROP[rop]);
		par->currentRop = rop;
	}
}

static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
				   int x2, int y2)
{
	struct nvidia_par *par = info->par;
	int h = y2 - y1 + 1;
	int w = x2 - x1 + 1;

	NVDmaStart(par, CLIP_POINT, 2);
	NVDmaNext(par, (y1 << 16) | x1);
	NVDmaNext(par, (h << 16) | w);
}

void NVResetGraphics(struct fb_info *info)
{
	struct nvidia_par *par = info->par;
	u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
	int pitch, i;

	pitch = info->fix.line_length;

	par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);

	for (i = 0; i < SKIPS; i++)
		NV_WR32(&par->dmaBase[i], 0, 0x00000000);

	NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
	NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
	NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
	NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
	NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
	NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
	NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
	NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
	NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
	NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
	NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
	NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
	NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
	NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
	NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
	NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);

	par->dmaPut = 0;
	par->dmaCurrent = 16 + SKIPS;
	par->dmaMax = 8191;
	par->dmaFree = par->dmaMax - par->dmaCurrent;

	switch (info->var.bits_per_pixel) {
	case 32:
	case 24:
		surfaceFormat = SURFACE_FORMAT_DEPTH24;
		patternFormat = PATTERN_FORMAT_DEPTH24;
		rectFormat = RECT_FORMAT_DEPTH24;
		lineFormat = LINE_FORMAT_DEPTH24;
		break;
	case 16:
		surfaceFormat = SURFACE_FORMAT_DEPTH16;
		patternFormat = PATTERN_FORMAT_DEPTH16;
		rectFormat = RECT_FORMAT_DEPTH16;
		lineFormat = LINE_FORMAT_DEPTH16;
		break;
	default:
		surfaceFormat = SURFACE_FORMAT_DEPTH8;
		patternFormat = PATTERN_FORMAT_DEPTH8;
		rectFormat = RECT_FORMAT_DEPTH8;
		lineFormat = LINE_FORMAT_DEPTH8;
		break;
	}

	NVDmaStart(par, SURFACE_FORMAT, 4);
	NVDmaNext(par, surfaceFormat);
	NVDmaNext(par, pitch | (pitch << 16));
	NVDmaNext(par, 0);
	NVDmaNext(par, 0);

	NVDmaStart(par, PATTERN_FORMAT, 1);
	NVDmaNext(par, patternFormat);

	NVDmaStart(par, RECT_FORMAT, 1);
	NVDmaNext(par, rectFormat);

	NVDmaStart(par, LINE_FORMAT, 1);
	NVDmaNext(par, lineFormat);

	par->currentRop = ~0;	/* set to something invalid */
	NVSetRopSolid(par, ROP_COPY, ~0);

	NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
			       info->var.yres_virtual);

	NVDmaKickoff(par);
}

int nvidiafb_sync(struct fb_info *info)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return 0;

	if (!par->lockup)
		NVFlush(par);

	if (!par->lockup)
		NVSync(par);

	return 0;
}

void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (par->lockup)
		return cfb_copyarea(info, region);

	NVDmaStart(par, BLIT_POINT_SRC, 3);
	NVDmaNext(par, (region->sy << 16) | region->sx);
	NVDmaNext(par, (region->dy << 16) | region->dx);
	NVDmaNext(par, (region->height << 16) | region->width);

	NVDmaKickoff(par);
}

void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct nvidia_par *par = info->par;
	u32 color;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (par->lockup)
		return cfb_fillrect(info, rect);

	if (info->var.bits_per_pixel == 8)
		color = rect->color;
	else
		color = ((u32 *) info->pseudo_palette)[rect->color];

	if (rect->rop != ROP_COPY)
		NVSetRopSolid(par, rect->rop, ~0);

	NVDmaStart(par, RECT_SOLID_COLOR, 1);
	NVDmaNext(par, color);

	NVDmaStart(par, RECT_SOLID_RECTS(0), 2);
	NVDmaNext(par, (rect->dx << 16) | rect->dy);
	NVDmaNext(par, (rect->width << 16) | rect->height);

	NVDmaKickoff(par);

	if (rect->rop != ROP_COPY)
		NVSetRopSolid(par, ROP_COPY, ~0);
}

static void nvidiafb_mono_color_expand(struct fb_info *info,
				       const struct fb_image *image)
{
	struct nvidia_par *par = info->par;
	u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
	u32 dsize, width, *data = (u32 *) image->data, tmp;
	int j, k = 0;

	width = (image->width + 31) & ~31;
	dsize = (width * image->height) >> 5;

	if (info->var.bits_per_pixel == 8) {
		fg = image->fg_color | mask;
		bg = image->bg_color | mask;
	} else {
		fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
		bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
	}

	NVDmaStart(par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
	NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
	NVDmaNext(par, ((image->dy + image->height) << 16) |
		  ((image->dx + image->width) & 0xffff));
	NVDmaNext(par, bg);
	NVDmaNext(par, fg);
	NVDmaNext(par, (image->height << 16) | width);
	NVDmaNext(par, (image->height << 16) | width);
	NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));

	while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
		NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0),
			   RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);

		for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
			tmp = data[k++];
			reverse_order(&tmp);
			NVDmaNext(par, tmp);
		}

		dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
	}

	if (dsize) {
		NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);

		for (j = dsize; j--;) {
			tmp = data[k++];
			reverse_order(&tmp);
			NVDmaNext(par, tmp);
		}
	}

	NVDmaKickoff(par);
}

void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct nvidia_par *par = info->par;

	if (info->state != FBINFO_STATE_RUNNING)
		return;

	if (image->depth == 1 && !par->lockup)
		nvidiafb_mono_color_expand(info, image);
	else
		cfb_imageblit(info, image);
}
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************\
	2	\|* *\|
	3	\|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *\|
	4	\|* *\|
	5	\|* NOTICE TO USER: The source code is copyrighted under U.S. and *\|
	6	\|* international laws. Users and possessors of this source code are *\|
	7	\|* hereby granted a nonexclusive, royalty-free copyright license to *\|
	8	\|* use this code in individual and commercial software. *\|
	9	\|* *\|
	10	\|* Any use of this source code must include, in the user documenta- *\|
	11	\|* tion and internal comments to the code, notices to the end user *\|
	12	\|* as follows: *\|
	13	\|* *\|
	14	\|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *\|
	15	\|* *\|
	16	\|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *\|
	17	\|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *\|
	18	\|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *\|
	19	\|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *\|
	20	\|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *\|
	21	\|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *\|
	22	\|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *\|
	23	\|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *\|
	24	\|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *\|
	25	\|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *\|
	26	\|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *\|
	27	\|* *\|
	28	\|* U.S. Government End Users. This source code is a "commercial *\|
	29	\|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *\|
	30	\|* consisting of "commercial computer software" and "commercial *\|
	31	\|* computer software documentation," as such terms are used in *\|
	32	\|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *\|
	33	\|* ment only as a commercial end item. Consistent with 48 C.F.R. *\|
	34	\|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *\|
	35	\|* all U.S. Government End Users acquire the source code with only *\|
	36	\|* those rights set forth herein. *\|
	37	\|* *\|
	38	\***************************************************************************/
	39
	40	/*
	41	* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
	42	* XFree86 'nv' driver, this source code is provided under MIT-style licensing
	43	* where the source code is provided "as is" without warranty of any kind.
	44	* The only usage restriction is for the copyright notices to be retained
	45	* whenever code is used.
	46	*
	47	* Antonino Daplas <adaplas@pol.net> 2005-03-11
	48	*/
	49
	50	#include <linux/fb.h>
	51	#include "nv_type.h"
	52	#include "nv_proto.h"
	53	#include "nv_dma.h"
	54	#include "nv_local.h"
	55
	56	/* There is a HW race condition with videoram command buffers.
	57	You can't jump to the location of your put offset. We write put
	58	at the jump offset + SKIPS dwords with noop padding in between
	59	to solve this problem */
	60	#define SKIPS 8
	61
	62	static const int NVCopyROP[16] = {
	63	0xCC, /* copy */
	64	0x55 /* invert */
65	};
66
67	static const int NVCopyROP_PM[16] = {
68	0xCA, /* copy */
69	0x5A, /* invert */
70	};
71
72	static inline void NVFlush(struct nvidia_par *par)
73	{
74	int count = 1000000000;
75
76	while (--count && READ_GET(par) != par->dmaPut) ;
77
78	if (!count) {
79	printk("nvidiafb: DMA Flush lockup\n");
80	par->lockup = 1;
81	}
82	}
83
84	static inline void NVSync(struct nvidia_par *par)
85	{
86	int count = 1000000000;
87
88	while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
89
90	if (!count) {
91	printk("nvidiafb: DMA Sync lockup\n");
92	par->lockup = 1;
93	}
94	}
95
96	static void NVDmaKickoff(struct nvidia_par *par)
97	{
98	if (par->dmaCurrent != par->dmaPut) {
99	par->dmaPut = par->dmaCurrent;
100	WRITE_PUT(par, par->dmaPut);
101	}
102	}
103
104	static void NVDmaWait(struct nvidia_par *par, int size)
105	{
106	int dmaGet;
107	int count = 1000000000, cnt;
108	size++;
109
110	while (par->dmaFree < size && --count && !par->lockup) {
111	dmaGet = READ_GET(par);
112
113	if (par->dmaPut >= dmaGet) {
114	par->dmaFree = par->dmaMax - par->dmaCurrent;
115	if (par->dmaFree < size) {
116	NVDmaNext(par, 0x20000000);
117	if (dmaGet <= SKIPS) {
118	if (par->dmaPut <= SKIPS)
119	WRITE_PUT(par, SKIPS + 1);
120	cnt = 1000000000;
121	do {
122	dmaGet = READ_GET(par);
123	} while (--cnt && dmaGet <= SKIPS);
124	if (!cnt) {
125	printk("DMA Get lockup\n");
126	par->lockup = 1;
127	}
128	}
129	WRITE_PUT(par, SKIPS);
130	par->dmaCurrent = par->dmaPut = SKIPS;
131	par->dmaFree = dmaGet - (SKIPS + 1);
132	}
133	} else
134	par->dmaFree = dmaGet - par->dmaCurrent - 1;
135	}
136
137	if (!count) {
138	printk("DMA Wait Lockup\n");
139	par->lockup = 1;
140	}
141	}
142
143	static void NVSetPattern(struct nvidia_par *par, u32 clr0, u32 clr1,
144	u32 pat0, u32 pat1)
145	{
146	NVDmaStart(par, PATTERN_COLOR_0, 4);
147	NVDmaNext(par, clr0);
148	NVDmaNext(par, clr1);
149	NVDmaNext(par, pat0);
150	NVDmaNext(par, pat1);
151	}
152
153	static void NVSetRopSolid(struct nvidia_par *par, u32 rop, u32 planemask)
154	{
155	if (planemask != ~0) {
156	NVSetPattern(par, 0, planemask, ~0, ~0);
157	if (par->currentRop != (rop + 32)) {
158	NVDmaStart(par, ROP_SET, 1);
159	NVDmaNext(par, NVCopyROP_PM[rop]);
160	par->currentRop = rop + 32;
161	}
162	} else if (par->currentRop != rop) {
163	if (par->currentRop >= 16)
164	NVSetPattern(par, ~0, ~0, ~0, ~0);
165	NVDmaStart(par, ROP_SET, 1);
166	NVDmaNext(par, NVCopyROP[rop]);
167	par->currentRop = rop;
168	}
169	}
170
171	static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
172	int x2, int y2)
173	{
174	struct nvidia_par *par = info->par;
175	int h = y2 - y1 + 1;
176	int w = x2 - x1 + 1;
177
178	NVDmaStart(par, CLIP_POINT, 2);
179	NVDmaNext(par, (y1 << 16) \| x1);
180	NVDmaNext(par, (h << 16) \| w);
181	}
182
183	void NVResetGraphics(struct fb_info *info)
184	{
185	struct nvidia_par *par = info->par;
186	u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
187	int pitch, i;
188
189	pitch = info->fix.line_length;
190
191	par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
192
193	for (i = 0; i < SKIPS; i++)
194	NV_WR32(&par->dmaBase[i], 0, 0x00000000);
195
196	NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
197	NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
198	NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
199	NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
200	NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
201	NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
202	NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
203	NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
204	NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
205	NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
206	NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
207	NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
208	NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
209	NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
210	NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
211	NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
212
213	par->dmaPut = 0;
214	par->dmaCurrent = 16 + SKIPS;
215	par->dmaMax = 8191;
216	par->dmaFree = par->dmaMax - par->dmaCurrent;
217
218	switch (info->var.bits_per_pixel) {
219	case 32:
220	case 24:
221	surfaceFormat = SURFACE_FORMAT_DEPTH24;
222	patternFormat = PATTERN_FORMAT_DEPTH24;
223	rectFormat = RECT_FORMAT_DEPTH24;
224	lineFormat = LINE_FORMAT_DEPTH24;
225	break;
226	case 16:
227	surfaceFormat = SURFACE_FORMAT_DEPTH16;
228	patternFormat = PATTERN_FORMAT_DEPTH16;
229	rectFormat = RECT_FORMAT_DEPTH16;
230	lineFormat = LINE_FORMAT_DEPTH16;
231	break;
232	default:
233	surfaceFormat = SURFACE_FORMAT_DEPTH8;
234	patternFormat = PATTERN_FORMAT_DEPTH8;
235	rectFormat = RECT_FORMAT_DEPTH8;
236	lineFormat = LINE_FORMAT_DEPTH8;
237	break;
238	}
239
240	NVDmaStart(par, SURFACE_FORMAT, 4);
241	NVDmaNext(par, surfaceFormat);
242	NVDmaNext(par, pitch \| (pitch << 16));
243	NVDmaNext(par, 0);
244	NVDmaNext(par, 0);
245
246	NVDmaStart(par, PATTERN_FORMAT, 1);
247	NVDmaNext(par, patternFormat);
248
249	NVDmaStart(par, RECT_FORMAT, 1);
250	NVDmaNext(par, rectFormat);
251
252	NVDmaStart(par, LINE_FORMAT, 1);
253	NVDmaNext(par, lineFormat);
254
255	par->currentRop = ~0; /* set to something invalid */
256	NVSetRopSolid(par, ROP_COPY, ~0);
257
258	NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
259	info->var.yres_virtual);
260
261	NVDmaKickoff(par);
262	}
263
1da177e4 LT	264	int nvidiafb_sync(struct fb_info *info)
	265	{
	266	struct nvidia_par *par = info->par;
	267
7a07cd78 AD	268	if (info->state != FBINFO_STATE_RUNNING)
	269	return 0;
	270
1da177e4 LT	271	if (!par->lockup)
	272	NVFlush(par);
	273
	274	if (!par->lockup)
	275	NVSync(par);
	276
	277	return 0;
	278	}
	279
	280	void nvidiafb_copyarea(struct fb_info info, const struct fb_copyarea region)
	281	{
	282	struct nvidia_par *par = info->par;
	283
7a07cd78 AD	284	if (info->state != FBINFO_STATE_RUNNING)
	285	return;
	286
1da177e4 LT	287	if (par->lockup)
	288	return cfb_copyarea(info, region);
	289
	290	NVDmaStart(par, BLIT_POINT_SRC, 3);
	291	NVDmaNext(par, (region->sy << 16) \| region->sx);
	292	NVDmaNext(par, (region->dy << 16) \| region->dx);
	293	NVDmaNext(par, (region->height << 16) \| region->width);
	294
	295	NVDmaKickoff(par);
	296	}
	297
	298	void nvidiafb_fillrect(struct fb_info info, const struct fb_fillrect rect)
	299	{
	300	struct nvidia_par *par = info->par;
	301	u32 color;
	302
7a07cd78 AD	303	if (info->state != FBINFO_STATE_RUNNING)
	304	return;
	305
1da177e4 LT	306	if (par->lockup)
	307	return cfb_fillrect(info, rect);
	308
	309	if (info->var.bits_per_pixel == 8)
	310	color = rect->color;
	311	else
	312	color = ((u32 *) info->pseudo_palette)[rect->color];
	313
	314	if (rect->rop != ROP_COPY)
	315	NVSetRopSolid(par, rect->rop, ~0);
	316
	317	NVDmaStart(par, RECT_SOLID_COLOR, 1);
	318	NVDmaNext(par, color);
	319
	320	NVDmaStart(par, RECT_SOLID_RECTS(0), 2);
	321	NVDmaNext(par, (rect->dx << 16) \| rect->dy);
	322	NVDmaNext(par, (rect->width << 16) \| rect->height);
	323
	324	NVDmaKickoff(par);
	325
	326	if (rect->rop != ROP_COPY)
	327	NVSetRopSolid(par, ROP_COPY, ~0);
	328	}
	329
	330	static void nvidiafb_mono_color_expand(struct fb_info *info,
	331	const struct fb_image *image)
	332	{
	333	struct nvidia_par *par = info->par;
	334	u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
	335	u32 dsize, width, data = (u32 ) image->data, tmp;
	336	int j, k = 0;
	337
	338	width = (image->width + 31) & ~31;
	339	dsize = (width * image->height) >> 5;
	340
	341	if (info->var.bits_per_pixel == 8) {
	342	fg = image->fg_color \| mask;
	343	bg = image->bg_color \| mask;
	344	} else {
	345	fg = ((u32 *) info->pseudo_palette)[image->fg_color] \| mask;
	346	bg = ((u32 *) info->pseudo_palette)[image->bg_color] \| mask;
	347	}
	348
	349	NVDmaStart(par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
	350	NVDmaNext(par, (image->dy << 16) \| (image->dx & 0xffff));
	351	NVDmaNext(par, ((image->dy + image->height) << 16) \|
	352	((image->dx + image->width) & 0xffff));
	353	NVDmaNext(par, bg);
	354	NVDmaNext(par, fg);
	355	NVDmaNext(par, (image->height << 16) \| width);
	356	NVDmaNext(par, (image->height << 16) \| width);
	357	NVDmaNext(par, (image->dy << 16) \| (image->dx & 0xffff));
	358
	359	while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
	360	NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0),
	361	RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
	362
	363	for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
	364	tmp = data[k++];
	365	reverse_order(&tmp);
	366	NVDmaNext(par, tmp);
	367	}
	368
	369	dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
370	}
371
372	if (dsize) {
373	NVDmaStart(par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
374
375	for (j = dsize; j--;) {
376	tmp = data[k++];
377	reverse_order(&tmp);
378	NVDmaNext(par, tmp);
379	}
380	}
381
382	NVDmaKickoff(par);
383	}
384
385	void nvidiafb_imageblit(struct fb_info info, const struct fb_image image)
386	{
387	struct nvidia_par *par = info->par;
388
7a07cd78 AD	389	if (info->state != FBINFO_STATE_RUNNING)
	390	return;
	391
1da177e4 LT	392	if (image->depth == 1 && !par->lockup)
	393	nvidiafb_mono_color_expand(info, image);
	394	else
	395	cfb_imageblit(info, image);
	396	}