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7a055fc2 ID |
1 | /* |
2 | * OMAP2 display controller support | |
3 | * | |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Author: Imre Deak <imre.deak@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/dma-mapping.h> | |
27ac792c | 23 | #include <linux/mm.h> |
7a055fc2 ID |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/io.h> | |
27 | ||
ce491cf8 TL |
28 | #include <plat/sram.h> |
29 | #include <plat/omapfb.h> | |
30 | #include <plat/board.h> | |
7a055fc2 ID |
31 | |
32 | #include "dispc.h" | |
33 | ||
34 | #define MODULE_NAME "dispc" | |
35 | ||
36 | #define DSS_BASE 0x48050000 | |
37 | #define DSS_SYSCONFIG 0x0010 | |
38 | ||
39 | #define DISPC_BASE 0x48050400 | |
40 | ||
41 | /* DISPC common */ | |
42 | #define DISPC_REVISION 0x0000 | |
43 | #define DISPC_SYSCONFIG 0x0010 | |
44 | #define DISPC_SYSSTATUS 0x0014 | |
45 | #define DISPC_IRQSTATUS 0x0018 | |
46 | #define DISPC_IRQENABLE 0x001C | |
47 | #define DISPC_CONTROL 0x0040 | |
48 | #define DISPC_CONFIG 0x0044 | |
49 | #define DISPC_CAPABLE 0x0048 | |
50 | #define DISPC_DEFAULT_COLOR0 0x004C | |
51 | #define DISPC_DEFAULT_COLOR1 0x0050 | |
52 | #define DISPC_TRANS_COLOR0 0x0054 | |
53 | #define DISPC_TRANS_COLOR1 0x0058 | |
54 | #define DISPC_LINE_STATUS 0x005C | |
55 | #define DISPC_LINE_NUMBER 0x0060 | |
56 | #define DISPC_TIMING_H 0x0064 | |
57 | #define DISPC_TIMING_V 0x0068 | |
58 | #define DISPC_POL_FREQ 0x006C | |
59 | #define DISPC_DIVISOR 0x0070 | |
60 | #define DISPC_SIZE_DIG 0x0078 | |
61 | #define DISPC_SIZE_LCD 0x007C | |
62 | ||
63 | #define DISPC_DATA_CYCLE1 0x01D4 | |
64 | #define DISPC_DATA_CYCLE2 0x01D8 | |
65 | #define DISPC_DATA_CYCLE3 0x01DC | |
66 | ||
67 | /* DISPC GFX plane */ | |
68 | #define DISPC_GFX_BA0 0x0080 | |
69 | #define DISPC_GFX_BA1 0x0084 | |
70 | #define DISPC_GFX_POSITION 0x0088 | |
71 | #define DISPC_GFX_SIZE 0x008C | |
72 | #define DISPC_GFX_ATTRIBUTES 0x00A0 | |
73 | #define DISPC_GFX_FIFO_THRESHOLD 0x00A4 | |
74 | #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8 | |
75 | #define DISPC_GFX_ROW_INC 0x00AC | |
76 | #define DISPC_GFX_PIXEL_INC 0x00B0 | |
77 | #define DISPC_GFX_WINDOW_SKIP 0x00B4 | |
78 | #define DISPC_GFX_TABLE_BA 0x00B8 | |
79 | ||
80 | /* DISPC Video plane 1/2 */ | |
81 | #define DISPC_VID1_BASE 0x00BC | |
82 | #define DISPC_VID2_BASE 0x014C | |
83 | ||
84 | /* Offsets into DISPC_VID1/2_BASE */ | |
85 | #define DISPC_VID_BA0 0x0000 | |
86 | #define DISPC_VID_BA1 0x0004 | |
87 | #define DISPC_VID_POSITION 0x0008 | |
88 | #define DISPC_VID_SIZE 0x000C | |
89 | #define DISPC_VID_ATTRIBUTES 0x0010 | |
90 | #define DISPC_VID_FIFO_THRESHOLD 0x0014 | |
91 | #define DISPC_VID_FIFO_SIZE_STATUS 0x0018 | |
92 | #define DISPC_VID_ROW_INC 0x001C | |
93 | #define DISPC_VID_PIXEL_INC 0x0020 | |
94 | #define DISPC_VID_FIR 0x0024 | |
95 | #define DISPC_VID_PICTURE_SIZE 0x0028 | |
96 | #define DISPC_VID_ACCU0 0x002C | |
97 | #define DISPC_VID_ACCU1 0x0030 | |
98 | ||
99 | /* 8 elements in 8 byte increments */ | |
100 | #define DISPC_VID_FIR_COEF_H0 0x0034 | |
101 | /* 8 elements in 8 byte increments */ | |
102 | #define DISPC_VID_FIR_COEF_HV0 0x0038 | |
103 | /* 5 elements in 4 byte increments */ | |
104 | #define DISPC_VID_CONV_COEF0 0x0074 | |
105 | ||
106 | #define DISPC_IRQ_FRAMEMASK 0x0001 | |
107 | #define DISPC_IRQ_VSYNC 0x0002 | |
108 | #define DISPC_IRQ_EVSYNC_EVEN 0x0004 | |
109 | #define DISPC_IRQ_EVSYNC_ODD 0x0008 | |
110 | #define DISPC_IRQ_ACBIAS_COUNT_STAT 0x0010 | |
111 | #define DISPC_IRQ_PROG_LINE_NUM 0x0020 | |
112 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW 0x0040 | |
113 | #define DISPC_IRQ_GFX_END_WIN 0x0080 | |
114 | #define DISPC_IRQ_PAL_GAMMA_MASK 0x0100 | |
115 | #define DISPC_IRQ_OCP_ERR 0x0200 | |
116 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW 0x0400 | |
117 | #define DISPC_IRQ_VID1_END_WIN 0x0800 | |
118 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW 0x1000 | |
119 | #define DISPC_IRQ_VID2_END_WIN 0x2000 | |
120 | #define DISPC_IRQ_SYNC_LOST 0x4000 | |
121 | ||
122 | #define DISPC_IRQ_MASK_ALL 0x7fff | |
123 | ||
124 | #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ | |
125 | DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ | |
126 | DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ | |
127 | DISPC_IRQ_SYNC_LOST) | |
128 | ||
129 | #define RFBI_CONTROL 0x48050040 | |
130 | ||
131 | #define MAX_PALETTE_SIZE (256 * 16) | |
132 | ||
133 | #define FLD_MASK(pos, len) (((1 << len) - 1) << pos) | |
134 | ||
135 | #define MOD_REG_FLD(reg, mask, val) \ | |
136 | dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val)); | |
137 | ||
138 | #define OMAP2_SRAM_START 0x40200000 | |
139 | /* Maximum size, in reality this is smaller if SRAM is partially locked. */ | |
140 | #define OMAP2_SRAM_SIZE 0xa0000 /* 640k */ | |
141 | ||
142 | /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */ | |
143 | #define DISPC_MEMTYPE_NUM 2 | |
144 | ||
145 | #define RESMAP_SIZE(_page_cnt) \ | |
146 | ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8) | |
147 | #define RESMAP_PTR(_res_map, _page_nr) \ | |
148 | (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8)) | |
149 | #define RESMAP_MASK(_page_nr) \ | |
150 | (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1))) | |
151 | ||
152 | struct resmap { | |
153 | unsigned long start; | |
154 | unsigned page_cnt; | |
155 | unsigned long *map; | |
156 | }; | |
157 | ||
4c88ef17 DS |
158 | #define MAX_IRQ_HANDLERS 4 |
159 | ||
7a055fc2 | 160 | static struct { |
55c381e4 | 161 | void __iomem *base; |
7a055fc2 ID |
162 | |
163 | struct omapfb_mem_desc mem_desc; | |
164 | struct resmap *res_map[DISPC_MEMTYPE_NUM]; | |
165 | atomic_t map_count[OMAPFB_PLANE_NUM]; | |
166 | ||
167 | dma_addr_t palette_paddr; | |
168 | void *palette_vaddr; | |
169 | ||
170 | int ext_mode; | |
171 | ||
4c88ef17 DS |
172 | struct { |
173 | u32 irq_mask; | |
174 | void (*callback)(void *); | |
175 | void *data; | |
176 | } irq_handlers[MAX_IRQ_HANDLERS]; | |
7a055fc2 ID |
177 | struct completion frame_done; |
178 | ||
179 | int fir_hinc[OMAPFB_PLANE_NUM]; | |
180 | int fir_vinc[OMAPFB_PLANE_NUM]; | |
181 | ||
182 | struct clk *dss_ick, *dss1_fck; | |
183 | struct clk *dss_54m_fck; | |
184 | ||
185 | enum omapfb_update_mode update_mode; | |
186 | struct omapfb_device *fbdev; | |
187 | ||
188 | struct omapfb_color_key color_key; | |
189 | } dispc; | |
190 | ||
191 | static void enable_lcd_clocks(int enable); | |
192 | ||
193 | static void inline dispc_write_reg(int idx, u32 val) | |
194 | { | |
195 | __raw_writel(val, dispc.base + idx); | |
196 | } | |
197 | ||
198 | static u32 inline dispc_read_reg(int idx) | |
199 | { | |
200 | u32 l = __raw_readl(dispc.base + idx); | |
201 | return l; | |
202 | } | |
203 | ||
204 | /* Select RFBI or bypass mode */ | |
205 | static void enable_rfbi_mode(int enable) | |
206 | { | |
b0002e0e | 207 | void __iomem *rfbi_control; |
7a055fc2 ID |
208 | u32 l; |
209 | ||
210 | l = dispc_read_reg(DISPC_CONTROL); | |
211 | /* Enable RFBI, GPIO0/1 */ | |
212 | l &= ~((1 << 11) | (1 << 15) | (1 << 16)); | |
213 | l |= enable ? (1 << 11) : 0; | |
214 | /* RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11 */ | |
215 | l |= 1 << 15; | |
216 | l |= enable ? 0 : (1 << 16); | |
217 | dispc_write_reg(DISPC_CONTROL, l); | |
218 | ||
219 | /* Set bypass mode in RFBI module */ | |
b0002e0e TL |
220 | rfbi_control = ioremap(RFBI_CONTROL, SZ_1K); |
221 | if (!rfbi_control) { | |
222 | pr_err("Unable to ioremap rfbi_control\n"); | |
223 | return; | |
224 | } | |
225 | l = __raw_readl(rfbi_control); | |
7a055fc2 | 226 | l |= enable ? 0 : (1 << 1); |
b0002e0e TL |
227 | __raw_writel(l, rfbi_control); |
228 | iounmap(rfbi_control); | |
7a055fc2 ID |
229 | } |
230 | ||
231 | static void set_lcd_data_lines(int data_lines) | |
232 | { | |
233 | u32 l; | |
234 | int code = 0; | |
235 | ||
236 | switch (data_lines) { | |
237 | case 12: | |
238 | code = 0; | |
239 | break; | |
240 | case 16: | |
241 | code = 1; | |
242 | break; | |
243 | case 18: | |
244 | code = 2; | |
245 | break; | |
246 | case 24: | |
247 | code = 3; | |
248 | break; | |
249 | default: | |
250 | BUG(); | |
251 | } | |
252 | ||
253 | l = dispc_read_reg(DISPC_CONTROL); | |
254 | l &= ~(0x03 << 8); | |
255 | l |= code << 8; | |
256 | dispc_write_reg(DISPC_CONTROL, l); | |
257 | } | |
258 | ||
259 | static void set_load_mode(int mode) | |
260 | { | |
261 | BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY | | |
262 | DISPC_LOAD_CLUT_ONCE_FRAME)); | |
263 | MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1); | |
264 | } | |
265 | ||
266 | void omap_dispc_set_lcd_size(int x, int y) | |
267 | { | |
268 | BUG_ON((x > (1 << 11)) || (y > (1 << 11))); | |
269 | enable_lcd_clocks(1); | |
270 | MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11), | |
271 | ((y - 1) << 16) | (x - 1)); | |
272 | enable_lcd_clocks(0); | |
273 | } | |
274 | EXPORT_SYMBOL(omap_dispc_set_lcd_size); | |
275 | ||
276 | void omap_dispc_set_digit_size(int x, int y) | |
277 | { | |
278 | BUG_ON((x > (1 << 11)) || (y > (1 << 11))); | |
279 | enable_lcd_clocks(1); | |
280 | MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11), | |
281 | ((y - 1) << 16) | (x - 1)); | |
282 | enable_lcd_clocks(0); | |
283 | } | |
284 | EXPORT_SYMBOL(omap_dispc_set_digit_size); | |
285 | ||
286 | static void setup_plane_fifo(int plane, int ext_mode) | |
287 | { | |
288 | const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, | |
289 | DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD, | |
290 | DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD }; | |
291 | const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, | |
292 | DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS, | |
293 | DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS }; | |
294 | int low, high; | |
295 | u32 l; | |
296 | ||
297 | BUG_ON(plane > 2); | |
298 | ||
299 | l = dispc_read_reg(fsz_reg[plane]); | |
fd0eecbd | 300 | l &= FLD_MASK(0, 11); |
7a055fc2 ID |
301 | if (ext_mode) { |
302 | low = l * 3 / 4; | |
303 | high = l; | |
304 | } else { | |
305 | low = l / 4; | |
306 | high = l * 3 / 4; | |
307 | } | |
fd0eecbd | 308 | MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12), |
7a055fc2 ID |
309 | (high << 16) | low); |
310 | } | |
311 | ||
312 | void omap_dispc_enable_lcd_out(int enable) | |
313 | { | |
314 | enable_lcd_clocks(1); | |
315 | MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0); | |
316 | enable_lcd_clocks(0); | |
317 | } | |
318 | EXPORT_SYMBOL(omap_dispc_enable_lcd_out); | |
319 | ||
320 | void omap_dispc_enable_digit_out(int enable) | |
321 | { | |
322 | enable_lcd_clocks(1); | |
323 | MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0); | |
324 | enable_lcd_clocks(0); | |
325 | } | |
326 | EXPORT_SYMBOL(omap_dispc_enable_digit_out); | |
327 | ||
328 | static inline int _setup_plane(int plane, int channel_out, | |
329 | u32 paddr, int screen_width, | |
330 | int pos_x, int pos_y, int width, int height, | |
331 | int color_mode) | |
332 | { | |
333 | const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES, | |
334 | DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, | |
335 | DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; | |
336 | const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0, | |
337 | DISPC_VID2_BASE + DISPC_VID_BA0 }; | |
338 | const u32 ps_reg[] = { DISPC_GFX_POSITION, | |
339 | DISPC_VID1_BASE + DISPC_VID_POSITION, | |
340 | DISPC_VID2_BASE + DISPC_VID_POSITION }; | |
341 | const u32 sz_reg[] = { DISPC_GFX_SIZE, | |
342 | DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE, | |
343 | DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE }; | |
344 | const u32 ri_reg[] = { DISPC_GFX_ROW_INC, | |
345 | DISPC_VID1_BASE + DISPC_VID_ROW_INC, | |
346 | DISPC_VID2_BASE + DISPC_VID_ROW_INC }; | |
347 | const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE, | |
348 | DISPC_VID2_BASE + DISPC_VID_SIZE }; | |
349 | ||
350 | int chout_shift, burst_shift; | |
351 | int chout_val; | |
352 | int color_code; | |
353 | int bpp; | |
354 | int cconv_en; | |
355 | int set_vsize; | |
356 | u32 l; | |
357 | ||
358 | #ifdef VERBOSE | |
359 | dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d" | |
360 | " pos_x %d pos_y %d width %d height %d color_mode %d\n", | |
361 | plane, channel_out, paddr, screen_width, pos_x, pos_y, | |
362 | width, height, color_mode); | |
363 | #endif | |
364 | ||
365 | set_vsize = 0; | |
366 | switch (plane) { | |
367 | case OMAPFB_PLANE_GFX: | |
368 | burst_shift = 6; | |
369 | chout_shift = 8; | |
370 | break; | |
371 | case OMAPFB_PLANE_VID1: | |
372 | case OMAPFB_PLANE_VID2: | |
373 | burst_shift = 14; | |
374 | chout_shift = 16; | |
375 | set_vsize = 1; | |
376 | break; | |
377 | default: | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
381 | switch (channel_out) { | |
382 | case OMAPFB_CHANNEL_OUT_LCD: | |
383 | chout_val = 0; | |
384 | break; | |
385 | case OMAPFB_CHANNEL_OUT_DIGIT: | |
386 | chout_val = 1; | |
387 | break; | |
388 | default: | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
392 | cconv_en = 0; | |
393 | switch (color_mode) { | |
394 | case OMAPFB_COLOR_RGB565: | |
395 | color_code = DISPC_RGB_16_BPP; | |
396 | bpp = 16; | |
397 | break; | |
398 | case OMAPFB_COLOR_YUV422: | |
399 | if (plane == 0) | |
400 | return -EINVAL; | |
401 | color_code = DISPC_UYVY_422; | |
402 | cconv_en = 1; | |
403 | bpp = 16; | |
404 | break; | |
405 | case OMAPFB_COLOR_YUY422: | |
406 | if (plane == 0) | |
407 | return -EINVAL; | |
408 | color_code = DISPC_YUV2_422; | |
409 | cconv_en = 1; | |
410 | bpp = 16; | |
411 | break; | |
412 | default: | |
413 | return -EINVAL; | |
414 | } | |
415 | ||
416 | l = dispc_read_reg(at_reg[plane]); | |
417 | ||
418 | l &= ~(0x0f << 1); | |
419 | l |= color_code << 1; | |
420 | l &= ~(1 << 9); | |
421 | l |= cconv_en << 9; | |
422 | ||
423 | l &= ~(0x03 << burst_shift); | |
424 | l |= DISPC_BURST_8x32 << burst_shift; | |
425 | ||
426 | l &= ~(1 << chout_shift); | |
427 | l |= chout_val << chout_shift; | |
428 | ||
429 | dispc_write_reg(at_reg[plane], l); | |
430 | ||
431 | dispc_write_reg(ba_reg[plane], paddr); | |
432 | MOD_REG_FLD(ps_reg[plane], | |
433 | FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x); | |
434 | ||
435 | MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11), | |
436 | ((height - 1) << 16) | (width - 1)); | |
437 | ||
438 | if (set_vsize) { | |
439 | /* Set video size if set_scale hasn't set it */ | |
440 | if (!dispc.fir_vinc[plane]) | |
441 | MOD_REG_FLD(vs_reg[plane], | |
442 | FLD_MASK(16, 11), (height - 1) << 16); | |
443 | if (!dispc.fir_hinc[plane]) | |
444 | MOD_REG_FLD(vs_reg[plane], | |
445 | FLD_MASK(0, 11), width - 1); | |
446 | } | |
447 | ||
448 | dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1); | |
449 | ||
450 | return height * screen_width * bpp / 8; | |
451 | } | |
452 | ||
453 | static int omap_dispc_setup_plane(int plane, int channel_out, | |
454 | unsigned long offset, | |
455 | int screen_width, | |
456 | int pos_x, int pos_y, int width, int height, | |
457 | int color_mode) | |
458 | { | |
459 | u32 paddr; | |
460 | int r; | |
461 | ||
462 | if ((unsigned)plane > dispc.mem_desc.region_cnt) | |
463 | return -EINVAL; | |
464 | paddr = dispc.mem_desc.region[plane].paddr + offset; | |
465 | enable_lcd_clocks(1); | |
466 | r = _setup_plane(plane, channel_out, paddr, | |
467 | screen_width, | |
468 | pos_x, pos_y, width, height, color_mode); | |
469 | enable_lcd_clocks(0); | |
470 | return r; | |
471 | } | |
472 | ||
473 | static void write_firh_reg(int plane, int reg, u32 value) | |
474 | { | |
475 | u32 base; | |
476 | ||
477 | if (plane == 1) | |
478 | base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0; | |
479 | else | |
480 | base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0; | |
481 | dispc_write_reg(base + reg * 8, value); | |
482 | } | |
483 | ||
484 | static void write_firhv_reg(int plane, int reg, u32 value) | |
485 | { | |
486 | u32 base; | |
487 | ||
488 | if (plane == 1) | |
489 | base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0; | |
490 | else | |
491 | base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0; | |
492 | dispc_write_reg(base + reg * 8, value); | |
493 | } | |
494 | ||
495 | static void set_upsampling_coef_table(int plane) | |
496 | { | |
497 | const u32 coef[][2] = { | |
498 | { 0x00800000, 0x00800000 }, | |
499 | { 0x0D7CF800, 0x037B02FF }, | |
500 | { 0x1E70F5FF, 0x0C6F05FE }, | |
501 | { 0x335FF5FE, 0x205907FB }, | |
502 | { 0xF74949F7, 0x00404000 }, | |
503 | { 0xF55F33FB, 0x075920FE }, | |
504 | { 0xF5701EFE, 0x056F0CFF }, | |
505 | { 0xF87C0DFF, 0x027B0300 }, | |
506 | }; | |
507 | int i; | |
508 | ||
509 | for (i = 0; i < 8; i++) { | |
510 | write_firh_reg(plane, i, coef[i][0]); | |
511 | write_firhv_reg(plane, i, coef[i][1]); | |
512 | } | |
513 | } | |
514 | ||
515 | static int omap_dispc_set_scale(int plane, | |
516 | int orig_width, int orig_height, | |
517 | int out_width, int out_height) | |
518 | { | |
519 | const u32 at_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, | |
520 | DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; | |
521 | const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE, | |
522 | DISPC_VID2_BASE + DISPC_VID_SIZE }; | |
523 | const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR, | |
524 | DISPC_VID2_BASE + DISPC_VID_FIR }; | |
525 | ||
526 | u32 l; | |
527 | int fir_hinc; | |
528 | int fir_vinc; | |
529 | ||
530 | if ((unsigned)plane > OMAPFB_PLANE_NUM) | |
531 | return -ENODEV; | |
532 | ||
533 | if (plane == OMAPFB_PLANE_GFX && | |
534 | (out_width != orig_width || out_height != orig_height)) | |
535 | return -EINVAL; | |
536 | ||
537 | enable_lcd_clocks(1); | |
538 | if (orig_width < out_width) { | |
539 | /* | |
540 | * Upsampling. | |
541 | * Currently you can only scale both dimensions in one way. | |
542 | */ | |
543 | if (orig_height > out_height || | |
544 | orig_width * 8 < out_width || | |
545 | orig_height * 8 < out_height) { | |
546 | enable_lcd_clocks(0); | |
547 | return -EINVAL; | |
548 | } | |
549 | set_upsampling_coef_table(plane); | |
550 | } else if (orig_width > out_width) { | |
551 | /* Downsampling not yet supported | |
552 | */ | |
553 | ||
554 | enable_lcd_clocks(0); | |
555 | return -EINVAL; | |
556 | } | |
557 | if (!orig_width || orig_width == out_width) | |
558 | fir_hinc = 0; | |
559 | else | |
560 | fir_hinc = 1024 * orig_width / out_width; | |
561 | if (!orig_height || orig_height == out_height) | |
562 | fir_vinc = 0; | |
563 | else | |
564 | fir_vinc = 1024 * orig_height / out_height; | |
565 | dispc.fir_hinc[plane] = fir_hinc; | |
566 | dispc.fir_vinc[plane] = fir_vinc; | |
567 | ||
568 | MOD_REG_FLD(fir_reg[plane], | |
569 | FLD_MASK(16, 12) | FLD_MASK(0, 12), | |
570 | ((fir_vinc & 4095) << 16) | | |
571 | (fir_hinc & 4095)); | |
572 | ||
573 | dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d " | |
574 | "orig_height %d fir_hinc %d fir_vinc %d\n", | |
575 | out_width, out_height, orig_width, orig_height, | |
576 | fir_hinc, fir_vinc); | |
577 | ||
578 | MOD_REG_FLD(vs_reg[plane], | |
579 | FLD_MASK(16, 11) | FLD_MASK(0, 11), | |
580 | ((out_height - 1) << 16) | (out_width - 1)); | |
581 | ||
582 | l = dispc_read_reg(at_reg[plane]); | |
583 | l &= ~(0x03 << 5); | |
584 | l |= fir_hinc ? (1 << 5) : 0; | |
585 | l |= fir_vinc ? (1 << 6) : 0; | |
586 | dispc_write_reg(at_reg[plane], l); | |
587 | ||
588 | enable_lcd_clocks(0); | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static int omap_dispc_enable_plane(int plane, int enable) | |
593 | { | |
594 | const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES, | |
595 | DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, | |
596 | DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; | |
597 | if ((unsigned int)plane > dispc.mem_desc.region_cnt) | |
598 | return -EINVAL; | |
599 | ||
600 | enable_lcd_clocks(1); | |
601 | MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0); | |
602 | enable_lcd_clocks(0); | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static int omap_dispc_set_color_key(struct omapfb_color_key *ck) | |
608 | { | |
609 | u32 df_reg, tr_reg; | |
610 | int shift, val; | |
611 | ||
612 | switch (ck->channel_out) { | |
613 | case OMAPFB_CHANNEL_OUT_LCD: | |
614 | df_reg = DISPC_DEFAULT_COLOR0; | |
615 | tr_reg = DISPC_TRANS_COLOR0; | |
616 | shift = 10; | |
617 | break; | |
618 | case OMAPFB_CHANNEL_OUT_DIGIT: | |
619 | df_reg = DISPC_DEFAULT_COLOR1; | |
620 | tr_reg = DISPC_TRANS_COLOR1; | |
621 | shift = 12; | |
622 | break; | |
623 | default: | |
624 | return -EINVAL; | |
625 | } | |
626 | switch (ck->key_type) { | |
627 | case OMAPFB_COLOR_KEY_DISABLED: | |
628 | val = 0; | |
629 | break; | |
630 | case OMAPFB_COLOR_KEY_GFX_DST: | |
631 | val = 1; | |
632 | break; | |
633 | case OMAPFB_COLOR_KEY_VID_SRC: | |
634 | val = 3; | |
635 | break; | |
636 | default: | |
637 | return -EINVAL; | |
638 | } | |
639 | enable_lcd_clocks(1); | |
640 | MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift); | |
641 | ||
642 | if (val != 0) | |
643 | dispc_write_reg(tr_reg, ck->trans_key); | |
644 | dispc_write_reg(df_reg, ck->background); | |
645 | enable_lcd_clocks(0); | |
646 | ||
647 | dispc.color_key = *ck; | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | static int omap_dispc_get_color_key(struct omapfb_color_key *ck) | |
653 | { | |
654 | *ck = dispc.color_key; | |
655 | return 0; | |
656 | } | |
657 | ||
658 | static void load_palette(void) | |
659 | { | |
660 | } | |
661 | ||
662 | static int omap_dispc_set_update_mode(enum omapfb_update_mode mode) | |
663 | { | |
664 | int r = 0; | |
665 | ||
666 | if (mode != dispc.update_mode) { | |
667 | switch (mode) { | |
668 | case OMAPFB_AUTO_UPDATE: | |
669 | case OMAPFB_MANUAL_UPDATE: | |
670 | enable_lcd_clocks(1); | |
671 | omap_dispc_enable_lcd_out(1); | |
672 | dispc.update_mode = mode; | |
673 | break; | |
674 | case OMAPFB_UPDATE_DISABLED: | |
675 | init_completion(&dispc.frame_done); | |
676 | omap_dispc_enable_lcd_out(0); | |
677 | if (!wait_for_completion_timeout(&dispc.frame_done, | |
678 | msecs_to_jiffies(500))) { | |
679 | dev_err(dispc.fbdev->dev, | |
680 | "timeout waiting for FRAME DONE\n"); | |
681 | } | |
682 | dispc.update_mode = mode; | |
683 | enable_lcd_clocks(0); | |
684 | break; | |
685 | default: | |
686 | r = -EINVAL; | |
687 | } | |
688 | } | |
689 | ||
690 | return r; | |
691 | } | |
692 | ||
693 | static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps) | |
694 | { | |
695 | caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM; | |
696 | if (plane > 0) | |
697 | caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE; | |
698 | caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) | | |
699 | (1 << OMAPFB_COLOR_YUV422) | | |
700 | (1 << OMAPFB_COLOR_YUY422); | |
701 | if (plane == 0) | |
702 | caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) | | |
703 | (1 << OMAPFB_COLOR_CLUT_4BPP) | | |
704 | (1 << OMAPFB_COLOR_CLUT_2BPP) | | |
705 | (1 << OMAPFB_COLOR_CLUT_1BPP) | | |
706 | (1 << OMAPFB_COLOR_RGB444); | |
707 | } | |
708 | ||
709 | static enum omapfb_update_mode omap_dispc_get_update_mode(void) | |
710 | { | |
711 | return dispc.update_mode; | |
712 | } | |
713 | ||
714 | static void setup_color_conv_coef(void) | |
715 | { | |
716 | u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11); | |
717 | int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0; | |
718 | int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0; | |
719 | int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES; | |
720 | int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES; | |
721 | const struct color_conv_coef { | |
722 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
723 | int full_range; | |
724 | } ctbl_bt601_5 = { | |
725 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, | |
726 | }; | |
727 | const struct color_conv_coef *ct; | |
728 | #define CVAL(x, y) (((x & 2047) << 16) | (y & 2047)) | |
729 | ||
730 | ct = &ctbl_bt601_5; | |
731 | ||
732 | MOD_REG_FLD(cf1_reg, mask, CVAL(ct->rcr, ct->ry)); | |
733 | MOD_REG_FLD(cf1_reg + 4, mask, CVAL(ct->gy, ct->rcb)); | |
734 | MOD_REG_FLD(cf1_reg + 8, mask, CVAL(ct->gcb, ct->gcr)); | |
735 | MOD_REG_FLD(cf1_reg + 12, mask, CVAL(ct->bcr, ct->by)); | |
736 | MOD_REG_FLD(cf1_reg + 16, mask, CVAL(0, ct->bcb)); | |
737 | ||
738 | MOD_REG_FLD(cf2_reg, mask, CVAL(ct->rcr, ct->ry)); | |
739 | MOD_REG_FLD(cf2_reg + 4, mask, CVAL(ct->gy, ct->rcb)); | |
740 | MOD_REG_FLD(cf2_reg + 8, mask, CVAL(ct->gcb, ct->gcr)); | |
741 | MOD_REG_FLD(cf2_reg + 12, mask, CVAL(ct->bcr, ct->by)); | |
742 | MOD_REG_FLD(cf2_reg + 16, mask, CVAL(0, ct->bcb)); | |
743 | #undef CVAL | |
744 | ||
745 | MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range); | |
746 | MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); | |
747 | } | |
748 | ||
749 | static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) | |
750 | { | |
751 | unsigned long fck, lck; | |
752 | ||
753 | *lck_div = 1; | |
754 | pck = max(1, pck); | |
755 | fck = clk_get_rate(dispc.dss1_fck); | |
756 | lck = fck; | |
757 | *pck_div = (lck + pck - 1) / pck; | |
758 | if (is_tft) | |
759 | *pck_div = max(2, *pck_div); | |
760 | else | |
761 | *pck_div = max(3, *pck_div); | |
762 | if (*pck_div > 255) { | |
763 | *pck_div = 255; | |
764 | lck = pck * *pck_div; | |
765 | *lck_div = fck / lck; | |
766 | BUG_ON(*lck_div < 1); | |
767 | if (*lck_div > 255) { | |
768 | *lck_div = 255; | |
769 | dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n", | |
770 | pck / 1000); | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
775 | static void set_lcd_tft_mode(int enable) | |
776 | { | |
777 | u32 mask; | |
778 | ||
779 | mask = 1 << 3; | |
780 | MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0); | |
781 | } | |
782 | ||
783 | static void set_lcd_timings(void) | |
784 | { | |
785 | u32 l; | |
786 | int lck_div, pck_div; | |
787 | struct lcd_panel *panel = dispc.fbdev->panel; | |
788 | int is_tft = panel->config & OMAP_LCDC_PANEL_TFT; | |
789 | unsigned long fck; | |
790 | ||
791 | l = dispc_read_reg(DISPC_TIMING_H); | |
792 | l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8)); | |
793 | l |= ( max(1, (min(64, panel->hsw))) - 1 ) << 0; | |
794 | l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8; | |
795 | l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20; | |
796 | dispc_write_reg(DISPC_TIMING_H, l); | |
797 | ||
798 | l = dispc_read_reg(DISPC_TIMING_V); | |
799 | l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8)); | |
800 | l |= ( max(1, (min(64, panel->vsw))) - 1 ) << 0; | |
801 | l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8; | |
802 | l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20; | |
803 | dispc_write_reg(DISPC_TIMING_V, l); | |
804 | ||
805 | l = dispc_read_reg(DISPC_POL_FREQ); | |
806 | l &= ~FLD_MASK(12, 6); | |
807 | l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12; | |
808 | l |= panel->acb & 0xff; | |
809 | dispc_write_reg(DISPC_POL_FREQ, l); | |
810 | ||
811 | calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div); | |
812 | ||
813 | l = dispc_read_reg(DISPC_DIVISOR); | |
814 | l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8)); | |
815 | l |= (lck_div << 16) | (pck_div << 0); | |
816 | dispc_write_reg(DISPC_DIVISOR, l); | |
817 | ||
818 | /* update panel info with the exact clock */ | |
819 | fck = clk_get_rate(dispc.dss1_fck); | |
820 | panel->pixel_clock = fck / lck_div / pck_div / 1000; | |
821 | } | |
822 | ||
4c88ef17 | 823 | static void recalc_irq_mask(void) |
7a055fc2 | 824 | { |
4c88ef17 DS |
825 | int i; |
826 | unsigned long irq_mask = DISPC_IRQ_MASK_ERROR; | |
7a055fc2 | 827 | |
4c88ef17 DS |
828 | for (i = 0; i < MAX_IRQ_HANDLERS; i++) { |
829 | if (!dispc.irq_handlers[i].callback) | |
830 | continue; | |
7a055fc2 | 831 | |
4c88ef17 | 832 | irq_mask |= dispc.irq_handlers[i].irq_mask; |
7a055fc2 ID |
833 | } |
834 | ||
7a055fc2 | 835 | enable_lcd_clocks(1); |
7a055fc2 ID |
836 | MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask); |
837 | enable_lcd_clocks(0); | |
838 | } | |
7a055fc2 | 839 | |
4c88ef17 DS |
840 | int omap_dispc_request_irq(unsigned long irq_mask, void (*callback)(void *data), |
841 | void *data) | |
7a055fc2 | 842 | { |
4c88ef17 DS |
843 | int i; |
844 | ||
845 | BUG_ON(callback == NULL); | |
846 | ||
847 | for (i = 0; i < MAX_IRQ_HANDLERS; i++) { | |
848 | if (dispc.irq_handlers[i].callback) | |
849 | continue; | |
850 | ||
851 | dispc.irq_handlers[i].irq_mask = irq_mask; | |
852 | dispc.irq_handlers[i].callback = callback; | |
853 | dispc.irq_handlers[i].data = data; | |
854 | recalc_irq_mask(); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | return -EBUSY; | |
7a055fc2 | 860 | } |
4c88ef17 | 861 | EXPORT_SYMBOL(omap_dispc_request_irq); |
7a055fc2 | 862 | |
4c88ef17 DS |
863 | void omap_dispc_free_irq(unsigned long irq_mask, void (*callback)(void *data), |
864 | void *data) | |
7a055fc2 | 865 | { |
4c88ef17 DS |
866 | int i; |
867 | ||
868 | for (i = 0; i < MAX_IRQ_HANDLERS; i++) { | |
869 | if (dispc.irq_handlers[i].callback == callback && | |
870 | dispc.irq_handlers[i].data == data) { | |
871 | dispc.irq_handlers[i].irq_mask = 0; | |
872 | dispc.irq_handlers[i].callback = NULL; | |
873 | dispc.irq_handlers[i].data = NULL; | |
874 | recalc_irq_mask(); | |
875 | return; | |
876 | } | |
877 | } | |
878 | ||
879 | BUG(); | |
7a055fc2 ID |
880 | } |
881 | EXPORT_SYMBOL(omap_dispc_free_irq); | |
882 | ||
883 | static irqreturn_t omap_dispc_irq_handler(int irq, void *dev) | |
884 | { | |
f9e2bc8d | 885 | u32 stat; |
4c88ef17 | 886 | int i = 0; |
7a055fc2 | 887 | |
f9e2bc8d JH |
888 | enable_lcd_clocks(1); |
889 | ||
890 | stat = dispc_read_reg(DISPC_IRQSTATUS); | |
7a055fc2 ID |
891 | if (stat & DISPC_IRQ_FRAMEMASK) |
892 | complete(&dispc.frame_done); | |
893 | ||
894 | if (stat & DISPC_IRQ_MASK_ERROR) { | |
895 | if (printk_ratelimit()) { | |
896 | dev_err(dispc.fbdev->dev, "irq error status %04x\n", | |
897 | stat & 0x7fff); | |
898 | } | |
899 | } | |
900 | ||
4c88ef17 DS |
901 | for (i = 0; i < MAX_IRQ_HANDLERS; i++) { |
902 | if (unlikely(dispc.irq_handlers[i].callback && | |
903 | (stat & dispc.irq_handlers[i].irq_mask))) | |
904 | dispc.irq_handlers[i].callback( | |
905 | dispc.irq_handlers[i].data); | |
906 | } | |
7a055fc2 ID |
907 | |
908 | dispc_write_reg(DISPC_IRQSTATUS, stat); | |
909 | ||
f9e2bc8d JH |
910 | enable_lcd_clocks(0); |
911 | ||
7a055fc2 ID |
912 | return IRQ_HANDLED; |
913 | } | |
914 | ||
915 | static int get_dss_clocks(void) | |
916 | { | |
005187ee TL |
917 | dispc.dss_ick = clk_get(dispc.fbdev->dev, "ick"); |
918 | if (IS_ERR(dispc.dss_ick)) { | |
919 | dev_err(dispc.fbdev->dev, "can't get ick\n"); | |
7a055fc2 ID |
920 | return PTR_ERR(dispc.dss_ick); |
921 | } | |
922 | ||
005187ee TL |
923 | dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck"); |
924 | if (IS_ERR(dispc.dss1_fck)) { | |
898eb71c | 925 | dev_err(dispc.fbdev->dev, "can't get dss1_fck\n"); |
7a055fc2 ID |
926 | clk_put(dispc.dss_ick); |
927 | return PTR_ERR(dispc.dss1_fck); | |
928 | } | |
929 | ||
005187ee TL |
930 | dispc.dss_54m_fck = clk_get(dispc.fbdev->dev, "tv_fck"); |
931 | if (IS_ERR(dispc.dss_54m_fck)) { | |
932 | dev_err(dispc.fbdev->dev, "can't get tv_fck\n"); | |
7a055fc2 ID |
933 | clk_put(dispc.dss_ick); |
934 | clk_put(dispc.dss1_fck); | |
935 | return PTR_ERR(dispc.dss_54m_fck); | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
941 | static void put_dss_clocks(void) | |
942 | { | |
943 | clk_put(dispc.dss_54m_fck); | |
944 | clk_put(dispc.dss1_fck); | |
945 | clk_put(dispc.dss_ick); | |
946 | } | |
947 | ||
948 | static void enable_lcd_clocks(int enable) | |
949 | { | |
f9e2bc8d JH |
950 | if (enable) { |
951 | clk_enable(dispc.dss_ick); | |
7a055fc2 | 952 | clk_enable(dispc.dss1_fck); |
f9e2bc8d | 953 | } else { |
7a055fc2 | 954 | clk_disable(dispc.dss1_fck); |
7a055fc2 | 955 | clk_disable(dispc.dss_ick); |
f9e2bc8d | 956 | } |
7a055fc2 ID |
957 | } |
958 | ||
959 | static void enable_digit_clocks(int enable) | |
960 | { | |
961 | if (enable) | |
962 | clk_enable(dispc.dss_54m_fck); | |
963 | else | |
964 | clk_disable(dispc.dss_54m_fck); | |
965 | } | |
966 | ||
967 | static void omap_dispc_suspend(void) | |
968 | { | |
969 | if (dispc.update_mode == OMAPFB_AUTO_UPDATE) { | |
970 | init_completion(&dispc.frame_done); | |
971 | omap_dispc_enable_lcd_out(0); | |
972 | if (!wait_for_completion_timeout(&dispc.frame_done, | |
973 | msecs_to_jiffies(500))) { | |
974 | dev_err(dispc.fbdev->dev, | |
975 | "timeout waiting for FRAME DONE\n"); | |
976 | } | |
977 | enable_lcd_clocks(0); | |
978 | } | |
979 | } | |
980 | ||
981 | static void omap_dispc_resume(void) | |
982 | { | |
983 | if (dispc.update_mode == OMAPFB_AUTO_UPDATE) { | |
984 | enable_lcd_clocks(1); | |
985 | if (!dispc.ext_mode) { | |
986 | set_lcd_timings(); | |
987 | load_palette(); | |
988 | } | |
989 | omap_dispc_enable_lcd_out(1); | |
990 | } | |
991 | } | |
992 | ||
993 | ||
994 | static int omap_dispc_update_window(struct fb_info *fbi, | |
995 | struct omapfb_update_window *win, | |
996 | void (*complete_callback)(void *arg), | |
997 | void *complete_callback_data) | |
998 | { | |
999 | return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0; | |
1000 | } | |
1001 | ||
1002 | static int mmap_kern(struct omapfb_mem_region *region) | |
1003 | { | |
1004 | struct vm_struct *kvma; | |
1005 | struct vm_area_struct vma; | |
1006 | pgprot_t pgprot; | |
1007 | unsigned long vaddr; | |
1008 | ||
1009 | kvma = get_vm_area(region->size, VM_IOREMAP); | |
1010 | if (kvma == NULL) { | |
1011 | dev_err(dispc.fbdev->dev, "can't get kernel vm area\n"); | |
1012 | return -ENOMEM; | |
1013 | } | |
1014 | vma.vm_mm = &init_mm; | |
1015 | ||
1016 | vaddr = (unsigned long)kvma->addr; | |
1017 | ||
1018 | pgprot = pgprot_writecombine(pgprot_kernel); | |
1019 | vma.vm_start = vaddr; | |
1020 | vma.vm_end = vaddr + region->size; | |
1021 | if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT, | |
1022 | region->size, pgprot) < 0) { | |
1023 | dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n"); | |
1024 | return -EAGAIN; | |
1025 | } | |
1026 | region->vaddr = (void *)vaddr; | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | static void mmap_user_open(struct vm_area_struct *vma) | |
1032 | { | |
1033 | int plane = (int)vma->vm_private_data; | |
1034 | ||
1035 | atomic_inc(&dispc.map_count[plane]); | |
1036 | } | |
1037 | ||
1038 | static void mmap_user_close(struct vm_area_struct *vma) | |
1039 | { | |
1040 | int plane = (int)vma->vm_private_data; | |
1041 | ||
1042 | atomic_dec(&dispc.map_count[plane]); | |
1043 | } | |
1044 | ||
f0f37e2f | 1045 | static const struct vm_operations_struct mmap_user_ops = { |
7a055fc2 ID |
1046 | .open = mmap_user_open, |
1047 | .close = mmap_user_close, | |
1048 | }; | |
1049 | ||
1050 | static int omap_dispc_mmap_user(struct fb_info *info, | |
1051 | struct vm_area_struct *vma) | |
1052 | { | |
1053 | struct omapfb_plane_struct *plane = info->par; | |
1054 | unsigned long off; | |
1055 | unsigned long start; | |
1056 | u32 len; | |
1057 | ||
1058 | if (vma->vm_end - vma->vm_start == 0) | |
1059 | return 0; | |
1060 | if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) | |
1061 | return -EINVAL; | |
1062 | off = vma->vm_pgoff << PAGE_SHIFT; | |
1063 | ||
1064 | start = info->fix.smem_start; | |
1065 | len = info->fix.smem_len; | |
1066 | if (off >= len) | |
1067 | return -EINVAL; | |
1068 | if ((vma->vm_end - vma->vm_start + off) > len) | |
1069 | return -EINVAL; | |
1070 | off += start; | |
1071 | vma->vm_pgoff = off >> PAGE_SHIFT; | |
1072 | vma->vm_flags |= VM_IO | VM_RESERVED; | |
1073 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
1074 | vma->vm_ops = &mmap_user_ops; | |
1075 | vma->vm_private_data = (void *)plane->idx; | |
1076 | if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, | |
1077 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
1078 | return -EAGAIN; | |
1079 | /* vm_ops.open won't be called for mmap itself. */ | |
1080 | atomic_inc(&dispc.map_count[plane->idx]); | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static void unmap_kern(struct omapfb_mem_region *region) | |
1085 | { | |
1086 | vunmap(region->vaddr); | |
1087 | } | |
1088 | ||
1089 | static int alloc_palette_ram(void) | |
1090 | { | |
1091 | dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev, | |
1092 | MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL); | |
1093 | if (dispc.palette_vaddr == NULL) { | |
1094 | dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n"); | |
1095 | return -ENOMEM; | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static void free_palette_ram(void) | |
1102 | { | |
1103 | dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE, | |
1104 | dispc.palette_vaddr, dispc.palette_paddr); | |
1105 | } | |
1106 | ||
1107 | static int alloc_fbmem(struct omapfb_mem_region *region) | |
1108 | { | |
1109 | region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev, | |
1110 | region->size, ®ion->paddr, GFP_KERNEL); | |
1111 | ||
1112 | if (region->vaddr == NULL) { | |
1113 | dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n"); | |
1114 | return -ENOMEM; | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static void free_fbmem(struct omapfb_mem_region *region) | |
1121 | { | |
1122 | dma_free_writecombine(dispc.fbdev->dev, region->size, | |
1123 | region->vaddr, region->paddr); | |
1124 | } | |
1125 | ||
1126 | static struct resmap *init_resmap(unsigned long start, size_t size) | |
1127 | { | |
1128 | unsigned page_cnt; | |
1129 | struct resmap *res_map; | |
1130 | ||
1131 | page_cnt = PAGE_ALIGN(size) / PAGE_SIZE; | |
1132 | res_map = | |
1133 | kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL); | |
1134 | if (res_map == NULL) | |
1135 | return NULL; | |
1136 | res_map->start = start; | |
1137 | res_map->page_cnt = page_cnt; | |
1138 | res_map->map = (unsigned long *)(res_map + 1); | |
1139 | return res_map; | |
1140 | } | |
1141 | ||
1142 | static void cleanup_resmap(struct resmap *res_map) | |
1143 | { | |
1144 | kfree(res_map); | |
1145 | } | |
1146 | ||
1147 | static inline int resmap_mem_type(unsigned long start) | |
1148 | { | |
1149 | if (start >= OMAP2_SRAM_START && | |
1150 | start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE) | |
1151 | return OMAPFB_MEMTYPE_SRAM; | |
1152 | else | |
1153 | return OMAPFB_MEMTYPE_SDRAM; | |
1154 | } | |
1155 | ||
1156 | static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr) | |
1157 | { | |
1158 | return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0; | |
1159 | } | |
1160 | ||
1161 | static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr) | |
1162 | { | |
1163 | BUG_ON(resmap_page_reserved(res_map, page_nr)); | |
1164 | *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr); | |
1165 | } | |
1166 | ||
1167 | static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr) | |
1168 | { | |
1169 | BUG_ON(!resmap_page_reserved(res_map, page_nr)); | |
1170 | *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr); | |
1171 | } | |
1172 | ||
1173 | static void resmap_reserve_region(unsigned long start, size_t size) | |
1174 | { | |
1175 | ||
1176 | struct resmap *res_map; | |
1177 | unsigned start_page; | |
1178 | unsigned end_page; | |
1179 | int mtype; | |
1180 | unsigned i; | |
1181 | ||
1182 | mtype = resmap_mem_type(start); | |
1183 | res_map = dispc.res_map[mtype]; | |
1184 | dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n", | |
1185 | mtype, start, size); | |
1186 | start_page = (start - res_map->start) / PAGE_SIZE; | |
1187 | end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE; | |
1188 | for (i = start_page; i < end_page; i++) | |
1189 | resmap_reserve_page(res_map, i); | |
1190 | } | |
1191 | ||
1192 | static void resmap_free_region(unsigned long start, size_t size) | |
1193 | { | |
1194 | struct resmap *res_map; | |
1195 | unsigned start_page; | |
1196 | unsigned end_page; | |
1197 | unsigned i; | |
1198 | int mtype; | |
1199 | ||
1200 | mtype = resmap_mem_type(start); | |
1201 | res_map = dispc.res_map[mtype]; | |
1202 | dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n", | |
1203 | mtype, start, size); | |
1204 | start_page = (start - res_map->start) / PAGE_SIZE; | |
1205 | end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE; | |
1206 | for (i = start_page; i < end_page; i++) | |
1207 | resmap_free_page(res_map, i); | |
1208 | } | |
1209 | ||
1210 | static unsigned long resmap_alloc_region(int mtype, size_t size) | |
1211 | { | |
1212 | unsigned i; | |
1213 | unsigned total; | |
1214 | unsigned start_page; | |
1215 | unsigned long start; | |
1216 | struct resmap *res_map = dispc.res_map[mtype]; | |
1217 | ||
1218 | BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size); | |
1219 | ||
1220 | size = PAGE_ALIGN(size) / PAGE_SIZE; | |
1221 | start_page = 0; | |
1222 | total = 0; | |
1223 | for (i = 0; i < res_map->page_cnt; i++) { | |
1224 | if (resmap_page_reserved(res_map, i)) { | |
1225 | start_page = i + 1; | |
1226 | total = 0; | |
1227 | } else if (++total == size) | |
1228 | break; | |
1229 | } | |
1230 | if (total < size) | |
1231 | return 0; | |
1232 | ||
1233 | start = res_map->start + start_page * PAGE_SIZE; | |
1234 | resmap_reserve_region(start, size * PAGE_SIZE); | |
1235 | ||
1236 | return start; | |
1237 | } | |
1238 | ||
1239 | /* Note that this will only work for user mappings, we don't deal with | |
1240 | * kernel mappings here, so fbcon will keep using the old region. | |
1241 | */ | |
1242 | static int omap_dispc_setup_mem(int plane, size_t size, int mem_type, | |
1243 | unsigned long *paddr) | |
1244 | { | |
1245 | struct omapfb_mem_region *rg; | |
1246 | unsigned long new_addr = 0; | |
1247 | ||
1248 | if ((unsigned)plane > dispc.mem_desc.region_cnt) | |
1249 | return -EINVAL; | |
1250 | if (mem_type >= DISPC_MEMTYPE_NUM) | |
1251 | return -EINVAL; | |
1252 | if (dispc.res_map[mem_type] == NULL) | |
1253 | return -ENOMEM; | |
1254 | rg = &dispc.mem_desc.region[plane]; | |
1255 | if (size == rg->size && mem_type == rg->type) | |
1256 | return 0; | |
1257 | if (atomic_read(&dispc.map_count[plane])) | |
1258 | return -EBUSY; | |
1259 | if (rg->size != 0) | |
1260 | resmap_free_region(rg->paddr, rg->size); | |
1261 | if (size != 0) { | |
1262 | new_addr = resmap_alloc_region(mem_type, size); | |
1263 | if (!new_addr) { | |
1264 | /* Reallocate old region. */ | |
1265 | resmap_reserve_region(rg->paddr, rg->size); | |
1266 | return -ENOMEM; | |
1267 | } | |
1268 | } | |
1269 | rg->paddr = new_addr; | |
1270 | rg->size = size; | |
1271 | rg->type = mem_type; | |
1272 | ||
1273 | *paddr = new_addr; | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | static int setup_fbmem(struct omapfb_mem_desc *req_md) | |
1279 | { | |
1280 | struct omapfb_mem_region *rg; | |
1281 | int i; | |
1282 | int r; | |
1283 | unsigned long mem_start[DISPC_MEMTYPE_NUM]; | |
1284 | unsigned long mem_end[DISPC_MEMTYPE_NUM]; | |
1285 | ||
1286 | if (!req_md->region_cnt) { | |
1287 | dev_err(dispc.fbdev->dev, "no memory regions defined\n"); | |
1288 | return -ENOENT; | |
1289 | } | |
1290 | ||
1291 | rg = &req_md->region[0]; | |
1292 | memset(mem_start, 0xff, sizeof(mem_start)); | |
1293 | memset(mem_end, 0, sizeof(mem_end)); | |
1294 | ||
1295 | for (i = 0; i < req_md->region_cnt; i++, rg++) { | |
1296 | int mtype; | |
1297 | if (rg->paddr) { | |
1298 | rg->alloc = 0; | |
1299 | if (rg->vaddr == NULL) { | |
1300 | rg->map = 1; | |
1301 | if ((r = mmap_kern(rg)) < 0) | |
1302 | return r; | |
1303 | } | |
1304 | } else { | |
1305 | if (rg->type != OMAPFB_MEMTYPE_SDRAM) { | |
1306 | dev_err(dispc.fbdev->dev, | |
1307 | "unsupported memory type\n"); | |
1308 | return -EINVAL; | |
1309 | } | |
1310 | rg->alloc = rg->map = 1; | |
1311 | if ((r = alloc_fbmem(rg)) < 0) | |
1312 | return r; | |
1313 | } | |
1314 | mtype = rg->type; | |
1315 | ||
1316 | if (rg->paddr < mem_start[mtype]) | |
1317 | mem_start[mtype] = rg->paddr; | |
1318 | if (rg->paddr + rg->size > mem_end[mtype]) | |
1319 | mem_end[mtype] = rg->paddr + rg->size; | |
1320 | } | |
1321 | ||
1322 | for (i = 0; i < DISPC_MEMTYPE_NUM; i++) { | |
1323 | unsigned long start; | |
1324 | size_t size; | |
1325 | if (mem_end[i] == 0) | |
1326 | continue; | |
1327 | start = mem_start[i]; | |
1328 | size = mem_end[i] - start; | |
1329 | dispc.res_map[i] = init_resmap(start, size); | |
1330 | r = -ENOMEM; | |
1331 | if (dispc.res_map[i] == NULL) | |
1332 | goto fail; | |
1333 | /* Initial state is that everything is reserved. This | |
1334 | * includes possible holes as well, which will never be | |
1335 | * freed. | |
1336 | */ | |
1337 | resmap_reserve_region(start, size); | |
1338 | } | |
1339 | ||
1340 | dispc.mem_desc = *req_md; | |
1341 | ||
1342 | return 0; | |
1343 | fail: | |
1344 | for (i = 0; i < DISPC_MEMTYPE_NUM; i++) { | |
1345 | if (dispc.res_map[i] != NULL) | |
1346 | cleanup_resmap(dispc.res_map[i]); | |
1347 | } | |
1348 | return r; | |
1349 | } | |
1350 | ||
1351 | static void cleanup_fbmem(void) | |
1352 | { | |
1353 | struct omapfb_mem_region *rg; | |
1354 | int i; | |
1355 | ||
1356 | for (i = 0; i < DISPC_MEMTYPE_NUM; i++) { | |
1357 | if (dispc.res_map[i] != NULL) | |
1358 | cleanup_resmap(dispc.res_map[i]); | |
1359 | } | |
1360 | rg = &dispc.mem_desc.region[0]; | |
1361 | for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) { | |
1362 | if (rg->alloc) | |
1363 | free_fbmem(rg); | |
1364 | else { | |
1365 | if (rg->map) | |
1366 | unmap_kern(rg); | |
1367 | } | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode, | |
1372 | struct omapfb_mem_desc *req_vram) | |
1373 | { | |
1374 | int r; | |
1375 | u32 l; | |
1376 | struct lcd_panel *panel = fbdev->panel; | |
b0002e0e | 1377 | void __iomem *ram_fw_base; |
7a055fc2 ID |
1378 | int tmo = 10000; |
1379 | int skip_init = 0; | |
1380 | int i; | |
1381 | ||
1382 | memset(&dispc, 0, sizeof(dispc)); | |
1383 | ||
55c381e4 RK |
1384 | dispc.base = ioremap(DISPC_BASE, SZ_1K); |
1385 | if (!dispc.base) { | |
1386 | dev_err(fbdev->dev, "can't ioremap DISPC\n"); | |
1387 | return -ENOMEM; | |
1388 | } | |
1389 | ||
7a055fc2 ID |
1390 | dispc.fbdev = fbdev; |
1391 | dispc.ext_mode = ext_mode; | |
1392 | ||
1393 | init_completion(&dispc.frame_done); | |
1394 | ||
1395 | if ((r = get_dss_clocks()) < 0) | |
55c381e4 | 1396 | goto fail0; |
7a055fc2 | 1397 | |
7a055fc2 ID |
1398 | enable_lcd_clocks(1); |
1399 | ||
1400 | #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT | |
1401 | l = dispc_read_reg(DISPC_CONTROL); | |
1402 | /* LCD enabled ? */ | |
1403 | if (l & 1) { | |
1404 | pr_info("omapfb: skipping hardware initialization\n"); | |
1405 | skip_init = 1; | |
1406 | } | |
1407 | #endif | |
1408 | ||
1409 | if (!skip_init) { | |
1410 | /* Reset monitoring works only w/ the 54M clk */ | |
1411 | enable_digit_clocks(1); | |
1412 | ||
1413 | /* Soft reset */ | |
1414 | MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1); | |
1415 | ||
1416 | while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) { | |
1417 | if (!--tmo) { | |
1418 | dev_err(dispc.fbdev->dev, "soft reset failed\n"); | |
1419 | r = -ENODEV; | |
1420 | enable_digit_clocks(0); | |
1421 | goto fail1; | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | enable_digit_clocks(0); | |
1426 | } | |
1427 | ||
48a00e7f | 1428 | /* Enable smart standby/idle, autoidle and wakeup */ |
fd0eecbd | 1429 | l = dispc_read_reg(DISPC_SYSCONFIG); |
7a055fc2 | 1430 | l &= ~((3 << 12) | (3 << 3)); |
48a00e7f | 1431 | l |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0); |
7a055fc2 ID |
1432 | dispc_write_reg(DISPC_SYSCONFIG, l); |
1433 | omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG); | |
1434 | ||
1435 | /* Set functional clock autogating */ | |
1436 | l = dispc_read_reg(DISPC_CONFIG); | |
1437 | l |= 1 << 9; | |
1438 | dispc_write_reg(DISPC_CONFIG, l); | |
1439 | ||
1440 | l = dispc_read_reg(DISPC_IRQSTATUS); | |
fd0eecbd | 1441 | dispc_write_reg(DISPC_IRQSTATUS, l); |
7a055fc2 | 1442 | |
4c88ef17 | 1443 | recalc_irq_mask(); |
7a055fc2 ID |
1444 | |
1445 | if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler, | |
1446 | 0, MODULE_NAME, fbdev)) < 0) { | |
1447 | dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n"); | |
1448 | goto fail1; | |
1449 | } | |
1450 | ||
1451 | /* L3 firewall setting: enable access to OCM RAM */ | |
b0002e0e TL |
1452 | ram_fw_base = ioremap(0x68005000, SZ_1K); |
1453 | if (!ram_fw_base) { | |
1454 | dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n"); | |
1455 | goto fail1; | |
1456 | } | |
1457 | __raw_writel(0x402000b0, ram_fw_base + 0xa0); | |
1458 | iounmap(ram_fw_base); | |
7a055fc2 ID |
1459 | |
1460 | if ((r = alloc_palette_ram()) < 0) | |
1461 | goto fail2; | |
1462 | ||
1463 | if ((r = setup_fbmem(req_vram)) < 0) | |
1464 | goto fail3; | |
1465 | ||
1466 | if (!skip_init) { | |
1467 | for (i = 0; i < dispc.mem_desc.region_cnt; i++) { | |
1468 | memset(dispc.mem_desc.region[i].vaddr, 0, | |
1469 | dispc.mem_desc.region[i].size); | |
1470 | } | |
1471 | ||
1472 | /* Set logic clock to fck, pixel clock to fck/2 for now */ | |
1473 | MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16); | |
1474 | MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0); | |
1475 | ||
1476 | setup_plane_fifo(0, ext_mode); | |
1477 | setup_plane_fifo(1, ext_mode); | |
1478 | setup_plane_fifo(2, ext_mode); | |
1479 | ||
1480 | setup_color_conv_coef(); | |
1481 | ||
1482 | set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT); | |
1483 | set_load_mode(DISPC_LOAD_FRAME_ONLY); | |
1484 | ||
1485 | if (!ext_mode) { | |
1486 | set_lcd_data_lines(panel->data_lines); | |
1487 | omap_dispc_set_lcd_size(panel->x_res, panel->y_res); | |
1488 | set_lcd_timings(); | |
1489 | } else | |
1490 | set_lcd_data_lines(panel->bpp); | |
1491 | enable_rfbi_mode(ext_mode); | |
1492 | } | |
1493 | ||
1494 | l = dispc_read_reg(DISPC_REVISION); | |
1495 | pr_info("omapfb: DISPC version %d.%d initialized\n", | |
1496 | l >> 4 & 0x0f, l & 0x0f); | |
1497 | enable_lcd_clocks(0); | |
1498 | ||
1499 | return 0; | |
1500 | fail3: | |
1501 | free_palette_ram(); | |
1502 | fail2: | |
1503 | free_irq(INT_24XX_DSS_IRQ, fbdev); | |
1504 | fail1: | |
1505 | enable_lcd_clocks(0); | |
7a055fc2 | 1506 | put_dss_clocks(); |
55c381e4 RK |
1507 | fail0: |
1508 | iounmap(dispc.base); | |
7a055fc2 ID |
1509 | return r; |
1510 | } | |
1511 | ||
1512 | static void omap_dispc_cleanup(void) | |
1513 | { | |
1514 | int i; | |
1515 | ||
1516 | omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED); | |
1517 | /* This will also disable clocks that are on */ | |
1518 | for (i = 0; i < dispc.mem_desc.region_cnt; i++) | |
1519 | omap_dispc_enable_plane(i, 0); | |
1520 | cleanup_fbmem(); | |
1521 | free_palette_ram(); | |
1522 | free_irq(INT_24XX_DSS_IRQ, dispc.fbdev); | |
7a055fc2 | 1523 | put_dss_clocks(); |
55c381e4 | 1524 | iounmap(dispc.base); |
7a055fc2 ID |
1525 | } |
1526 | ||
1527 | const struct lcd_ctrl omap2_int_ctrl = { | |
1528 | .name = "internal", | |
1529 | .init = omap_dispc_init, | |
1530 | .cleanup = omap_dispc_cleanup, | |
1531 | .get_caps = omap_dispc_get_caps, | |
1532 | .set_update_mode = omap_dispc_set_update_mode, | |
1533 | .get_update_mode = omap_dispc_get_update_mode, | |
1534 | .update_window = omap_dispc_update_window, | |
1535 | .suspend = omap_dispc_suspend, | |
1536 | .resume = omap_dispc_resume, | |
1537 | .setup_plane = omap_dispc_setup_plane, | |
1538 | .setup_mem = omap_dispc_setup_mem, | |
1539 | .set_scale = omap_dispc_set_scale, | |
1540 | .enable_plane = omap_dispc_enable_plane, | |
1541 | .set_color_key = omap_dispc_set_color_key, | |
1542 | .get_color_key = omap_dispc_get_color_key, | |
1543 | .mmap = omap_dispc_mmap_user, | |
1544 | }; |