]>
Commit | Line | Data |
---|---|---|
9ce4ad0a GI |
1 | /* |
2 | * LCD panel driver for TPO TD043MTEA1 | |
3 | * | |
4 | * Author: Gražvydas Ignotas <notasas@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/spi/spi.h> | |
15 | #include <linux/regulator/consumer.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/err.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
9ce4ad0a | 19 | |
a0b38cc4 | 20 | #include <video/omapdss.h> |
9ce4ad0a GI |
21 | |
22 | #define TPO_R02_MODE(x) ((x) & 7) | |
23 | #define TPO_R02_MODE_800x480 7 | |
24 | #define TPO_R02_NCLK_RISING BIT(3) | |
25 | #define TPO_R02_HSYNC_HIGH BIT(4) | |
26 | #define TPO_R02_VSYNC_HIGH BIT(5) | |
27 | ||
28 | #define TPO_R03_NSTANDBY BIT(0) | |
29 | #define TPO_R03_EN_CP_CLK BIT(1) | |
30 | #define TPO_R03_EN_VGL_PUMP BIT(2) | |
31 | #define TPO_R03_EN_PWM BIT(3) | |
32 | #define TPO_R03_DRIVING_CAP_100 BIT(4) | |
33 | #define TPO_R03_EN_PRE_CHARGE BIT(6) | |
34 | #define TPO_R03_SOFTWARE_CTL BIT(7) | |
35 | ||
36 | #define TPO_R04_NFLIP_H BIT(0) | |
37 | #define TPO_R04_NFLIP_V BIT(1) | |
38 | #define TPO_R04_CP_CLK_FREQ_1H BIT(2) | |
39 | #define TPO_R04_VGL_FREQ_1H BIT(4) | |
40 | ||
41 | #define TPO_R03_VAL_NORMAL (TPO_R03_NSTANDBY | TPO_R03_EN_CP_CLK | \ | |
42 | TPO_R03_EN_VGL_PUMP | TPO_R03_EN_PWM | \ | |
43 | TPO_R03_DRIVING_CAP_100 | TPO_R03_EN_PRE_CHARGE | \ | |
44 | TPO_R03_SOFTWARE_CTL) | |
45 | ||
46 | #define TPO_R03_VAL_STANDBY (TPO_R03_DRIVING_CAP_100 | \ | |
47 | TPO_R03_EN_PRE_CHARGE | TPO_R03_SOFTWARE_CTL) | |
48 | ||
49 | static const u16 tpo_td043_def_gamma[12] = { | |
4306b721 | 50 | 105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023 |
9ce4ad0a GI |
51 | }; |
52 | ||
53 | struct tpo_td043_device { | |
54 | struct spi_device *spi; | |
55 | struct regulator *vcc_reg; | |
8df4f5ce | 56 | int nreset_gpio; |
9ce4ad0a GI |
57 | u16 gamma[12]; |
58 | u32 mode; | |
59 | u32 hmirror:1; | |
60 | u32 vmirror:1; | |
8df4f5ce GI |
61 | u32 powered_on:1; |
62 | u32 spi_suspended:1; | |
63 | u32 power_on_resume:1; | |
9ce4ad0a GI |
64 | }; |
65 | ||
66 | static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data) | |
67 | { | |
68 | struct spi_message m; | |
69 | struct spi_transfer xfer; | |
70 | u16 w; | |
71 | int r; | |
72 | ||
73 | spi_message_init(&m); | |
74 | ||
75 | memset(&xfer, 0, sizeof(xfer)); | |
76 | ||
77 | w = ((u16)addr << 10) | (1 << 8) | data; | |
78 | xfer.tx_buf = &w; | |
79 | xfer.bits_per_word = 16; | |
80 | xfer.len = 2; | |
81 | spi_message_add_tail(&xfer, &m); | |
82 | ||
83 | r = spi_sync(spi, &m); | |
84 | if (r < 0) | |
85 | dev_warn(&spi->dev, "failed to write to LCD reg (%d)\n", r); | |
86 | return r; | |
87 | } | |
88 | ||
89 | static void tpo_td043_write_gamma(struct spi_device *spi, u16 gamma[12]) | |
90 | { | |
91 | u8 i, val; | |
92 | ||
93 | /* gamma bits [9:8] */ | |
94 | for (val = i = 0; i < 4; i++) | |
95 | val |= (gamma[i] & 0x300) >> ((i + 1) * 2); | |
96 | tpo_td043_write(spi, 0x11, val); | |
97 | ||
98 | for (val = i = 0; i < 4; i++) | |
99 | val |= (gamma[i+4] & 0x300) >> ((i + 1) * 2); | |
100 | tpo_td043_write(spi, 0x12, val); | |
101 | ||
102 | for (val = i = 0; i < 4; i++) | |
103 | val |= (gamma[i+8] & 0x300) >> ((i + 1) * 2); | |
104 | tpo_td043_write(spi, 0x13, val); | |
105 | ||
106 | /* gamma bits [7:0] */ | |
107 | for (val = i = 0; i < 12; i++) | |
108 | tpo_td043_write(spi, 0x14 + i, gamma[i] & 0xff); | |
109 | } | |
110 | ||
111 | static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v) | |
112 | { | |
113 | u8 reg4 = TPO_R04_NFLIP_H | TPO_R04_NFLIP_V | \ | |
114 | TPO_R04_CP_CLK_FREQ_1H | TPO_R04_VGL_FREQ_1H; | |
115 | if (h) | |
116 | reg4 &= ~TPO_R04_NFLIP_H; | |
117 | if (v) | |
118 | reg4 &= ~TPO_R04_NFLIP_V; | |
119 | ||
120 | return tpo_td043_write(spi, 4, reg4); | |
121 | } | |
122 | ||
123 | static int tpo_td043_set_hmirror(struct omap_dss_device *dssdev, bool enable) | |
124 | { | |
125 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
126 | ||
127 | tpo_td043->hmirror = enable; | |
128 | return tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, | |
129 | tpo_td043->vmirror); | |
130 | } | |
131 | ||
132 | static bool tpo_td043_get_hmirror(struct omap_dss_device *dssdev) | |
133 | { | |
134 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
135 | ||
136 | return tpo_td043->hmirror; | |
137 | } | |
138 | ||
139 | static ssize_t tpo_td043_vmirror_show(struct device *dev, | |
140 | struct device_attribute *attr, char *buf) | |
141 | { | |
142 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
143 | ||
144 | return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->vmirror); | |
145 | } | |
146 | ||
147 | static ssize_t tpo_td043_vmirror_store(struct device *dev, | |
148 | struct device_attribute *attr, const char *buf, size_t count) | |
149 | { | |
150 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
e3502ce9 | 151 | int val; |
9ce4ad0a GI |
152 | int ret; |
153 | ||
e3502ce9 | 154 | ret = kstrtoint(buf, 0, &val); |
9ce4ad0a GI |
155 | if (ret < 0) |
156 | return ret; | |
157 | ||
e3502ce9 TV |
158 | val = !!val; |
159 | ||
9ce4ad0a GI |
160 | ret = tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, val); |
161 | if (ret < 0) | |
162 | return ret; | |
163 | ||
164 | tpo_td043->vmirror = val; | |
165 | ||
166 | return count; | |
167 | } | |
168 | ||
169 | static ssize_t tpo_td043_mode_show(struct device *dev, | |
170 | struct device_attribute *attr, char *buf) | |
171 | { | |
172 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
173 | ||
174 | return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->mode); | |
175 | } | |
176 | ||
177 | static ssize_t tpo_td043_mode_store(struct device *dev, | |
178 | struct device_attribute *attr, const char *buf, size_t count) | |
179 | { | |
180 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
181 | long val; | |
182 | int ret; | |
183 | ||
e3502ce9 | 184 | ret = kstrtol(buf, 0, &val); |
9ce4ad0a GI |
185 | if (ret != 0 || val & ~7) |
186 | return -EINVAL; | |
187 | ||
188 | tpo_td043->mode = val; | |
189 | ||
190 | val |= TPO_R02_NCLK_RISING; | |
191 | tpo_td043_write(tpo_td043->spi, 2, val); | |
192 | ||
193 | return count; | |
194 | } | |
195 | ||
196 | static ssize_t tpo_td043_gamma_show(struct device *dev, | |
197 | struct device_attribute *attr, char *buf) | |
198 | { | |
199 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
200 | ssize_t len = 0; | |
201 | int ret; | |
202 | int i; | |
203 | ||
204 | for (i = 0; i < ARRAY_SIZE(tpo_td043->gamma); i++) { | |
205 | ret = snprintf(buf + len, PAGE_SIZE - len, "%u ", | |
206 | tpo_td043->gamma[i]); | |
207 | if (ret < 0) | |
208 | return ret; | |
209 | len += ret; | |
210 | } | |
211 | buf[len - 1] = '\n'; | |
212 | ||
213 | return len; | |
214 | } | |
215 | ||
216 | static ssize_t tpo_td043_gamma_store(struct device *dev, | |
217 | struct device_attribute *attr, const char *buf, size_t count) | |
218 | { | |
219 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
220 | unsigned int g[12]; | |
221 | int ret; | |
222 | int i; | |
223 | ||
224 | ret = sscanf(buf, "%u %u %u %u %u %u %u %u %u %u %u %u", | |
225 | &g[0], &g[1], &g[2], &g[3], &g[4], &g[5], | |
226 | &g[6], &g[7], &g[8], &g[9], &g[10], &g[11]); | |
227 | ||
228 | if (ret != 12) | |
229 | return -EINVAL; | |
230 | ||
231 | for (i = 0; i < 12; i++) | |
232 | tpo_td043->gamma[i] = g[i]; | |
233 | ||
234 | tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma); | |
235 | ||
236 | return count; | |
237 | } | |
238 | ||
239 | static DEVICE_ATTR(vmirror, S_IRUGO | S_IWUSR, | |
240 | tpo_td043_vmirror_show, tpo_td043_vmirror_store); | |
241 | static DEVICE_ATTR(mode, S_IRUGO | S_IWUSR, | |
242 | tpo_td043_mode_show, tpo_td043_mode_store); | |
243 | static DEVICE_ATTR(gamma, S_IRUGO | S_IWUSR, | |
244 | tpo_td043_gamma_show, tpo_td043_gamma_store); | |
245 | ||
246 | static struct attribute *tpo_td043_attrs[] = { | |
247 | &dev_attr_vmirror.attr, | |
248 | &dev_attr_mode.attr, | |
249 | &dev_attr_gamma.attr, | |
250 | NULL, | |
251 | }; | |
252 | ||
253 | static struct attribute_group tpo_td043_attr_group = { | |
254 | .attrs = tpo_td043_attrs, | |
255 | }; | |
256 | ||
257 | static const struct omap_video_timings tpo_td043_timings = { | |
258 | .x_res = 800, | |
259 | .y_res = 480, | |
260 | ||
261 | .pixel_clock = 36000, | |
262 | ||
263 | .hsw = 1, | |
264 | .hfp = 68, | |
265 | .hbp = 214, | |
266 | ||
267 | .vsw = 1, | |
268 | .vfp = 39, | |
269 | .vbp = 34, | |
270 | }; | |
271 | ||
8df4f5ce | 272 | static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043) |
9ce4ad0a | 273 | { |
8df4f5ce | 274 | int nreset_gpio = tpo_td043->nreset_gpio; |
956107ea | 275 | int r; |
9ce4ad0a | 276 | |
8df4f5ce | 277 | if (tpo_td043->powered_on) |
18016e35 SM |
278 | return 0; |
279 | ||
956107ea MB |
280 | r = regulator_enable(tpo_td043->vcc_reg); |
281 | if (r != 0) | |
282 | return r; | |
9ce4ad0a | 283 | |
2c83af49 | 284 | /* wait for panel to stabilize */ |
9ce4ad0a GI |
285 | msleep(160); |
286 | ||
287 | if (gpio_is_valid(nreset_gpio)) | |
288 | gpio_set_value(nreset_gpio, 1); | |
289 | ||
290 | tpo_td043_write(tpo_td043->spi, 2, | |
291 | TPO_R02_MODE(tpo_td043->mode) | TPO_R02_NCLK_RISING); | |
292 | tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_NORMAL); | |
293 | tpo_td043_write(tpo_td043->spi, 0x20, 0xf0); | |
294 | tpo_td043_write(tpo_td043->spi, 0x21, 0xf0); | |
295 | tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, | |
296 | tpo_td043->vmirror); | |
297 | tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma); | |
298 | ||
8df4f5ce | 299 | tpo_td043->powered_on = 1; |
9ce4ad0a GI |
300 | return 0; |
301 | } | |
302 | ||
8df4f5ce | 303 | static void tpo_td043_power_off(struct tpo_td043_device *tpo_td043) |
9ce4ad0a | 304 | { |
8df4f5ce | 305 | int nreset_gpio = tpo_td043->nreset_gpio; |
9ce4ad0a | 306 | |
8df4f5ce | 307 | if (!tpo_td043->powered_on) |
18016e35 SM |
308 | return; |
309 | ||
9ce4ad0a GI |
310 | tpo_td043_write(tpo_td043->spi, 3, |
311 | TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM); | |
312 | ||
313 | if (gpio_is_valid(nreset_gpio)) | |
314 | gpio_set_value(nreset_gpio, 0); | |
315 | ||
316 | /* wait for at least 2 vsyncs before cutting off power */ | |
317 | msleep(50); | |
318 | ||
319 | tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_STANDBY); | |
320 | ||
321 | regulator_disable(tpo_td043->vcc_reg); | |
322 | ||
8df4f5ce GI |
323 | tpo_td043->powered_on = 0; |
324 | } | |
325 | ||
326 | static int tpo_td043_enable_dss(struct omap_dss_device *dssdev) | |
327 | { | |
328 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
329 | int r; | |
330 | ||
331 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) | |
332 | return 0; | |
333 | ||
334 | r = omapdss_dpi_display_enable(dssdev); | |
335 | if (r) | |
336 | goto err0; | |
337 | ||
338 | if (dssdev->platform_enable) { | |
339 | r = dssdev->platform_enable(dssdev); | |
340 | if (r) | |
341 | goto err1; | |
342 | } | |
343 | ||
344 | /* | |
345 | * If we are resuming from system suspend, SPI clocks might not be | |
346 | * enabled yet, so we'll program the LCD from SPI PM resume callback. | |
347 | */ | |
348 | if (!tpo_td043->spi_suspended) { | |
349 | r = tpo_td043_power_on(tpo_td043); | |
350 | if (r) | |
351 | goto err1; | |
352 | } | |
353 | ||
354 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | |
355 | ||
356 | return 0; | |
357 | err1: | |
358 | omapdss_dpi_display_disable(dssdev); | |
359 | err0: | |
360 | return r; | |
361 | } | |
362 | ||
363 | static void tpo_td043_disable_dss(struct omap_dss_device *dssdev) | |
364 | { | |
365 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
366 | ||
367 | if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) | |
368 | return; | |
369 | ||
9ce4ad0a GI |
370 | if (dssdev->platform_disable) |
371 | dssdev->platform_disable(dssdev); | |
37ac60e4 TV |
372 | |
373 | omapdss_dpi_display_disable(dssdev); | |
8df4f5ce GI |
374 | |
375 | if (!tpo_td043->spi_suspended) | |
376 | tpo_td043_power_off(tpo_td043); | |
37ac60e4 TV |
377 | } |
378 | ||
379 | static int tpo_td043_enable(struct omap_dss_device *dssdev) | |
380 | { | |
37ac60e4 TV |
381 | dev_dbg(&dssdev->dev, "enable\n"); |
382 | ||
8df4f5ce | 383 | return tpo_td043_enable_dss(dssdev); |
37ac60e4 TV |
384 | } |
385 | ||
386 | static void tpo_td043_disable(struct omap_dss_device *dssdev) | |
387 | { | |
388 | dev_dbg(&dssdev->dev, "disable\n"); | |
389 | ||
8df4f5ce | 390 | tpo_td043_disable_dss(dssdev); |
37ac60e4 TV |
391 | |
392 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | |
9ce4ad0a GI |
393 | } |
394 | ||
395 | static int tpo_td043_suspend(struct omap_dss_device *dssdev) | |
396 | { | |
8df4f5ce GI |
397 | dev_dbg(&dssdev->dev, "suspend\n"); |
398 | ||
399 | tpo_td043_disable_dss(dssdev); | |
400 | ||
37ac60e4 | 401 | dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; |
8df4f5ce | 402 | |
9ce4ad0a GI |
403 | return 0; |
404 | } | |
405 | ||
406 | static int tpo_td043_resume(struct omap_dss_device *dssdev) | |
407 | { | |
8df4f5ce | 408 | dev_dbg(&dssdev->dev, "resume\n"); |
37ac60e4 | 409 | |
8df4f5ce | 410 | return tpo_td043_enable_dss(dssdev); |
9ce4ad0a GI |
411 | } |
412 | ||
413 | static int tpo_td043_probe(struct omap_dss_device *dssdev) | |
414 | { | |
415 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
416 | int nreset_gpio = dssdev->reset_gpio; | |
417 | int ret = 0; | |
418 | ||
419 | dev_dbg(&dssdev->dev, "probe\n"); | |
420 | ||
421 | if (tpo_td043 == NULL) { | |
422 | dev_err(&dssdev->dev, "missing tpo_td043_device\n"); | |
423 | return -ENODEV; | |
424 | } | |
425 | ||
5ae9eaa6 AT |
426 | dssdev->panel.config = OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS | |
427 | OMAP_DSS_LCD_IPC; | |
9ce4ad0a GI |
428 | dssdev->panel.timings = tpo_td043_timings; |
429 | dssdev->ctrl.pixel_size = 24; | |
430 | ||
431 | tpo_td043->mode = TPO_R02_MODE_800x480; | |
432 | memcpy(tpo_td043->gamma, tpo_td043_def_gamma, sizeof(tpo_td043->gamma)); | |
433 | ||
434 | tpo_td043->vcc_reg = regulator_get(&dssdev->dev, "vcc"); | |
435 | if (IS_ERR(tpo_td043->vcc_reg)) { | |
436 | dev_err(&dssdev->dev, "failed to get LCD VCC regulator\n"); | |
437 | ret = PTR_ERR(tpo_td043->vcc_reg); | |
438 | goto fail_regulator; | |
439 | } | |
440 | ||
441 | if (gpio_is_valid(nreset_gpio)) { | |
f8bd4934 JH |
442 | ret = gpio_request_one(nreset_gpio, GPIOF_OUT_INIT_LOW, |
443 | "lcd reset"); | |
9ce4ad0a GI |
444 | if (ret < 0) { |
445 | dev_err(&dssdev->dev, "couldn't request reset GPIO\n"); | |
446 | goto fail_gpio_req; | |
447 | } | |
9ce4ad0a GI |
448 | } |
449 | ||
450 | ret = sysfs_create_group(&dssdev->dev.kobj, &tpo_td043_attr_group); | |
451 | if (ret) | |
452 | dev_warn(&dssdev->dev, "failed to create sysfs files\n"); | |
453 | ||
454 | return 0; | |
455 | ||
9ce4ad0a GI |
456 | fail_gpio_req: |
457 | regulator_put(tpo_td043->vcc_reg); | |
458 | fail_regulator: | |
459 | kfree(tpo_td043); | |
460 | return ret; | |
461 | } | |
462 | ||
463 | static void tpo_td043_remove(struct omap_dss_device *dssdev) | |
464 | { | |
465 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
466 | int nreset_gpio = dssdev->reset_gpio; | |
467 | ||
468 | dev_dbg(&dssdev->dev, "remove\n"); | |
469 | ||
470 | sysfs_remove_group(&dssdev->dev.kobj, &tpo_td043_attr_group); | |
471 | regulator_put(tpo_td043->vcc_reg); | |
472 | if (gpio_is_valid(nreset_gpio)) | |
473 | gpio_free(nreset_gpio); | |
474 | } | |
475 | ||
31e8dfe1 GI |
476 | static void tpo_td043_set_timings(struct omap_dss_device *dssdev, |
477 | struct omap_video_timings *timings) | |
478 | { | |
479 | dpi_set_timings(dssdev, timings); | |
480 | } | |
481 | ||
482 | static int tpo_td043_check_timings(struct omap_dss_device *dssdev, | |
483 | struct omap_video_timings *timings) | |
484 | { | |
485 | return dpi_check_timings(dssdev, timings); | |
486 | } | |
487 | ||
9ce4ad0a GI |
488 | static struct omap_dss_driver tpo_td043_driver = { |
489 | .probe = tpo_td043_probe, | |
490 | .remove = tpo_td043_remove, | |
491 | ||
492 | .enable = tpo_td043_enable, | |
493 | .disable = tpo_td043_disable, | |
494 | .suspend = tpo_td043_suspend, | |
495 | .resume = tpo_td043_resume, | |
496 | .set_mirror = tpo_td043_set_hmirror, | |
497 | .get_mirror = tpo_td043_get_hmirror, | |
498 | ||
31e8dfe1 GI |
499 | .set_timings = tpo_td043_set_timings, |
500 | .check_timings = tpo_td043_check_timings, | |
501 | ||
9ce4ad0a GI |
502 | .driver = { |
503 | .name = "tpo_td043mtea1_panel", | |
504 | .owner = THIS_MODULE, | |
505 | }, | |
506 | }; | |
507 | ||
508 | static int tpo_td043_spi_probe(struct spi_device *spi) | |
509 | { | |
510 | struct omap_dss_device *dssdev = spi->dev.platform_data; | |
511 | struct tpo_td043_device *tpo_td043; | |
512 | int ret; | |
513 | ||
514 | if (dssdev == NULL) { | |
515 | dev_err(&spi->dev, "missing dssdev\n"); | |
516 | return -ENODEV; | |
517 | } | |
518 | ||
519 | spi->bits_per_word = 16; | |
520 | spi->mode = SPI_MODE_0; | |
521 | ||
522 | ret = spi_setup(spi); | |
523 | if (ret < 0) { | |
524 | dev_err(&spi->dev, "spi_setup failed: %d\n", ret); | |
525 | return ret; | |
526 | } | |
527 | ||
528 | tpo_td043 = kzalloc(sizeof(*tpo_td043), GFP_KERNEL); | |
529 | if (tpo_td043 == NULL) | |
530 | return -ENOMEM; | |
531 | ||
532 | tpo_td043->spi = spi; | |
8df4f5ce | 533 | tpo_td043->nreset_gpio = dssdev->reset_gpio; |
9ce4ad0a GI |
534 | dev_set_drvdata(&spi->dev, tpo_td043); |
535 | dev_set_drvdata(&dssdev->dev, tpo_td043); | |
536 | ||
537 | omap_dss_register_driver(&tpo_td043_driver); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static int __devexit tpo_td043_spi_remove(struct spi_device *spi) | |
543 | { | |
544 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&spi->dev); | |
545 | ||
546 | omap_dss_unregister_driver(&tpo_td043_driver); | |
547 | kfree(tpo_td043); | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
8df4f5ce GI |
552 | #ifdef CONFIG_PM_SLEEP |
553 | static int tpo_td043_spi_suspend(struct device *dev) | |
554 | { | |
555 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
556 | ||
557 | dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", tpo_td043); | |
558 | ||
559 | tpo_td043->power_on_resume = tpo_td043->powered_on; | |
560 | tpo_td043_power_off(tpo_td043); | |
561 | tpo_td043->spi_suspended = 1; | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | static int tpo_td043_spi_resume(struct device *dev) | |
567 | { | |
568 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
569 | int ret; | |
570 | ||
571 | dev_dbg(dev, "tpo_td043_spi_resume\n"); | |
572 | ||
573 | if (tpo_td043->power_on_resume) { | |
574 | ret = tpo_td043_power_on(tpo_td043); | |
575 | if (ret) | |
576 | return ret; | |
577 | } | |
578 | tpo_td043->spi_suspended = 0; | |
579 | ||
580 | return 0; | |
581 | } | |
582 | #endif | |
583 | ||
584 | static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm, | |
585 | tpo_td043_spi_suspend, tpo_td043_spi_resume); | |
586 | ||
9ce4ad0a GI |
587 | static struct spi_driver tpo_td043_spi_driver = { |
588 | .driver = { | |
589 | .name = "tpo_td043mtea1_panel_spi", | |
9ce4ad0a | 590 | .owner = THIS_MODULE, |
8df4f5ce | 591 | .pm = &tpo_td043_spi_pm, |
9ce4ad0a GI |
592 | }, |
593 | .probe = tpo_td043_spi_probe, | |
594 | .remove = __devexit_p(tpo_td043_spi_remove), | |
595 | }; | |
596 | ||
c6d242aa | 597 | module_spi_driver(tpo_td043_spi_driver); |
9ce4ad0a GI |
598 | |
599 | MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>"); | |
600 | MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver"); | |
601 | MODULE_LICENSE("GPL"); |