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Commit | Line | Data |
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9ce4ad0a GI |
1 | /* |
2 | * LCD panel driver for TPO TD043MTEA1 | |
3 | * | |
4 | * Author: Gražvydas Ignotas <notasas@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/spi/spi.h> | |
15 | #include <linux/regulator/consumer.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/err.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
9ce4ad0a | 19 | |
a0b38cc4 | 20 | #include <video/omapdss.h> |
9ce4ad0a GI |
21 | |
22 | #define TPO_R02_MODE(x) ((x) & 7) | |
23 | #define TPO_R02_MODE_800x480 7 | |
24 | #define TPO_R02_NCLK_RISING BIT(3) | |
25 | #define TPO_R02_HSYNC_HIGH BIT(4) | |
26 | #define TPO_R02_VSYNC_HIGH BIT(5) | |
27 | ||
28 | #define TPO_R03_NSTANDBY BIT(0) | |
29 | #define TPO_R03_EN_CP_CLK BIT(1) | |
30 | #define TPO_R03_EN_VGL_PUMP BIT(2) | |
31 | #define TPO_R03_EN_PWM BIT(3) | |
32 | #define TPO_R03_DRIVING_CAP_100 BIT(4) | |
33 | #define TPO_R03_EN_PRE_CHARGE BIT(6) | |
34 | #define TPO_R03_SOFTWARE_CTL BIT(7) | |
35 | ||
36 | #define TPO_R04_NFLIP_H BIT(0) | |
37 | #define TPO_R04_NFLIP_V BIT(1) | |
38 | #define TPO_R04_CP_CLK_FREQ_1H BIT(2) | |
39 | #define TPO_R04_VGL_FREQ_1H BIT(4) | |
40 | ||
41 | #define TPO_R03_VAL_NORMAL (TPO_R03_NSTANDBY | TPO_R03_EN_CP_CLK | \ | |
42 | TPO_R03_EN_VGL_PUMP | TPO_R03_EN_PWM | \ | |
43 | TPO_R03_DRIVING_CAP_100 | TPO_R03_EN_PRE_CHARGE | \ | |
44 | TPO_R03_SOFTWARE_CTL) | |
45 | ||
46 | #define TPO_R03_VAL_STANDBY (TPO_R03_DRIVING_CAP_100 | \ | |
47 | TPO_R03_EN_PRE_CHARGE | TPO_R03_SOFTWARE_CTL) | |
48 | ||
49 | static const u16 tpo_td043_def_gamma[12] = { | |
4306b721 | 50 | 105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023 |
9ce4ad0a GI |
51 | }; |
52 | ||
53 | struct tpo_td043_device { | |
54 | struct spi_device *spi; | |
55 | struct regulator *vcc_reg; | |
8df4f5ce | 56 | int nreset_gpio; |
9ce4ad0a GI |
57 | u16 gamma[12]; |
58 | u32 mode; | |
59 | u32 hmirror:1; | |
60 | u32 vmirror:1; | |
8df4f5ce GI |
61 | u32 powered_on:1; |
62 | u32 spi_suspended:1; | |
63 | u32 power_on_resume:1; | |
9ce4ad0a GI |
64 | }; |
65 | ||
a2f9b2a5 GI |
66 | /* used to pass spi_device from SPI to DSS portion of the driver */ |
67 | static struct tpo_td043_device *g_tpo_td043; | |
68 | ||
9ce4ad0a GI |
69 | static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data) |
70 | { | |
71 | struct spi_message m; | |
72 | struct spi_transfer xfer; | |
73 | u16 w; | |
74 | int r; | |
75 | ||
76 | spi_message_init(&m); | |
77 | ||
78 | memset(&xfer, 0, sizeof(xfer)); | |
79 | ||
80 | w = ((u16)addr << 10) | (1 << 8) | data; | |
81 | xfer.tx_buf = &w; | |
82 | xfer.bits_per_word = 16; | |
83 | xfer.len = 2; | |
84 | spi_message_add_tail(&xfer, &m); | |
85 | ||
86 | r = spi_sync(spi, &m); | |
87 | if (r < 0) | |
88 | dev_warn(&spi->dev, "failed to write to LCD reg (%d)\n", r); | |
89 | return r; | |
90 | } | |
91 | ||
92 | static void tpo_td043_write_gamma(struct spi_device *spi, u16 gamma[12]) | |
93 | { | |
94 | u8 i, val; | |
95 | ||
96 | /* gamma bits [9:8] */ | |
97 | for (val = i = 0; i < 4; i++) | |
98 | val |= (gamma[i] & 0x300) >> ((i + 1) * 2); | |
99 | tpo_td043_write(spi, 0x11, val); | |
100 | ||
101 | for (val = i = 0; i < 4; i++) | |
102 | val |= (gamma[i+4] & 0x300) >> ((i + 1) * 2); | |
103 | tpo_td043_write(spi, 0x12, val); | |
104 | ||
105 | for (val = i = 0; i < 4; i++) | |
106 | val |= (gamma[i+8] & 0x300) >> ((i + 1) * 2); | |
107 | tpo_td043_write(spi, 0x13, val); | |
108 | ||
109 | /* gamma bits [7:0] */ | |
110 | for (val = i = 0; i < 12; i++) | |
111 | tpo_td043_write(spi, 0x14 + i, gamma[i] & 0xff); | |
112 | } | |
113 | ||
114 | static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v) | |
115 | { | |
116 | u8 reg4 = TPO_R04_NFLIP_H | TPO_R04_NFLIP_V | \ | |
117 | TPO_R04_CP_CLK_FREQ_1H | TPO_R04_VGL_FREQ_1H; | |
118 | if (h) | |
119 | reg4 &= ~TPO_R04_NFLIP_H; | |
120 | if (v) | |
121 | reg4 &= ~TPO_R04_NFLIP_V; | |
122 | ||
123 | return tpo_td043_write(spi, 4, reg4); | |
124 | } | |
125 | ||
126 | static int tpo_td043_set_hmirror(struct omap_dss_device *dssdev, bool enable) | |
127 | { | |
128 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
129 | ||
130 | tpo_td043->hmirror = enable; | |
131 | return tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, | |
132 | tpo_td043->vmirror); | |
133 | } | |
134 | ||
135 | static bool tpo_td043_get_hmirror(struct omap_dss_device *dssdev) | |
136 | { | |
137 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
138 | ||
139 | return tpo_td043->hmirror; | |
140 | } | |
141 | ||
142 | static ssize_t tpo_td043_vmirror_show(struct device *dev, | |
143 | struct device_attribute *attr, char *buf) | |
144 | { | |
145 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
146 | ||
147 | return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->vmirror); | |
148 | } | |
149 | ||
150 | static ssize_t tpo_td043_vmirror_store(struct device *dev, | |
151 | struct device_attribute *attr, const char *buf, size_t count) | |
152 | { | |
153 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
e3502ce9 | 154 | int val; |
9ce4ad0a GI |
155 | int ret; |
156 | ||
e3502ce9 | 157 | ret = kstrtoint(buf, 0, &val); |
9ce4ad0a GI |
158 | if (ret < 0) |
159 | return ret; | |
160 | ||
e3502ce9 TV |
161 | val = !!val; |
162 | ||
9ce4ad0a GI |
163 | ret = tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, val); |
164 | if (ret < 0) | |
165 | return ret; | |
166 | ||
167 | tpo_td043->vmirror = val; | |
168 | ||
169 | return count; | |
170 | } | |
171 | ||
172 | static ssize_t tpo_td043_mode_show(struct device *dev, | |
173 | struct device_attribute *attr, char *buf) | |
174 | { | |
175 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
176 | ||
177 | return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->mode); | |
178 | } | |
179 | ||
180 | static ssize_t tpo_td043_mode_store(struct device *dev, | |
181 | struct device_attribute *attr, const char *buf, size_t count) | |
182 | { | |
183 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
184 | long val; | |
185 | int ret; | |
186 | ||
e3502ce9 | 187 | ret = kstrtol(buf, 0, &val); |
9ce4ad0a GI |
188 | if (ret != 0 || val & ~7) |
189 | return -EINVAL; | |
190 | ||
191 | tpo_td043->mode = val; | |
192 | ||
193 | val |= TPO_R02_NCLK_RISING; | |
194 | tpo_td043_write(tpo_td043->spi, 2, val); | |
195 | ||
196 | return count; | |
197 | } | |
198 | ||
199 | static ssize_t tpo_td043_gamma_show(struct device *dev, | |
200 | struct device_attribute *attr, char *buf) | |
201 | { | |
202 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
203 | ssize_t len = 0; | |
204 | int ret; | |
205 | int i; | |
206 | ||
207 | for (i = 0; i < ARRAY_SIZE(tpo_td043->gamma); i++) { | |
208 | ret = snprintf(buf + len, PAGE_SIZE - len, "%u ", | |
209 | tpo_td043->gamma[i]); | |
210 | if (ret < 0) | |
211 | return ret; | |
212 | len += ret; | |
213 | } | |
214 | buf[len - 1] = '\n'; | |
215 | ||
216 | return len; | |
217 | } | |
218 | ||
219 | static ssize_t tpo_td043_gamma_store(struct device *dev, | |
220 | struct device_attribute *attr, const char *buf, size_t count) | |
221 | { | |
222 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
223 | unsigned int g[12]; | |
224 | int ret; | |
225 | int i; | |
226 | ||
227 | ret = sscanf(buf, "%u %u %u %u %u %u %u %u %u %u %u %u", | |
228 | &g[0], &g[1], &g[2], &g[3], &g[4], &g[5], | |
229 | &g[6], &g[7], &g[8], &g[9], &g[10], &g[11]); | |
230 | ||
231 | if (ret != 12) | |
232 | return -EINVAL; | |
233 | ||
234 | for (i = 0; i < 12; i++) | |
235 | tpo_td043->gamma[i] = g[i]; | |
236 | ||
237 | tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma); | |
238 | ||
239 | return count; | |
240 | } | |
241 | ||
242 | static DEVICE_ATTR(vmirror, S_IRUGO | S_IWUSR, | |
243 | tpo_td043_vmirror_show, tpo_td043_vmirror_store); | |
244 | static DEVICE_ATTR(mode, S_IRUGO | S_IWUSR, | |
245 | tpo_td043_mode_show, tpo_td043_mode_store); | |
246 | static DEVICE_ATTR(gamma, S_IRUGO | S_IWUSR, | |
247 | tpo_td043_gamma_show, tpo_td043_gamma_store); | |
248 | ||
249 | static struct attribute *tpo_td043_attrs[] = { | |
250 | &dev_attr_vmirror.attr, | |
251 | &dev_attr_mode.attr, | |
252 | &dev_attr_gamma.attr, | |
253 | NULL, | |
254 | }; | |
255 | ||
256 | static struct attribute_group tpo_td043_attr_group = { | |
257 | .attrs = tpo_td043_attrs, | |
258 | }; | |
259 | ||
260 | static const struct omap_video_timings tpo_td043_timings = { | |
261 | .x_res = 800, | |
262 | .y_res = 480, | |
263 | ||
264 | .pixel_clock = 36000, | |
265 | ||
266 | .hsw = 1, | |
267 | .hfp = 68, | |
268 | .hbp = 214, | |
269 | ||
270 | .vsw = 1, | |
271 | .vfp = 39, | |
272 | .vbp = 34, | |
a8d5e41c AT |
273 | |
274 | .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, | |
275 | .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, | |
276 | .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, | |
277 | .de_level = OMAPDSS_SIG_ACTIVE_HIGH, | |
278 | .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | |
9ce4ad0a GI |
279 | }; |
280 | ||
8df4f5ce | 281 | static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043) |
9ce4ad0a | 282 | { |
8df4f5ce | 283 | int nreset_gpio = tpo_td043->nreset_gpio; |
956107ea | 284 | int r; |
9ce4ad0a | 285 | |
8df4f5ce | 286 | if (tpo_td043->powered_on) |
18016e35 SM |
287 | return 0; |
288 | ||
956107ea MB |
289 | r = regulator_enable(tpo_td043->vcc_reg); |
290 | if (r != 0) | |
291 | return r; | |
9ce4ad0a | 292 | |
2c83af49 | 293 | /* wait for panel to stabilize */ |
9ce4ad0a GI |
294 | msleep(160); |
295 | ||
296 | if (gpio_is_valid(nreset_gpio)) | |
297 | gpio_set_value(nreset_gpio, 1); | |
298 | ||
299 | tpo_td043_write(tpo_td043->spi, 2, | |
300 | TPO_R02_MODE(tpo_td043->mode) | TPO_R02_NCLK_RISING); | |
301 | tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_NORMAL); | |
302 | tpo_td043_write(tpo_td043->spi, 0x20, 0xf0); | |
303 | tpo_td043_write(tpo_td043->spi, 0x21, 0xf0); | |
304 | tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, | |
305 | tpo_td043->vmirror); | |
306 | tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma); | |
307 | ||
8df4f5ce | 308 | tpo_td043->powered_on = 1; |
9ce4ad0a GI |
309 | return 0; |
310 | } | |
311 | ||
8df4f5ce | 312 | static void tpo_td043_power_off(struct tpo_td043_device *tpo_td043) |
9ce4ad0a | 313 | { |
8df4f5ce | 314 | int nreset_gpio = tpo_td043->nreset_gpio; |
9ce4ad0a | 315 | |
8df4f5ce | 316 | if (!tpo_td043->powered_on) |
18016e35 SM |
317 | return; |
318 | ||
9ce4ad0a GI |
319 | tpo_td043_write(tpo_td043->spi, 3, |
320 | TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM); | |
321 | ||
322 | if (gpio_is_valid(nreset_gpio)) | |
323 | gpio_set_value(nreset_gpio, 0); | |
324 | ||
325 | /* wait for at least 2 vsyncs before cutting off power */ | |
326 | msleep(50); | |
327 | ||
328 | tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_STANDBY); | |
329 | ||
330 | regulator_disable(tpo_td043->vcc_reg); | |
331 | ||
8df4f5ce GI |
332 | tpo_td043->powered_on = 0; |
333 | } | |
334 | ||
335 | static int tpo_td043_enable_dss(struct omap_dss_device *dssdev) | |
336 | { | |
337 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
338 | int r; | |
339 | ||
340 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) | |
341 | return 0; | |
342 | ||
c499144c | 343 | omapdss_dpi_set_timings(dssdev, &dssdev->panel.timings); |
c6b393d4 | 344 | omapdss_dpi_set_data_lines(dssdev, dssdev->phy.dpi.data_lines); |
c499144c | 345 | |
8df4f5ce GI |
346 | r = omapdss_dpi_display_enable(dssdev); |
347 | if (r) | |
348 | goto err0; | |
349 | ||
350 | if (dssdev->platform_enable) { | |
351 | r = dssdev->platform_enable(dssdev); | |
352 | if (r) | |
353 | goto err1; | |
354 | } | |
355 | ||
356 | /* | |
357 | * If we are resuming from system suspend, SPI clocks might not be | |
358 | * enabled yet, so we'll program the LCD from SPI PM resume callback. | |
359 | */ | |
360 | if (!tpo_td043->spi_suspended) { | |
361 | r = tpo_td043_power_on(tpo_td043); | |
362 | if (r) | |
363 | goto err1; | |
364 | } | |
365 | ||
366 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | |
367 | ||
368 | return 0; | |
369 | err1: | |
370 | omapdss_dpi_display_disable(dssdev); | |
371 | err0: | |
372 | return r; | |
373 | } | |
374 | ||
375 | static void tpo_td043_disable_dss(struct omap_dss_device *dssdev) | |
376 | { | |
377 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
378 | ||
379 | if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) | |
380 | return; | |
381 | ||
9ce4ad0a GI |
382 | if (dssdev->platform_disable) |
383 | dssdev->platform_disable(dssdev); | |
37ac60e4 TV |
384 | |
385 | omapdss_dpi_display_disable(dssdev); | |
8df4f5ce GI |
386 | |
387 | if (!tpo_td043->spi_suspended) | |
388 | tpo_td043_power_off(tpo_td043); | |
37ac60e4 TV |
389 | } |
390 | ||
391 | static int tpo_td043_enable(struct omap_dss_device *dssdev) | |
392 | { | |
37ac60e4 TV |
393 | dev_dbg(&dssdev->dev, "enable\n"); |
394 | ||
8df4f5ce | 395 | return tpo_td043_enable_dss(dssdev); |
37ac60e4 TV |
396 | } |
397 | ||
398 | static void tpo_td043_disable(struct omap_dss_device *dssdev) | |
399 | { | |
400 | dev_dbg(&dssdev->dev, "disable\n"); | |
401 | ||
8df4f5ce | 402 | tpo_td043_disable_dss(dssdev); |
37ac60e4 TV |
403 | |
404 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | |
9ce4ad0a GI |
405 | } |
406 | ||
9ce4ad0a GI |
407 | static int tpo_td043_probe(struct omap_dss_device *dssdev) |
408 | { | |
a2f9b2a5 | 409 | struct tpo_td043_device *tpo_td043 = g_tpo_td043; |
9ce4ad0a GI |
410 | int nreset_gpio = dssdev->reset_gpio; |
411 | int ret = 0; | |
412 | ||
413 | dev_dbg(&dssdev->dev, "probe\n"); | |
414 | ||
415 | if (tpo_td043 == NULL) { | |
416 | dev_err(&dssdev->dev, "missing tpo_td043_device\n"); | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
9ce4ad0a GI |
420 | dssdev->panel.timings = tpo_td043_timings; |
421 | dssdev->ctrl.pixel_size = 24; | |
422 | ||
423 | tpo_td043->mode = TPO_R02_MODE_800x480; | |
424 | memcpy(tpo_td043->gamma, tpo_td043_def_gamma, sizeof(tpo_td043->gamma)); | |
425 | ||
426 | tpo_td043->vcc_reg = regulator_get(&dssdev->dev, "vcc"); | |
427 | if (IS_ERR(tpo_td043->vcc_reg)) { | |
428 | dev_err(&dssdev->dev, "failed to get LCD VCC regulator\n"); | |
429 | ret = PTR_ERR(tpo_td043->vcc_reg); | |
430 | goto fail_regulator; | |
431 | } | |
432 | ||
433 | if (gpio_is_valid(nreset_gpio)) { | |
f8bd4934 JH |
434 | ret = gpio_request_one(nreset_gpio, GPIOF_OUT_INIT_LOW, |
435 | "lcd reset"); | |
9ce4ad0a GI |
436 | if (ret < 0) { |
437 | dev_err(&dssdev->dev, "couldn't request reset GPIO\n"); | |
438 | goto fail_gpio_req; | |
439 | } | |
9ce4ad0a GI |
440 | } |
441 | ||
442 | ret = sysfs_create_group(&dssdev->dev.kobj, &tpo_td043_attr_group); | |
443 | if (ret) | |
444 | dev_warn(&dssdev->dev, "failed to create sysfs files\n"); | |
445 | ||
a2f9b2a5 GI |
446 | dev_set_drvdata(&dssdev->dev, tpo_td043); |
447 | ||
9ce4ad0a GI |
448 | return 0; |
449 | ||
9ce4ad0a GI |
450 | fail_gpio_req: |
451 | regulator_put(tpo_td043->vcc_reg); | |
452 | fail_regulator: | |
453 | kfree(tpo_td043); | |
454 | return ret; | |
455 | } | |
456 | ||
457 | static void tpo_td043_remove(struct omap_dss_device *dssdev) | |
458 | { | |
459 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev); | |
460 | int nreset_gpio = dssdev->reset_gpio; | |
461 | ||
462 | dev_dbg(&dssdev->dev, "remove\n"); | |
463 | ||
464 | sysfs_remove_group(&dssdev->dev.kobj, &tpo_td043_attr_group); | |
465 | regulator_put(tpo_td043->vcc_reg); | |
466 | if (gpio_is_valid(nreset_gpio)) | |
467 | gpio_free(nreset_gpio); | |
468 | } | |
469 | ||
31e8dfe1 GI |
470 | static void tpo_td043_set_timings(struct omap_dss_device *dssdev, |
471 | struct omap_video_timings *timings) | |
472 | { | |
c499144c | 473 | omapdss_dpi_set_timings(dssdev, timings); |
bdcae3cc AT |
474 | |
475 | dssdev->panel.timings = *timings; | |
31e8dfe1 GI |
476 | } |
477 | ||
478 | static int tpo_td043_check_timings(struct omap_dss_device *dssdev, | |
479 | struct omap_video_timings *timings) | |
480 | { | |
481 | return dpi_check_timings(dssdev, timings); | |
482 | } | |
483 | ||
9ce4ad0a GI |
484 | static struct omap_dss_driver tpo_td043_driver = { |
485 | .probe = tpo_td043_probe, | |
486 | .remove = tpo_td043_remove, | |
487 | ||
488 | .enable = tpo_td043_enable, | |
489 | .disable = tpo_td043_disable, | |
9ce4ad0a GI |
490 | .set_mirror = tpo_td043_set_hmirror, |
491 | .get_mirror = tpo_td043_get_hmirror, | |
492 | ||
31e8dfe1 GI |
493 | .set_timings = tpo_td043_set_timings, |
494 | .check_timings = tpo_td043_check_timings, | |
495 | ||
9ce4ad0a GI |
496 | .driver = { |
497 | .name = "tpo_td043mtea1_panel", | |
498 | .owner = THIS_MODULE, | |
499 | }, | |
500 | }; | |
501 | ||
502 | static int tpo_td043_spi_probe(struct spi_device *spi) | |
503 | { | |
504 | struct omap_dss_device *dssdev = spi->dev.platform_data; | |
505 | struct tpo_td043_device *tpo_td043; | |
506 | int ret; | |
507 | ||
508 | if (dssdev == NULL) { | |
509 | dev_err(&spi->dev, "missing dssdev\n"); | |
510 | return -ENODEV; | |
511 | } | |
512 | ||
a2f9b2a5 GI |
513 | if (g_tpo_td043 != NULL) |
514 | return -EBUSY; | |
515 | ||
9ce4ad0a GI |
516 | spi->bits_per_word = 16; |
517 | spi->mode = SPI_MODE_0; | |
518 | ||
519 | ret = spi_setup(spi); | |
520 | if (ret < 0) { | |
521 | dev_err(&spi->dev, "spi_setup failed: %d\n", ret); | |
522 | return ret; | |
523 | } | |
524 | ||
525 | tpo_td043 = kzalloc(sizeof(*tpo_td043), GFP_KERNEL); | |
526 | if (tpo_td043 == NULL) | |
527 | return -ENOMEM; | |
528 | ||
529 | tpo_td043->spi = spi; | |
8df4f5ce | 530 | tpo_td043->nreset_gpio = dssdev->reset_gpio; |
9ce4ad0a | 531 | dev_set_drvdata(&spi->dev, tpo_td043); |
a2f9b2a5 | 532 | g_tpo_td043 = tpo_td043; |
9ce4ad0a GI |
533 | |
534 | omap_dss_register_driver(&tpo_td043_driver); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
48c68c4f | 539 | static int tpo_td043_spi_remove(struct spi_device *spi) |
9ce4ad0a GI |
540 | { |
541 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&spi->dev); | |
542 | ||
543 | omap_dss_unregister_driver(&tpo_td043_driver); | |
544 | kfree(tpo_td043); | |
a2f9b2a5 | 545 | g_tpo_td043 = NULL; |
9ce4ad0a GI |
546 | |
547 | return 0; | |
548 | } | |
549 | ||
8df4f5ce GI |
550 | #ifdef CONFIG_PM_SLEEP |
551 | static int tpo_td043_spi_suspend(struct device *dev) | |
552 | { | |
553 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
554 | ||
555 | dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", tpo_td043); | |
556 | ||
557 | tpo_td043->power_on_resume = tpo_td043->powered_on; | |
558 | tpo_td043_power_off(tpo_td043); | |
559 | tpo_td043->spi_suspended = 1; | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static int tpo_td043_spi_resume(struct device *dev) | |
565 | { | |
566 | struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev); | |
567 | int ret; | |
568 | ||
569 | dev_dbg(dev, "tpo_td043_spi_resume\n"); | |
570 | ||
571 | if (tpo_td043->power_on_resume) { | |
572 | ret = tpo_td043_power_on(tpo_td043); | |
573 | if (ret) | |
574 | return ret; | |
575 | } | |
576 | tpo_td043->spi_suspended = 0; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | #endif | |
581 | ||
582 | static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm, | |
583 | tpo_td043_spi_suspend, tpo_td043_spi_resume); | |
584 | ||
9ce4ad0a GI |
585 | static struct spi_driver tpo_td043_spi_driver = { |
586 | .driver = { | |
587 | .name = "tpo_td043mtea1_panel_spi", | |
9ce4ad0a | 588 | .owner = THIS_MODULE, |
8df4f5ce | 589 | .pm = &tpo_td043_spi_pm, |
9ce4ad0a GI |
590 | }, |
591 | .probe = tpo_td043_spi_probe, | |
48c68c4f | 592 | .remove = tpo_td043_spi_remove, |
9ce4ad0a GI |
593 | }; |
594 | ||
c6d242aa | 595 | module_spi_driver(tpo_td043_spi_driver); |
9ce4ad0a GI |
596 | |
597 | MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>"); | |
598 | MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver"); | |
599 | MODULE_LICENSE("GPL"); |