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OMAPDSS: DISPC: Constify omap_overlay_info in dispc_ovl_setup()
[mirror_ubuntu-bionic-kernel.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
80c39712
TV		 49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
5ed8cf5b
TV		 64enum omap_burst_size {
65 BURST_SIZE_X2 = 0,
66 BURST_SIZE_X4 = 1,
67 BURST_SIZE_X8 = 2,
68};
69
80c39712
TV		 70#define REG_GET(idx, start, end) \
71 FLD_GET(dispc_read_reg(idx), start, end)
72
73#define REG_FLD_MOD(idx, val, start, end) \
74 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
75
dfc0fd8d
TV		 76struct dispc_irq_stats {
77 unsigned long last_reset;
78 unsigned irq_count;
79 unsigned irqs[32];
80};
81
dcbe765b
CM		 82struct dispc_features {
83 u8 sw_start;
84 u8 fp_start;
85 u8 bp_start;
86 u16 sw_max;
87 u16 vp_max;
88 u16 hp_max;
89 int (*calc_scaling) (enum omap_channel channel,
90 const struct omap_video_timings *mgr_timings,
91 u16 width, u16 height, u16 out_width, u16 out_height,
92 enum omap_color_mode color_mode, bool *five_taps,
93 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
94 u16 pos_x, unsigned long *core_clk);
95 unsigned long (*calc_core_clk) (enum omap_channel channel,
96 u16 width, u16 height, u16 out_width, u16 out_height);
42a6961c 97 u8 num_fifos;
66a0f9e4
TV		 98
99 /* swap GFX & WB fifos */
100 bool gfx_fifo_workaround:1;
dcbe765b
CM		 101};
102
42a6961c
TV		 103#define DISPC_MAX_NR_FIFOS 5
104
80c39712 105static struct {
060b6d9c 106 struct platform_device *pdev;
80c39712 107 void __iomem *base;
4fbafaf3
TV		 108
109 int ctx_loss_cnt;
110
affe360d 111 int irq;
4fbafaf3 112 struct clk *dss_clk;
80c39712 113
42a6961c
TV		 114 u32 fifo_size[DISPC_MAX_NR_FIFOS];
115 /* maps which plane is using a fifo. fifo-id -> plane-id */
116 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 117
118 spinlock_t irq_lock;
119 u32 irq_error_mask;
120 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
121 u32 error_irqs;
122 struct work_struct error_work;
123
49ea86f3 124 bool ctx_valid;
80c39712 125 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 126
dcbe765b
CM		 127 const struct dispc_features *feat;
128
dfc0fd8d
TV		 129#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
130 spinlock_t irq_stats_lock;
131 struct dispc_irq_stats irq_stats;
132#endif
80c39712
TV		 133} dispc;
134
0d66cbb5
AJ		 135enum omap_color_component {
136 /* used for all color formats for OMAP3 and earlier
137 * and for RGB and Y color component on OMAP4
138 */
139 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
140 /* used for UV component for
141 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
142 * color formats on OMAP4
143 */
144 DISPC_COLOR_COMPONENT_UV = 1 << 1,
145};
146
efa70b3b
CM		 147enum mgr_reg_fields {
148 DISPC_MGR_FLD_ENABLE,
149 DISPC_MGR_FLD_STNTFT,
150 DISPC_MGR_FLD_GO,
151 DISPC_MGR_FLD_TFTDATALINES,
152 DISPC_MGR_FLD_STALLMODE,
153 DISPC_MGR_FLD_TCKENABLE,
154 DISPC_MGR_FLD_TCKSELECTION,
155 DISPC_MGR_FLD_CPR,
156 DISPC_MGR_FLD_FIFOHANDCHECK,
157 /* used to maintain a count of the above fields */
158 DISPC_MGR_FLD_NUM,
159};
160
161static const struct {
162 const char *name;
163 u32 vsync_irq;
164 u32 framedone_irq;
165 u32 sync_lost_irq;
166 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
167} mgr_desc[] = {
168 [OMAP_DSS_CHANNEL_LCD] = {
169 .name = "LCD",
170 .vsync_irq = DISPC_IRQ_VSYNC,
171 .framedone_irq = DISPC_IRQ_FRAMEDONE,
172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_DIGIT] = {
186 .name = "DIGIT",
187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
188 .framedone_irq = 0,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
192 [DISPC_MGR_FLD_STNTFT] = { },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { },
195 [DISPC_MGR_FLD_STALLMODE] = { },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
198 [DISPC_MGR_FLD_CPR] = { },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
200 },
201 },
202 [OMAP_DSS_CHANNEL_LCD2] = {
203 .name = "LCD2",
204 .vsync_irq = DISPC_IRQ_VSYNC2,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
217 },
218 },
e86d456a
CM		 219 [OMAP_DSS_CHANNEL_LCD3] = {
220 .name = "LCD3",
221 .vsync_irq = DISPC_IRQ_VSYNC3,
222 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
224 .reg_desc = {
225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
234 },
235 },
efa70b3b
CM		 236};
237
80c39712
TV		 238static void _omap_dispc_set_irqs(void);
239
55978cc2 240static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 241{
55978cc2 242 __raw_writel(val, dispc.base + idx);
80c39712
TV		 243}
244
55978cc2 245static inline u32 dispc_read_reg(const u16 idx)
80c39712 246{
55978cc2 247 return __raw_readl(dispc.base + idx);
80c39712
TV		 248}
249
efa70b3b
CM		 250static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
251{
252 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
253 return REG_GET(rfld.reg, rfld.high, rfld.low);
254}
255
256static void mgr_fld_write(enum omap_channel channel,
257 enum mgr_reg_fields regfld, int val) {
258 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
259 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
260}
261
80c39712 262#define SR(reg) \
55978cc2 263 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 264#define RR(reg) \
55978cc2 265 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 266
4fbafaf3 267static void dispc_save_context(void)
80c39712 268{
c6104b8e 269 int i, j;
80c39712 270
4fbafaf3
TV		 271 DSSDBG("dispc_save_context\n");
272
80c39712
TV		 273 SR(IRQENABLE);
274 SR(CONTROL);
275 SR(CONFIG);
80c39712 276 SR(LINE_NUMBER);
11354dd5
AT		 277 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
278 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 279 SR(GLOBAL_ALPHA);
2a205f34
SS		 280 if (dss_has_feature(FEAT_MGR_LCD2)) {
281 SR(CONTROL2);
2a205f34
SS		 282 SR(CONFIG2);
283 }
e86d456a
CM		 284 if (dss_has_feature(FEAT_MGR_LCD3)) {
285 SR(CONTROL3);
286 SR(CONFIG3);
287 }
80c39712 288
c6104b8e
AT		 289 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
290 SR(DEFAULT_COLOR(i));
291 SR(TRANS_COLOR(i));
292 SR(SIZE_MGR(i));
293 if (i == OMAP_DSS_CHANNEL_DIGIT)
294 continue;
295 SR(TIMING_H(i));
296 SR(TIMING_V(i));
297 SR(POL_FREQ(i));
298 SR(DIVISORo(i));
299
300 SR(DATA_CYCLE1(i));
301 SR(DATA_CYCLE2(i));
302 SR(DATA_CYCLE3(i));
303
332e9d70 304 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 305 SR(CPR_COEF_R(i));
306 SR(CPR_COEF_G(i));
307 SR(CPR_COEF_B(i));
332e9d70 308 }
2a205f34 309 }
80c39712 310
c6104b8e
AT		 311 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
312 SR(OVL_BA0(i));
313 SR(OVL_BA1(i));
314 SR(OVL_POSITION(i));
315 SR(OVL_SIZE(i));
316 SR(OVL_ATTRIBUTES(i));
317 SR(OVL_FIFO_THRESHOLD(i));
318 SR(OVL_ROW_INC(i));
319 SR(OVL_PIXEL_INC(i));
320 if (dss_has_feature(FEAT_PRELOAD))
321 SR(OVL_PRELOAD(i));
322 if (i == OMAP_DSS_GFX) {
323 SR(OVL_WINDOW_SKIP(i));
324 SR(OVL_TABLE_BA(i));
325 continue;
326 }
327 SR(OVL_FIR(i));
328 SR(OVL_PICTURE_SIZE(i));
329 SR(OVL_ACCU0(i));
330 SR(OVL_ACCU1(i));
9b372c2d 331
c6104b8e
AT		 332 for (j = 0; j < 8; j++)
333 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 334
c6104b8e
AT		 335 for (j = 0; j < 8; j++)
336 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 337
c6104b8e
AT		 338 for (j = 0; j < 5; j++)
339 SR(OVL_CONV_COEF(i, j));
ab5ca071 340
c6104b8e
AT		 341 if (dss_has_feature(FEAT_FIR_COEF_V)) {
342 for (j = 0; j < 8; j++)
343 SR(OVL_FIR_COEF_V(i, j));
344 }
9b372c2d 345
c6104b8e
AT		 346 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
347 SR(OVL_BA0_UV(i));
348 SR(OVL_BA1_UV(i));
349 SR(OVL_FIR2(i));
350 SR(OVL_ACCU2_0(i));
351 SR(OVL_ACCU2_1(i));
ab5ca071 352
c6104b8e
AT		 353 for (j = 0; j < 8; j++)
354 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 355
c6104b8e
AT		 356 for (j = 0; j < 8; j++)
357 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 358
c6104b8e
AT		 359 for (j = 0; j < 8; j++)
360 SR(OVL_FIR_COEF_V2(i, j));
361 }
362 if (dss_has_feature(FEAT_ATTR2))
363 SR(OVL_ATTRIBUTES2(i));
ab5ca071 364 }
0cf35df3
MR		 365
366 if (dss_has_feature(FEAT_CORE_CLK_DIV))
367 SR(DIVISOR);
49ea86f3 368
00928eaf 369 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 370 dispc.ctx_valid = true;
371
372 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 373}
374
4fbafaf3 375static void dispc_restore_context(void)
80c39712 376{
c6104b8e 377 int i, j, ctx;
4fbafaf3
TV		 378
379 DSSDBG("dispc_restore_context\n");
380
49ea86f3
TV		 381 if (!dispc.ctx_valid)
382 return;
383
00928eaf 384 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 385
386 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
387 return;
388
389 DSSDBG("ctx_loss_count: saved %d, current %d\n",
390 dispc.ctx_loss_cnt, ctx);
391
75c7d59d 392 /*RR(IRQENABLE);*/
80c39712
TV		 393 /*RR(CONTROL);*/
394 RR(CONFIG);
80c39712 395 RR(LINE_NUMBER);
11354dd5
AT		 396 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
397 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 398 RR(GLOBAL_ALPHA);
c6104b8e 399 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 400 RR(CONFIG2);
e86d456a
CM		 401 if (dss_has_feature(FEAT_MGR_LCD3))
402 RR(CONFIG3);
80c39712 403
c6104b8e
AT		 404 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
405 RR(DEFAULT_COLOR(i));
406 RR(TRANS_COLOR(i));
407 RR(SIZE_MGR(i));
408 if (i == OMAP_DSS_CHANNEL_DIGIT)
409 continue;
410 RR(TIMING_H(i));
411 RR(TIMING_V(i));
412 RR(POL_FREQ(i));
413 RR(DIVISORo(i));
414
415 RR(DATA_CYCLE1(i));
416 RR(DATA_CYCLE2(i));
417 RR(DATA_CYCLE3(i));
2a205f34 418
332e9d70 419 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 420 RR(CPR_COEF_R(i));
421 RR(CPR_COEF_G(i));
422 RR(CPR_COEF_B(i));
332e9d70 423 }
2a205f34 424 }
80c39712 425
c6104b8e
AT		 426 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
427 RR(OVL_BA0(i));
428 RR(OVL_BA1(i));
429 RR(OVL_POSITION(i));
430 RR(OVL_SIZE(i));
431 RR(OVL_ATTRIBUTES(i));
432 RR(OVL_FIFO_THRESHOLD(i));
433 RR(OVL_ROW_INC(i));
434 RR(OVL_PIXEL_INC(i));
435 if (dss_has_feature(FEAT_PRELOAD))
436 RR(OVL_PRELOAD(i));
437 if (i == OMAP_DSS_GFX) {
438 RR(OVL_WINDOW_SKIP(i));
439 RR(OVL_TABLE_BA(i));
440 continue;
441 }
442 RR(OVL_FIR(i));
443 RR(OVL_PICTURE_SIZE(i));
444 RR(OVL_ACCU0(i));
445 RR(OVL_ACCU1(i));
9b372c2d 446
c6104b8e
AT		 447 for (j = 0; j < 8; j++)
448 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 449
c6104b8e
AT		 450 for (j = 0; j < 8; j++)
451 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 452
c6104b8e
AT		 453 for (j = 0; j < 5; j++)
454 RR(OVL_CONV_COEF(i, j));
ab5ca071 455
c6104b8e
AT		 456 if (dss_has_feature(FEAT_FIR_COEF_V)) {
457 for (j = 0; j < 8; j++)
458 RR(OVL_FIR_COEF_V(i, j));
459 }
9b372c2d 460
c6104b8e
AT		 461 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
462 RR(OVL_BA0_UV(i));
463 RR(OVL_BA1_UV(i));
464 RR(OVL_FIR2(i));
465 RR(OVL_ACCU2_0(i));
466 RR(OVL_ACCU2_1(i));
ab5ca071 467
c6104b8e
AT		 468 for (j = 0; j < 8; j++)
469 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 470
c6104b8e
AT		 471 for (j = 0; j < 8; j++)
472 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 473
c6104b8e
AT		 474 for (j = 0; j < 8; j++)
475 RR(OVL_FIR_COEF_V2(i, j));
476 }
477 if (dss_has_feature(FEAT_ATTR2))
478 RR(OVL_ATTRIBUTES2(i));
ab5ca071 479 }
80c39712 480
0cf35df3
MR		 481 if (dss_has_feature(FEAT_CORE_CLK_DIV))
482 RR(DIVISOR);
483
80c39712
TV		 484 /* enable last, because LCD & DIGIT enable are here */
485 RR(CONTROL);
2a205f34
SS		 486 if (dss_has_feature(FEAT_MGR_LCD2))
487 RR(CONTROL2);
e86d456a
CM		 488 if (dss_has_feature(FEAT_MGR_LCD3))
489 RR(CONTROL3);
75c7d59d
VS		 490 /* clear spurious SYNC_LOST_DIGIT interrupts */
491 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
492
493 /*
494 * enable last so IRQs won't trigger before
495 * the context is fully restored
496 */
497 RR(IRQENABLE);
49ea86f3
TV		 498
499 DSSDBG("context restored\n");
80c39712
TV		 500}
501
502#undef SR
503#undef RR
504
4fbafaf3
TV		 505int dispc_runtime_get(void)
506{
507 int r;
508
509 DSSDBG("dispc_runtime_get\n");
510
511 r = pm_runtime_get_sync(&dispc.pdev->dev);
512 WARN_ON(r < 0);
513 return r < 0 ? r : 0;
514}
515
516void dispc_runtime_put(void)
517{
518 int r;
519
520 DSSDBG("dispc_runtime_put\n");
521
0eaf9f52 522 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 523 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 524}
525
3dcec4d6
TV		 526u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
527{
efa70b3b 528 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 529}
530
7d1365c9
TV		 531u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
532{
efa70b3b 533 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 534}
535
26d9dd0d 536bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 537{
efa70b3b 538 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 539}
540
26d9dd0d 541void dispc_mgr_go(enum omap_channel channel)
80c39712 542{
2a205f34 543 bool enable_bit, go_bit;
80c39712 544
80c39712 545 /* if the channel is not enabled, we don't need GO */
efa70b3b 546 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 547
548 if (!enable_bit)
e6d80f95 549 return;
80c39712 550
efa70b3b 551 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 552
553 if (go_bit) {
80c39712 554 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 555 return;
80c39712
TV		 556 }
557
efa70b3b 558 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 559
efa70b3b 560 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 561}
562
f0e5caab 563static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 564{
9b372c2d 565 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 566}
567
f0e5caab 568static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 569{
9b372c2d 570 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 571}
572
f0e5caab 573static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 574{
9b372c2d 575 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 576}
577
f0e5caab 578static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 579{
580 BUG_ON(plane == OMAP_DSS_GFX);
581
582 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
583}
584
f0e5caab
TV		 585static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
586 u32 value)
ab5ca071
AJ		 587{
588 BUG_ON(plane == OMAP_DSS_GFX);
589
590 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
591}
592
f0e5caab 593static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 594{
595 BUG_ON(plane == OMAP_DSS_GFX);
596
597 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
598}
599
debd9074
CM		 600static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
601 int fir_vinc, int five_taps,
602 enum omap_color_component color_comp)
80c39712 603{
debd9074 604 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 605 int i;
606
debd9074
CM		 607 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
608 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 609
610 for (i = 0; i < 8; i++) {
611 u32 h, hv;
612
debd9074
CM		 613 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
614 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
615 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
616 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
617 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
618 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
619 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
620 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 621
0d66cbb5 622 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 623 dispc_ovl_write_firh_reg(plane, i, h);
624 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 625 } else {
f0e5caab
TV		 626 dispc_ovl_write_firh2_reg(plane, i, h);
627 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 628 }
629
80c39712
TV		 630 }
631
66be8f6c
GI		 632 if (five_taps) {
633 for (i = 0; i < 8; i++) {
634 u32 v;
debd9074
CM		 635 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
636 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 637 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 638 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 639 else
f0e5caab 640 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 641 }
80c39712
TV		 642 }
643}
644
645static void _dispc_setup_color_conv_coef(void)
646{
ac01c29e 647 int i;
80c39712
TV		 648 const struct color_conv_coef {
649 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
650 int full_range;
651 } ctbl_bt601_5 = {
652 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
653 };
654
655 const struct color_conv_coef *ct;
656
657#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
658
659 ct = &ctbl_bt601_5;
660
ac01c29e
AT		 661 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
662 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
663 CVAL(ct->rcr, ct->ry));
664 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
665 CVAL(ct->gy, ct->rcb));
666 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
667 CVAL(ct->gcb, ct->gcr));
668 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
669 CVAL(ct->bcr, ct->by));
670 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
671 CVAL(0, ct->bcb));
672
673 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
674 11, 11);
675 }
80c39712
TV		 676
677#undef CVAL
80c39712
TV		 678}
679
680
f0e5caab 681static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 682{
9b372c2d 683 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 684}
685
f0e5caab 686static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 687{
9b372c2d 688 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 689}
690
f0e5caab 691static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 692{
693 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
694}
695
f0e5caab 696static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 697{
698 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
699}
700
f0e5caab 701static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 702{
80c39712 703 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 704
705 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 706}
707
f0e5caab 708static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 709{
80c39712 710 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 711
712 if (plane == OMAP_DSS_GFX)
713 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
714 else
715 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 716}
717
f0e5caab 718static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 719{
720 u32 val;
80c39712
TV		 721
722 BUG_ON(plane == OMAP_DSS_GFX);
723
724 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 725
726 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 727}
728
54128701
AT		 729static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
730{
731 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
732
733 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
734 return;
735
736 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
737}
738
739static void dispc_ovl_enable_zorder_planes(void)
740{
741 int i;
742
743 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
744 return;
745
746 for (i = 0; i < dss_feat_get_num_ovls(); i++)
747 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
748}
749
f0e5caab 750static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 751{
f6dc8150 752 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 753
f6dc8150 754 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 755 return;
756
9b372c2d 757 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 758}
759
f0e5caab 760static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 761{
b8c095b4 762 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 763 int shift;
f6dc8150 764 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 765
f6dc8150 766 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 767 return;
a0acb557 768
fe3cc9d6
TV		 769 shift = shifts[plane];
770 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 771}
772
f0e5caab 773static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 774{
9b372c2d 775 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 776}
777
f0e5caab 778static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 779{
9b372c2d 780 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 781}
782
f0e5caab 783static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 784 enum omap_color_mode color_mode)
785{
786 u32 m = 0;
f20e4220
AJ		 787 if (plane != OMAP_DSS_GFX) {
788 switch (color_mode) {
789 case OMAP_DSS_COLOR_NV12:
790 m = 0x0; break;
08f3267e 791 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 792 m = 0x1; break;
793 case OMAP_DSS_COLOR_RGBA16:
794 m = 0x2; break;
08f3267e 795 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 796 m = 0x4; break;
797 case OMAP_DSS_COLOR_ARGB16:
798 m = 0x5; break;
799 case OMAP_DSS_COLOR_RGB16:
800 m = 0x6; break;
801 case OMAP_DSS_COLOR_ARGB16_1555:
802 m = 0x7; break;
803 case OMAP_DSS_COLOR_RGB24U:
804 m = 0x8; break;
805 case OMAP_DSS_COLOR_RGB24P:
806 m = 0x9; break;
807 case OMAP_DSS_COLOR_YUV2:
808 m = 0xa; break;
809 case OMAP_DSS_COLOR_UYVY:
810 m = 0xb; break;
811 case OMAP_DSS_COLOR_ARGB32:
812 m = 0xc; break;
813 case OMAP_DSS_COLOR_RGBA32:
814 m = 0xd; break;
815 case OMAP_DSS_COLOR_RGBX32:
816 m = 0xe; break;
817 case OMAP_DSS_COLOR_XRGB16_1555:
818 m = 0xf; break;
819 default:
c6eee968 820 BUG(); return;
f20e4220
AJ		 821 }
822 } else {
823 switch (color_mode) {
824 case OMAP_DSS_COLOR_CLUT1:
825 m = 0x0; break;
826 case OMAP_DSS_COLOR_CLUT2:
827 m = 0x1; break;
828 case OMAP_DSS_COLOR_CLUT4:
829 m = 0x2; break;
830 case OMAP_DSS_COLOR_CLUT8:
831 m = 0x3; break;
832 case OMAP_DSS_COLOR_RGB12U:
833 m = 0x4; break;
834 case OMAP_DSS_COLOR_ARGB16:
835 m = 0x5; break;
836 case OMAP_DSS_COLOR_RGB16:
837 m = 0x6; break;
838 case OMAP_DSS_COLOR_ARGB16_1555:
839 m = 0x7; break;
840 case OMAP_DSS_COLOR_RGB24U:
841 m = 0x8; break;
842 case OMAP_DSS_COLOR_RGB24P:
843 m = 0x9; break;
08f3267e 844 case OMAP_DSS_COLOR_RGBX16:
f20e4220 845 m = 0xa; break;
08f3267e 846 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 847 m = 0xb; break;
848 case OMAP_DSS_COLOR_ARGB32:
849 m = 0xc; break;
850 case OMAP_DSS_COLOR_RGBA32:
851 m = 0xd; break;
852 case OMAP_DSS_COLOR_RGBX32:
853 m = 0xe; break;
854 case OMAP_DSS_COLOR_XRGB16_1555:
855 m = 0xf; break;
856 default:
c6eee968 857 BUG(); return;
f20e4220 858 }
80c39712
TV		 859 }
860
9b372c2d 861 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 862}
863
65e006ff
CM		 864static void dispc_ovl_configure_burst_type(enum omap_plane plane,
865 enum omap_dss_rotation_type rotation_type)
866{
867 if (dss_has_feature(FEAT_BURST_2D) == 0)
868 return;
869
870 if (rotation_type == OMAP_DSS_ROT_TILER)
871 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
872 else
873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
874}
875
f427984e 876void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 877{
878 int shift;
879 u32 val;
2a205f34 880 int chan = 0, chan2 = 0;
80c39712
TV		 881
882 switch (plane) {
883 case OMAP_DSS_GFX:
884 shift = 8;
885 break;
886 case OMAP_DSS_VIDEO1:
887 case OMAP_DSS_VIDEO2:
b8c095b4 888 case OMAP_DSS_VIDEO3:
80c39712
TV		 889 shift = 16;
890 break;
891 default:
892 BUG();
893 return;
894 }
895
9b372c2d 896 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 897 if (dss_has_feature(FEAT_MGR_LCD2)) {
898 switch (channel) {
899 case OMAP_DSS_CHANNEL_LCD:
900 chan = 0;
901 chan2 = 0;
902 break;
903 case OMAP_DSS_CHANNEL_DIGIT:
904 chan = 1;
905 chan2 = 0;
906 break;
907 case OMAP_DSS_CHANNEL_LCD2:
908 chan = 0;
909 chan2 = 1;
910 break;
e86d456a
CM		 911 case OMAP_DSS_CHANNEL_LCD3:
912 if (dss_has_feature(FEAT_MGR_LCD3)) {
913 chan = 0;
914 chan2 = 2;
915 } else {
916 BUG();
917 return;
918 }
919 break;
2a205f34
SS		 920 default:
921 BUG();
c6eee968 922 return;
2a205f34
SS		 923 }
924
925 val = FLD_MOD(val, chan, shift, shift);
926 val = FLD_MOD(val, chan2, 31, 30);
927 } else {
928 val = FLD_MOD(val, channel, shift, shift);
929 }
9b372c2d 930 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 931}
932
2cc5d1af
TV		 933static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
934{
935 int shift;
936 u32 val;
937 enum omap_channel channel;
938
939 switch (plane) {
940 case OMAP_DSS_GFX:
941 shift = 8;
942 break;
943 case OMAP_DSS_VIDEO1:
944 case OMAP_DSS_VIDEO2:
945 case OMAP_DSS_VIDEO3:
946 shift = 16;
947 break;
948 default:
949 BUG();
c6eee968 950 return 0;
2cc5d1af
TV		 951 }
952
953 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
954
e86d456a
CM		 955 if (dss_has_feature(FEAT_MGR_LCD3)) {
956 if (FLD_GET(val, 31, 30) == 0)
957 channel = FLD_GET(val, shift, shift);
958 else if (FLD_GET(val, 31, 30) == 1)
959 channel = OMAP_DSS_CHANNEL_LCD2;
960 else
961 channel = OMAP_DSS_CHANNEL_LCD3;
962 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 963 if (FLD_GET(val, 31, 30) == 0)
964 channel = FLD_GET(val, shift, shift);
965 else
966 channel = OMAP_DSS_CHANNEL_LCD2;
967 } else {
968 channel = FLD_GET(val, shift, shift);
969 }
970
971 return channel;
972}
973
f0e5caab 974static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 975 enum omap_burst_size burst_size)
976{
b8c095b4 977 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 978 int shift;
80c39712 979
fe3cc9d6 980 shift = shifts[plane];
5ed8cf5b 981 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 982}
983
5ed8cf5b
TV		 984static void dispc_configure_burst_sizes(void)
985{
986 int i;
987 const int burst_size = BURST_SIZE_X8;
988
989 /* Configure burst size always to maximum size */
990 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 991 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 992}
993
83fa2f2e 994static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 995{
996 unsigned unit = dss_feat_get_burst_size_unit();
997 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
998 return unit * 8;
999}
1000
d3862610
M		 1001void dispc_enable_gamma_table(bool enable)
1002{
1003 /*
1004 * This is partially implemented to support only disabling of
1005 * the gamma table.
1006 */
1007 if (enable) {
1008 DSSWARN("Gamma table enabling for TV not yet supported");
1009 return;
1010 }
1011
1012 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1013}
1014
c64dca40 1015static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1016{
efa70b3b 1017 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1018 return;
1019
efa70b3b 1020 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1021}
1022
c64dca40 1023static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 1024 struct omap_dss_cpr_coefs *coefs)
1025{
1026 u32 coef_r, coef_g, coef_b;
1027
dd88b7a6 1028 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1029 return;
1030
1031 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1032 FLD_VAL(coefs->rb, 9, 0);
1033 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1034 FLD_VAL(coefs->gb, 9, 0);
1035 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1036 FLD_VAL(coefs->bb, 9, 0);
1037
1038 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1039 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1040 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1041}
1042
f0e5caab 1043static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1044{
1045 u32 val;
1046
1047 BUG_ON(plane == OMAP_DSS_GFX);
1048
9b372c2d 1049 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1050 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1051 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1052}
1053
c3d92529 1054static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 1055{
b8c095b4 1056 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1057 int shift;
80c39712 1058
fe3cc9d6
TV		 1059 shift = shifts[plane];
1060 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1061}
1062
8f366162 1063static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1064 u16 height)
80c39712
TV		 1065{
1066 u32 val;
80c39712 1067
80c39712 1068 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1069 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1070}
1071
42a6961c 1072static void dispc_init_fifos(void)
80c39712 1073{
80c39712 1074 u32 size;
42a6961c 1075 int fifo;
a0acb557 1076 u8 start, end;
5ed8cf5b
TV		 1077 u32 unit;
1078
1079 unit = dss_feat_get_buffer_size_unit();
80c39712 1080
a0acb557 1081 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1082
42a6961c
TV		 1083 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1084 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1085 size *= unit;
42a6961c
TV		 1086 dispc.fifo_size[fifo] = size;
1087
1088 /*
1089 * By default fifos are mapped directly to overlays, fifo 0 to
1090 * ovl 0, fifo 1 to ovl 1, etc.
1091 */
1092 dispc.fifo_assignment[fifo] = fifo;
80c39712 1093 }
66a0f9e4
TV		 1094
1095 /*
1096 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1097 * causes problems with certain use cases, like using the tiler in 2D
1098 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1099 * giving GFX plane a larger fifo. WB but should work fine with a
1100 * smaller fifo.
1101 */
1102 if (dispc.feat->gfx_fifo_workaround) {
1103 u32 v;
1104
1105 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1106
1107 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1108 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1109 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1110 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1111
1112 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1113
1114 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1115 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1116 }
80c39712
TV		 1117}
1118
83fa2f2e 1119static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1120{
42a6961c
TV		 1121 int fifo;
1122 u32 size = 0;
1123
1124 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1125 if (dispc.fifo_assignment[fifo] == plane)
1126 size += dispc.fifo_size[fifo];
1127 }
1128
1129 return size;
80c39712
TV		 1130}
1131
6f04e1bf 1132void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1133{
a0acb557 1134 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1135 u32 unit;
1136
1137 unit = dss_feat_get_buffer_size_unit();
1138
1139 WARN_ON(low % unit != 0);
1140 WARN_ON(high % unit != 0);
1141
1142 low /= unit;
1143 high /= unit;
a0acb557 1144
9b372c2d
AT		 1145 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1146 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1147
3cb5d966 1148 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1149 plane,
9b372c2d 1150 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1151 lo_start, lo_end) * unit,
9b372c2d 1152 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1153 hi_start, hi_end) * unit,
1154 low * unit, high * unit);
80c39712 1155
9b372c2d 1156 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1157 FLD_VAL(high, hi_start, hi_end) |
1158 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1159}
1160
1161void dispc_enable_fifomerge(bool enable)
1162{
e6b0f884
TV		 1163 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1164 WARN_ON(enable);
1165 return;
1166 }
1167
80c39712
TV		 1168 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1169 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1170}
1171
83fa2f2e 1172void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1173 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1174 bool manual_update)
83fa2f2e
TV		 1175{
1176 /*
1177 * All sizes are in bytes. Both the buffer and burst are made of
1178 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1179 */
1180
1181 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1182 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1183 int i;
83fa2f2e
TV		 1184
1185 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1186 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1187
e0e405b9
TV		 1188 if (use_fifomerge) {
1189 total_fifo_size = 0;
1190 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1191 total_fifo_size += dispc_ovl_get_fifo_size(i);
1192 } else {
1193 total_fifo_size = ovl_fifo_size;
1194 }
1195
1196 /*
1197 * We use the same low threshold for both fifomerge and non-fifomerge
1198 * cases, but for fifomerge we calculate the high threshold using the
1199 * combined fifo size
1200 */
1201
3568f2a4 1202 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1203 *fifo_low = ovl_fifo_size - burst_size * 2;
1204 *fifo_high = total_fifo_size - burst_size;
1205 } else {
1206 *fifo_low = ovl_fifo_size - burst_size;
1207 *fifo_high = total_fifo_size - buf_unit;
1208 }
83fa2f2e
TV		 1209}
1210
f0e5caab 1211static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1212 int hinc, int vinc,
1213 enum omap_color_component color_comp)
80c39712
TV		 1214{
1215 u32 val;
80c39712 1216
0d66cbb5
AJ		 1217 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1218 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1219
0d66cbb5
AJ		 1220 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1221 &hinc_start, &hinc_end);
1222 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1223 &vinc_start, &vinc_end);
1224 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1225 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1226
0d66cbb5
AJ		 1227 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1228 } else {
1229 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1230 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1231 }
80c39712
TV		 1232}
1233
f0e5caab 1234static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1235{
1236 u32 val;
87a7484b 1237 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1238
87a7484b
AT		 1239 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1240 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1241
1242 val = FLD_VAL(vaccu, vert_start, vert_end) |
1243 FLD_VAL(haccu, hor_start, hor_end);
1244
9b372c2d 1245 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1246}
1247
f0e5caab 1248static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1249{
1250 u32 val;
87a7484b 1251 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1252
87a7484b
AT		 1253 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1254 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1255
1256 val = FLD_VAL(vaccu, vert_start, vert_end) |
1257 FLD_VAL(haccu, hor_start, hor_end);
1258
9b372c2d 1259 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1260}
1261
f0e5caab
TV		 1262static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1263 int vaccu)
ab5ca071
AJ		 1264{
1265 u32 val;
1266
1267 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1268 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1269}
1270
f0e5caab
TV		 1271static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1272 int vaccu)
ab5ca071
AJ		 1273{
1274 u32 val;
1275
1276 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1277 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1278}
80c39712 1279
f0e5caab 1280static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1281 u16 orig_width, u16 orig_height,
1282 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1283 bool five_taps, u8 rotation,
1284 enum omap_color_component color_comp)
80c39712 1285{
0d66cbb5 1286 int fir_hinc, fir_vinc;
80c39712 1287
ed14a3ce
AJ		 1288 fir_hinc = 1024 * orig_width / out_width;
1289 fir_vinc = 1024 * orig_height / out_height;
80c39712 1290
debd9074
CM		 1291 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1292 color_comp);
f0e5caab 1293 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1294}
1295
05dd0f53
CM		 1296static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1297 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1298 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1299{
1300 int h_accu2_0, h_accu2_1;
1301 int v_accu2_0, v_accu2_1;
1302 int chroma_hinc, chroma_vinc;
1303 int idx;
1304
1305 struct accu {
1306 s8 h0_m, h0_n;
1307 s8 h1_m, h1_n;
1308 s8 v0_m, v0_n;
1309 s8 v1_m, v1_n;
1310 };
1311
1312 const struct accu *accu_table;
1313 const struct accu *accu_val;
1314
1315 static const struct accu accu_nv12[4] = {
1316 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1317 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1318 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1319 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1320 };
1321
1322 static const struct accu accu_nv12_ilace[4] = {
1323 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1324 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1325 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1326 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1327 };
1328
1329 static const struct accu accu_yuv[4] = {
1330 { 0, 1, 0, 1, 0, 1, 0, 1 },
1331 { 0, 1, 0, 1, 0, 1, 0, 1 },
1332 { -1, 1, 0, 1, 0, 1, 0, 1 },
1333 { 0, 1, 0, 1, -1, 1, 0, 1 },
1334 };
1335
1336 switch (rotation) {
1337 case OMAP_DSS_ROT_0:
1338 idx = 0;
1339 break;
1340 case OMAP_DSS_ROT_90:
1341 idx = 1;
1342 break;
1343 case OMAP_DSS_ROT_180:
1344 idx = 2;
1345 break;
1346 case OMAP_DSS_ROT_270:
1347 idx = 3;
1348 break;
1349 default:
1350 BUG();
c6eee968 1351 return;
05dd0f53
CM		 1352 }
1353
1354 switch (color_mode) {
1355 case OMAP_DSS_COLOR_NV12:
1356 if (ilace)
1357 accu_table = accu_nv12_ilace;
1358 else
1359 accu_table = accu_nv12;
1360 break;
1361 case OMAP_DSS_COLOR_YUV2:
1362 case OMAP_DSS_COLOR_UYVY:
1363 accu_table = accu_yuv;
1364 break;
1365 default:
1366 BUG();
c6eee968 1367 return;
05dd0f53
CM		 1368 }
1369
1370 accu_val = &accu_table[idx];
1371
1372 chroma_hinc = 1024 * orig_width / out_width;
1373 chroma_vinc = 1024 * orig_height / out_height;
1374
1375 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1376 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1377 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1378 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1379
1380 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1381 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1382}
1383
f0e5caab 1384static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1385 u16 orig_width, u16 orig_height,
1386 u16 out_width, u16 out_height,
1387 bool ilace, bool five_taps,
1388 bool fieldmode, enum omap_color_mode color_mode,
1389 u8 rotation)
1390{
1391 int accu0 = 0;
1392 int accu1 = 0;
1393 u32 l;
80c39712 1394
f0e5caab 1395 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1396 out_width, out_height, five_taps,
1397 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1398 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1399
87a7484b
AT		 1400 /* RESIZEENABLE and VERTICALTAPS */
1401 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1402 l |= (orig_width != out_width) ? (1 << 5) : 0;
1403 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1404 l |= five_taps ? (1 << 21) : 0;
80c39712 1405
87a7484b
AT		 1406 /* VRESIZECONF and HRESIZECONF */
1407 if (dss_has_feature(FEAT_RESIZECONF)) {
1408 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1409 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1410 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1411 }
80c39712 1412
87a7484b
AT		 1413 /* LINEBUFFERSPLIT */
1414 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1415 l &= ~(0x1 << 22);
1416 l |= five_taps ? (1 << 22) : 0;
1417 }
80c39712 1418
9b372c2d 1419 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1420
1421 /*
1422 * field 0 = even field = bottom field
1423 * field 1 = odd field = top field
1424 */
1425 if (ilace && !fieldmode) {
1426 accu1 = 0;
0d66cbb5 1427 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1428 if (accu0 >= 1024/2) {
1429 accu1 = 1024/2;
1430 accu0 -= accu1;
1431 }
1432 }
1433
f0e5caab
TV		 1434 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1435 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1436}
1437
f0e5caab 1438static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1439 u16 orig_width, u16 orig_height,
1440 u16 out_width, u16 out_height,
1441 bool ilace, bool five_taps,
1442 bool fieldmode, enum omap_color_mode color_mode,
1443 u8 rotation)
1444{
1445 int scale_x = out_width != orig_width;
1446 int scale_y = out_height != orig_height;
1447
1448 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1449 return;
1450 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1451 color_mode != OMAP_DSS_COLOR_UYVY &&
1452 color_mode != OMAP_DSS_COLOR_NV12)) {
1453 /* reset chroma resampling for RGB formats */
1454 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1455 return;
1456 }
36377357
TV		 1457
1458 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1459 out_height, ilace, color_mode, rotation);
1460
0d66cbb5
AJ		 1461 switch (color_mode) {
1462 case OMAP_DSS_COLOR_NV12:
1463 /* UV is subsampled by 2 vertically*/
1464 orig_height >>= 1;
1465 /* UV is subsampled by 2 horz.*/
1466 orig_width >>= 1;
1467 break;
1468 case OMAP_DSS_COLOR_YUV2:
1469 case OMAP_DSS_COLOR_UYVY:
1470 /*For YUV422 with 90/270 rotation,
1471 *we don't upsample chroma
1472 */
1473 if (rotation == OMAP_DSS_ROT_0 ||
1474 rotation == OMAP_DSS_ROT_180)
1475 /* UV is subsampled by 2 hrz*/
1476 orig_width >>= 1;
1477 /* must use FIR for YUV422 if rotated */
1478 if (rotation != OMAP_DSS_ROT_0)
1479 scale_x = scale_y = true;
1480 break;
1481 default:
1482 BUG();
c6eee968 1483 return;
0d66cbb5
AJ		 1484 }
1485
1486 if (out_width != orig_width)
1487 scale_x = true;
1488 if (out_height != orig_height)
1489 scale_y = true;
1490
f0e5caab 1491 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1492 out_width, out_height, five_taps,
1493 rotation, DISPC_COLOR_COMPONENT_UV);
1494
1495 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1496 (scale_x || scale_y) ? 1 : 0, 8, 8);
1497 /* set H scaling */
1498 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1499 /* set V scaling */
1500 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1501}
1502
f0e5caab 1503static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1504 u16 orig_width, u16 orig_height,
1505 u16 out_width, u16 out_height,
1506 bool ilace, bool five_taps,
1507 bool fieldmode, enum omap_color_mode color_mode,
1508 u8 rotation)
1509{
1510 BUG_ON(plane == OMAP_DSS_GFX);
1511
f0e5caab 1512 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1513 orig_width, orig_height,
1514 out_width, out_height,
1515 ilace, five_taps,
1516 fieldmode, color_mode,
1517 rotation);
1518
f0e5caab 1519 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1520 orig_width, orig_height,
1521 out_width, out_height,
1522 ilace, five_taps,
1523 fieldmode, color_mode,
1524 rotation);
1525}
1526
f0e5caab 1527static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1528 bool mirroring, enum omap_color_mode color_mode)
1529{
87a7484b
AT		 1530 bool row_repeat = false;
1531 int vidrot = 0;
1532
80c39712
TV		 1533 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1534 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1535
1536 if (mirroring) {
1537 switch (rotation) {
1538 case OMAP_DSS_ROT_0:
1539 vidrot = 2;
1540 break;
1541 case OMAP_DSS_ROT_90:
1542 vidrot = 1;
1543 break;
1544 case OMAP_DSS_ROT_180:
1545 vidrot = 0;
1546 break;
1547 case OMAP_DSS_ROT_270:
1548 vidrot = 3;
1549 break;
1550 }
1551 } else {
1552 switch (rotation) {
1553 case OMAP_DSS_ROT_0:
1554 vidrot = 0;
1555 break;
1556 case OMAP_DSS_ROT_90:
1557 vidrot = 1;
1558 break;
1559 case OMAP_DSS_ROT_180:
1560 vidrot = 2;
1561 break;
1562 case OMAP_DSS_ROT_270:
1563 vidrot = 3;
1564 break;
1565 }
1566 }
1567
80c39712 1568 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1569 row_repeat = true;
80c39712 1570 else
87a7484b 1571 row_repeat = false;
80c39712 1572 }
87a7484b 1573
9b372c2d 1574 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1575 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1576 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1577 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1578}
1579
1580static int color_mode_to_bpp(enum omap_color_mode color_mode)
1581{
1582 switch (color_mode) {
1583 case OMAP_DSS_COLOR_CLUT1:
1584 return 1;
1585 case OMAP_DSS_COLOR_CLUT2:
1586 return 2;
1587 case OMAP_DSS_COLOR_CLUT4:
1588 return 4;
1589 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1590 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1591 return 8;
1592 case OMAP_DSS_COLOR_RGB12U:
1593 case OMAP_DSS_COLOR_RGB16:
1594 case OMAP_DSS_COLOR_ARGB16:
1595 case OMAP_DSS_COLOR_YUV2:
1596 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1597 case OMAP_DSS_COLOR_RGBA16:
1598 case OMAP_DSS_COLOR_RGBX16:
1599 case OMAP_DSS_COLOR_ARGB16_1555:
1600 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1601 return 16;
1602 case OMAP_DSS_COLOR_RGB24P:
1603 return 24;
1604 case OMAP_DSS_COLOR_RGB24U:
1605 case OMAP_DSS_COLOR_ARGB32:
1606 case OMAP_DSS_COLOR_RGBA32:
1607 case OMAP_DSS_COLOR_RGBX32:
1608 return 32;
1609 default:
1610 BUG();
c6eee968 1611 return 0;
80c39712
TV		 1612 }
1613}
1614
1615static s32 pixinc(int pixels, u8 ps)
1616{
1617 if (pixels == 1)
1618 return 1;
1619 else if (pixels > 1)
1620 return 1 + (pixels - 1) * ps;
1621 else if (pixels < 0)
1622 return 1 - (-pixels + 1) * ps;
1623 else
1624 BUG();
c6eee968 1625 return 0;
80c39712
TV		 1626}
1627
1628static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1629 u16 screen_width,
1630 u16 width, u16 height,
1631 enum omap_color_mode color_mode, bool fieldmode,
1632 unsigned int field_offset,
1633 unsigned *offset0, unsigned *offset1,
aed74b55 1634 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1635{
1636 u8 ps;
1637
1638 /* FIXME CLUT formats */
1639 switch (color_mode) {
1640 case OMAP_DSS_COLOR_CLUT1:
1641 case OMAP_DSS_COLOR_CLUT2:
1642 case OMAP_DSS_COLOR_CLUT4:
1643 case OMAP_DSS_COLOR_CLUT8:
1644 BUG();
1645 return;
1646 case OMAP_DSS_COLOR_YUV2:
1647 case OMAP_DSS_COLOR_UYVY:
1648 ps = 4;
1649 break;
1650 default:
1651 ps = color_mode_to_bpp(color_mode) / 8;
1652 break;
1653 }
1654
1655 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1656 width, height);
1657
1658 /*
1659 * field 0 = even field = bottom field
1660 * field 1 = odd field = top field
1661 */
1662 switch (rotation + mirror * 4) {
1663 case OMAP_DSS_ROT_0:
1664 case OMAP_DSS_ROT_180:
1665 /*
1666 * If the pixel format is YUV or UYVY divide the width
1667 * of the image by 2 for 0 and 180 degree rotation.
1668 */
1669 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1670 color_mode == OMAP_DSS_COLOR_UYVY)
1671 width = width >> 1;
1672 case OMAP_DSS_ROT_90:
1673 case OMAP_DSS_ROT_270:
1674 *offset1 = 0;
1675 if (field_offset)
1676 *offset0 = field_offset * screen_width * ps;
1677 else
1678 *offset0 = 0;
1679
aed74b55
CM		 1680 *row_inc = pixinc(1 +
1681 (y_predecim * screen_width - x_predecim * width) +
1682 (fieldmode ? screen_width : 0), ps);
1683 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1684 break;
1685
1686 case OMAP_DSS_ROT_0 + 4:
1687 case OMAP_DSS_ROT_180 + 4:
1688 /* If the pixel format is YUV or UYVY divide the width
1689 * of the image by 2 for 0 degree and 180 degree
1690 */
1691 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1692 color_mode == OMAP_DSS_COLOR_UYVY)
1693 width = width >> 1;
1694 case OMAP_DSS_ROT_90 + 4:
1695 case OMAP_DSS_ROT_270 + 4:
1696 *offset1 = 0;
1697 if (field_offset)
1698 *offset0 = field_offset * screen_width * ps;
1699 else
1700 *offset0 = 0;
aed74b55
CM		 1701 *row_inc = pixinc(1 -
1702 (y_predecim * screen_width + x_predecim * width) -
1703 (fieldmode ? screen_width : 0), ps);
1704 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1705 break;
1706
1707 default:
1708 BUG();
c6eee968 1709 return;
80c39712
TV		 1710 }
1711}
1712
1713static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1714 u16 screen_width,
1715 u16 width, u16 height,
1716 enum omap_color_mode color_mode, bool fieldmode,
1717 unsigned int field_offset,
1718 unsigned *offset0, unsigned *offset1,
aed74b55 1719 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1720{
1721 u8 ps;
1722 u16 fbw, fbh;
1723
1724 /* FIXME CLUT formats */
1725 switch (color_mode) {
1726 case OMAP_DSS_COLOR_CLUT1:
1727 case OMAP_DSS_COLOR_CLUT2:
1728 case OMAP_DSS_COLOR_CLUT4:
1729 case OMAP_DSS_COLOR_CLUT8:
1730 BUG();
1731 return;
1732 default:
1733 ps = color_mode_to_bpp(color_mode) / 8;
1734 break;
1735 }
1736
1737 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1738 width, height);
1739
1740 /* width & height are overlay sizes, convert to fb sizes */
1741
1742 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1743 fbw = width;
1744 fbh = height;
1745 } else {
1746 fbw = height;
1747 fbh = width;
1748 }
1749
1750 /*
1751 * field 0 = even field = bottom field
1752 * field 1 = odd field = top field
1753 */
1754 switch (rotation + mirror * 4) {
1755 case OMAP_DSS_ROT_0:
1756 *offset1 = 0;
1757 if (field_offset)
1758 *offset0 = *offset1 + field_offset * screen_width * ps;
1759 else
1760 *offset0 = *offset1;
aed74b55
CM		 1761 *row_inc = pixinc(1 +
1762 (y_predecim * screen_width - fbw * x_predecim) +
1763 (fieldmode ? screen_width : 0), ps);
1764 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1765 color_mode == OMAP_DSS_COLOR_UYVY)
1766 *pix_inc = pixinc(x_predecim, 2 * ps);
1767 else
1768 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1769 break;
1770 case OMAP_DSS_ROT_90:
1771 *offset1 = screen_width * (fbh - 1) * ps;
1772 if (field_offset)
1773 *offset0 = *offset1 + field_offset * ps;
1774 else
1775 *offset0 = *offset1;
aed74b55
CM		 1776 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1777 y_predecim + (fieldmode ? 1 : 0), ps);
1778 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1779 break;
1780 case OMAP_DSS_ROT_180:
1781 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1782 if (field_offset)
1783 *offset0 = *offset1 - field_offset * screen_width * ps;
1784 else
1785 *offset0 = *offset1;
1786 *row_inc = pixinc(-1 -
aed74b55
CM		 1787 (y_predecim * screen_width - fbw * x_predecim) -
1788 (fieldmode ? screen_width : 0), ps);
1789 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1790 color_mode == OMAP_DSS_COLOR_UYVY)
1791 *pix_inc = pixinc(-x_predecim, 2 * ps);
1792 else
1793 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1794 break;
1795 case OMAP_DSS_ROT_270:
1796 *offset1 = (fbw - 1) * ps;
1797 if (field_offset)
1798 *offset0 = *offset1 - field_offset * ps;
1799 else
1800 *offset0 = *offset1;
aed74b55
CM		 1801 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1802 y_predecim - (fieldmode ? 1 : 0), ps);
1803 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1804 break;
1805
1806 /* mirroring */
1807 case OMAP_DSS_ROT_0 + 4:
1808 *offset1 = (fbw - 1) * ps;
1809 if (field_offset)
1810 *offset0 = *offset1 + field_offset * screen_width * ps;
1811 else
1812 *offset0 = *offset1;
aed74b55 1813 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1814 (fieldmode ? screen_width : 0),
1815 ps);
aed74b55
CM		 1816 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1817 color_mode == OMAP_DSS_COLOR_UYVY)
1818 *pix_inc = pixinc(-x_predecim, 2 * ps);
1819 else
1820 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1821 break;
1822
1823 case OMAP_DSS_ROT_90 + 4:
1824 *offset1 = 0;
1825 if (field_offset)
1826 *offset0 = *offset1 + field_offset * ps;
1827 else
1828 *offset0 = *offset1;
aed74b55
CM		 1829 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1830 y_predecim + (fieldmode ? 1 : 0),
80c39712 1831 ps);
aed74b55 1832 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1833 break;
1834
1835 case OMAP_DSS_ROT_180 + 4:
1836 *offset1 = screen_width * (fbh - 1) * ps;
1837 if (field_offset)
1838 *offset0 = *offset1 - field_offset * screen_width * ps;
1839 else
1840 *offset0 = *offset1;
aed74b55 1841 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1842 (fieldmode ? screen_width : 0),
1843 ps);
aed74b55
CM		 1844 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1845 color_mode == OMAP_DSS_COLOR_UYVY)
1846 *pix_inc = pixinc(x_predecim, 2 * ps);
1847 else
1848 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1849 break;
1850
1851 case OMAP_DSS_ROT_270 + 4:
1852 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1853 if (field_offset)
1854 *offset0 = *offset1 - field_offset * ps;
1855 else
1856 *offset0 = *offset1;
aed74b55
CM		 1857 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1858 y_predecim - (fieldmode ? 1 : 0),
80c39712 1859 ps);
aed74b55 1860 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1861 break;
1862
1863 default:
1864 BUG();
c6eee968 1865 return;
80c39712
TV		 1866 }
1867}
1868
65e006ff
CM		 1869static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1870 enum omap_color_mode color_mode, bool fieldmode,
1871 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1872 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1873{
1874 u8 ps;
1875
1876 switch (color_mode) {
1877 case OMAP_DSS_COLOR_CLUT1:
1878 case OMAP_DSS_COLOR_CLUT2:
1879 case OMAP_DSS_COLOR_CLUT4:
1880 case OMAP_DSS_COLOR_CLUT8:
1881 BUG();
1882 return;
1883 default:
1884 ps = color_mode_to_bpp(color_mode) / 8;
1885 break;
1886 }
1887
1888 DSSDBG("scrw %d, width %d\n", screen_width, width);
1889
1890 /*
1891 * field 0 = even field = bottom field
1892 * field 1 = odd field = top field
1893 */
1894 *offset1 = 0;
1895 if (field_offset)
1896 *offset0 = *offset1 + field_offset * screen_width * ps;
1897 else
1898 *offset0 = *offset1;
1899 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1900 (fieldmode ? screen_width : 0), ps);
1901 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1902 color_mode == OMAP_DSS_COLOR_UYVY)
1903 *pix_inc = pixinc(x_predecim, 2 * ps);
1904 else
1905 *pix_inc = pixinc(x_predecim, ps);
1906}
1907
7faa9233
CM		 1908/*
1909 * This function is used to avoid synclosts in OMAP3, because of some
1910 * undocumented horizontal position and timing related limitations.
1911 */
81ab95b7
AT		 1912static int check_horiz_timing_omap3(enum omap_channel channel,
1913 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1914 u16 width, u16 height, u16 out_width, u16 out_height)
1915{
1916 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1917 unsigned long nonactive, lclk, pclk;
1918 static const u8 limits[3] = { 8, 10, 20 };
1919 u64 val, blank;
1920 int i;
1921
81ab95b7 1922 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233 1923 pclk = dispc_mgr_pclk_rate(channel);
dd88b7a6 1924 if (dss_mgr_is_lcd(channel))
7faa9233
CM		 1925 lclk = dispc_mgr_lclk_rate(channel);
1926 else
1927 lclk = dispc_fclk_rate();
1928
1929 i = 0;
1930 if (out_height < height)
1931 i++;
1932 if (out_width < width)
1933 i++;
81ab95b7 1934 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1935 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1936 if (blank <= limits[i])
1937 return -EINVAL;
1938
1939 /*
1940 * Pixel data should be prepared before visible display point starts.
1941 * So, atleast DS-2 lines must have already been fetched by DISPC
1942 * during nonactive - pos_x period.
1943 */
1944 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1945 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1946 val, max(0, DS - 2) * width);
1947 if (val < max(0, DS - 2) * width)
1948 return -EINVAL;
1949
1950 /*
1951 * All lines need to be refilled during the nonactive period of which
1952 * only one line can be loaded during the active period. So, atleast
1953 * DS - 1 lines should be loaded during nonactive period.
1954 */
1955 val = div_u64((u64)nonactive * lclk, pclk);
1956 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1957 val, max(0, DS - 1) * width);
1958 if (val < max(0, DS - 1) * width)
1959 return -EINVAL;
1960
1961 return 0;
1962}
1963
8b53d991 1964static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1965 const struct omap_video_timings *mgr_timings, u16 width,
1966 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1967 enum omap_color_mode color_mode)
80c39712 1968{
8b53d991 1969 u32 core_clk = 0;
26d9dd0d 1970 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1971
7282f1b7
CM		 1972 if (height <= out_height && width <= out_width)
1973 return (unsigned long) pclk;
1974
80c39712 1975 if (height > out_height) {
81ab95b7 1976 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1977
1978 tmp = pclk * height * out_width;
1979 do_div(tmp, 2 * out_height * ppl);
8b53d991 1980 core_clk = tmp;
80c39712 1981
2d9c5597
VS		 1982 if (height > 2 * out_height) {
1983 if (ppl == out_width)
1984 return 0;
1985
80c39712
TV		 1986 tmp = pclk * (height - 2 * out_height) * out_width;
1987 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1988 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1989 }
1990 }
1991
1992 if (width > out_width) {
1993 tmp = pclk * width;
1994 do_div(tmp, out_width);
8b53d991 1995 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1996
1997 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1998 core_clk <<= 1;
80c39712
TV		 1999 }
2000
8b53d991 2001 return core_clk;
80c39712
TV		 2002}
2003
dcbe765b
CM		 2004static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width,
2005 u16 height, u16 out_width, u16 out_height)
2006{
2007 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2008
2009 if (height > out_height && width > out_width)
2010 return pclk * 4;
2011 else
2012 return pclk * 2;
2013}
2014
2015static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width,
ff1b2cde 2016 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 2017{
2018 unsigned int hf, vf;
79ee89cd 2019 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 2020
2021 /*
2022 * FIXME how to determine the 'A' factor
2023 * for the no downscaling case ?
2024 */
2025
2026 if (width > 3 * out_width)
2027 hf = 4;
2028 else if (width > 2 * out_width)
2029 hf = 3;
2030 else if (width > out_width)
2031 hf = 2;
2032 else
2033 hf = 1;
80c39712
TV		 2034 if (height > out_height)
2035 vf = 2;
2036 else
2037 vf = 1;
2038
dcbe765b
CM		 2039 return pclk * vf * hf;
2040}
2041
2042static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width,
2043 u16 height, u16 out_width, u16 out_height)
2044{
2045 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2046
2047 if (width > out_width)
2048 return DIV_ROUND_UP(pclk, out_width) * width;
2049 else
2050 return pclk;
2051}
2052
2053static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel,
2054 const struct omap_video_timings *mgr_timings,
2055 u16 width, u16 height, u16 out_width, u16 out_height,
2056 enum omap_color_mode color_mode, bool *five_taps,
2057 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2058 u16 pos_x, unsigned long *core_clk)
2059{
2060 int error;
2061 u16 in_width, in_height;
2062 int min_factor = min(*decim_x, *decim_y);
2063 const int maxsinglelinewidth =
2064 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2065 *five_taps = false;
2066
2067 do {
2068 in_height = DIV_ROUND_UP(height, *decim_y);
2069 in_width = DIV_ROUND_UP(width, *decim_x);
2070 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2071 in_height, out_width, out_height);
2072 error = (in_width > maxsinglelinewidth || !*core_clk ||
2073 *core_clk > dispc_core_clk_rate());
2074 if (error) {
2075 if (*decim_x == *decim_y) {
2076 *decim_x = min_factor;
2077 ++*decim_y;
2078 } else {
2079 swap(*decim_x, *decim_y);
2080 if (*decim_x < *decim_y)
2081 ++*decim_x;
2082 }
2083 }
2084 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2085
2086 if (in_width > maxsinglelinewidth) {
2087 DSSERR("Cannot scale max input width exceeded");
2088 return -EINVAL;
2089 }
2090 return 0;
2091}
2092
2093static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel,
2094 const struct omap_video_timings *mgr_timings,
2095 u16 width, u16 height, u16 out_width, u16 out_height,
2096 enum omap_color_mode color_mode, bool *five_taps,
2097 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2098 u16 pos_x, unsigned long *core_clk)
2099{
2100 int error;
2101 u16 in_width, in_height;
2102 int min_factor = min(*decim_x, *decim_y);
2103 const int maxsinglelinewidth =
2104 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2105
2106 do {
2107 in_height = DIV_ROUND_UP(height, *decim_y);
2108 in_width = DIV_ROUND_UP(width, *decim_x);
2109 *core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2110 in_width, in_height, out_width, out_height, color_mode);
2111
2112 error = check_horiz_timing_omap3(channel, mgr_timings, pos_x,
2113 in_width, in_height, out_width, out_height);
2114
2115 if (in_width > maxsinglelinewidth)
2116 if (in_height > out_height &&
2117 in_height < out_height * 2)
2118 *five_taps = false;
2119 if (!*five_taps)
2120 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2121 in_height, out_width, out_height);
2122
2123 error = (error || in_width > maxsinglelinewidth * 2 ||
2124 (in_width > maxsinglelinewidth && *five_taps) ||
2125 !*core_clk || *core_clk > dispc_core_clk_rate());
2126 if (error) {
2127 if (*decim_x == *decim_y) {
2128 *decim_x = min_factor;
2129 ++*decim_y;
2130 } else {
2131 swap(*decim_x, *decim_y);
2132 if (*decim_x < *decim_y)
2133 ++*decim_x;
2134 }
2135 }
2136 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2137
2138 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height,
2139 out_width, out_height)){
2140 DSSERR("horizontal timing too tight\n");
2141 return -EINVAL;
7282f1b7 2142 }
dcbe765b
CM		 2143
2144 if (in_width > (maxsinglelinewidth * 2)) {
2145 DSSERR("Cannot setup scaling");
2146 DSSERR("width exceeds maximum width possible");
2147 return -EINVAL;
2148 }
2149
2150 if (in_width > maxsinglelinewidth && *five_taps) {
2151 DSSERR("cannot setup scaling with five taps");
2152 return -EINVAL;
2153 }
2154 return 0;
2155}
2156
2157static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel,
2158 const struct omap_video_timings *mgr_timings,
2159 u16 width, u16 height, u16 out_width, u16 out_height,
2160 enum omap_color_mode color_mode, bool *five_taps,
2161 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2162 u16 pos_x, unsigned long *core_clk)
2163{
2164 u16 in_width, in_width_max;
2165 int decim_x_min = *decim_x;
2166 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2167 const int maxsinglelinewidth =
2168 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2169
2170 in_width_max = dispc_core_clk_rate() /
2171 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width);
2172 *decim_x = DIV_ROUND_UP(width, in_width_max);
2173
2174 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2175 if (*decim_x > *x_predecim)
2176 return -EINVAL;
2177
2178 do {
2179 in_width = DIV_ROUND_UP(width, *decim_x);
2180 } while (*decim_x <= *x_predecim &&
2181 in_width > maxsinglelinewidth && ++*decim_x);
2182
2183 if (in_width > maxsinglelinewidth) {
2184 DSSERR("Cannot scale width exceeds max line width");
2185 return -EINVAL;
2186 }
2187
2188 *core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height,
2189 out_width, out_height);
2190 return 0;
80c39712
TV		 2191}
2192
79ad75f2 2193static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 2194 enum omap_channel channel,
2195 const struct omap_video_timings *mgr_timings,
2196 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2197 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf
CM		 2198 int *x_predecim, int *y_predecim, u16 pos_x,
2199 enum omap_dss_rotation_type rotation_type)
79ad75f2
AT		 2200{
2201 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 2202 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2203 const int max_decim_limit = 16;
8b53d991 2204 unsigned long core_clk = 0;
dcbe765b 2205 int decim_x, decim_y, ret;
79ad75f2 2206
f95cb5eb
TV		 2207 if (width == out_width && height == out_height)
2208 return 0;
2209
2210 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2211 return -EINVAL;
79ad75f2 2212
aed74b55 2213 *x_predecim = max_decim_limit;
d557a9cf
CM		 2214 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2215 dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit;
aed74b55
CM		 2216
2217 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2218 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2219 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2220 color_mode == OMAP_DSS_COLOR_CLUT8) {
2221 *x_predecim = 1;
2222 *y_predecim = 1;
2223 *five_taps = false;
2224 return 0;
2225 }
2226
2227 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2228 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2229
aed74b55 2230 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2231 return -EINVAL;
2232
aed74b55 2233 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2234 return -EINVAL;
2235
dcbe765b
CM		 2236 ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height,
2237 out_width, out_height, color_mode, five_taps, x_predecim,
2238 y_predecim, &decim_x, &decim_y, pos_x, &core_clk);
2239 if (ret)
2240 return ret;
79ad75f2 2241
8b53d991
CM		 2242 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2243 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2244
8b53d991 2245 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2246 DSSERR("failed to set up scaling, "
8b53d991
CM		 2247 "required core clk rate = %lu Hz, "
2248 "current core clk rate = %lu Hz\n",
2249 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2250 return -EINVAL;
2251 }
2252
aed74b55
CM		 2253 *x_predecim = decim_x;
2254 *y_predecim = decim_y;
79ad75f2
AT		 2255 return 0;
2256}
2257
8eeb7019 2258int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8050cbe4 2259 bool replication, const struct omap_video_timings *mgr_timings)
80c39712 2260{
79ad75f2 2261 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2262 bool five_taps = true;
80c39712 2263 bool fieldmode = 0;
79ad75f2 2264 int r, cconv = 0;
80c39712
TV		 2265 unsigned offset0, offset1;
2266 s32 row_inc;
2267 s32 pix_inc;
a4273b7c 2268 u16 frame_height = oi->height;
80c39712 2269 unsigned int field_offset = 0;
aed74b55
CM		 2270 u16 in_height = oi->height;
2271 u16 in_width = oi->width;
2272 u16 out_width, out_height;
2cc5d1af 2273 enum omap_channel channel;
aed74b55 2274 int x_predecim = 1, y_predecim = 1;
8050cbe4 2275 bool ilace = mgr_timings->interlace;
8eeb7019 2276 u16 pos_y = oi->pos_y;
2cc5d1af
TV		 2277
2278 channel = dispc_ovl_get_channel_out(plane);
80c39712 2279
a4273b7c 2280 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2281 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2282 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2283 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2284 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2285 oi->mirror, ilace, channel, replication);
e6d80f95 2286
a4273b7c 2287 if (oi->paddr == 0)
80c39712
TV		 2288 return -EINVAL;
2289
aed74b55
CM		 2290 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2291 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2292
aed74b55 2293 if (ilace && oi->height == out_height)
80c39712
TV		 2294 fieldmode = 1;
2295
2296 if (ilace) {
2297 if (fieldmode)
aed74b55 2298 in_height /= 2;
8eeb7019 2299 pos_y /= 2;
aed74b55 2300 out_height /= 2;
80c39712
TV		 2301
2302 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2303 "out_height %d\n",
8eeb7019 2304 in_height, pos_y, out_height);
80c39712
TV		 2305 }
2306
a4273b7c 2307 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2308 return -EINVAL;
2309
81ab95b7
AT		 2310 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2311 in_height, out_width, out_height, oi->color_mode,
d557a9cf
CM		 2312 &five_taps, &x_predecim, &y_predecim, oi->pos_x,
2313 oi->rotation_type);
79ad75f2
AT		 2314 if (r)
2315 return r;
80c39712 2316
aed74b55
CM		 2317 in_width = DIV_ROUND_UP(in_width, x_predecim);
2318 in_height = DIV_ROUND_UP(in_height, y_predecim);
2319
79ad75f2
AT		 2320 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2321 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2322 oi->color_mode == OMAP_DSS_COLOR_NV12)
2323 cconv = 1;
80c39712
TV		 2324
2325 if (ilace && !fieldmode) {
2326 /*
2327 * when downscaling the bottom field may have to start several
2328 * source lines below the top field. Unfortunately ACCUI
2329 * registers will only hold the fractional part of the offset
2330 * so the integer part must be added to the base address of the
2331 * bottom field.
2332 */
aed74b55 2333 if (!in_height || in_height == out_height)
80c39712
TV		 2334 field_offset = 0;
2335 else
aed74b55 2336 field_offset = in_height / out_height / 2;
80c39712
TV		 2337 }
2338
2339 /* Fields are independent but interleaved in memory. */
2340 if (fieldmode)
2341 field_offset = 1;
2342
c6eee968
TV		 2343 offset0 = 0;
2344 offset1 = 0;
2345 row_inc = 0;
2346 pix_inc = 0;
2347
65e006ff
CM		 2348 if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2349 calc_tiler_rotation_offset(oi->screen_width, in_width,
2350 oi->color_mode, fieldmode, field_offset,
2351 &offset0, &offset1, &row_inc, &pix_inc,
2352 x_predecim, y_predecim);
2353 else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
a4273b7c 2354 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2355 oi->screen_width, in_width, frame_height,
a4273b7c 2356 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2357 &offset0, &offset1, &row_inc, &pix_inc,
2358 x_predecim, y_predecim);
80c39712 2359 else
a4273b7c 2360 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2361 oi->screen_width, in_width, frame_height,
a4273b7c 2362 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2363 &offset0, &offset1, &row_inc, &pix_inc,
2364 x_predecim, y_predecim);
80c39712
TV		 2365
2366 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2367 offset0, offset1, row_inc, pix_inc);
2368
a4273b7c 2369 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2370
65e006ff
CM		 2371 dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2372
a4273b7c
AT		 2373 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2374 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2375
a4273b7c
AT		 2376 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2377 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2378 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2379 }
2380
2381
f0e5caab
TV		 2382 dispc_ovl_set_row_inc(plane, row_inc);
2383 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2384
aed74b55
CM		 2385 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2386 in_height, out_width, out_height);
80c39712 2387
8eeb7019 2388 dispc_ovl_set_pos(plane, oi->pos_x, pos_y);
80c39712 2389
aed74b55 2390 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2391
79ad75f2 2392 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2393 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2394 out_height, ilace, five_taps, fieldmode,
a4273b7c 2395 oi->color_mode, oi->rotation);
aed74b55 2396 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2397 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2398 }
2399
a4273b7c
AT		 2400 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2401 oi->color_mode);
80c39712 2402
54128701 2403 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2404 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2405 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2406
c3d92529 2407 dispc_ovl_enable_replication(plane, replication);
c3d92529 2408
80c39712
TV		 2409 return 0;
2410}
2411
f0e5caab 2412int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2413{
e6d80f95
TV		 2414 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2415
9b372c2d 2416 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2417
2418 return 0;
80c39712
TV		 2419}
2420
2421static void dispc_disable_isr(void *data, u32 mask)
2422{
2423 struct completion *compl = data;
2424 complete(compl);
2425}
2426
2a205f34 2427static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2428{
efa70b3b
CM		 2429 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2430 /* flush posted write */
2431 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2432}
2433
26d9dd0d 2434static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2435{
2436 struct completion frame_done_completion;
2437 bool is_on;
2438 int r;
2a205f34 2439 u32 irq;
80c39712 2440
80c39712
TV		 2441 /* When we disable LCD output, we need to wait until frame is done.
2442 * Otherwise the DSS is still working, and turning off the clocks
2443 * prevents DSS from going to OFF mode */
efa70b3b 2444 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2a205f34 2445
efa70b3b 2446 irq = mgr_desc[channel].framedone_irq;
80c39712
TV		 2447
2448 if (!enable && is_on) {
2449 init_completion(&frame_done_completion);
2450
2451 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2452 &frame_done_completion, irq);
80c39712
TV		 2453
2454 if (r)
2455 DSSERR("failed to register FRAMEDONE isr\n");
2456 }
2457
2a205f34 2458 _enable_lcd_out(channel, enable);
80c39712
TV		 2459
2460 if (!enable && is_on) {
2461 if (!wait_for_completion_timeout(&frame_done_completion,
2462 msecs_to_jiffies(100)))
2463 DSSERR("timeout waiting for FRAME DONE\n");
2464
2465 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2466 &frame_done_completion, irq);
80c39712
TV		 2467
2468 if (r)
2469 DSSERR("failed to unregister FRAMEDONE isr\n");
2470 }
80c39712
TV		 2471}
2472
2473static void _enable_digit_out(bool enable)
2474{
2475 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2476 /* flush posted write */
2477 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2478}
2479
26d9dd0d 2480static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2481{
2482 struct completion frame_done_completion;
e82b090b
TV		 2483 enum dss_hdmi_venc_clk_source_select src;
2484 int r, i;
2485 u32 irq_mask;
2486 int num_irqs;
80c39712 2487
e6d80f95 2488 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2489 return;
80c39712 2490
e82b090b
TV		 2491 src = dss_get_hdmi_venc_clk_source();
2492
80c39712
TV		 2493 if (enable) {
2494 unsigned long flags;
2495 /* When we enable digit output, we'll get an extra digit
2496 * sync lost interrupt, that we need to ignore */
2497 spin_lock_irqsave(&dispc.irq_lock, flags);
2498 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2499 _omap_dispc_set_irqs();
2500 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2501 }
2502
2503 /* When we disable digit output, we need to wait until fields are done.
2504 * Otherwise the DSS is still working, and turning off the clocks
2505 * prevents DSS from going to OFF mode. And when enabling, we need to
2506 * wait for the extra sync losts */
2507 init_completion(&frame_done_completion);
2508
e82b090b
TV		 2509 if (src == DSS_HDMI_M_PCLK && enable == false) {
2510 irq_mask = DISPC_IRQ_FRAMEDONETV;
2511 num_irqs = 1;
2512 } else {
2513 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2514 /* XXX I understand from TRM that we should only wait for the
2515 * current field to complete. But it seems we have to wait for
2516 * both fields */
2517 num_irqs = 2;
2518 }
2519
80c39712 2520 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2521 irq_mask);
80c39712 2522 if (r)
e82b090b 2523 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2524
2525 _enable_digit_out(enable);
2526
e82b090b
TV		 2527 for (i = 0; i < num_irqs; ++i) {
2528 if (!wait_for_completion_timeout(&frame_done_completion,
2529 msecs_to_jiffies(100)))
2530 DSSERR("timeout waiting for digit out to %s\n",
2531 enable ? "start" : "stop");
2532 }
80c39712 2533
e82b090b
TV		 2534 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2535 irq_mask);
80c39712 2536 if (r)
e82b090b 2537 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2538
2539 if (enable) {
2540 unsigned long flags;
2541 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2542 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2543 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2544 _omap_dispc_set_irqs();
2545 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2546 }
80c39712
TV		 2547}
2548
26d9dd0d 2549bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84 2550{
efa70b3b 2551 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
a2faee84
TV		 2552}
2553
26d9dd0d 2554void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2555{
dd88b7a6 2556 if (dss_mgr_is_lcd(channel))
26d9dd0d 2557 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2558 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2559 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2560 else
2561 BUG();
2562}
2563
80c39712
TV		 2564void dispc_lcd_enable_signal_polarity(bool act_high)
2565{
6ced40bf
AT		 2566 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2567 return;
2568
80c39712 2569 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2570}
2571
2572void dispc_lcd_enable_signal(bool enable)
2573{
6ced40bf
AT		 2574 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2575 return;
2576
80c39712 2577 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2578}
2579
2580void dispc_pck_free_enable(bool enable)
2581{
6ced40bf
AT		 2582 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2583 return;
2584
80c39712 2585 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2586}
2587
26d9dd0d 2588void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2589{
efa70b3b 2590 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2591}
2592
2593
d21f43bc 2594void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2595{
d21f43bc 2596 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2597}
2598
2599void dispc_set_loadmode(enum omap_dss_load_mode mode)
2600{
80c39712 2601 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2602}
2603
2604
c64dca40 2605static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2606{
8613b000 2607 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2608}
2609
c64dca40 2610static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2611 enum omap_dss_trans_key_type type,
2612 u32 trans_key)
2613{
efa70b3b 2614 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2615
8613b000 2616 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2617}
2618
c64dca40 2619static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2620{
efa70b3b 2621 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2622}
11354dd5 2623
c64dca40
TV		 2624static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2625 bool enable)
80c39712 2626{
11354dd5 2627 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2628 return;
2629
80c39712
TV		 2630 if (ch == OMAP_DSS_CHANNEL_LCD)
2631 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2632 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2633 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2634}
11354dd5 2635
c64dca40
TV		 2636void dispc_mgr_setup(enum omap_channel channel,
2637 struct omap_overlay_manager_info *info)
2638{
2639 dispc_mgr_set_default_color(channel, info->default_color);
2640 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2641 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2642 dispc_mgr_enable_alpha_fixed_zorder(channel,
2643 info->partial_alpha_enabled);
2644 if (dss_has_feature(FEAT_CPR)) {
2645 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2646 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2647 }
2648}
80c39712 2649
26d9dd0d 2650void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2651{
2652 int code;
2653
2654 switch (data_lines) {
2655 case 12:
2656 code = 0;
2657 break;
2658 case 16:
2659 code = 1;
2660 break;
2661 case 18:
2662 code = 2;
2663 break;
2664 case 24:
2665 code = 3;
2666 break;
2667 default:
2668 BUG();
2669 return;
2670 }
2671
efa70b3b 2672 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2673}
2674
569969d6 2675void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2676{
2677 u32 l;
569969d6 2678 int gpout0, gpout1;
80c39712
TV		 2679
2680 switch (mode) {
569969d6
AT		 2681 case DSS_IO_PAD_MODE_RESET:
2682 gpout0 = 0;
2683 gpout1 = 0;
80c39712 2684 break;
569969d6
AT		 2685 case DSS_IO_PAD_MODE_RFBI:
2686 gpout0 = 1;
80c39712
TV		 2687 gpout1 = 0;
2688 break;
569969d6
AT		 2689 case DSS_IO_PAD_MODE_BYPASS:
2690 gpout0 = 1;
80c39712
TV		 2691 gpout1 = 1;
2692 break;
80c39712
TV		 2693 default:
2694 BUG();
2695 return;
2696 }
2697
569969d6
AT		 2698 l = dispc_read_reg(DISPC_CONTROL);
2699 l = FLD_MOD(l, gpout0, 15, 15);
2700 l = FLD_MOD(l, gpout1, 16, 16);
2701 dispc_write_reg(DISPC_CONTROL, l);
2702}
2703
2704void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2705{
efa70b3b 2706 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2707}
2708
8f366162
AT		 2709static bool _dispc_mgr_size_ok(u16 width, u16 height)
2710{
2711 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2712 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2713}
2714
80c39712
TV		 2715static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2716 int vsw, int vfp, int vbp)
2717{
dcbe765b
CM		 2718 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2719 hfp < 1 || hfp > dispc.feat->hp_max ||
2720 hbp < 1 || hbp > dispc.feat->hp_max ||
2721 vsw < 1 || vsw > dispc.feat->sw_max ||
2722 vfp < 0 || vfp > dispc.feat->vp_max ||
2723 vbp < 0 || vbp > dispc.feat->vp_max)
2724 return false;
80c39712
TV		 2725 return true;
2726}
2727
8f366162 2728bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2729 const struct omap_video_timings *timings)
80c39712 2730{
8f366162
AT		 2731 bool timings_ok;
2732
2733 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2734
dd88b7a6 2735 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2736 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2737 timings->hfp, timings->hbp,
2738 timings->vsw, timings->vfp,
2739 timings->vbp);
2740
2741 return timings_ok;
80c39712
TV		 2742}
2743
26d9dd0d 2744static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2745 int hfp, int hbp, int vsw, int vfp, int vbp,
2746 enum omap_dss_signal_level vsync_level,
2747 enum omap_dss_signal_level hsync_level,
2748 enum omap_dss_signal_edge data_pclk_edge,
2749 enum omap_dss_signal_level de_level,
2750 enum omap_dss_signal_edge sync_pclk_edge)
2751
80c39712 2752{
655e2941
AT		 2753 u32 timing_h, timing_v, l;
2754 bool onoff, rf, ipc;
80c39712 2755
dcbe765b
CM		 2756 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2757 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2758 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2759 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2760 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2761 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2762
64ba4f74
SS		 2763 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2764 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2765
2766 switch (data_pclk_edge) {
2767 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2768 ipc = false;
2769 break;
2770 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2771 ipc = true;
2772 break;
2773 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2774 default:
2775 BUG();
2776 }
2777
2778 switch (sync_pclk_edge) {
2779 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2780 onoff = false;
2781 rf = false;
2782 break;
2783 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2784 onoff = true;
2785 rf = false;
2786 break;
2787 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2788 onoff = true;
2789 rf = true;
2790 break;
2791 default:
2792 BUG();
2793 };
2794
2795 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2796 l |= FLD_VAL(onoff, 17, 17);
2797 l |= FLD_VAL(rf, 16, 16);
2798 l |= FLD_VAL(de_level, 15, 15);
2799 l |= FLD_VAL(ipc, 14, 14);
2800 l |= FLD_VAL(hsync_level, 13, 13);
2801 l |= FLD_VAL(vsync_level, 12, 12);
2802 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2803}
2804
2805/* change name to mode? */
c51d921a 2806void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2807 struct omap_video_timings *timings)
80c39712
TV		 2808{
2809 unsigned xtot, ytot;
2810 unsigned long ht, vt;
2aefad49 2811 struct omap_video_timings t = *timings;
80c39712 2812
2aefad49 2813 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2814
2aefad49 2815 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2816 BUG();
c6eee968
TV		 2817 return;
2818 }
80c39712 2819
dd88b7a6 2820 if (dss_mgr_is_lcd(channel)) {
2aefad49 2821 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2822 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2823 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2824
2aefad49
AT		 2825 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2826 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2827
c51d921a
AT		 2828 ht = (timings->pixel_clock * 1000) / xtot;
2829 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2830
2831 DSSDBG("pck %u\n", timings->pixel_clock);
2832 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2833 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2834 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2835 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2836 t.de_level, t.sync_pclk_edge);
80c39712 2837
c51d921a 2838 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2839 } else {
23c8f88e 2840 if (t.interlace == true)
2aefad49 2841 t.y_res /= 2;
c51d921a 2842 }
8f366162 2843
2aefad49 2844 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 2845}
2846
26d9dd0d 2847static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2848 u16 pck_div)
80c39712
TV		 2849{
2850 BUG_ON(lck_div < 1);
9eaaf207 2851 BUG_ON(pck_div < 1);
80c39712 2852
ce7fa5eb 2853 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2854 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2855}
2856
26d9dd0d 2857static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2858 int *pck_div)
80c39712
TV		 2859{
2860 u32 l;
ce7fa5eb 2861 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2862 *lck_div = FLD_GET(l, 23, 16);
2863 *pck_div = FLD_GET(l, 7, 0);
2864}
2865
2866unsigned long dispc_fclk_rate(void)
2867{
a72b64b9 2868 struct platform_device *dsidev;
80c39712
TV		 2869 unsigned long r = 0;
2870
66534e8e 2871 switch (dss_get_dispc_clk_source()) {
89a35e51 2872 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2873 r = clk_get_rate(dispc.dss_clk);
66534e8e 2874 break;
89a35e51 2875 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2876 dsidev = dsi_get_dsidev_from_id(0);
2877 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2878 break;
5a8b572d
AT		 2879 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2880 dsidev = dsi_get_dsidev_from_id(1);
2881 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2882 break;
66534e8e
AT		 2883 default:
2884 BUG();
c6eee968 2885 return 0;
66534e8e
AT		 2886 }
2887
80c39712
TV		 2888 return r;
2889}
2890
26d9dd0d 2891unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2892{
a72b64b9 2893 struct platform_device *dsidev;
80c39712
TV		 2894 int lcd;
2895 unsigned long r;
2896 u32 l;
2897
ce7fa5eb 2898 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2899
2900 lcd = FLD_GET(l, 23, 16);
2901
ea75159e 2902 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2903 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2904 r = clk_get_rate(dispc.dss_clk);
ea75159e 2905 break;
89a35e51 2906 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2907 dsidev = dsi_get_dsidev_from_id(0);
2908 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2909 break;
5a8b572d
AT		 2910 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2911 dsidev = dsi_get_dsidev_from_id(1);
2912 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2913 break;
ea75159e
AT		 2914 default:
2915 BUG();
c6eee968 2916 return 0;
ea75159e 2917 }
80c39712
TV		 2918
2919 return r / lcd;
2920}
2921
26d9dd0d 2922unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2923{
80c39712 2924 unsigned long r;
80c39712 2925
dd88b7a6 2926 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 2927 int pcd;
2928 u32 l;
80c39712 2929
c3dc6a7a 2930 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2931
c3dc6a7a 2932 pcd = FLD_GET(l, 7, 0);
80c39712 2933
c3dc6a7a
AT		 2934 r = dispc_mgr_lclk_rate(channel);
2935
2936 return r / pcd;
2937 } else {
3fa03ba8 2938 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2939
3fa03ba8
AT		 2940 source = dss_get_hdmi_venc_clk_source();
2941
2942 switch (source) {
2943 case DSS_VENC_TV_CLK:
c3dc6a7a 2944 return venc_get_pixel_clock();
3fa03ba8 2945 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2946 return hdmi_get_pixel_clock();
2947 default:
2948 BUG();
c6eee968 2949 return 0;
c3dc6a7a
AT		 2950 }
2951 }
80c39712
TV		 2952}
2953
8b53d991
CM		 2954unsigned long dispc_core_clk_rate(void)
2955{
2956 int lcd;
2957 unsigned long fclk = dispc_fclk_rate();
2958
2959 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2960 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2961 else
2962 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2963
2964 return fclk / lcd;
2965}
2966
6f1891fc 2967static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 2968{
2969 int lcd, pcd;
6f1891fc
CM		 2970 enum omap_dss_clk_source lcd_clk_src;
2971
2972 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
2973
2974 lcd_clk_src = dss_get_lcd_clk_source(channel);
2975
2976 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
2977 dss_get_generic_clk_source_name(lcd_clk_src),
2978 dss_feat_get_clk_source_name(lcd_clk_src));
2979
2980 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
2981
2982 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2983 dispc_mgr_lclk_rate(channel), lcd);
2984 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2985 dispc_mgr_pclk_rate(channel), pcd);
2986}
2987
2988void dispc_dump_clocks(struct seq_file *s)
2989{
2990 int lcd;
0cf35df3 2991 u32 l;
89a35e51 2992 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 2993
4fbafaf3
TV		 2994 if (dispc_runtime_get())
2995 return;
80c39712 2996
80c39712
TV		 2997 seq_printf(s, "- DISPC -\n");
2998
067a57e4
AT		 2999 seq_printf(s, "dispc fclk source = %s (%s)\n",
3000 dss_get_generic_clk_source_name(dispc_clk_src),
3001 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3002
3003 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3004
0cf35df3
MR		 3005 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3006 seq_printf(s, "- DISPC-CORE-CLK -\n");
3007 l = dispc_read_reg(DISPC_DIVISOR);
3008 lcd = FLD_GET(l, 23, 16);
3009
3010 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3011 (dispc_fclk_rate()/lcd), lcd);
3012 }
2a205f34 3013
6f1891fc 3014 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3015
6f1891fc
CM		 3016 if (dss_has_feature(FEAT_MGR_LCD2))
3017 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3018 if (dss_has_feature(FEAT_MGR_LCD3))
3019 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3020
3021 dispc_runtime_put();
80c39712
TV		 3022}
3023
dfc0fd8d
TV		 3024#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3025void dispc_dump_irqs(struct seq_file *s)
3026{
3027 unsigned long flags;
3028 struct dispc_irq_stats stats;
3029
3030 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3031
3032 stats = dispc.irq_stats;
3033 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3034 dispc.irq_stats.last_reset = jiffies;
3035
3036 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3037
3038 seq_printf(s, "period %u ms\n",
3039 jiffies_to_msecs(jiffies - stats.last_reset));
3040
3041 seq_printf(s, "irqs %d\n", stats.irq_count);
3042#define PIS(x) \
3043 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3044
3045 PIS(FRAMEDONE);
3046 PIS(VSYNC);
3047 PIS(EVSYNC_EVEN);
3048 PIS(EVSYNC_ODD);
3049 PIS(ACBIAS_COUNT_STAT);
3050 PIS(PROG_LINE_NUM);
3051 PIS(GFX_FIFO_UNDERFLOW);
3052 PIS(GFX_END_WIN);
3053 PIS(PAL_GAMMA_MASK);
3054 PIS(OCP_ERR);
3055 PIS(VID1_FIFO_UNDERFLOW);
3056 PIS(VID1_END_WIN);
3057 PIS(VID2_FIFO_UNDERFLOW);
3058 PIS(VID2_END_WIN);
b8c095b4
AT		 3059 if (dss_feat_get_num_ovls() > 3) {
3060 PIS(VID3_FIFO_UNDERFLOW);
3061 PIS(VID3_END_WIN);
3062 }
dfc0fd8d
TV		 3063 PIS(SYNC_LOST);
3064 PIS(SYNC_LOST_DIGIT);
3065 PIS(WAKEUP);
2a205f34
SS		 3066 if (dss_has_feature(FEAT_MGR_LCD2)) {
3067 PIS(FRAMEDONE2);
3068 PIS(VSYNC2);
3069 PIS(ACBIAS_COUNT_STAT2);
3070 PIS(SYNC_LOST2);
3071 }
6f1891fc
CM		 3072 if (dss_has_feature(FEAT_MGR_LCD3)) {
3073 PIS(FRAMEDONE3);
3074 PIS(VSYNC3);
3075 PIS(ACBIAS_COUNT_STAT3);
3076 PIS(SYNC_LOST3);
3077 }
dfc0fd8d
TV		 3078#undef PIS
3079}
dfc0fd8d
TV		 3080#endif
3081
e40402cf 3082static void dispc_dump_regs(struct seq_file *s)
80c39712 3083{
4dd2da15
AT		 3084 int i, j;
3085 const char *mgr_names[] = {
3086 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3087 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3088 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3089 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3090 };
3091 const char *ovl_names[] = {
3092 [OMAP_DSS_GFX] = "GFX",
3093 [OMAP_DSS_VIDEO1] = "VID1",
3094 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3095 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3096 };
3097 const char **p_names;
3098
9b372c2d 3099#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3100
4fbafaf3
TV		 3101 if (dispc_runtime_get())
3102 return;
80c39712 3103
5010be80 3104 /* DISPC common registers */
80c39712
TV		 3105 DUMPREG(DISPC_REVISION);
3106 DUMPREG(DISPC_SYSCONFIG);
3107 DUMPREG(DISPC_SYSSTATUS);
3108 DUMPREG(DISPC_IRQSTATUS);
3109 DUMPREG(DISPC_IRQENABLE);
3110 DUMPREG(DISPC_CONTROL);
3111 DUMPREG(DISPC_CONFIG);
3112 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3113 DUMPREG(DISPC_LINE_STATUS);
3114 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3115 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3116 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3117 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3118 if (dss_has_feature(FEAT_MGR_LCD2)) {
3119 DUMPREG(DISPC_CONTROL2);
3120 DUMPREG(DISPC_CONFIG2);
5010be80 3121 }
6f1891fc
CM		 3122 if (dss_has_feature(FEAT_MGR_LCD3)) {
3123 DUMPREG(DISPC_CONTROL3);
3124 DUMPREG(DISPC_CONFIG3);
3125 }
5010be80
AT		 3126
3127#undef DUMPREG
3128
3129#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 3130#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3131 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 3132 dispc_read_reg(DISPC_REG(i, r)))
3133
4dd2da15 3134 p_names = mgr_names;
5010be80 3135
4dd2da15
AT		 3136 /* DISPC channel specific registers */
3137 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3138 DUMPREG(i, DISPC_DEFAULT_COLOR);
3139 DUMPREG(i, DISPC_TRANS_COLOR);
3140 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3141
4dd2da15
AT		 3142 if (i == OMAP_DSS_CHANNEL_DIGIT)
3143 continue;
5010be80 3144
4dd2da15
AT		 3145 DUMPREG(i, DISPC_DEFAULT_COLOR);
3146 DUMPREG(i, DISPC_TRANS_COLOR);
3147 DUMPREG(i, DISPC_TIMING_H);
3148 DUMPREG(i, DISPC_TIMING_V);
3149 DUMPREG(i, DISPC_POL_FREQ);
3150 DUMPREG(i, DISPC_DIVISORo);
3151 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3152
4dd2da15
AT		 3153 DUMPREG(i, DISPC_DATA_CYCLE1);
3154 DUMPREG(i, DISPC_DATA_CYCLE2);
3155 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3156
332e9d70 3157 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3158 DUMPREG(i, DISPC_CPR_COEF_R);
3159 DUMPREG(i, DISPC_CPR_COEF_G);
3160 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3161 }
2a205f34 3162 }
80c39712 3163
4dd2da15
AT		 3164 p_names = ovl_names;
3165
3166 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3167 DUMPREG(i, DISPC_OVL_BA0);
3168 DUMPREG(i, DISPC_OVL_BA1);
3169 DUMPREG(i, DISPC_OVL_POSITION);
3170 DUMPREG(i, DISPC_OVL_SIZE);
3171 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3172 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3173 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3174 DUMPREG(i, DISPC_OVL_ROW_INC);
3175 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3176 if (dss_has_feature(FEAT_PRELOAD))
3177 DUMPREG(i, DISPC_OVL_PRELOAD);
3178
3179 if (i == OMAP_DSS_GFX) {
3180 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3181 DUMPREG(i, DISPC_OVL_TABLE_BA);
3182 continue;
3183 }
3184
3185 DUMPREG(i, DISPC_OVL_FIR);
3186 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3187 DUMPREG(i, DISPC_OVL_ACCU0);
3188 DUMPREG(i, DISPC_OVL_ACCU1);
3189 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3190 DUMPREG(i, DISPC_OVL_BA0_UV);
3191 DUMPREG(i, DISPC_OVL_BA1_UV);
3192 DUMPREG(i, DISPC_OVL_FIR2);
3193 DUMPREG(i, DISPC_OVL_ACCU2_0);
3194 DUMPREG(i, DISPC_OVL_ACCU2_1);
3195 }
3196 if (dss_has_feature(FEAT_ATTR2))
3197 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3198 if (dss_has_feature(FEAT_PRELOAD))
3199 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3200 }
5010be80
AT		 3201
3202#undef DISPC_REG
3203#undef DUMPREG
3204
3205#define DISPC_REG(plane, name, i) name(plane, i)
3206#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3207 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3208 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3209 dispc_read_reg(DISPC_REG(plane, name, i)))
3210
4dd2da15 3211 /* Video pipeline coefficient registers */
332e9d70 3212
4dd2da15
AT		 3213 /* start from OMAP_DSS_VIDEO1 */
3214 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3215 for (j = 0; j < 8; j++)
3216 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3217
4dd2da15
AT		 3218 for (j = 0; j < 8; j++)
3219 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3220
4dd2da15
AT		 3221 for (j = 0; j < 5; j++)
3222 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3223
4dd2da15
AT		 3224 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3225 for (j = 0; j < 8; j++)
3226 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3227 }
3228
3229 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3230 for (j = 0; j < 8; j++)
3231 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3232
3233 for (j = 0; j < 8; j++)
3234 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3235
3236 for (j = 0; j < 8; j++)
3237 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3238 }
332e9d70 3239 }
80c39712 3240
4fbafaf3 3241 dispc_runtime_put();
5010be80
AT		 3242
3243#undef DISPC_REG
80c39712
TV		 3244#undef DUMPREG
3245}
3246
80c39712 3247/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3248void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3249 struct dispc_clock_info *cinfo)
3250{
9eaaf207 3251 u16 pcd_min, pcd_max;
80c39712
TV		 3252 unsigned long best_pck;
3253 u16 best_ld, cur_ld;
3254 u16 best_pd, cur_pd;
3255
9eaaf207
TV		 3256 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3257 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3258
80c39712
TV		 3259 best_pck = 0;
3260 best_ld = 0;
3261 best_pd = 0;
3262
3263 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3264 unsigned long lck = fck / cur_ld;
3265
9eaaf207 3266 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3267 unsigned long pck = lck / cur_pd;
3268 long old_delta = abs(best_pck - req_pck);
3269 long new_delta = abs(pck - req_pck);
3270
3271 if (best_pck == 0 || new_delta < old_delta) {
3272 best_pck = pck;
3273 best_ld = cur_ld;
3274 best_pd = cur_pd;
3275
3276 if (pck == req_pck)
3277 goto found;
3278 }
3279
3280 if (pck < req_pck)
3281 break;
3282 }
3283
3284 if (lck / pcd_min < req_pck)
3285 break;
3286 }
3287
3288found:
3289 cinfo->lck_div = best_ld;
3290 cinfo->pck_div = best_pd;
3291 cinfo->lck = fck / cinfo->lck_div;
3292 cinfo->pck = cinfo->lck / cinfo->pck_div;
3293}
3294
3295/* calculate clock rates using dividers in cinfo */
3296int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3297 struct dispc_clock_info *cinfo)
3298{
3299 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3300 return -EINVAL;
9eaaf207 3301 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3302 return -EINVAL;
3303
3304 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3305 cinfo->pck = cinfo->lck / cinfo->pck_div;
3306
3307 return 0;
3308}
3309
f0d08f89 3310void dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3311 struct dispc_clock_info *cinfo)
80c39712
TV		 3312{
3313 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3314 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3315
26d9dd0d 3316 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3317}
3318
26d9dd0d 3319int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3320 struct dispc_clock_info *cinfo)
80c39712
TV		 3321{
3322 unsigned long fck;
3323
3324 fck = dispc_fclk_rate();
3325
ce7fa5eb
MR		 3326 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3327 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3328
3329 cinfo->lck = fck / cinfo->lck_div;
3330 cinfo->pck = cinfo->lck / cinfo->pck_div;
3331
3332 return 0;
3333}
3334
3335/* dispc.irq_lock has to be locked by the caller */
3336static void _omap_dispc_set_irqs(void)
3337{
3338 u32 mask;
3339 u32 old_mask;
3340 int i;
3341 struct omap_dispc_isr_data *isr_data;
3342
3343 mask = dispc.irq_error_mask;
3344
3345 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3346 isr_data = &dispc.registered_isr[i];
3347
3348 if (isr_data->isr == NULL)
3349 continue;
3350
3351 mask |= isr_data->mask;
3352 }
3353
80c39712
TV		 3354 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3355 /* clear the irqstatus for newly enabled irqs */
3356 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3357
3358 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3359}
3360
3361int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3362{
3363 int i;
3364 int ret;
3365 unsigned long flags;
3366 struct omap_dispc_isr_data *isr_data;
3367
3368 if (isr == NULL)
3369 return -EINVAL;
3370
3371 spin_lock_irqsave(&dispc.irq_lock, flags);
3372
3373 /* check for duplicate entry */
3374 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3375 isr_data = &dispc.registered_isr[i];
3376 if (isr_data->isr == isr && isr_data->arg == arg &&
3377 isr_data->mask == mask) {
3378 ret = -EINVAL;
3379 goto err;
3380 }
3381 }
3382
3383 isr_data = NULL;
3384 ret = -EBUSY;
3385
3386 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3387 isr_data = &dispc.registered_isr[i];
3388
3389 if (isr_data->isr != NULL)
3390 continue;
3391
3392 isr_data->isr = isr;
3393 isr_data->arg = arg;
3394 isr_data->mask = mask;
3395 ret = 0;
3396
3397 break;
3398 }
3399
b9cb0984
TV		 3400 if (ret)
3401 goto err;
3402
80c39712
TV		 3403 _omap_dispc_set_irqs();
3404
3405 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3406
3407 return 0;
3408err:
3409 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3410
3411 return ret;
3412}
3413EXPORT_SYMBOL(omap_dispc_register_isr);
3414
3415int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3416{
3417 int i;
3418 unsigned long flags;
3419 int ret = -EINVAL;
3420 struct omap_dispc_isr_data *isr_data;
3421
3422 spin_lock_irqsave(&dispc.irq_lock, flags);
3423
3424 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3425 isr_data = &dispc.registered_isr[i];
3426 if (isr_data->isr != isr || isr_data->arg != arg ||
3427 isr_data->mask != mask)
3428 continue;
3429
3430 /* found the correct isr */
3431
3432 isr_data->isr = NULL;
3433 isr_data->arg = NULL;
3434 isr_data->mask = 0;
3435
3436 ret = 0;
3437 break;
3438 }
3439
3440 if (ret == 0)
3441 _omap_dispc_set_irqs();
3442
3443 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3444
3445 return ret;
3446}
3447EXPORT_SYMBOL(omap_dispc_unregister_isr);
3448
3449#ifdef DEBUG
3450static void print_irq_status(u32 status)
3451{
3452 if ((status & dispc.irq_error_mask) == 0)
3453 return;
3454
3455 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3456
3457#define PIS(x) \
3458 if (status & DISPC_IRQ_##x) \
3459 printk(#x " ");
3460 PIS(GFX_FIFO_UNDERFLOW);
3461 PIS(OCP_ERR);
3462 PIS(VID1_FIFO_UNDERFLOW);
3463 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3464 if (dss_feat_get_num_ovls() > 3)
3465 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3466 PIS(SYNC_LOST);
3467 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3468 if (dss_has_feature(FEAT_MGR_LCD2))
3469 PIS(SYNC_LOST2);
6f1891fc
CM		 3470 if (dss_has_feature(FEAT_MGR_LCD3))
3471 PIS(SYNC_LOST3);
80c39712
TV		 3472#undef PIS
3473
3474 printk("\n");
3475}
3476#endif
3477
3478/* Called from dss.c. Note that we don't touch clocks here,
3479 * but we presume they are on because we got an IRQ. However,
3480 * an irq handler may turn the clocks off, so we may not have
3481 * clock later in the function. */
affe360d 3482static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3483{
3484 int i;
affe360d 3485 u32 irqstatus, irqenable;
80c39712
TV		 3486 u32 handledirqs = 0;
3487 u32 unhandled_errors;
3488 struct omap_dispc_isr_data *isr_data;
3489 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3490
3491 spin_lock(&dispc.irq_lock);
3492
3493 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d
AT		 3494 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3495
3496 /* IRQ is not for us */
3497 if (!(irqstatus & irqenable)) {
3498 spin_unlock(&dispc.irq_lock);
3499 return IRQ_NONE;
3500 }
80c39712 3501
dfc0fd8d
TV		 3502#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3503 spin_lock(&dispc.irq_stats_lock);
3504 dispc.irq_stats.irq_count++;
3505 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3506 spin_unlock(&dispc.irq_stats_lock);
3507#endif
3508
80c39712
TV		 3509#ifdef DEBUG
3510 if (dss_debug)
3511 print_irq_status(irqstatus);
3512#endif
3513 /* Ack the interrupt. Do it here before clocks are possibly turned
3514 * off */
3515 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3516 /* flush posted write */
3517 dispc_read_reg(DISPC_IRQSTATUS);
3518
3519 /* make a copy and unlock, so that isrs can unregister
3520 * themselves */
3521 memcpy(registered_isr, dispc.registered_isr,
3522 sizeof(registered_isr));
3523
3524 spin_unlock(&dispc.irq_lock);
3525
3526 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3527 isr_data = &registered_isr[i];
3528
3529 if (!isr_data->isr)
3530 continue;
3531
3532 if (isr_data->mask & irqstatus) {
3533 isr_data->isr(isr_data->arg, irqstatus);
3534 handledirqs |= isr_data->mask;
3535 }
3536 }
3537
3538 spin_lock(&dispc.irq_lock);
3539
3540 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3541
3542 if (unhandled_errors) {
3543 dispc.error_irqs |= unhandled_errors;
3544
3545 dispc.irq_error_mask &= ~unhandled_errors;
3546 _omap_dispc_set_irqs();
3547
3548 schedule_work(&dispc.error_work);
3549 }
3550
3551 spin_unlock(&dispc.irq_lock);
affe360d
AT		 3552
3553 return IRQ_HANDLED;
80c39712
TV		 3554}
3555
3556static void dispc_error_worker(struct work_struct *work)
3557{
3558 int i;
3559 u32 errors;
3560 unsigned long flags;
fe3cc9d6
TV		 3561 static const unsigned fifo_underflow_bits[] = {
3562 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3563 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3564 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3565 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3566 };
3567
80c39712
TV		 3568 spin_lock_irqsave(&dispc.irq_lock, flags);
3569 errors = dispc.error_irqs;
3570 dispc.error_irqs = 0;
3571 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3572
13eae1f9
DZ		 3573 dispc_runtime_get();
3574
fe3cc9d6
TV		 3575 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3576 struct omap_overlay *ovl;
3577 unsigned bit;
80c39712 3578
fe3cc9d6
TV		 3579 ovl = omap_dss_get_overlay(i);
3580 bit = fifo_underflow_bits[i];
80c39712 3581
fe3cc9d6
TV		 3582 if (bit & errors) {
3583 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3584 ovl->name);
f0e5caab 3585 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3586 dispc_mgr_go(ovl->manager->id);
d7ad718d 3587 msleep(50);
80c39712
TV		 3588 }
3589 }
3590
fe3cc9d6
TV		 3591 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3592 struct omap_overlay_manager *mgr;
3593 unsigned bit;
80c39712 3594
fe3cc9d6 3595 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3596 bit = mgr_desc[i].sync_lost_irq;
80c39712 3597
fe3cc9d6 3598 if (bit & errors) {
794bc4ee 3599 struct omap_dss_device *dssdev = mgr->get_device(mgr);
fe3cc9d6 3600 bool enable;
80c39712 3601
fe3cc9d6
TV		 3602 DSSERR("SYNC_LOST on channel %s, restarting the output "
3603 "with video overlays disabled\n",
3604 mgr->name);
2a205f34 3605
fe3cc9d6
TV		 3606 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3607 dssdev->driver->disable(dssdev);
2a205f34 3608
2a205f34
SS		 3609 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3610 struct omap_overlay *ovl;
3611 ovl = omap_dss_get_overlay(i);
3612
fe3cc9d6
TV		 3613 if (ovl->id != OMAP_DSS_GFX &&
3614 ovl->manager == mgr)
f0e5caab 3615 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3616 }
3617
26d9dd0d 3618 dispc_mgr_go(mgr->id);
d7ad718d 3619 msleep(50);
fe3cc9d6 3620
2a205f34
SS		 3621 if (enable)
3622 dssdev->driver->enable(dssdev);
3623 }
3624 }
3625
80c39712
TV		 3626 if (errors & DISPC_IRQ_OCP_ERR) {
3627 DSSERR("OCP_ERR\n");
3628 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3629 struct omap_overlay_manager *mgr;
794bc4ee
AT		 3630 struct omap_dss_device *dssdev;
3631
80c39712 3632 mgr = omap_dss_get_overlay_manager(i);
794bc4ee
AT		 3633 dssdev = mgr->get_device(mgr);
3634
3635 if (dssdev && dssdev->driver)
3636 dssdev->driver->disable(dssdev);
80c39712
TV		 3637 }
3638 }
3639
3640 spin_lock_irqsave(&dispc.irq_lock, flags);
3641 dispc.irq_error_mask |= errors;
3642 _omap_dispc_set_irqs();
3643 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3644
3645 dispc_runtime_put();
80c39712
TV		 3646}
3647
3648int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3649{
3650 void dispc_irq_wait_handler(void *data, u32 mask)
3651 {
3652 complete((struct completion *)data);
3653 }
3654
3655 int r;
3656 DECLARE_COMPLETION_ONSTACK(completion);
3657
3658 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3659 irqmask);
3660
3661 if (r)
3662 return r;
3663
3664 timeout = wait_for_completion_timeout(&completion, timeout);
3665
3666 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3667
3668 if (timeout == 0)
3669 return -ETIMEDOUT;
3670
3671 if (timeout == -ERESTARTSYS)
3672 return -ERESTARTSYS;
3673
3674 return 0;
3675}
3676
3677int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3678 unsigned long timeout)
3679{
3680 void dispc_irq_wait_handler(void *data, u32 mask)
3681 {
3682 complete((struct completion *)data);
3683 }
3684
3685 int r;
3686 DECLARE_COMPLETION_ONSTACK(completion);
3687
3688 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3689 irqmask);
3690
3691 if (r)
3692 return r;
3693
3694 timeout = wait_for_completion_interruptible_timeout(&completion,
3695 timeout);
3696
3697 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3698
3699 if (timeout == 0)
3700 return -ETIMEDOUT;
3701
3702 if (timeout == -ERESTARTSYS)
3703 return -ERESTARTSYS;
3704
3705 return 0;
3706}
3707
80c39712
TV		 3708static void _omap_dispc_initialize_irq(void)
3709{
3710 unsigned long flags;
3711
3712 spin_lock_irqsave(&dispc.irq_lock, flags);
3713
3714 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3715
3716 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3717 if (dss_has_feature(FEAT_MGR_LCD2))
3718 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3719 if (dss_has_feature(FEAT_MGR_LCD3))
3720 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 3721 if (dss_feat_get_num_ovls() > 3)
3722 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3723
3724 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3725 * so clear it */
3726 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3727
3728 _omap_dispc_set_irqs();
3729
3730 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3731}
3732
3733void dispc_enable_sidle(void)
3734{
3735 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3736}
3737
3738void dispc_disable_sidle(void)
3739{
3740 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3741}
3742
3743static void _omap_dispc_initial_config(void)
3744{
3745 u32 l;
3746
0cf35df3
MR		 3747 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3748 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3749 l = dispc_read_reg(DISPC_DIVISOR);
3750 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3751 l = FLD_MOD(l, 1, 0, 0);
3752 l = FLD_MOD(l, 1, 23, 16);
3753 dispc_write_reg(DISPC_DIVISOR, l);
3754 }
3755
80c39712 3756 /* FUNCGATED */
6ced40bf
AT		 3757 if (dss_has_feature(FEAT_FUNCGATED))
3758 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3759
80c39712
TV		 3760 _dispc_setup_color_conv_coef();
3761
3762 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3763
42a6961c 3764 dispc_init_fifos();
5ed8cf5b
TV		 3765
3766 dispc_configure_burst_sizes();
54128701
AT		 3767
3768 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3769}
3770
dcbe765b
CM		 3771static const struct dispc_features omap24xx_dispc_feats __initconst = {
3772 .sw_start = 5,
3773 .fp_start = 15,
3774 .bp_start = 27,
3775 .sw_max = 64,
3776 .vp_max = 255,
3777 .hp_max = 256,
3778 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3779 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3780 .num_fifos = 3,
dcbe765b
CM		 3781};
3782
3783static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3784 .sw_start = 5,
3785 .fp_start = 15,
3786 .bp_start = 27,
3787 .sw_max = 64,
3788 .vp_max = 255,
3789 .hp_max = 256,
3790 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3791 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3792 .num_fifos = 3,
dcbe765b
CM		 3793};
3794
3795static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3796 .sw_start = 7,
3797 .fp_start = 19,
3798 .bp_start = 31,
3799 .sw_max = 256,
3800 .vp_max = 4095,
3801 .hp_max = 4096,
3802 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3803 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3804 .num_fifos = 3,
dcbe765b
CM		 3805};
3806
3807static const struct dispc_features omap44xx_dispc_feats __initconst = {
3808 .sw_start = 7,
3809 .fp_start = 19,
3810 .bp_start = 31,
3811 .sw_max = 256,
3812 .vp_max = 4095,
3813 .hp_max = 4096,
3814 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3815 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3816 .num_fifos = 5,
66a0f9e4 3817 .gfx_fifo_workaround = true,
dcbe765b
CM		 3818};
3819
3820static int __init dispc_init_features(struct device *dev)
3821{
3822 const struct dispc_features *src;
3823 struct dispc_features *dst;
3824
3825 dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3826 if (!dst) {
3827 dev_err(dev, "Failed to allocate DISPC Features\n");
3828 return -ENOMEM;
3829 }
3830
3831 if (cpu_is_omap24xx()) {
3832 src = &omap24xx_dispc_feats;
3833 } else if (cpu_is_omap34xx()) {
3834 if (omap_rev() < OMAP3430_REV_ES3_0)
3835 src = &omap34xx_rev1_0_dispc_feats;
3836 else
3837 src = &omap34xx_rev3_0_dispc_feats;
3838 } else if (cpu_is_omap44xx()) {
3839 src = &omap44xx_dispc_feats;
23362832
AT		 3840 } else if (soc_is_omap54xx()) {
3841 src = &omap44xx_dispc_feats;
dcbe765b
CM		 3842 } else {
3843 return -ENODEV;
3844 }
3845
3846 memcpy(dst, src, sizeof(*dst));
3847 dispc.feat = dst;
3848
3849 return 0;
3850}
3851
060b6d9c 3852/* DISPC HW IP initialisation */
6e7e8f06 3853static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3854{
3855 u32 rev;
affe360d 3856 int r = 0;
ea9da36a 3857 struct resource *dispc_mem;
4fbafaf3 3858 struct clk *clk;
ea9da36a 3859
060b6d9c
SG		 3860 dispc.pdev = pdev;
3861
dcbe765b
CM		 3862 r = dispc_init_features(&dispc.pdev->dev);
3863 if (r)
3864 return r;
3865
060b6d9c
SG		 3866 spin_lock_init(&dispc.irq_lock);
3867
3868#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3869 spin_lock_init(&dispc.irq_stats_lock);
3870 dispc.irq_stats.last_reset = jiffies;
3871#endif
3872
3873 INIT_WORK(&dispc.error_work, dispc_error_worker);
3874
ea9da36a
SG		 3875 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3876 if (!dispc_mem) {
3877 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3878 return -EINVAL;
ea9da36a 3879 }
cd3b3449 3880
6e2a14d2
JL		 3881 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3882 resource_size(dispc_mem));
060b6d9c
SG		 3883 if (!dispc.base) {
3884 DSSERR("can't ioremap DISPC\n");
cd3b3449 3885 return -ENOMEM;
affe360d 3886 }
cd3b3449 3887
affe360d
AT		 3888 dispc.irq = platform_get_irq(dispc.pdev, 0);
3889 if (dispc.irq < 0) {
3890 DSSERR("platform_get_irq failed\n");
cd3b3449 3891 return -ENODEV;
affe360d
AT		 3892 }
3893
6e2a14d2
JL		 3894 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3895 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d
AT		 3896 if (r < 0) {
3897 DSSERR("request_irq failed\n");
cd3b3449
TV		 3898 return r;
3899 }
3900
3901 clk = clk_get(&pdev->dev, "fck");
3902 if (IS_ERR(clk)) {
3903 DSSERR("can't get fck\n");
3904 r = PTR_ERR(clk);
3905 return r;
060b6d9c
SG		 3906 }
3907
cd3b3449
TV		 3908 dispc.dss_clk = clk;
3909
4fbafaf3
TV		 3910 pm_runtime_enable(&pdev->dev);
3911
3912 r = dispc_runtime_get();
3913 if (r)
3914 goto err_runtime_get;
060b6d9c
SG		 3915
3916 _omap_dispc_initial_config();
3917
3918 _omap_dispc_initialize_irq();
3919
060b6d9c 3920 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3921 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3922 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3923
4fbafaf3 3924 dispc_runtime_put();
060b6d9c 3925
e40402cf
TV		 3926 dss_debugfs_create_file("dispc", dispc_dump_regs);
3927
3928#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3929 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3930#endif
060b6d9c 3931 return 0;
4fbafaf3
TV		 3932
3933err_runtime_get:
3934 pm_runtime_disable(&pdev->dev);
4fbafaf3 3935 clk_put(dispc.dss_clk);
affe360d 3936 return r;
060b6d9c
SG		 3937}
3938
6e7e8f06 3939static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3940{
4fbafaf3
TV		 3941 pm_runtime_disable(&pdev->dev);
3942
3943 clk_put(dispc.dss_clk);
3944
060b6d9c
SG		 3945 return 0;
3946}
3947
4fbafaf3
TV		 3948static int dispc_runtime_suspend(struct device *dev)
3949{
3950 dispc_save_context();
4fbafaf3
TV		 3951
3952 return 0;
3953}
3954
3955static int dispc_runtime_resume(struct device *dev)
3956{
49ea86f3 3957 dispc_restore_context();
4fbafaf3
TV		 3958
3959 return 0;
3960}
3961
3962static const struct dev_pm_ops dispc_pm_ops = {
3963 .runtime_suspend = dispc_runtime_suspend,
3964 .runtime_resume = dispc_runtime_resume,
3965};
3966
060b6d9c 3967static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3968 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3969 .driver = {
3970 .name = "omapdss_dispc",
3971 .owner = THIS_MODULE,
4fbafaf3 3972 .pm = &dispc_pm_ops,
060b6d9c
SG		 3973 },
3974};
3975
6e7e8f06 3976int __init dispc_init_platform_driver(void)
060b6d9c 3977{
11436e1d 3978 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3979}
3980
6e7e8f06 3981void __exit dispc_uninit_platform_driver(void)
060b6d9c 3982{
04c742c3 3983 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3984}
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