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OMAP2,3: DSS2: replace printk with dev_dbg in init
[mirror_ubuntu-bionic-kernel.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
80c39712
TV		 35
36#include <plat/sram.h>
37#include <plat/clock.h>
38
39#include <plat/display.h>
40
41#include "dss.h"
a0acb557 42#include "dss_features.h"
80c39712
TV		 43
44/* DISPC */
45#define DISPC_BASE 0x48050400
46
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712
TV		 48
49struct dispc_reg { u16 idx; };
50
51#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
52
8613b000
SS		 53/*
54 * DISPC common registers and
55 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
56 * DIGIT, and ch = 2 for LCD2
57 */
80c39712
TV		 58#define DISPC_REVISION DISPC_REG(0x0000)
59#define DISPC_SYSCONFIG DISPC_REG(0x0010)
60#define DISPC_SYSSTATUS DISPC_REG(0x0014)
61#define DISPC_IRQSTATUS DISPC_REG(0x0018)
62#define DISPC_IRQENABLE DISPC_REG(0x001C)
63#define DISPC_CONTROL DISPC_REG(0x0040)
8613b000 64#define DISPC_CONTROL2 DISPC_REG(0x0238)
80c39712 65#define DISPC_CONFIG DISPC_REG(0x0044)
8613b000 66#define DISPC_CONFIG2 DISPC_REG(0x0620)
80c39712 67#define DISPC_CAPABLE DISPC_REG(0x0048)
8613b000
SS		 68#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
69 (ch == 1 ? 0x0050 : 0x03AC))
70#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
71 (ch == 1 ? 0x0058 : 0x03B0))
80c39712
TV		 72#define DISPC_LINE_STATUS DISPC_REG(0x005C)
73#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
8613b000
SS		 74#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
75#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
76#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
77#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
80c39712
TV		 78#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
79#define DISPC_SIZE_DIG DISPC_REG(0x0078)
8613b000 80#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
80c39712
TV		 81
82/* DISPC GFX plane */
83#define DISPC_GFX_BA0 DISPC_REG(0x0080)
84#define DISPC_GFX_BA1 DISPC_REG(0x0084)
85#define DISPC_GFX_POSITION DISPC_REG(0x0088)
86#define DISPC_GFX_SIZE DISPC_REG(0x008C)
87#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
88#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
89#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
90#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
91#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
92#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
93#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
94
8613b000
SS		 95#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
96#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
97#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
98#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
99#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
100#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
80c39712
TV		 101
102#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
103
104/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
105#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
106
107#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
108#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
109#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
110#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
111#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
112#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
113#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
114#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
115#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
116#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
117#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
118#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
119#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
120
121/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
123/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
124#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
125/* coef index i = {0, 1, 2, 3, 4} */
126#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
127/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
128#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
129
130#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
131
132
133#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
134 DISPC_IRQ_OCP_ERR | \
135 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
136 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
137 DISPC_IRQ_SYNC_LOST | \
138 DISPC_IRQ_SYNC_LOST_DIGIT)
139
140#define DISPC_MAX_NR_ISRS 8
141
142struct omap_dispc_isr_data {
143 omap_dispc_isr_t isr;
144 void *arg;
145 u32 mask;
146};
147
66be8f6c
GI		 148struct dispc_h_coef {
149 s8 hc4;
150 s8 hc3;
151 u8 hc2;
152 s8 hc1;
153 s8 hc0;
154};
155
156struct dispc_v_coef {
157 s8 vc22;
158 s8 vc2;
159 u8 vc1;
160 s8 vc0;
161 s8 vc00;
162};
163
80c39712
TV		 164#define REG_GET(idx, start, end) \
165 FLD_GET(dispc_read_reg(idx), start, end)
166
167#define REG_FLD_MOD(idx, val, start, end) \
168 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
169
170static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
171 DISPC_VID_ATTRIBUTES(0),
172 DISPC_VID_ATTRIBUTES(1) };
173
dfc0fd8d
TV		 174struct dispc_irq_stats {
175 unsigned long last_reset;
176 unsigned irq_count;
177 unsigned irqs[32];
178};
179
80c39712 180static struct {
060b6d9c 181 struct platform_device *pdev;
80c39712
TV		 182 void __iomem *base;
183
184 u32 fifo_size[3];
185
186 spinlock_t irq_lock;
187 u32 irq_error_mask;
188 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
189 u32 error_irqs;
190 struct work_struct error_work;
191
192 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 193
194#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
195 spinlock_t irq_stats_lock;
196 struct dispc_irq_stats irq_stats;
197#endif
80c39712
TV		 198} dispc;
199
200static void _omap_dispc_set_irqs(void);
201
202static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
203{
204 __raw_writel(val, dispc.base + idx.idx);
205}
206
207static inline u32 dispc_read_reg(const struct dispc_reg idx)
208{
209 return __raw_readl(dispc.base + idx.idx);
210}
211
212#define SR(reg) \
213 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
214#define RR(reg) \
215 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
216
217void dispc_save_context(void)
218{
219 if (cpu_is_omap24xx())
220 return;
221
222 SR(SYSCONFIG);
223 SR(IRQENABLE);
224 SR(CONTROL);
225 SR(CONFIG);
8613b000
SS		 226 SR(DEFAULT_COLOR(0));
227 SR(DEFAULT_COLOR(1));
228 SR(TRANS_COLOR(0));
229 SR(TRANS_COLOR(1));
80c39712 230 SR(LINE_NUMBER);
8613b000
SS		 231 SR(TIMING_H(0));
232 SR(TIMING_V(0));
233 SR(POL_FREQ(0));
234 SR(DIVISOR(0));
80c39712
TV		 235 SR(GLOBAL_ALPHA);
236 SR(SIZE_DIG);
8613b000 237 SR(SIZE_LCD(0));
2a205f34
SS		 238 if (dss_has_feature(FEAT_MGR_LCD2)) {
239 SR(CONTROL2);
240 SR(DEFAULT_COLOR(2));
241 SR(TRANS_COLOR(2));
242 SR(SIZE_LCD(2));
243 SR(TIMING_H(2));
244 SR(TIMING_V(2));
245 SR(POL_FREQ(2));
246 SR(DIVISOR(2));
247 SR(CONFIG2);
248 }
80c39712
TV		 249
250 SR(GFX_BA0);
251 SR(GFX_BA1);
252 SR(GFX_POSITION);
253 SR(GFX_SIZE);
254 SR(GFX_ATTRIBUTES);
255 SR(GFX_FIFO_THRESHOLD);
256 SR(GFX_ROW_INC);
257 SR(GFX_PIXEL_INC);
258 SR(GFX_WINDOW_SKIP);
259 SR(GFX_TABLE_BA);
260
8613b000
SS		 261 SR(DATA_CYCLE1(0));
262 SR(DATA_CYCLE2(0));
263 SR(DATA_CYCLE3(0));
80c39712 264
8613b000
SS		 265 SR(CPR_COEF_R(0));
266 SR(CPR_COEF_G(0));
267 SR(CPR_COEF_B(0));
2a205f34
SS		 268 if (dss_has_feature(FEAT_MGR_LCD2)) {
269 SR(CPR_COEF_B(2));
270 SR(CPR_COEF_G(2));
271 SR(CPR_COEF_R(2));
272
273 SR(DATA_CYCLE1(2));
274 SR(DATA_CYCLE2(2));
275 SR(DATA_CYCLE3(2));
276 }
80c39712
TV		 277
278 SR(GFX_PRELOAD);
279
280 /* VID1 */
281 SR(VID_BA0(0));
282 SR(VID_BA1(0));
283 SR(VID_POSITION(0));
284 SR(VID_SIZE(0));
285 SR(VID_ATTRIBUTES(0));
286 SR(VID_FIFO_THRESHOLD(0));
287 SR(VID_ROW_INC(0));
288 SR(VID_PIXEL_INC(0));
289 SR(VID_FIR(0));
290 SR(VID_PICTURE_SIZE(0));
291 SR(VID_ACCU0(0));
292 SR(VID_ACCU1(0));
293
294 SR(VID_FIR_COEF_H(0, 0));
295 SR(VID_FIR_COEF_H(0, 1));
296 SR(VID_FIR_COEF_H(0, 2));
297 SR(VID_FIR_COEF_H(0, 3));
298 SR(VID_FIR_COEF_H(0, 4));
299 SR(VID_FIR_COEF_H(0, 5));
300 SR(VID_FIR_COEF_H(0, 6));
301 SR(VID_FIR_COEF_H(0, 7));
302
303 SR(VID_FIR_COEF_HV(0, 0));
304 SR(VID_FIR_COEF_HV(0, 1));
305 SR(VID_FIR_COEF_HV(0, 2));
306 SR(VID_FIR_COEF_HV(0, 3));
307 SR(VID_FIR_COEF_HV(0, 4));
308 SR(VID_FIR_COEF_HV(0, 5));
309 SR(VID_FIR_COEF_HV(0, 6));
310 SR(VID_FIR_COEF_HV(0, 7));
311
312 SR(VID_CONV_COEF(0, 0));
313 SR(VID_CONV_COEF(0, 1));
314 SR(VID_CONV_COEF(0, 2));
315 SR(VID_CONV_COEF(0, 3));
316 SR(VID_CONV_COEF(0, 4));
317
318 SR(VID_FIR_COEF_V(0, 0));
319 SR(VID_FIR_COEF_V(0, 1));
320 SR(VID_FIR_COEF_V(0, 2));
321 SR(VID_FIR_COEF_V(0, 3));
322 SR(VID_FIR_COEF_V(0, 4));
323 SR(VID_FIR_COEF_V(0, 5));
324 SR(VID_FIR_COEF_V(0, 6));
325 SR(VID_FIR_COEF_V(0, 7));
326
327 SR(VID_PRELOAD(0));
328
329 /* VID2 */
330 SR(VID_BA0(1));
331 SR(VID_BA1(1));
332 SR(VID_POSITION(1));
333 SR(VID_SIZE(1));
334 SR(VID_ATTRIBUTES(1));
335 SR(VID_FIFO_THRESHOLD(1));
336 SR(VID_ROW_INC(1));
337 SR(VID_PIXEL_INC(1));
338 SR(VID_FIR(1));
339 SR(VID_PICTURE_SIZE(1));
340 SR(VID_ACCU0(1));
341 SR(VID_ACCU1(1));
342
343 SR(VID_FIR_COEF_H(1, 0));
344 SR(VID_FIR_COEF_H(1, 1));
345 SR(VID_FIR_COEF_H(1, 2));
346 SR(VID_FIR_COEF_H(1, 3));
347 SR(VID_FIR_COEF_H(1, 4));
348 SR(VID_FIR_COEF_H(1, 5));
349 SR(VID_FIR_COEF_H(1, 6));
350 SR(VID_FIR_COEF_H(1, 7));
351
352 SR(VID_FIR_COEF_HV(1, 0));
353 SR(VID_FIR_COEF_HV(1, 1));
354 SR(VID_FIR_COEF_HV(1, 2));
355 SR(VID_FIR_COEF_HV(1, 3));
356 SR(VID_FIR_COEF_HV(1, 4));
357 SR(VID_FIR_COEF_HV(1, 5));
358 SR(VID_FIR_COEF_HV(1, 6));
359 SR(VID_FIR_COEF_HV(1, 7));
360
361 SR(VID_CONV_COEF(1, 0));
362 SR(VID_CONV_COEF(1, 1));
363 SR(VID_CONV_COEF(1, 2));
364 SR(VID_CONV_COEF(1, 3));
365 SR(VID_CONV_COEF(1, 4));
366
367 SR(VID_FIR_COEF_V(1, 0));
368 SR(VID_FIR_COEF_V(1, 1));
369 SR(VID_FIR_COEF_V(1, 2));
370 SR(VID_FIR_COEF_V(1, 3));
371 SR(VID_FIR_COEF_V(1, 4));
372 SR(VID_FIR_COEF_V(1, 5));
373 SR(VID_FIR_COEF_V(1, 6));
374 SR(VID_FIR_COEF_V(1, 7));
375
376 SR(VID_PRELOAD(1));
377}
378
379void dispc_restore_context(void)
380{
381 RR(SYSCONFIG);
75c7d59d 382 /*RR(IRQENABLE);*/
80c39712
TV		 383 /*RR(CONTROL);*/
384 RR(CONFIG);
8613b000
SS		 385 RR(DEFAULT_COLOR(0));
386 RR(DEFAULT_COLOR(1));
387 RR(TRANS_COLOR(0));
388 RR(TRANS_COLOR(1));
80c39712 389 RR(LINE_NUMBER);
8613b000
SS		 390 RR(TIMING_H(0));
391 RR(TIMING_V(0));
392 RR(POL_FREQ(0));
393 RR(DIVISOR(0));
80c39712
TV		 394 RR(GLOBAL_ALPHA);
395 RR(SIZE_DIG);
8613b000 396 RR(SIZE_LCD(0));
2a205f34
SS		 397 if (dss_has_feature(FEAT_MGR_LCD2)) {
398 RR(DEFAULT_COLOR(2));
399 RR(TRANS_COLOR(2));
400 RR(SIZE_LCD(2));
401 RR(TIMING_H(2));
402 RR(TIMING_V(2));
403 RR(POL_FREQ(2));
404 RR(DIVISOR(2));
405 RR(CONFIG2);
406 }
80c39712
TV		 407
408 RR(GFX_BA0);
409 RR(GFX_BA1);
410 RR(GFX_POSITION);
411 RR(GFX_SIZE);
412 RR(GFX_ATTRIBUTES);
413 RR(GFX_FIFO_THRESHOLD);
414 RR(GFX_ROW_INC);
415 RR(GFX_PIXEL_INC);
416 RR(GFX_WINDOW_SKIP);
417 RR(GFX_TABLE_BA);
418
8613b000
SS		 419 RR(DATA_CYCLE1(0));
420 RR(DATA_CYCLE2(0));
421 RR(DATA_CYCLE3(0));
80c39712 422
8613b000
SS		 423 RR(CPR_COEF_R(0));
424 RR(CPR_COEF_G(0));
425 RR(CPR_COEF_B(0));
2a205f34
SS		 426 if (dss_has_feature(FEAT_MGR_LCD2)) {
427 RR(DATA_CYCLE1(2));
428 RR(DATA_CYCLE2(2));
429 RR(DATA_CYCLE3(2));
430
431 RR(CPR_COEF_B(2));
432 RR(CPR_COEF_G(2));
433 RR(CPR_COEF_R(2));
434 }
80c39712
TV		 435
436 RR(GFX_PRELOAD);
437
438 /* VID1 */
439 RR(VID_BA0(0));
440 RR(VID_BA1(0));
441 RR(VID_POSITION(0));
442 RR(VID_SIZE(0));
443 RR(VID_ATTRIBUTES(0));
444 RR(VID_FIFO_THRESHOLD(0));
445 RR(VID_ROW_INC(0));
446 RR(VID_PIXEL_INC(0));
447 RR(VID_FIR(0));
448 RR(VID_PICTURE_SIZE(0));
449 RR(VID_ACCU0(0));
450 RR(VID_ACCU1(0));
451
452 RR(VID_FIR_COEF_H(0, 0));
453 RR(VID_FIR_COEF_H(0, 1));
454 RR(VID_FIR_COEF_H(0, 2));
455 RR(VID_FIR_COEF_H(0, 3));
456 RR(VID_FIR_COEF_H(0, 4));
457 RR(VID_FIR_COEF_H(0, 5));
458 RR(VID_FIR_COEF_H(0, 6));
459 RR(VID_FIR_COEF_H(0, 7));
460
461 RR(VID_FIR_COEF_HV(0, 0));
462 RR(VID_FIR_COEF_HV(0, 1));
463 RR(VID_FIR_COEF_HV(0, 2));
464 RR(VID_FIR_COEF_HV(0, 3));
465 RR(VID_FIR_COEF_HV(0, 4));
466 RR(VID_FIR_COEF_HV(0, 5));
467 RR(VID_FIR_COEF_HV(0, 6));
468 RR(VID_FIR_COEF_HV(0, 7));
469
470 RR(VID_CONV_COEF(0, 0));
471 RR(VID_CONV_COEF(0, 1));
472 RR(VID_CONV_COEF(0, 2));
473 RR(VID_CONV_COEF(0, 3));
474 RR(VID_CONV_COEF(0, 4));
475
476 RR(VID_FIR_COEF_V(0, 0));
477 RR(VID_FIR_COEF_V(0, 1));
478 RR(VID_FIR_COEF_V(0, 2));
479 RR(VID_FIR_COEF_V(0, 3));
480 RR(VID_FIR_COEF_V(0, 4));
481 RR(VID_FIR_COEF_V(0, 5));
482 RR(VID_FIR_COEF_V(0, 6));
483 RR(VID_FIR_COEF_V(0, 7));
484
485 RR(VID_PRELOAD(0));
486
487 /* VID2 */
488 RR(VID_BA0(1));
489 RR(VID_BA1(1));
490 RR(VID_POSITION(1));
491 RR(VID_SIZE(1));
492 RR(VID_ATTRIBUTES(1));
493 RR(VID_FIFO_THRESHOLD(1));
494 RR(VID_ROW_INC(1));
495 RR(VID_PIXEL_INC(1));
496 RR(VID_FIR(1));
497 RR(VID_PICTURE_SIZE(1));
498 RR(VID_ACCU0(1));
499 RR(VID_ACCU1(1));
500
501 RR(VID_FIR_COEF_H(1, 0));
502 RR(VID_FIR_COEF_H(1, 1));
503 RR(VID_FIR_COEF_H(1, 2));
504 RR(VID_FIR_COEF_H(1, 3));
505 RR(VID_FIR_COEF_H(1, 4));
506 RR(VID_FIR_COEF_H(1, 5));
507 RR(VID_FIR_COEF_H(1, 6));
508 RR(VID_FIR_COEF_H(1, 7));
509
510 RR(VID_FIR_COEF_HV(1, 0));
511 RR(VID_FIR_COEF_HV(1, 1));
512 RR(VID_FIR_COEF_HV(1, 2));
513 RR(VID_FIR_COEF_HV(1, 3));
514 RR(VID_FIR_COEF_HV(1, 4));
515 RR(VID_FIR_COEF_HV(1, 5));
516 RR(VID_FIR_COEF_HV(1, 6));
517 RR(VID_FIR_COEF_HV(1, 7));
518
519 RR(VID_CONV_COEF(1, 0));
520 RR(VID_CONV_COEF(1, 1));
521 RR(VID_CONV_COEF(1, 2));
522 RR(VID_CONV_COEF(1, 3));
523 RR(VID_CONV_COEF(1, 4));
524
525 RR(VID_FIR_COEF_V(1, 0));
526 RR(VID_FIR_COEF_V(1, 1));
527 RR(VID_FIR_COEF_V(1, 2));
528 RR(VID_FIR_COEF_V(1, 3));
529 RR(VID_FIR_COEF_V(1, 4));
530 RR(VID_FIR_COEF_V(1, 5));
531 RR(VID_FIR_COEF_V(1, 6));
532 RR(VID_FIR_COEF_V(1, 7));
533
534 RR(VID_PRELOAD(1));
535
536 /* enable last, because LCD & DIGIT enable are here */
537 RR(CONTROL);
2a205f34
SS		 538 if (dss_has_feature(FEAT_MGR_LCD2))
539 RR(CONTROL2);
75c7d59d
VS		 540 /* clear spurious SYNC_LOST_DIGIT interrupts */
541 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
542
543 /*
544 * enable last so IRQs won't trigger before
545 * the context is fully restored
546 */
547 RR(IRQENABLE);
80c39712
TV		 548}
549
550#undef SR
551#undef RR
552
553static inline void enable_clocks(bool enable)
554{
555 if (enable)
556 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
557 else
558 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
559}
560
561bool dispc_go_busy(enum omap_channel channel)
562{
563 int bit;
564
2a205f34
SS		 565 if (channel == OMAP_DSS_CHANNEL_LCD ||
566 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 567 bit = 5; /* GOLCD */
568 else
569 bit = 6; /* GODIGIT */
570
2a205f34
SS		 571 if (channel == OMAP_DSS_CHANNEL_LCD2)
572 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
573 else
574 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 575}
576
577void dispc_go(enum omap_channel channel)
578{
579 int bit;
2a205f34 580 bool enable_bit, go_bit;
80c39712
TV		 581
582 enable_clocks(1);
583
2a205f34
SS		 584 if (channel == OMAP_DSS_CHANNEL_LCD ||
585 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 586 bit = 0; /* LCDENABLE */
587 else
588 bit = 1; /* DIGITALENABLE */
589
590 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 591 if (channel == OMAP_DSS_CHANNEL_LCD2)
592 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
593 else
594 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
595
596 if (!enable_bit)
80c39712
TV		 597 goto end;
598
2a205f34
SS		 599 if (channel == OMAP_DSS_CHANNEL_LCD ||
600 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 601 bit = 5; /* GOLCD */
602 else
603 bit = 6; /* GODIGIT */
604
2a205f34
SS		 605 if (channel == OMAP_DSS_CHANNEL_LCD2)
606 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
607 else
608 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
609
610 if (go_bit) {
80c39712
TV		 611 DSSERR("GO bit not down for channel %d\n", channel);
612 goto end;
613 }
614
2a205f34
SS		 615 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
616 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 617
2a205f34
SS		 618 if (channel == OMAP_DSS_CHANNEL_LCD2)
619 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
620 else
621 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 622end:
623 enable_clocks(0);
624}
625
626static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
627{
628 BUG_ON(plane == OMAP_DSS_GFX);
629
630 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
631}
632
633static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
634{
635 BUG_ON(plane == OMAP_DSS_GFX);
636
637 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
638}
639
640static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
641{
642 BUG_ON(plane == OMAP_DSS_GFX);
643
644 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
645}
646
647static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
648 int vscaleup, int five_taps)
649{
650 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 651 static const struct dispc_h_coef coef_hup[8] = {
652 { 0, 0, 128, 0, 0 },
653 { -1, 13, 124, -8, 0 },
654 { -2, 30, 112, -11, -1 },
655 { -5, 51, 95, -11, -2 },
656 { 0, -9, 73, 73, -9 },
657 { -2, -11, 95, 51, -5 },
658 { -1, -11, 112, 30, -2 },
659 { 0, -8, 124, 13, -1 },
80c39712
TV		 660 };
661
66be8f6c
GI		 662 /* Coefficients for vertical up-sampling */
663 static const struct dispc_v_coef coef_vup_3tap[8] = {
664 { 0, 0, 128, 0, 0 },
665 { 0, 3, 123, 2, 0 },
666 { 0, 12, 111, 5, 0 },
667 { 0, 32, 89, 7, 0 },
668 { 0, 0, 64, 64, 0 },
669 { 0, 7, 89, 32, 0 },
670 { 0, 5, 111, 12, 0 },
671 { 0, 2, 123, 3, 0 },
80c39712
TV		 672 };
673
66be8f6c
GI		 674 static const struct dispc_v_coef coef_vup_5tap[8] = {
675 { 0, 0, 128, 0, 0 },
676 { -1, 13, 124, -8, 0 },
677 { -2, 30, 112, -11, -1 },
678 { -5, 51, 95, -11, -2 },
679 { 0, -9, 73, 73, -9 },
680 { -2, -11, 95, 51, -5 },
681 { -1, -11, 112, 30, -2 },
682 { 0, -8, 124, 13, -1 },
80c39712
TV		 683 };
684
66be8f6c
GI		 685 /* Coefficients for horizontal down-sampling */
686 static const struct dispc_h_coef coef_hdown[8] = {
687 { 0, 36, 56, 36, 0 },
688 { 4, 40, 55, 31, -2 },
689 { 8, 44, 54, 27, -5 },
690 { 12, 48, 53, 22, -7 },
691 { -9, 17, 52, 51, 17 },
692 { -7, 22, 53, 48, 12 },
693 { -5, 27, 54, 44, 8 },
694 { -2, 31, 55, 40, 4 },
80c39712
TV		 695 };
696
66be8f6c
GI		 697 /* Coefficients for vertical down-sampling */
698 static const struct dispc_v_coef coef_vdown_3tap[8] = {
699 { 0, 36, 56, 36, 0 },
700 { 0, 40, 57, 31, 0 },
701 { 0, 45, 56, 27, 0 },
702 { 0, 50, 55, 23, 0 },
703 { 0, 18, 55, 55, 0 },
704 { 0, 23, 55, 50, 0 },
705 { 0, 27, 56, 45, 0 },
706 { 0, 31, 57, 40, 0 },
80c39712
TV		 707 };
708
66be8f6c
GI		 709 static const struct dispc_v_coef coef_vdown_5tap[8] = {
710 { 0, 36, 56, 36, 0 },
711 { 4, 40, 55, 31, -2 },
712 { 8, 44, 54, 27, -5 },
713 { 12, 48, 53, 22, -7 },
714 { -9, 17, 52, 51, 17 },
715 { -7, 22, 53, 48, 12 },
716 { -5, 27, 54, 44, 8 },
717 { -2, 31, 55, 40, 4 },
80c39712
TV		 718 };
719
66be8f6c
GI		 720 const struct dispc_h_coef *h_coef;
721 const struct dispc_v_coef *v_coef;
80c39712
TV		 722 int i;
723
724 if (hscaleup)
725 h_coef = coef_hup;
726 else
727 h_coef = coef_hdown;
728
66be8f6c
GI		 729 if (vscaleup)
730 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
731 else
732 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 733
734 for (i = 0; i < 8; i++) {
735 u32 h, hv;
736
66be8f6c
GI		 737 h = FLD_VAL(h_coef[i].hc0, 7, 0)
738 | FLD_VAL(h_coef[i].hc1, 15, 8)
739 | FLD_VAL(h_coef[i].hc2, 23, 16)
740 | FLD_VAL(h_coef[i].hc3, 31, 24);
741 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
742 | FLD_VAL(v_coef[i].vc0, 15, 8)
743 | FLD_VAL(v_coef[i].vc1, 23, 16)
744 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712
TV		 745
746 _dispc_write_firh_reg(plane, i, h);
747 _dispc_write_firhv_reg(plane, i, hv);
748 }
749
66be8f6c
GI		 750 if (five_taps) {
751 for (i = 0; i < 8; i++) {
752 u32 v;
753 v = FLD_VAL(v_coef[i].vc00, 7, 0)
754 | FLD_VAL(v_coef[i].vc22, 15, 8);
755 _dispc_write_firv_reg(plane, i, v);
756 }
80c39712
TV		 757 }
758}
759
760static void _dispc_setup_color_conv_coef(void)
761{
762 const struct color_conv_coef {
763 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
764 int full_range;
765 } ctbl_bt601_5 = {
766 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
767 };
768
769 const struct color_conv_coef *ct;
770
771#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
772
773 ct = &ctbl_bt601_5;
774
775 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
776 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
777 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
778 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
779 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
780
781 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
782 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
783 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
784 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
785 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
786
787#undef CVAL
788
789 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
790 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
791}
792
793
794static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
795{
796 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
797 DISPC_VID_BA0(0),
798 DISPC_VID_BA0(1) };
799
800 dispc_write_reg(ba0_reg[plane], paddr);
801}
802
803static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
804{
805 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
806 DISPC_VID_BA1(0),
807 DISPC_VID_BA1(1) };
808
809 dispc_write_reg(ba1_reg[plane], paddr);
810}
811
812static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
813{
814 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
815 DISPC_VID_POSITION(0),
816 DISPC_VID_POSITION(1) };
817
818 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
819 dispc_write_reg(pos_reg[plane], val);
820}
821
822static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
823{
824 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
825 DISPC_VID_PICTURE_SIZE(0),
826 DISPC_VID_PICTURE_SIZE(1) };
827 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
828 dispc_write_reg(siz_reg[plane], val);
829}
830
831static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
832{
833 u32 val;
834 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
835 DISPC_VID_SIZE(1) };
836
837 BUG_ON(plane == OMAP_DSS_GFX);
838
839 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
840 dispc_write_reg(vsi_reg[plane-1], val);
841}
842
fd28a390
R		 843static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
844{
845 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
846 return;
847
848 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
849 plane == OMAP_DSS_VIDEO1)
850 return;
851
852 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
853}
854
80c39712
TV		 855static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
856{
a0acb557 857 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 858 return;
859
fd28a390
R		 860 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
861 plane == OMAP_DSS_VIDEO1)
862 return;
a0acb557 863
80c39712
TV		 864 if (plane == OMAP_DSS_GFX)
865 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
866 else if (plane == OMAP_DSS_VIDEO2)
867 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
868}
869
870static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
871{
872 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
873 DISPC_VID_PIXEL_INC(0),
874 DISPC_VID_PIXEL_INC(1) };
875
876 dispc_write_reg(ri_reg[plane], inc);
877}
878
879static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
880{
881 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
882 DISPC_VID_ROW_INC(0),
883 DISPC_VID_ROW_INC(1) };
884
885 dispc_write_reg(ri_reg[plane], inc);
886}
887
888static void _dispc_set_color_mode(enum omap_plane plane,
889 enum omap_color_mode color_mode)
890{
891 u32 m = 0;
892
893 switch (color_mode) {
894 case OMAP_DSS_COLOR_CLUT1:
895 m = 0x0; break;
896 case OMAP_DSS_COLOR_CLUT2:
897 m = 0x1; break;
898 case OMAP_DSS_COLOR_CLUT4:
899 m = 0x2; break;
900 case OMAP_DSS_COLOR_CLUT8:
901 m = 0x3; break;
902 case OMAP_DSS_COLOR_RGB12U:
903 m = 0x4; break;
904 case OMAP_DSS_COLOR_ARGB16:
905 m = 0x5; break;
906 case OMAP_DSS_COLOR_RGB16:
907 m = 0x6; break;
908 case OMAP_DSS_COLOR_RGB24U:
909 m = 0x8; break;
910 case OMAP_DSS_COLOR_RGB24P:
911 m = 0x9; break;
912 case OMAP_DSS_COLOR_YUV2:
913 m = 0xa; break;
914 case OMAP_DSS_COLOR_UYVY:
915 m = 0xb; break;
916 case OMAP_DSS_COLOR_ARGB32:
917 m = 0xc; break;
918 case OMAP_DSS_COLOR_RGBA32:
919 m = 0xd; break;
920 case OMAP_DSS_COLOR_RGBX32:
921 m = 0xe; break;
922 default:
923 BUG(); break;
924 }
925
926 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
927}
928
929static void _dispc_set_channel_out(enum omap_plane plane,
930 enum omap_channel channel)
931{
932 int shift;
933 u32 val;
2a205f34 934 int chan = 0, chan2 = 0;
80c39712
TV		 935
936 switch (plane) {
937 case OMAP_DSS_GFX:
938 shift = 8;
939 break;
940 case OMAP_DSS_VIDEO1:
941 case OMAP_DSS_VIDEO2:
942 shift = 16;
943 break;
944 default:
945 BUG();
946 return;
947 }
948
949 val = dispc_read_reg(dispc_reg_att[plane]);
2a205f34
SS		 950 if (dss_has_feature(FEAT_MGR_LCD2)) {
951 switch (channel) {
952 case OMAP_DSS_CHANNEL_LCD:
953 chan = 0;
954 chan2 = 0;
955 break;
956 case OMAP_DSS_CHANNEL_DIGIT:
957 chan = 1;
958 chan2 = 0;
959 break;
960 case OMAP_DSS_CHANNEL_LCD2:
961 chan = 0;
962 chan2 = 1;
963 break;
964 default:
965 BUG();
966 }
967
968 val = FLD_MOD(val, chan, shift, shift);
969 val = FLD_MOD(val, chan2, 31, 30);
970 } else {
971 val = FLD_MOD(val, channel, shift, shift);
972 }
80c39712
TV		 973 dispc_write_reg(dispc_reg_att[plane], val);
974}
975
976void dispc_set_burst_size(enum omap_plane plane,
977 enum omap_burst_size burst_size)
978{
979 int shift;
980 u32 val;
981
982 enable_clocks(1);
983
984 switch (plane) {
985 case OMAP_DSS_GFX:
986 shift = 6;
987 break;
988 case OMAP_DSS_VIDEO1:
989 case OMAP_DSS_VIDEO2:
990 shift = 14;
991 break;
992 default:
993 BUG();
994 return;
995 }
996
997 val = dispc_read_reg(dispc_reg_att[plane]);
998 val = FLD_MOD(val, burst_size, shift+1, shift);
999 dispc_write_reg(dispc_reg_att[plane], val);
1000
1001 enable_clocks(0);
1002}
1003
1004static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1005{
1006 u32 val;
1007
1008 BUG_ON(plane == OMAP_DSS_GFX);
1009
1010 val = dispc_read_reg(dispc_reg_att[plane]);
1011 val = FLD_MOD(val, enable, 9, 9);
1012 dispc_write_reg(dispc_reg_att[plane], val);
1013}
1014
1015void dispc_enable_replication(enum omap_plane plane, bool enable)
1016{
1017 int bit;
1018
1019 if (plane == OMAP_DSS_GFX)
1020 bit = 5;
1021 else
1022 bit = 10;
1023
1024 enable_clocks(1);
1025 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1026 enable_clocks(0);
1027}
1028
64ba4f74 1029void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1030{
1031 u32 val;
1032 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1033 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1034 enable_clocks(1);
64ba4f74 1035 dispc_write_reg(DISPC_SIZE_LCD(channel), val);
80c39712
TV		 1036 enable_clocks(0);
1037}
1038
1039void dispc_set_digit_size(u16 width, u16 height)
1040{
1041 u32 val;
1042 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1043 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1044 enable_clocks(1);
1045 dispc_write_reg(DISPC_SIZE_DIG, val);
1046 enable_clocks(0);
1047}
1048
1049static void dispc_read_plane_fifo_sizes(void)
1050{
1051 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1052 DISPC_VID_FIFO_SIZE_STATUS(0),
1053 DISPC_VID_FIFO_SIZE_STATUS(1) };
1054 u32 size;
1055 int plane;
a0acb557 1056 u8 start, end;
80c39712
TV		 1057
1058 enable_clocks(1);
1059
a0acb557 1060 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1061
a0acb557
AT		 1062 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1063 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
80c39712
TV		 1064 dispc.fifo_size[plane] = size;
1065 }
1066
1067 enable_clocks(0);
1068}
1069
1070u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1071{
1072 return dispc.fifo_size[plane];
1073}
1074
1075void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1076{
1077 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1078 DISPC_VID_FIFO_THRESHOLD(0),
1079 DISPC_VID_FIFO_THRESHOLD(1) };
a0acb557
AT		 1080 u8 hi_start, hi_end, lo_start, lo_end;
1081
80c39712
TV		 1082 enable_clocks(1);
1083
1084 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1085 plane,
1086 REG_GET(ftrs_reg[plane], 11, 0),
1087 REG_GET(ftrs_reg[plane], 27, 16),
1088 low, high);
1089
a0acb557
AT		 1090 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1091 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1092
1093 dispc_write_reg(ftrs_reg[plane],
1094 FLD_VAL(high, hi_start, hi_end) |
1095 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1096
1097 enable_clocks(0);
1098}
1099
1100void dispc_enable_fifomerge(bool enable)
1101{
1102 enable_clocks(1);
1103
1104 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1105 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1106
1107 enable_clocks(0);
1108}
1109
1110static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1111{
1112 u32 val;
1113 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1114 DISPC_VID_FIR(1) };
a0acb557 1115 u8 hinc_start, hinc_end, vinc_start, vinc_end;
80c39712
TV		 1116
1117 BUG_ON(plane == OMAP_DSS_GFX);
1118
a0acb557
AT		 1119 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1120 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1121
1122 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1123 FLD_VAL(hinc, hinc_start, hinc_end);
1124
80c39712
TV		 1125 dispc_write_reg(fir_reg[plane-1], val);
1126}
1127
1128static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1129{
1130 u32 val;
1131 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1132 DISPC_VID_ACCU0(1) };
1133
1134 BUG_ON(plane == OMAP_DSS_GFX);
1135
1136 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1137 dispc_write_reg(ac0_reg[plane-1], val);
1138}
1139
1140static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1141{
1142 u32 val;
1143 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1144 DISPC_VID_ACCU1(1) };
1145
1146 BUG_ON(plane == OMAP_DSS_GFX);
1147
1148 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1149 dispc_write_reg(ac1_reg[plane-1], val);
1150}
1151
1152
1153static void _dispc_set_scaling(enum omap_plane plane,
1154 u16 orig_width, u16 orig_height,
1155 u16 out_width, u16 out_height,
1156 bool ilace, bool five_taps,
1157 bool fieldmode)
1158{
1159 int fir_hinc;
1160 int fir_vinc;
1161 int hscaleup, vscaleup;
1162 int accu0 = 0;
1163 int accu1 = 0;
1164 u32 l;
1165
1166 BUG_ON(plane == OMAP_DSS_GFX);
1167
1168 hscaleup = orig_width <= out_width;
1169 vscaleup = orig_height <= out_height;
1170
1171 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1172
1173 if (!orig_width || orig_width == out_width)
1174 fir_hinc = 0;
1175 else
1176 fir_hinc = 1024 * orig_width / out_width;
1177
1178 if (!orig_height || orig_height == out_height)
1179 fir_vinc = 0;
1180 else
1181 fir_vinc = 1024 * orig_height / out_height;
1182
1183 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1184
1185 l = dispc_read_reg(dispc_reg_att[plane]);
1186 l &= ~((0x0f << 5) | (0x3 << 21));
1187
1188 l |= fir_hinc ? (1 << 5) : 0;
1189 l |= fir_vinc ? (1 << 6) : 0;
1190
1191 l |= hscaleup ? 0 : (1 << 7);
1192 l |= vscaleup ? 0 : (1 << 8);
1193
1194 l |= five_taps ? (1 << 21) : 0;
1195 l |= five_taps ? (1 << 22) : 0;
1196
1197 dispc_write_reg(dispc_reg_att[plane], l);
1198
1199 /*
1200 * field 0 = even field = bottom field
1201 * field 1 = odd field = top field
1202 */
1203 if (ilace && !fieldmode) {
1204 accu1 = 0;
1205 accu0 = (fir_vinc / 2) & 0x3ff;
1206 if (accu0 >= 1024/2) {
1207 accu1 = 1024/2;
1208 accu0 -= accu1;
1209 }
1210 }
1211
1212 _dispc_set_vid_accu0(plane, 0, accu0);
1213 _dispc_set_vid_accu1(plane, 0, accu1);
1214}
1215
1216static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1217 bool mirroring, enum omap_color_mode color_mode)
1218{
1219 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1220 color_mode == OMAP_DSS_COLOR_UYVY) {
1221 int vidrot = 0;
1222
1223 if (mirroring) {
1224 switch (rotation) {
1225 case OMAP_DSS_ROT_0:
1226 vidrot = 2;
1227 break;
1228 case OMAP_DSS_ROT_90:
1229 vidrot = 1;
1230 break;
1231 case OMAP_DSS_ROT_180:
1232 vidrot = 0;
1233 break;
1234 case OMAP_DSS_ROT_270:
1235 vidrot = 3;
1236 break;
1237 }
1238 } else {
1239 switch (rotation) {
1240 case OMAP_DSS_ROT_0:
1241 vidrot = 0;
1242 break;
1243 case OMAP_DSS_ROT_90:
1244 vidrot = 1;
1245 break;
1246 case OMAP_DSS_ROT_180:
1247 vidrot = 2;
1248 break;
1249 case OMAP_DSS_ROT_270:
1250 vidrot = 3;
1251 break;
1252 }
1253 }
1254
1255 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1256
1257 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1258 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1259 else
1260 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1261 } else {
1262 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1263 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1264 }
1265}
1266
1267static int color_mode_to_bpp(enum omap_color_mode color_mode)
1268{
1269 switch (color_mode) {
1270 case OMAP_DSS_COLOR_CLUT1:
1271 return 1;
1272 case OMAP_DSS_COLOR_CLUT2:
1273 return 2;
1274 case OMAP_DSS_COLOR_CLUT4:
1275 return 4;
1276 case OMAP_DSS_COLOR_CLUT8:
1277 return 8;
1278 case OMAP_DSS_COLOR_RGB12U:
1279 case OMAP_DSS_COLOR_RGB16:
1280 case OMAP_DSS_COLOR_ARGB16:
1281 case OMAP_DSS_COLOR_YUV2:
1282 case OMAP_DSS_COLOR_UYVY:
1283 return 16;
1284 case OMAP_DSS_COLOR_RGB24P:
1285 return 24;
1286 case OMAP_DSS_COLOR_RGB24U:
1287 case OMAP_DSS_COLOR_ARGB32:
1288 case OMAP_DSS_COLOR_RGBA32:
1289 case OMAP_DSS_COLOR_RGBX32:
1290 return 32;
1291 default:
1292 BUG();
1293 }
1294}
1295
1296static s32 pixinc(int pixels, u8 ps)
1297{
1298 if (pixels == 1)
1299 return 1;
1300 else if (pixels > 1)
1301 return 1 + (pixels - 1) * ps;
1302 else if (pixels < 0)
1303 return 1 - (-pixels + 1) * ps;
1304 else
1305 BUG();
1306}
1307
1308static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1309 u16 screen_width,
1310 u16 width, u16 height,
1311 enum omap_color_mode color_mode, bool fieldmode,
1312 unsigned int field_offset,
1313 unsigned *offset0, unsigned *offset1,
1314 s32 *row_inc, s32 *pix_inc)
1315{
1316 u8 ps;
1317
1318 /* FIXME CLUT formats */
1319 switch (color_mode) {
1320 case OMAP_DSS_COLOR_CLUT1:
1321 case OMAP_DSS_COLOR_CLUT2:
1322 case OMAP_DSS_COLOR_CLUT4:
1323 case OMAP_DSS_COLOR_CLUT8:
1324 BUG();
1325 return;
1326 case OMAP_DSS_COLOR_YUV2:
1327 case OMAP_DSS_COLOR_UYVY:
1328 ps = 4;
1329 break;
1330 default:
1331 ps = color_mode_to_bpp(color_mode) / 8;
1332 break;
1333 }
1334
1335 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1336 width, height);
1337
1338 /*
1339 * field 0 = even field = bottom field
1340 * field 1 = odd field = top field
1341 */
1342 switch (rotation + mirror * 4) {
1343 case OMAP_DSS_ROT_0:
1344 case OMAP_DSS_ROT_180:
1345 /*
1346 * If the pixel format is YUV or UYVY divide the width
1347 * of the image by 2 for 0 and 180 degree rotation.
1348 */
1349 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1350 color_mode == OMAP_DSS_COLOR_UYVY)
1351 width = width >> 1;
1352 case OMAP_DSS_ROT_90:
1353 case OMAP_DSS_ROT_270:
1354 *offset1 = 0;
1355 if (field_offset)
1356 *offset0 = field_offset * screen_width * ps;
1357 else
1358 *offset0 = 0;
1359
1360 *row_inc = pixinc(1 + (screen_width - width) +
1361 (fieldmode ? screen_width : 0),
1362 ps);
1363 *pix_inc = pixinc(1, ps);
1364 break;
1365
1366 case OMAP_DSS_ROT_0 + 4:
1367 case OMAP_DSS_ROT_180 + 4:
1368 /* If the pixel format is YUV or UYVY divide the width
1369 * of the image by 2 for 0 degree and 180 degree
1370 */
1371 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1372 color_mode == OMAP_DSS_COLOR_UYVY)
1373 width = width >> 1;
1374 case OMAP_DSS_ROT_90 + 4:
1375 case OMAP_DSS_ROT_270 + 4:
1376 *offset1 = 0;
1377 if (field_offset)
1378 *offset0 = field_offset * screen_width * ps;
1379 else
1380 *offset0 = 0;
1381 *row_inc = pixinc(1 - (screen_width + width) -
1382 (fieldmode ? screen_width : 0),
1383 ps);
1384 *pix_inc = pixinc(1, ps);
1385 break;
1386
1387 default:
1388 BUG();
1389 }
1390}
1391
1392static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1393 u16 screen_width,
1394 u16 width, u16 height,
1395 enum omap_color_mode color_mode, bool fieldmode,
1396 unsigned int field_offset,
1397 unsigned *offset0, unsigned *offset1,
1398 s32 *row_inc, s32 *pix_inc)
1399{
1400 u8 ps;
1401 u16 fbw, fbh;
1402
1403 /* FIXME CLUT formats */
1404 switch (color_mode) {
1405 case OMAP_DSS_COLOR_CLUT1:
1406 case OMAP_DSS_COLOR_CLUT2:
1407 case OMAP_DSS_COLOR_CLUT4:
1408 case OMAP_DSS_COLOR_CLUT8:
1409 BUG();
1410 return;
1411 default:
1412 ps = color_mode_to_bpp(color_mode) / 8;
1413 break;
1414 }
1415
1416 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1417 width, height);
1418
1419 /* width & height are overlay sizes, convert to fb sizes */
1420
1421 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1422 fbw = width;
1423 fbh = height;
1424 } else {
1425 fbw = height;
1426 fbh = width;
1427 }
1428
1429 /*
1430 * field 0 = even field = bottom field
1431 * field 1 = odd field = top field
1432 */
1433 switch (rotation + mirror * 4) {
1434 case OMAP_DSS_ROT_0:
1435 *offset1 = 0;
1436 if (field_offset)
1437 *offset0 = *offset1 + field_offset * screen_width * ps;
1438 else
1439 *offset0 = *offset1;
1440 *row_inc = pixinc(1 + (screen_width - fbw) +
1441 (fieldmode ? screen_width : 0),
1442 ps);
1443 *pix_inc = pixinc(1, ps);
1444 break;
1445 case OMAP_DSS_ROT_90:
1446 *offset1 = screen_width * (fbh - 1) * ps;
1447 if (field_offset)
1448 *offset0 = *offset1 + field_offset * ps;
1449 else
1450 *offset0 = *offset1;
1451 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1452 (fieldmode ? 1 : 0), ps);
1453 *pix_inc = pixinc(-screen_width, ps);
1454 break;
1455 case OMAP_DSS_ROT_180:
1456 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1457 if (field_offset)
1458 *offset0 = *offset1 - field_offset * screen_width * ps;
1459 else
1460 *offset0 = *offset1;
1461 *row_inc = pixinc(-1 -
1462 (screen_width - fbw) -
1463 (fieldmode ? screen_width : 0),
1464 ps);
1465 *pix_inc = pixinc(-1, ps);
1466 break;
1467 case OMAP_DSS_ROT_270:
1468 *offset1 = (fbw - 1) * ps;
1469 if (field_offset)
1470 *offset0 = *offset1 - field_offset * ps;
1471 else
1472 *offset0 = *offset1;
1473 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1474 (fieldmode ? 1 : 0), ps);
1475 *pix_inc = pixinc(screen_width, ps);
1476 break;
1477
1478 /* mirroring */
1479 case OMAP_DSS_ROT_0 + 4:
1480 *offset1 = (fbw - 1) * ps;
1481 if (field_offset)
1482 *offset0 = *offset1 + field_offset * screen_width * ps;
1483 else
1484 *offset0 = *offset1;
1485 *row_inc = pixinc(screen_width * 2 - 1 +
1486 (fieldmode ? screen_width : 0),
1487 ps);
1488 *pix_inc = pixinc(-1, ps);
1489 break;
1490
1491 case OMAP_DSS_ROT_90 + 4:
1492 *offset1 = 0;
1493 if (field_offset)
1494 *offset0 = *offset1 + field_offset * ps;
1495 else
1496 *offset0 = *offset1;
1497 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1498 (fieldmode ? 1 : 0),
1499 ps);
1500 *pix_inc = pixinc(screen_width, ps);
1501 break;
1502
1503 case OMAP_DSS_ROT_180 + 4:
1504 *offset1 = screen_width * (fbh - 1) * ps;
1505 if (field_offset)
1506 *offset0 = *offset1 - field_offset * screen_width * ps;
1507 else
1508 *offset0 = *offset1;
1509 *row_inc = pixinc(1 - screen_width * 2 -
1510 (fieldmode ? screen_width : 0),
1511 ps);
1512 *pix_inc = pixinc(1, ps);
1513 break;
1514
1515 case OMAP_DSS_ROT_270 + 4:
1516 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1517 if (field_offset)
1518 *offset0 = *offset1 - field_offset * ps;
1519 else
1520 *offset0 = *offset1;
1521 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1522 (fieldmode ? 1 : 0),
1523 ps);
1524 *pix_inc = pixinc(-screen_width, ps);
1525 break;
1526
1527 default:
1528 BUG();
1529 }
1530}
1531
ff1b2cde
SS		 1532static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1533 u16 height, u16 out_width, u16 out_height,
1534 enum omap_color_mode color_mode)
80c39712
TV		 1535{
1536 u32 fclk = 0;
1537 /* FIXME venc pclk? */
ff1b2cde 1538 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1539
1540 if (height > out_height) {
1541 /* FIXME get real display PPL */
1542 unsigned int ppl = 800;
1543
1544 tmp = pclk * height * out_width;
1545 do_div(tmp, 2 * out_height * ppl);
1546 fclk = tmp;
1547
2d9c5597
VS		 1548 if (height > 2 * out_height) {
1549 if (ppl == out_width)
1550 return 0;
1551
80c39712
TV		 1552 tmp = pclk * (height - 2 * out_height) * out_width;
1553 do_div(tmp, 2 * out_height * (ppl - out_width));
1554 fclk = max(fclk, (u32) tmp);
1555 }
1556 }
1557
1558 if (width > out_width) {
1559 tmp = pclk * width;
1560 do_div(tmp, out_width);
1561 fclk = max(fclk, (u32) tmp);
1562
1563 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1564 fclk <<= 1;
1565 }
1566
1567 return fclk;
1568}
1569
ff1b2cde
SS		 1570static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1571 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1572{
1573 unsigned int hf, vf;
1574
1575 /*
1576 * FIXME how to determine the 'A' factor
1577 * for the no downscaling case ?
1578 */
1579
1580 if (width > 3 * out_width)
1581 hf = 4;
1582 else if (width > 2 * out_width)
1583 hf = 3;
1584 else if (width > out_width)
1585 hf = 2;
1586 else
1587 hf = 1;
1588
1589 if (height > out_height)
1590 vf = 2;
1591 else
1592 vf = 1;
1593
1594 /* FIXME venc pclk? */
ff1b2cde 1595 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1596}
1597
1598void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1599{
1600 enable_clocks(1);
1601 _dispc_set_channel_out(plane, channel_out);
1602 enable_clocks(0);
1603}
1604
1605static int _dispc_setup_plane(enum omap_plane plane,
1606 u32 paddr, u16 screen_width,
1607 u16 pos_x, u16 pos_y,
1608 u16 width, u16 height,
1609 u16 out_width, u16 out_height,
1610 enum omap_color_mode color_mode,
1611 bool ilace,
1612 enum omap_dss_rotation_type rotation_type,
1613 u8 rotation, int mirror,
18faa1b6
SS		 1614 u8 global_alpha, u8 pre_mult_alpha,
1615 enum omap_channel channel)
80c39712
TV		 1616{
1617 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1618 bool five_taps = 0;
1619 bool fieldmode = 0;
1620 int cconv = 0;
1621 unsigned offset0, offset1;
1622 s32 row_inc;
1623 s32 pix_inc;
1624 u16 frame_height = height;
1625 unsigned int field_offset = 0;
1626
1627 if (paddr == 0)
1628 return -EINVAL;
1629
1630 if (ilace && height == out_height)
1631 fieldmode = 1;
1632
1633 if (ilace) {
1634 if (fieldmode)
1635 height /= 2;
1636 pos_y /= 2;
1637 out_height /= 2;
1638
1639 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1640 "out_height %d\n",
1641 height, pos_y, out_height);
1642 }
1643
8dad2ab6
AT		 1644 if (!dss_feat_color_mode_supported(plane, color_mode))
1645 return -EINVAL;
1646
80c39712
TV		 1647 if (plane == OMAP_DSS_GFX) {
1648 if (width != out_width || height != out_height)
1649 return -EINVAL;
80c39712
TV		 1650 } else {
1651 /* video plane */
1652
1653 unsigned long fclk = 0;
1654
1655 if (out_width < width / maxdownscale ||
1656 out_width > width * 8)
1657 return -EINVAL;
1658
1659 if (out_height < height / maxdownscale ||
1660 out_height > height * 8)
1661 return -EINVAL;
1662
8dad2ab6
AT		 1663 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1664 color_mode == OMAP_DSS_COLOR_UYVY)
80c39712 1665 cconv = 1;
80c39712
TV		 1666
1667 /* Must use 5-tap filter? */
1668 five_taps = height > out_height * 2;
1669
1670 if (!five_taps) {
18faa1b6
SS		 1671 fclk = calc_fclk(channel, width, height, out_width,
1672 out_height);
80c39712
TV		 1673
1674 /* Try 5-tap filter if 3-tap fclk is too high */
1675 if (cpu_is_omap34xx() && height > out_height &&
1676 fclk > dispc_fclk_rate())
1677 five_taps = true;
1678 }
1679
1680 if (width > (2048 >> five_taps)) {
1681 DSSERR("failed to set up scaling, fclk too low\n");
1682 return -EINVAL;
1683 }
1684
1685 if (five_taps)
18faa1b6
SS		 1686 fclk = calc_fclk_five_taps(channel, width, height,
1687 out_width, out_height, color_mode);
80c39712
TV		 1688
1689 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1690 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1691
2d9c5597 1692 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1693 DSSERR("failed to set up scaling, "
1694 "required fclk rate = %lu Hz, "
1695 "current fclk rate = %lu Hz\n",
1696 fclk, dispc_fclk_rate());
1697 return -EINVAL;
1698 }
1699 }
1700
1701 if (ilace && !fieldmode) {
1702 /*
1703 * when downscaling the bottom field may have to start several
1704 * source lines below the top field. Unfortunately ACCUI
1705 * registers will only hold the fractional part of the offset
1706 * so the integer part must be added to the base address of the
1707 * bottom field.
1708 */
1709 if (!height || height == out_height)
1710 field_offset = 0;
1711 else
1712 field_offset = height / out_height / 2;
1713 }
1714
1715 /* Fields are independent but interleaved in memory. */
1716 if (fieldmode)
1717 field_offset = 1;
1718
1719 if (rotation_type == OMAP_DSS_ROT_DMA)
1720 calc_dma_rotation_offset(rotation, mirror,
1721 screen_width, width, frame_height, color_mode,
1722 fieldmode, field_offset,
1723 &offset0, &offset1, &row_inc, &pix_inc);
1724 else
1725 calc_vrfb_rotation_offset(rotation, mirror,
1726 screen_width, width, frame_height, color_mode,
1727 fieldmode, field_offset,
1728 &offset0, &offset1, &row_inc, &pix_inc);
1729
1730 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1731 offset0, offset1, row_inc, pix_inc);
1732
1733 _dispc_set_color_mode(plane, color_mode);
1734
1735 _dispc_set_plane_ba0(plane, paddr + offset0);
1736 _dispc_set_plane_ba1(plane, paddr + offset1);
1737
1738 _dispc_set_row_inc(plane, row_inc);
1739 _dispc_set_pix_inc(plane, pix_inc);
1740
1741 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1742 out_width, out_height);
1743
1744 _dispc_set_plane_pos(plane, pos_x, pos_y);
1745
1746 _dispc_set_pic_size(plane, width, height);
1747
1748 if (plane != OMAP_DSS_GFX) {
1749 _dispc_set_scaling(plane, width, height,
1750 out_width, out_height,
1751 ilace, five_taps, fieldmode);
1752 _dispc_set_vid_size(plane, out_width, out_height);
1753 _dispc_set_vid_color_conv(plane, cconv);
1754 }
1755
1756 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1757
fd28a390
R		 1758 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1759 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1760
1761 return 0;
1762}
1763
1764static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1765{
1766 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1767}
1768
1769static void dispc_disable_isr(void *data, u32 mask)
1770{
1771 struct completion *compl = data;
1772 complete(compl);
1773}
1774
2a205f34 1775static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1776{
2a205f34
SS		 1777 if (channel == OMAP_DSS_CHANNEL_LCD2)
1778 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1779 else
1780 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1781}
1782
2a205f34 1783static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1784{
1785 struct completion frame_done_completion;
1786 bool is_on;
1787 int r;
2a205f34 1788 u32 irq;
80c39712
TV		 1789
1790 enable_clocks(1);
1791
1792 /* When we disable LCD output, we need to wait until frame is done.
1793 * Otherwise the DSS is still working, and turning off the clocks
1794 * prevents DSS from going to OFF mode */
2a205f34
SS		 1795 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1796 REG_GET(DISPC_CONTROL2, 0, 0) :
1797 REG_GET(DISPC_CONTROL, 0, 0);
1798
1799 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1800 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1801
1802 if (!enable && is_on) {
1803 init_completion(&frame_done_completion);
1804
1805 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1806 &frame_done_completion, irq);
80c39712
TV		 1807
1808 if (r)
1809 DSSERR("failed to register FRAMEDONE isr\n");
1810 }
1811
2a205f34 1812 _enable_lcd_out(channel, enable);
80c39712
TV		 1813
1814 if (!enable && is_on) {
1815 if (!wait_for_completion_timeout(&frame_done_completion,
1816 msecs_to_jiffies(100)))
1817 DSSERR("timeout waiting for FRAME DONE\n");
1818
1819 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1820 &frame_done_completion, irq);
80c39712
TV		 1821
1822 if (r)
1823 DSSERR("failed to unregister FRAMEDONE isr\n");
1824 }
1825
1826 enable_clocks(0);
1827}
1828
1829static void _enable_digit_out(bool enable)
1830{
1831 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1832}
1833
a2faee84 1834static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1835{
1836 struct completion frame_done_completion;
1837 int r;
1838
1839 enable_clocks(1);
1840
1841 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1842 enable_clocks(0);
1843 return;
1844 }
1845
1846 if (enable) {
1847 unsigned long flags;
1848 /* When we enable digit output, we'll get an extra digit
1849 * sync lost interrupt, that we need to ignore */
1850 spin_lock_irqsave(&dispc.irq_lock, flags);
1851 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1852 _omap_dispc_set_irqs();
1853 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1854 }
1855
1856 /* When we disable digit output, we need to wait until fields are done.
1857 * Otherwise the DSS is still working, and turning off the clocks
1858 * prevents DSS from going to OFF mode. And when enabling, we need to
1859 * wait for the extra sync losts */
1860 init_completion(&frame_done_completion);
1861
1862 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1863 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1864 if (r)
1865 DSSERR("failed to register EVSYNC isr\n");
1866
1867 _enable_digit_out(enable);
1868
1869 /* XXX I understand from TRM that we should only wait for the
1870 * current field to complete. But it seems we have to wait
1871 * for both fields */
1872 if (!wait_for_completion_timeout(&frame_done_completion,
1873 msecs_to_jiffies(100)))
1874 DSSERR("timeout waiting for EVSYNC\n");
1875
1876 if (!wait_for_completion_timeout(&frame_done_completion,
1877 msecs_to_jiffies(100)))
1878 DSSERR("timeout waiting for EVSYNC\n");
1879
1880 r = omap_dispc_unregister_isr(dispc_disable_isr,
1881 &frame_done_completion,
1882 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1883 if (r)
1884 DSSERR("failed to unregister EVSYNC isr\n");
1885
1886 if (enable) {
1887 unsigned long flags;
1888 spin_lock_irqsave(&dispc.irq_lock, flags);
1889 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1890 if (dss_has_feature(FEAT_MGR_LCD2))
1891 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1892 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1893 _omap_dispc_set_irqs();
1894 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1895 }
1896
1897 enable_clocks(0);
1898}
1899
a2faee84
TV		 1900bool dispc_is_channel_enabled(enum omap_channel channel)
1901{
1902 if (channel == OMAP_DSS_CHANNEL_LCD)
1903 return !!REG_GET(DISPC_CONTROL, 0, 0);
1904 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1905 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 1906 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1907 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 1908 else
1909 BUG();
1910}
1911
1912void dispc_enable_channel(enum omap_channel channel, bool enable)
1913{
2a205f34
SS		 1914 if (channel == OMAP_DSS_CHANNEL_LCD ||
1915 channel == OMAP_DSS_CHANNEL_LCD2)
1916 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 1917 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1918 dispc_enable_digit_out(enable);
1919 else
1920 BUG();
1921}
1922
80c39712
TV		 1923void dispc_lcd_enable_signal_polarity(bool act_high)
1924{
6ced40bf
AT		 1925 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1926 return;
1927
80c39712
TV		 1928 enable_clocks(1);
1929 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1930 enable_clocks(0);
1931}
1932
1933void dispc_lcd_enable_signal(bool enable)
1934{
6ced40bf
AT		 1935 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1936 return;
1937
80c39712
TV		 1938 enable_clocks(1);
1939 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1940 enable_clocks(0);
1941}
1942
1943void dispc_pck_free_enable(bool enable)
1944{
6ced40bf
AT		 1945 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1946 return;
1947
80c39712
TV		 1948 enable_clocks(1);
1949 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1950 enable_clocks(0);
1951}
1952
64ba4f74 1953void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 1954{
1955 enable_clocks(1);
2a205f34
SS		 1956 if (channel == OMAP_DSS_CHANNEL_LCD2)
1957 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1958 else
1959 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 1960 enable_clocks(0);
1961}
1962
1963
64ba4f74
SS		 1964void dispc_set_lcd_display_type(enum omap_channel channel,
1965 enum omap_lcd_display_type type)
80c39712
TV		 1966{
1967 int mode;
1968
1969 switch (type) {
1970 case OMAP_DSS_LCD_DISPLAY_STN:
1971 mode = 0;
1972 break;
1973
1974 case OMAP_DSS_LCD_DISPLAY_TFT:
1975 mode = 1;
1976 break;
1977
1978 default:
1979 BUG();
1980 return;
1981 }
1982
1983 enable_clocks(1);
2a205f34
SS		 1984 if (channel == OMAP_DSS_CHANNEL_LCD2)
1985 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1986 else
1987 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 1988 enable_clocks(0);
1989}
1990
1991void dispc_set_loadmode(enum omap_dss_load_mode mode)
1992{
1993 enable_clocks(1);
1994 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1995 enable_clocks(0);
1996}
1997
1998
1999void dispc_set_default_color(enum omap_channel channel, u32 color)
2000{
80c39712 2001 enable_clocks(1);
8613b000 2002 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2003 enable_clocks(0);
2004}
2005
2006u32 dispc_get_default_color(enum omap_channel channel)
2007{
80c39712
TV		 2008 u32 l;
2009
2010 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2011 channel != OMAP_DSS_CHANNEL_LCD &&
2012 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2013
2014 enable_clocks(1);
8613b000 2015 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2016 enable_clocks(0);
2017
2018 return l;
2019}
2020
2021void dispc_set_trans_key(enum omap_channel ch,
2022 enum omap_dss_trans_key_type type,
2023 u32 trans_key)
2024{
80c39712
TV		 2025 enable_clocks(1);
2026 if (ch == OMAP_DSS_CHANNEL_LCD)
2027 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2028 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2029 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2030 else /* OMAP_DSS_CHANNEL_LCD2 */
2031 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2032
8613b000 2033 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2034 enable_clocks(0);
2035}
2036
2037void dispc_get_trans_key(enum omap_channel ch,
2038 enum omap_dss_trans_key_type *type,
2039 u32 *trans_key)
2040{
80c39712
TV		 2041 enable_clocks(1);
2042 if (type) {
2043 if (ch == OMAP_DSS_CHANNEL_LCD)
2044 *type = REG_GET(DISPC_CONFIG, 11, 11);
2045 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2046 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2047 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2048 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2049 else
2050 BUG();
2051 }
2052
2053 if (trans_key)
8613b000 2054 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2055 enable_clocks(0);
2056}
2057
2058void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2059{
2060 enable_clocks(1);
2061 if (ch == OMAP_DSS_CHANNEL_LCD)
2062 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2063 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2064 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2065 else /* OMAP_DSS_CHANNEL_LCD2 */
2066 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2067 enable_clocks(0);
2068}
2069void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2070{
a0acb557 2071 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2072 return;
2073
2074 enable_clocks(1);
2075 if (ch == OMAP_DSS_CHANNEL_LCD)
2076 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2077 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2078 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2079 else /* OMAP_DSS_CHANNEL_LCD2 */
2080 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2081 enable_clocks(0);
2082}
2083bool dispc_alpha_blending_enabled(enum omap_channel ch)
2084{
2085 bool enabled;
2086
a0acb557 2087 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2088 return false;
2089
2090 enable_clocks(1);
2091 if (ch == OMAP_DSS_CHANNEL_LCD)
2092 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2093 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2094 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2095 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2096 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2097 else
2098 BUG();
2099 enable_clocks(0);
2100
2101 return enabled;
80c39712
TV		 2102}
2103
2104
2105bool dispc_trans_key_enabled(enum omap_channel ch)
2106{
2107 bool enabled;
2108
2109 enable_clocks(1);
2110 if (ch == OMAP_DSS_CHANNEL_LCD)
2111 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2112 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2113 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2114 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2115 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2116 else
2117 BUG();
2118 enable_clocks(0);
2119
2120 return enabled;
2121}
2122
2123
64ba4f74 2124void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2125{
2126 int code;
2127
2128 switch (data_lines) {
2129 case 12:
2130 code = 0;
2131 break;
2132 case 16:
2133 code = 1;
2134 break;
2135 case 18:
2136 code = 2;
2137 break;
2138 case 24:
2139 code = 3;
2140 break;
2141 default:
2142 BUG();
2143 return;
2144 }
2145
2146 enable_clocks(1);
2a205f34
SS		 2147 if (channel == OMAP_DSS_CHANNEL_LCD2)
2148 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2149 else
2150 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2151 enable_clocks(0);
2152}
2153
64ba4f74
SS		 2154void dispc_set_parallel_interface_mode(enum omap_channel channel,
2155 enum omap_parallel_interface_mode mode)
80c39712
TV		 2156{
2157 u32 l;
2158 int stallmode;
2159 int gpout0 = 1;
2160 int gpout1;
2161
2162 switch (mode) {
2163 case OMAP_DSS_PARALLELMODE_BYPASS:
2164 stallmode = 0;
2165 gpout1 = 1;
2166 break;
2167
2168 case OMAP_DSS_PARALLELMODE_RFBI:
2169 stallmode = 1;
2170 gpout1 = 0;
2171 break;
2172
2173 case OMAP_DSS_PARALLELMODE_DSI:
2174 stallmode = 1;
2175 gpout1 = 1;
2176 break;
2177
2178 default:
2179 BUG();
2180 return;
2181 }
2182
2183 enable_clocks(1);
2184
2a205f34
SS		 2185 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2186 l = dispc_read_reg(DISPC_CONTROL2);
2187 l = FLD_MOD(l, stallmode, 11, 11);
2188 dispc_write_reg(DISPC_CONTROL2, l);
2189 } else {
2190 l = dispc_read_reg(DISPC_CONTROL);
2191 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2192 l = FLD_MOD(l, gpout0, 15, 15);
2193 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2194 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2195 }
80c39712
TV		 2196
2197 enable_clocks(0);
2198}
2199
2200static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2201 int vsw, int vfp, int vbp)
2202{
2203 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2204 if (hsw < 1 || hsw > 64 ||
2205 hfp < 1 || hfp > 256 ||
2206 hbp < 1 || hbp > 256 ||
2207 vsw < 1 || vsw > 64 ||
2208 vfp < 0 || vfp > 255 ||
2209 vbp < 0 || vbp > 255)
2210 return false;
2211 } else {
2212 if (hsw < 1 || hsw > 256 ||
2213 hfp < 1 || hfp > 4096 ||
2214 hbp < 1 || hbp > 4096 ||
2215 vsw < 1 || vsw > 256 ||
2216 vfp < 0 || vfp > 4095 ||
2217 vbp < 0 || vbp > 4095)
2218 return false;
2219 }
2220
2221 return true;
2222}
2223
2224bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2225{
2226 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2227 timings->hbp, timings->vsw,
2228 timings->vfp, timings->vbp);
2229}
2230
64ba4f74
SS		 2231static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2232 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2233{
2234 u32 timing_h, timing_v;
2235
2236 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2237 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2238 FLD_VAL(hbp-1, 27, 20);
2239
2240 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2241 FLD_VAL(vbp, 27, 20);
2242 } else {
2243 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2244 FLD_VAL(hbp-1, 31, 20);
2245
2246 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2247 FLD_VAL(vbp, 31, 20);
2248 }
2249
2250 enable_clocks(1);
64ba4f74
SS		 2251 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2252 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2253 enable_clocks(0);
2254}
2255
2256/* change name to mode? */
64ba4f74
SS		 2257void dispc_set_lcd_timings(enum omap_channel channel,
2258 struct omap_video_timings *timings)
80c39712
TV		 2259{
2260 unsigned xtot, ytot;
2261 unsigned long ht, vt;
2262
2263 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2264 timings->hbp, timings->vsw,
2265 timings->vfp, timings->vbp))
2266 BUG();
2267
64ba4f74
SS		 2268 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2269 timings->hbp, timings->vsw, timings->vfp,
2270 timings->vbp);
80c39712 2271
64ba4f74 2272 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2273
2274 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2275 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2276
2277 ht = (timings->pixel_clock * 1000) / xtot;
2278 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2279
2a205f34
SS		 2280 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2281 timings->y_res);
80c39712
TV		 2282 DSSDBG("pck %u\n", timings->pixel_clock);
2283 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2284 timings->hsw, timings->hfp, timings->hbp,
2285 timings->vsw, timings->vfp, timings->vbp);
2286
2287 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2288}
2289
ff1b2cde
SS		 2290static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2291 u16 pck_div)
80c39712
TV		 2292{
2293 BUG_ON(lck_div < 1);
2294 BUG_ON(pck_div < 2);
2295
2296 enable_clocks(1);
ff1b2cde 2297 dispc_write_reg(DISPC_DIVISOR(channel),
80c39712
TV		 2298 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2299 enable_clocks(0);
2300}
2301
2a205f34
SS		 2302static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2303 int *pck_div)
80c39712
TV		 2304{
2305 u32 l;
2a205f34 2306 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2307 *lck_div = FLD_GET(l, 23, 16);
2308 *pck_div = FLD_GET(l, 7, 0);
2309}
2310
2311unsigned long dispc_fclk_rate(void)
2312{
2313 unsigned long r = 0;
2314
63cf28ac 2315 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
80c39712
TV		 2316 r = dss_clk_get_rate(DSS_CLK_FCK1);
2317 else
2318#ifdef CONFIG_OMAP2_DSS_DSI
2319 r = dsi_get_dsi1_pll_rate();
2320#else
2321 BUG();
2322#endif
2323 return r;
2324}
2325
ff1b2cde 2326unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712
TV		 2327{
2328 int lcd;
2329 unsigned long r;
2330 u32 l;
2331
ff1b2cde 2332 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2333
2334 lcd = FLD_GET(l, 23, 16);
2335
2336 r = dispc_fclk_rate();
2337
2338 return r / lcd;
2339}
2340
ff1b2cde 2341unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712
TV		 2342{
2343 int lcd, pcd;
2344 unsigned long r;
2345 u32 l;
2346
ff1b2cde 2347 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2348
2349 lcd = FLD_GET(l, 23, 16);
2350 pcd = FLD_GET(l, 7, 0);
2351
2352 r = dispc_fclk_rate();
2353
2354 return r / lcd / pcd;
2355}
2356
2357void dispc_dump_clocks(struct seq_file *s)
2358{
2359 int lcd, pcd;
2360
2361 enable_clocks(1);
2362
80c39712
TV		 2363 seq_printf(s, "- DISPC -\n");
2364
2365 seq_printf(s, "dispc fclk source = %s\n",
63cf28ac 2366 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
80c39712
TV		 2367 "dss1_alwon_fclk" : "dsi1_pll_fclk");
2368
2369 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34
SS		 2370
2371 seq_printf(s, "- LCD1 -\n");
2372
2373 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2374
ff1b2cde
SS		 2375 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2376 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2377 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2378 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2379 if (dss_has_feature(FEAT_MGR_LCD2)) {
2380 seq_printf(s, "- LCD2 -\n");
2381
2382 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2383
2a205f34
SS		 2384 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2385 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2386 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2387 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2388 }
80c39712
TV		 2389 enable_clocks(0);
2390}
2391
dfc0fd8d
TV		 2392#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2393void dispc_dump_irqs(struct seq_file *s)
2394{
2395 unsigned long flags;
2396 struct dispc_irq_stats stats;
2397
2398 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2399
2400 stats = dispc.irq_stats;
2401 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2402 dispc.irq_stats.last_reset = jiffies;
2403
2404 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2405
2406 seq_printf(s, "period %u ms\n",
2407 jiffies_to_msecs(jiffies - stats.last_reset));
2408
2409 seq_printf(s, "irqs %d\n", stats.irq_count);
2410#define PIS(x) \
2411 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2412
2413 PIS(FRAMEDONE);
2414 PIS(VSYNC);
2415 PIS(EVSYNC_EVEN);
2416 PIS(EVSYNC_ODD);
2417 PIS(ACBIAS_COUNT_STAT);
2418 PIS(PROG_LINE_NUM);
2419 PIS(GFX_FIFO_UNDERFLOW);
2420 PIS(GFX_END_WIN);
2421 PIS(PAL_GAMMA_MASK);
2422 PIS(OCP_ERR);
2423 PIS(VID1_FIFO_UNDERFLOW);
2424 PIS(VID1_END_WIN);
2425 PIS(VID2_FIFO_UNDERFLOW);
2426 PIS(VID2_END_WIN);
2427 PIS(SYNC_LOST);
2428 PIS(SYNC_LOST_DIGIT);
2429 PIS(WAKEUP);
2a205f34
SS		 2430 if (dss_has_feature(FEAT_MGR_LCD2)) {
2431 PIS(FRAMEDONE2);
2432 PIS(VSYNC2);
2433 PIS(ACBIAS_COUNT_STAT2);
2434 PIS(SYNC_LOST2);
2435 }
dfc0fd8d
TV		 2436#undef PIS
2437}
dfc0fd8d
TV		 2438#endif
2439
80c39712
TV		 2440void dispc_dump_regs(struct seq_file *s)
2441{
2442#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2443
2444 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2445
2446 DUMPREG(DISPC_REVISION);
2447 DUMPREG(DISPC_SYSCONFIG);
2448 DUMPREG(DISPC_SYSSTATUS);
2449 DUMPREG(DISPC_IRQSTATUS);
2450 DUMPREG(DISPC_IRQENABLE);
2451 DUMPREG(DISPC_CONTROL);
2452 DUMPREG(DISPC_CONFIG);
2453 DUMPREG(DISPC_CAPABLE);
8613b000
SS		 2454 DUMPREG(DISPC_DEFAULT_COLOR(0));
2455 DUMPREG(DISPC_DEFAULT_COLOR(1));
2456 DUMPREG(DISPC_TRANS_COLOR(0));
2457 DUMPREG(DISPC_TRANS_COLOR(1));
80c39712
TV		 2458 DUMPREG(DISPC_LINE_STATUS);
2459 DUMPREG(DISPC_LINE_NUMBER);
8613b000
SS		 2460 DUMPREG(DISPC_TIMING_H(0));
2461 DUMPREG(DISPC_TIMING_V(0));
2462 DUMPREG(DISPC_POL_FREQ(0));
2463 DUMPREG(DISPC_DIVISOR(0));
80c39712
TV		 2464 DUMPREG(DISPC_GLOBAL_ALPHA);
2465 DUMPREG(DISPC_SIZE_DIG);
8613b000 2466 DUMPREG(DISPC_SIZE_LCD(0));
2a205f34
SS		 2467 if (dss_has_feature(FEAT_MGR_LCD2)) {
2468 DUMPREG(DISPC_CONTROL2);
2469 DUMPREG(DISPC_CONFIG2);
2470 DUMPREG(DISPC_DEFAULT_COLOR(2));
2471 DUMPREG(DISPC_TRANS_COLOR(2));
2472 DUMPREG(DISPC_TIMING_H(2));
2473 DUMPREG(DISPC_TIMING_V(2));
2474 DUMPREG(DISPC_POL_FREQ(2));
2475 DUMPREG(DISPC_DIVISOR(2));
2476 DUMPREG(DISPC_SIZE_LCD(2));
2477 }
80c39712
TV		 2478
2479 DUMPREG(DISPC_GFX_BA0);
2480 DUMPREG(DISPC_GFX_BA1);
2481 DUMPREG(DISPC_GFX_POSITION);
2482 DUMPREG(DISPC_GFX_SIZE);
2483 DUMPREG(DISPC_GFX_ATTRIBUTES);
2484 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2485 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2486 DUMPREG(DISPC_GFX_ROW_INC);
2487 DUMPREG(DISPC_GFX_PIXEL_INC);
2488 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2489 DUMPREG(DISPC_GFX_TABLE_BA);
2490
8613b000
SS		 2491 DUMPREG(DISPC_DATA_CYCLE1(0));
2492 DUMPREG(DISPC_DATA_CYCLE2(0));
2493 DUMPREG(DISPC_DATA_CYCLE3(0));
80c39712 2494
8613b000
SS		 2495 DUMPREG(DISPC_CPR_COEF_R(0));
2496 DUMPREG(DISPC_CPR_COEF_G(0));
2497 DUMPREG(DISPC_CPR_COEF_B(0));
2a205f34
SS		 2498 if (dss_has_feature(FEAT_MGR_LCD2)) {
2499 DUMPREG(DISPC_DATA_CYCLE1(2));
2500 DUMPREG(DISPC_DATA_CYCLE2(2));
2501 DUMPREG(DISPC_DATA_CYCLE3(2));
2502
2503 DUMPREG(DISPC_CPR_COEF_R(2));
2504 DUMPREG(DISPC_CPR_COEF_G(2));
2505 DUMPREG(DISPC_CPR_COEF_B(2));
2506 }
80c39712
TV		 2507
2508 DUMPREG(DISPC_GFX_PRELOAD);
2509
2510 DUMPREG(DISPC_VID_BA0(0));
2511 DUMPREG(DISPC_VID_BA1(0));
2512 DUMPREG(DISPC_VID_POSITION(0));
2513 DUMPREG(DISPC_VID_SIZE(0));
2514 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2515 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2516 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2517 DUMPREG(DISPC_VID_ROW_INC(0));
2518 DUMPREG(DISPC_VID_PIXEL_INC(0));
2519 DUMPREG(DISPC_VID_FIR(0));
2520 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2521 DUMPREG(DISPC_VID_ACCU0(0));
2522 DUMPREG(DISPC_VID_ACCU1(0));
2523
2524 DUMPREG(DISPC_VID_BA0(1));
2525 DUMPREG(DISPC_VID_BA1(1));
2526 DUMPREG(DISPC_VID_POSITION(1));
2527 DUMPREG(DISPC_VID_SIZE(1));
2528 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2529 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2530 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2531 DUMPREG(DISPC_VID_ROW_INC(1));
2532 DUMPREG(DISPC_VID_PIXEL_INC(1));
2533 DUMPREG(DISPC_VID_FIR(1));
2534 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2535 DUMPREG(DISPC_VID_ACCU0(1));
2536 DUMPREG(DISPC_VID_ACCU1(1));
2537
2538 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2539 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2540 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2541 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2542 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2543 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2544 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2545 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2546 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2547 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2548 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2549 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2550 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2551 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2552 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2553 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2554 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2555 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2556 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2557 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2558 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2559 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2560 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2561 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2562 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2563 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2564 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2565 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2566 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2567
2568 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2569 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2570 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2571 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2572 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2573 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2574 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2575 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2576 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2577 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2578 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2579 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2580 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2581 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2582 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2583 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2584 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2585 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2586 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2587 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2588 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2589 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2590 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2591 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2592 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2593 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2594 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2595 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2596 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2597
2598 DUMPREG(DISPC_VID_PRELOAD(0));
2599 DUMPREG(DISPC_VID_PRELOAD(1));
2600
2601 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2602#undef DUMPREG
2603}
2604
ff1b2cde
SS		 2605static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2606 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2607{
2608 u32 l = 0;
2609
2610 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2611 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2612
2613 l |= FLD_VAL(onoff, 17, 17);
2614 l |= FLD_VAL(rf, 16, 16);
2615 l |= FLD_VAL(ieo, 15, 15);
2616 l |= FLD_VAL(ipc, 14, 14);
2617 l |= FLD_VAL(ihs, 13, 13);
2618 l |= FLD_VAL(ivs, 12, 12);
2619 l |= FLD_VAL(acbi, 11, 8);
2620 l |= FLD_VAL(acb, 7, 0);
2621
2622 enable_clocks(1);
ff1b2cde 2623 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2624 enable_clocks(0);
2625}
2626
ff1b2cde
SS		 2627void dispc_set_pol_freq(enum omap_channel channel,
2628 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2629{
ff1b2cde 2630 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2631 (config & OMAP_DSS_LCD_RF) != 0,
2632 (config & OMAP_DSS_LCD_IEO) != 0,
2633 (config & OMAP_DSS_LCD_IPC) != 0,
2634 (config & OMAP_DSS_LCD_IHS) != 0,
2635 (config & OMAP_DSS_LCD_IVS) != 0,
2636 acbi, acb);
2637}
2638
2639/* with fck as input clock rate, find dispc dividers that produce req_pck */
2640void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2641 struct dispc_clock_info *cinfo)
2642{
2643 u16 pcd_min = is_tft ? 2 : 3;
2644 unsigned long best_pck;
2645 u16 best_ld, cur_ld;
2646 u16 best_pd, cur_pd;
2647
2648 best_pck = 0;
2649 best_ld = 0;
2650 best_pd = 0;
2651
2652 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2653 unsigned long lck = fck / cur_ld;
2654
2655 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2656 unsigned long pck = lck / cur_pd;
2657 long old_delta = abs(best_pck - req_pck);
2658 long new_delta = abs(pck - req_pck);
2659
2660 if (best_pck == 0 || new_delta < old_delta) {
2661 best_pck = pck;
2662 best_ld = cur_ld;
2663 best_pd = cur_pd;
2664
2665 if (pck == req_pck)
2666 goto found;
2667 }
2668
2669 if (pck < req_pck)
2670 break;
2671 }
2672
2673 if (lck / pcd_min < req_pck)
2674 break;
2675 }
2676
2677found:
2678 cinfo->lck_div = best_ld;
2679 cinfo->pck_div = best_pd;
2680 cinfo->lck = fck / cinfo->lck_div;
2681 cinfo->pck = cinfo->lck / cinfo->pck_div;
2682}
2683
2684/* calculate clock rates using dividers in cinfo */
2685int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2686 struct dispc_clock_info *cinfo)
2687{
2688 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2689 return -EINVAL;
2690 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2691 return -EINVAL;
2692
2693 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2694 cinfo->pck = cinfo->lck / cinfo->pck_div;
2695
2696 return 0;
2697}
2698
ff1b2cde
SS		 2699int dispc_set_clock_div(enum omap_channel channel,
2700 struct dispc_clock_info *cinfo)
80c39712
TV		 2701{
2702 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2703 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2704
ff1b2cde 2705 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2706
2707 return 0;
2708}
2709
ff1b2cde
SS		 2710int dispc_get_clock_div(enum omap_channel channel,
2711 struct dispc_clock_info *cinfo)
80c39712
TV		 2712{
2713 unsigned long fck;
2714
2715 fck = dispc_fclk_rate();
2716
ff1b2cde
SS		 2717 cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
2718 cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
80c39712
TV		 2719
2720 cinfo->lck = fck / cinfo->lck_div;
2721 cinfo->pck = cinfo->lck / cinfo->pck_div;
2722
2723 return 0;
2724}
2725
2726/* dispc.irq_lock has to be locked by the caller */
2727static void _omap_dispc_set_irqs(void)
2728{
2729 u32 mask;
2730 u32 old_mask;
2731 int i;
2732 struct omap_dispc_isr_data *isr_data;
2733
2734 mask = dispc.irq_error_mask;
2735
2736 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2737 isr_data = &dispc.registered_isr[i];
2738
2739 if (isr_data->isr == NULL)
2740 continue;
2741
2742 mask |= isr_data->mask;
2743 }
2744
2745 enable_clocks(1);
2746
2747 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2748 /* clear the irqstatus for newly enabled irqs */
2749 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2750
2751 dispc_write_reg(DISPC_IRQENABLE, mask);
2752
2753 enable_clocks(0);
2754}
2755
2756int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2757{
2758 int i;
2759 int ret;
2760 unsigned long flags;
2761 struct omap_dispc_isr_data *isr_data;
2762
2763 if (isr == NULL)
2764 return -EINVAL;
2765
2766 spin_lock_irqsave(&dispc.irq_lock, flags);
2767
2768 /* check for duplicate entry */
2769 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2770 isr_data = &dispc.registered_isr[i];
2771 if (isr_data->isr == isr && isr_data->arg == arg &&
2772 isr_data->mask == mask) {
2773 ret = -EINVAL;
2774 goto err;
2775 }
2776 }
2777
2778 isr_data = NULL;
2779 ret = -EBUSY;
2780
2781 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2782 isr_data = &dispc.registered_isr[i];
2783
2784 if (isr_data->isr != NULL)
2785 continue;
2786
2787 isr_data->isr = isr;
2788 isr_data->arg = arg;
2789 isr_data->mask = mask;
2790 ret = 0;
2791
2792 break;
2793 }
2794
2795 _omap_dispc_set_irqs();
2796
2797 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2798
2799 return 0;
2800err:
2801 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2802
2803 return ret;
2804}
2805EXPORT_SYMBOL(omap_dispc_register_isr);
2806
2807int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2808{
2809 int i;
2810 unsigned long flags;
2811 int ret = -EINVAL;
2812 struct omap_dispc_isr_data *isr_data;
2813
2814 spin_lock_irqsave(&dispc.irq_lock, flags);
2815
2816 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2817 isr_data = &dispc.registered_isr[i];
2818 if (isr_data->isr != isr || isr_data->arg != arg ||
2819 isr_data->mask != mask)
2820 continue;
2821
2822 /* found the correct isr */
2823
2824 isr_data->isr = NULL;
2825 isr_data->arg = NULL;
2826 isr_data->mask = 0;
2827
2828 ret = 0;
2829 break;
2830 }
2831
2832 if (ret == 0)
2833 _omap_dispc_set_irqs();
2834
2835 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2836
2837 return ret;
2838}
2839EXPORT_SYMBOL(omap_dispc_unregister_isr);
2840
2841#ifdef DEBUG
2842static void print_irq_status(u32 status)
2843{
2844 if ((status & dispc.irq_error_mask) == 0)
2845 return;
2846
2847 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2848
2849#define PIS(x) \
2850 if (status & DISPC_IRQ_##x) \
2851 printk(#x " ");
2852 PIS(GFX_FIFO_UNDERFLOW);
2853 PIS(OCP_ERR);
2854 PIS(VID1_FIFO_UNDERFLOW);
2855 PIS(VID2_FIFO_UNDERFLOW);
2856 PIS(SYNC_LOST);
2857 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2858 if (dss_has_feature(FEAT_MGR_LCD2))
2859 PIS(SYNC_LOST2);
80c39712
TV		 2860#undef PIS
2861
2862 printk("\n");
2863}
2864#endif
2865
2866/* Called from dss.c. Note that we don't touch clocks here,
2867 * but we presume they are on because we got an IRQ. However,
2868 * an irq handler may turn the clocks off, so we may not have
2869 * clock later in the function. */
2870void dispc_irq_handler(void)
2871{
2872 int i;
2873 u32 irqstatus;
2874 u32 handledirqs = 0;
2875 u32 unhandled_errors;
2876 struct omap_dispc_isr_data *isr_data;
2877 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2878
2879 spin_lock(&dispc.irq_lock);
2880
2881 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2882
dfc0fd8d
TV		 2883#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2884 spin_lock(&dispc.irq_stats_lock);
2885 dispc.irq_stats.irq_count++;
2886 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2887 spin_unlock(&dispc.irq_stats_lock);
2888#endif
2889
80c39712
TV		 2890#ifdef DEBUG
2891 if (dss_debug)
2892 print_irq_status(irqstatus);
2893#endif
2894 /* Ack the interrupt. Do it here before clocks are possibly turned
2895 * off */
2896 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2897 /* flush posted write */
2898 dispc_read_reg(DISPC_IRQSTATUS);
2899
2900 /* make a copy and unlock, so that isrs can unregister
2901 * themselves */
2902 memcpy(registered_isr, dispc.registered_isr,
2903 sizeof(registered_isr));
2904
2905 spin_unlock(&dispc.irq_lock);
2906
2907 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2908 isr_data = &registered_isr[i];
2909
2910 if (!isr_data->isr)
2911 continue;
2912
2913 if (isr_data->mask & irqstatus) {
2914 isr_data->isr(isr_data->arg, irqstatus);
2915 handledirqs |= isr_data->mask;
2916 }
2917 }
2918
2919 spin_lock(&dispc.irq_lock);
2920
2921 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2922
2923 if (unhandled_errors) {
2924 dispc.error_irqs |= unhandled_errors;
2925
2926 dispc.irq_error_mask &= ~unhandled_errors;
2927 _omap_dispc_set_irqs();
2928
2929 schedule_work(&dispc.error_work);
2930 }
2931
2932 spin_unlock(&dispc.irq_lock);
2933}
2934
2935static void dispc_error_worker(struct work_struct *work)
2936{
2937 int i;
2938 u32 errors;
2939 unsigned long flags;
2940
2941 spin_lock_irqsave(&dispc.irq_lock, flags);
2942 errors = dispc.error_irqs;
2943 dispc.error_irqs = 0;
2944 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2945
2946 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2947 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2948 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2949 struct omap_overlay *ovl;
2950 ovl = omap_dss_get_overlay(i);
2951
2952 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2953 continue;
2954
2955 if (ovl->id == 0) {
2956 dispc_enable_plane(ovl->id, 0);
2957 dispc_go(ovl->manager->id);
2958 mdelay(50);
2959 break;
2960 }
2961 }
2962 }
2963
2964 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2965 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2966 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2967 struct omap_overlay *ovl;
2968 ovl = omap_dss_get_overlay(i);
2969
2970 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2971 continue;
2972
2973 if (ovl->id == 1) {
2974 dispc_enable_plane(ovl->id, 0);
2975 dispc_go(ovl->manager->id);
2976 mdelay(50);
2977 break;
2978 }
2979 }
2980 }
2981
2982 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2983 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2984 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2985 struct omap_overlay *ovl;
2986 ovl = omap_dss_get_overlay(i);
2987
2988 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2989 continue;
2990
2991 if (ovl->id == 2) {
2992 dispc_enable_plane(ovl->id, 0);
2993 dispc_go(ovl->manager->id);
2994 mdelay(50);
2995 break;
2996 }
2997 }
2998 }
2999
3000 if (errors & DISPC_IRQ_SYNC_LOST) {
3001 struct omap_overlay_manager *manager = NULL;
3002 bool enable = false;
3003
3004 DSSERR("SYNC_LOST, disabling LCD\n");
3005
3006 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3007 struct omap_overlay_manager *mgr;
3008 mgr = omap_dss_get_overlay_manager(i);
3009
3010 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3011 manager = mgr;
3012 enable = mgr->device->state ==
3013 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3014 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3015 break;
3016 }
3017 }
3018
3019 if (manager) {
37ac60e4 3020 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3021 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3022 struct omap_overlay *ovl;
3023 ovl = omap_dss_get_overlay(i);
3024
3025 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3026 continue;
3027
3028 if (ovl->id != 0 && ovl->manager == manager)
3029 dispc_enable_plane(ovl->id, 0);
3030 }
3031
3032 dispc_go(manager->id);
3033 mdelay(50);
3034 if (enable)
37ac60e4 3035 dssdev->driver->enable(dssdev);
80c39712
TV		 3036 }
3037 }
3038
3039 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3040 struct omap_overlay_manager *manager = NULL;
3041 bool enable = false;
3042
3043 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3044
3045 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3046 struct omap_overlay_manager *mgr;
3047 mgr = omap_dss_get_overlay_manager(i);
3048
3049 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3050 manager = mgr;
3051 enable = mgr->device->state ==
3052 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3053 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3054 break;
3055 }
3056 }
3057
3058 if (manager) {
37ac60e4 3059 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3060 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3061 struct omap_overlay *ovl;
3062 ovl = omap_dss_get_overlay(i);
3063
3064 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3065 continue;
3066
3067 if (ovl->id != 0 && ovl->manager == manager)
3068 dispc_enable_plane(ovl->id, 0);
3069 }
3070
3071 dispc_go(manager->id);
3072 mdelay(50);
3073 if (enable)
37ac60e4 3074 dssdev->driver->enable(dssdev);
80c39712
TV		 3075 }
3076 }
3077
2a205f34
SS		 3078 if (errors & DISPC_IRQ_SYNC_LOST2) {
3079 struct omap_overlay_manager *manager = NULL;
3080 bool enable = false;
3081
3082 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3083
3084 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3085 struct omap_overlay_manager *mgr;
3086 mgr = omap_dss_get_overlay_manager(i);
3087
3088 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3089 manager = mgr;
3090 enable = mgr->device->state ==
3091 OMAP_DSS_DISPLAY_ACTIVE;
3092 mgr->device->driver->disable(mgr->device);
3093 break;
3094 }
3095 }
3096
3097 if (manager) {
3098 struct omap_dss_device *dssdev = manager->device;
3099 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3100 struct omap_overlay *ovl;
3101 ovl = omap_dss_get_overlay(i);
3102
3103 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3104 continue;
3105
3106 if (ovl->id != 0 && ovl->manager == manager)
3107 dispc_enable_plane(ovl->id, 0);
3108 }
3109
3110 dispc_go(manager->id);
3111 mdelay(50);
3112 if (enable)
3113 dssdev->driver->enable(dssdev);
3114 }
3115 }
3116
80c39712
TV		 3117 if (errors & DISPC_IRQ_OCP_ERR) {
3118 DSSERR("OCP_ERR\n");
3119 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3120 struct omap_overlay_manager *mgr;
3121 mgr = omap_dss_get_overlay_manager(i);
3122
3123 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3124 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3125 }
3126 }
3127
3128 spin_lock_irqsave(&dispc.irq_lock, flags);
3129 dispc.irq_error_mask |= errors;
3130 _omap_dispc_set_irqs();
3131 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3132}
3133
3134int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3135{
3136 void dispc_irq_wait_handler(void *data, u32 mask)
3137 {
3138 complete((struct completion *)data);
3139 }
3140
3141 int r;
3142 DECLARE_COMPLETION_ONSTACK(completion);
3143
3144 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3145 irqmask);
3146
3147 if (r)
3148 return r;
3149
3150 timeout = wait_for_completion_timeout(&completion, timeout);
3151
3152 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3153
3154 if (timeout == 0)
3155 return -ETIMEDOUT;
3156
3157 if (timeout == -ERESTARTSYS)
3158 return -ERESTARTSYS;
3159
3160 return 0;
3161}
3162
3163int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3164 unsigned long timeout)
3165{
3166 void dispc_irq_wait_handler(void *data, u32 mask)
3167 {
3168 complete((struct completion *)data);
3169 }
3170
3171 int r;
3172 DECLARE_COMPLETION_ONSTACK(completion);
3173
3174 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3175 irqmask);
3176
3177 if (r)
3178 return r;
3179
3180 timeout = wait_for_completion_interruptible_timeout(&completion,
3181 timeout);
3182
3183 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3184
3185 if (timeout == 0)
3186 return -ETIMEDOUT;
3187
3188 if (timeout == -ERESTARTSYS)
3189 return -ERESTARTSYS;
3190
3191 return 0;
3192}
3193
3194#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3195void dispc_fake_vsync_irq(void)
3196{
3197 u32 irqstatus = DISPC_IRQ_VSYNC;
3198 int i;
3199
ab83b14c 3200 WARN_ON(!in_interrupt());
80c39712
TV		 3201
3202 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3203 struct omap_dispc_isr_data *isr_data;
3204 isr_data = &dispc.registered_isr[i];
3205
3206 if (!isr_data->isr)
3207 continue;
3208
3209 if (isr_data->mask & irqstatus)
3210 isr_data->isr(isr_data->arg, irqstatus);
3211 }
80c39712
TV		 3212}
3213#endif
3214
3215static void _omap_dispc_initialize_irq(void)
3216{
3217 unsigned long flags;
3218
3219 spin_lock_irqsave(&dispc.irq_lock, flags);
3220
3221 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3222
3223 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3224 if (dss_has_feature(FEAT_MGR_LCD2))
3225 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3226
3227 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3228 * so clear it */
3229 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3230
3231 _omap_dispc_set_irqs();
3232
3233 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3234}
3235
3236void dispc_enable_sidle(void)
3237{
3238 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3239}
3240
3241void dispc_disable_sidle(void)
3242{
3243 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3244}
3245
3246static void _omap_dispc_initial_config(void)
3247{
3248 u32 l;
3249
3250 l = dispc_read_reg(DISPC_SYSCONFIG);
3251 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3252 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3253 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3254 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3255 dispc_write_reg(DISPC_SYSCONFIG, l);
3256
3257 /* FUNCGATED */
6ced40bf
AT		 3258 if (dss_has_feature(FEAT_FUNCGATED))
3259 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3260
3261 /* L3 firewall setting: enable access to OCM RAM */
3262 /* XXX this should be somewhere in plat-omap */
3263 if (cpu_is_omap24xx())
3264 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3265
3266 _dispc_setup_color_conv_coef();
3267
3268 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3269
3270 dispc_read_plane_fifo_sizes();
3271}
3272
80c39712
TV		 3273int dispc_enable_plane(enum omap_plane plane, bool enable)
3274{
3275 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3276
3277 enable_clocks(1);
3278 _dispc_enable_plane(plane, enable);
3279 enable_clocks(0);
3280
3281 return 0;
3282}
3283
3284int dispc_setup_plane(enum omap_plane plane,
3285 u32 paddr, u16 screen_width,
3286 u16 pos_x, u16 pos_y,
3287 u16 width, u16 height,
3288 u16 out_width, u16 out_height,
3289 enum omap_color_mode color_mode,
3290 bool ilace,
3291 enum omap_dss_rotation_type rotation_type,
fd28a390 3292 u8 rotation, bool mirror, u8 global_alpha,
18faa1b6 3293 u8 pre_mult_alpha, enum omap_channel channel)
80c39712
TV		 3294{
3295 int r = 0;
3296
3297 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
18faa1b6 3298 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3299 plane, paddr, screen_width, pos_x, pos_y,
3300 width, height,
3301 out_width, out_height,
3302 ilace, color_mode,
18faa1b6 3303 rotation, mirror, channel);
80c39712
TV		 3304
3305 enable_clocks(1);
3306
3307 r = _dispc_setup_plane(plane,
3308 paddr, screen_width,
3309 pos_x, pos_y,
3310 width, height,
3311 out_width, out_height,
3312 color_mode, ilace,
3313 rotation_type,
3314 rotation, mirror,
fd28a390 3315 global_alpha,
18faa1b6 3316 pre_mult_alpha, channel);
80c39712
TV		 3317
3318 enable_clocks(0);
3319
3320 return r;
3321}
060b6d9c
SG		 3322
3323/* DISPC HW IP initialisation */
3324static int omap_dispchw_probe(struct platform_device *pdev)
3325{
3326 u32 rev;
3327 dispc.pdev = pdev;
3328
3329 spin_lock_init(&dispc.irq_lock);
3330
3331#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3332 spin_lock_init(&dispc.irq_stats_lock);
3333 dispc.irq_stats.last_reset = jiffies;
3334#endif
3335
3336 INIT_WORK(&dispc.error_work, dispc_error_worker);
3337
3338 dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3339 if (!dispc.base) {
3340 DSSERR("can't ioremap DISPC\n");
3341 return -ENOMEM;
3342 }
3343
3344 enable_clocks(1);
3345
3346 _omap_dispc_initial_config();
3347
3348 _omap_dispc_initialize_irq();
3349
3350 dispc_save_context();
3351
3352 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3353 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3354 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3355
3356 enable_clocks(0);
3357
3358 return 0;
3359}
3360
3361static int omap_dispchw_remove(struct platform_device *pdev)
3362{
3363 iounmap(dispc.base);
3364 return 0;
3365}
3366
3367static struct platform_driver omap_dispchw_driver = {
3368 .probe = omap_dispchw_probe,
3369 .remove = omap_dispchw_remove,
3370 .driver = {
3371 .name = "omapdss_dispc",
3372 .owner = THIS_MODULE,
3373 },
3374};
3375
3376int dispc_init_platform_driver(void)
3377{
3378 return platform_driver_register(&omap_dispchw_driver);
3379}
3380
3381void dispc_uninit_platform_driver(void)
3382{
3383 return platform_driver_unregister(&omap_dispchw_driver);
3384}
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