]>
Commit | Line | Data |
---|---|---|
553c48cf TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dpi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DPI" | |
24 | ||
25 | #include <linux/kernel.h> | |
553c48cf | 26 | #include <linux/delay.h> |
a8a35931 | 27 | #include <linux/export.h> |
8a2cfea8 | 28 | #include <linux/err.h> |
553c48cf | 29 | #include <linux/errno.h> |
8a2cfea8 TV |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
553c48cf | 32 | |
a0b38cc4 | 33 | #include <video/omapdss.h> |
553c48cf TV |
34 | #include <plat/cpu.h> |
35 | ||
36 | #include "dss.h" | |
37 | ||
38 | static struct { | |
8a2cfea8 | 39 | struct regulator *vdds_dsi_reg; |
a72b64b9 | 40 | struct platform_device *dsidev; |
553c48cf TV |
41 | } dpi; |
42 | ||
a72b64b9 AT |
43 | static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk) |
44 | { | |
45 | int dsi_module; | |
46 | ||
47 | dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1; | |
48 | ||
49 | return dsi_get_dsidev_from_id(dsi_module); | |
50 | } | |
51 | ||
7636b3b4 AT |
52 | static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev) |
53 | { | |
54 | if (dssdev->clocks.dispc.dispc_fclk_src == | |
55 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC || | |
5a8b572d AT |
56 | dssdev->clocks.dispc.dispc_fclk_src == |
57 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC || | |
7636b3b4 | 58 | dssdev->clocks.dispc.channel.lcd_clk_src == |
5a8b572d AT |
59 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC || |
60 | dssdev->clocks.dispc.channel.lcd_clk_src == | |
61 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC) | |
7636b3b4 AT |
62 | return true; |
63 | else | |
64 | return false; | |
65 | } | |
66 | ||
ff1b2cde SS |
67 | static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, |
68 | unsigned long pck_req, unsigned long *fck, int *lck_div, | |
69 | int *pck_div) | |
553c48cf TV |
70 | { |
71 | struct dsi_clock_info dsi_cinfo; | |
72 | struct dispc_clock_info dispc_cinfo; | |
73 | int r; | |
74 | ||
a72b64b9 AT |
75 | r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req, |
76 | &dsi_cinfo, &dispc_cinfo); | |
553c48cf TV |
77 | if (r) |
78 | return r; | |
79 | ||
a72b64b9 | 80 | r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo); |
553c48cf TV |
81 | if (r) |
82 | return r; | |
83 | ||
e8881662 | 84 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
553c48cf | 85 | |
26d9dd0d | 86 | r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
5e785091 TV |
87 | if (r) { |
88 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); | |
553c48cf | 89 | return r; |
5e785091 | 90 | } |
553c48cf | 91 | |
1bb47835 | 92 | *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
553c48cf TV |
93 | *lck_div = dispc_cinfo.lck_div; |
94 | *pck_div = dispc_cinfo.pck_div; | |
95 | ||
96 | return 0; | |
97 | } | |
7636b3b4 | 98 | |
ff1b2cde SS |
99 | static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft, |
100 | unsigned long pck_req, unsigned long *fck, int *lck_div, | |
101 | int *pck_div) | |
553c48cf TV |
102 | { |
103 | struct dss_clock_info dss_cinfo; | |
104 | struct dispc_clock_info dispc_cinfo; | |
105 | int r; | |
106 | ||
107 | r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo); | |
108 | if (r) | |
109 | return r; | |
110 | ||
111 | r = dss_set_clock_div(&dss_cinfo); | |
112 | if (r) | |
113 | return r; | |
114 | ||
26d9dd0d | 115 | r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
553c48cf TV |
116 | if (r) |
117 | return r; | |
118 | ||
119 | *fck = dss_cinfo.fck; | |
120 | *lck_div = dispc_cinfo.lck_div; | |
121 | *pck_div = dispc_cinfo.pck_div; | |
122 | ||
123 | return 0; | |
124 | } | |
553c48cf TV |
125 | |
126 | static int dpi_set_mode(struct omap_dss_device *dssdev) | |
127 | { | |
128 | struct omap_video_timings *t = &dssdev->panel.timings; | |
7636b3b4 AT |
129 | int lck_div = 0, pck_div = 0; |
130 | unsigned long fck = 0; | |
553c48cf TV |
131 | unsigned long pck; |
132 | bool is_tft; | |
133 | int r = 0; | |
134 | ||
26d9dd0d | 135 | dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config, |
ff1b2cde | 136 | dssdev->panel.acbi, dssdev->panel.acb); |
553c48cf TV |
137 | |
138 | is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; | |
139 | ||
7636b3b4 AT |
140 | if (dpi_use_dsi_pll(dssdev)) |
141 | r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, | |
142 | &fck, &lck_div, &pck_div); | |
143 | else | |
144 | r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, | |
145 | &fck, &lck_div, &pck_div); | |
553c48cf | 146 | if (r) |
4fbafaf3 | 147 | return r; |
553c48cf TV |
148 | |
149 | pck = fck / lck_div / pck_div / 1000; | |
150 | ||
151 | if (pck != t->pixel_clock) { | |
152 | DSSWARN("Could not find exact pixel clock. " | |
153 | "Requested %d kHz, got %lu kHz\n", | |
154 | t->pixel_clock, pck); | |
155 | ||
156 | t->pixel_clock = pck; | |
157 | } | |
158 | ||
41721163 | 159 | dss_mgr_set_timings(dssdev->manager, t); |
553c48cf | 160 | |
4fbafaf3 | 161 | return 0; |
553c48cf TV |
162 | } |
163 | ||
4fbafaf3 | 164 | static void dpi_basic_init(struct omap_dss_device *dssdev) |
553c48cf TV |
165 | { |
166 | bool is_tft; | |
167 | ||
168 | is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; | |
169 | ||
569969d6 AT |
170 | dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS); |
171 | dispc_mgr_enable_stallmode(dssdev->manager->id, false); | |
172 | ||
26d9dd0d | 173 | dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ? |
64ba4f74 | 174 | OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN); |
26d9dd0d | 175 | dispc_mgr_set_tft_data_lines(dssdev->manager->id, |
64ba4f74 | 176 | dssdev->phy.dpi.data_lines); |
553c48cf TV |
177 | } |
178 | ||
37ac60e4 | 179 | int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) |
553c48cf TV |
180 | { |
181 | int r; | |
182 | ||
40410715 RK |
183 | if (cpu_is_omap34xx() && !dpi.vdds_dsi_reg) { |
184 | DSSERR("no VDSS_DSI regulator\n"); | |
185 | return -ENODEV; | |
186 | } | |
187 | ||
05e1d606 TV |
188 | if (dssdev->manager == NULL) { |
189 | DSSERR("failed to enable display: no manager\n"); | |
190 | return -ENODEV; | |
191 | } | |
192 | ||
553c48cf TV |
193 | r = omap_dss_start_device(dssdev); |
194 | if (r) { | |
195 | DSSERR("failed to start device\n"); | |
4fbafaf3 | 196 | goto err_start_dev; |
553c48cf TV |
197 | } |
198 | ||
8a2cfea8 TV |
199 | if (cpu_is_omap34xx()) { |
200 | r = regulator_enable(dpi.vdds_dsi_reg); | |
201 | if (r) | |
4fbafaf3 | 202 | goto err_reg_enable; |
8a2cfea8 TV |
203 | } |
204 | ||
4fbafaf3 | 205 | r = dispc_runtime_get(); |
553c48cf | 206 | if (r) |
4fbafaf3 TV |
207 | goto err_get_dispc; |
208 | ||
209 | dpi_basic_init(dssdev); | |
553c48cf | 210 | |
7636b3b4 | 211 | if (dpi_use_dsi_pll(dssdev)) { |
4fbafaf3 TV |
212 | r = dsi_runtime_get(dpi.dsidev); |
213 | if (r) | |
214 | goto err_get_dsi; | |
215 | ||
a72b64b9 | 216 | r = dsi_pll_init(dpi.dsidev, 0, 1); |
7636b3b4 | 217 | if (r) |
4fbafaf3 | 218 | goto err_dsi_pll_init; |
7636b3b4 AT |
219 | } |
220 | ||
553c48cf TV |
221 | r = dpi_set_mode(dssdev); |
222 | if (r) | |
4fbafaf3 | 223 | goto err_set_mode; |
553c48cf TV |
224 | |
225 | mdelay(2); | |
226 | ||
33ca237f TV |
227 | r = dss_mgr_enable(dssdev->manager); |
228 | if (r) | |
229 | goto err_mgr_enable; | |
553c48cf | 230 | |
553c48cf TV |
231 | return 0; |
232 | ||
33ca237f | 233 | err_mgr_enable: |
4fbafaf3 | 234 | err_set_mode: |
7636b3b4 | 235 | if (dpi_use_dsi_pll(dssdev)) |
19077a73 | 236 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 TV |
237 | err_dsi_pll_init: |
238 | if (dpi_use_dsi_pll(dssdev)) | |
239 | dsi_runtime_put(dpi.dsidev); | |
240 | err_get_dsi: | |
241 | dispc_runtime_put(); | |
242 | err_get_dispc: | |
8a2cfea8 TV |
243 | if (cpu_is_omap34xx()) |
244 | regulator_disable(dpi.vdds_dsi_reg); | |
4fbafaf3 | 245 | err_reg_enable: |
553c48cf | 246 | omap_dss_stop_device(dssdev); |
4fbafaf3 | 247 | err_start_dev: |
553c48cf TV |
248 | return r; |
249 | } | |
37ac60e4 | 250 | EXPORT_SYMBOL(omapdss_dpi_display_enable); |
553c48cf | 251 | |
37ac60e4 | 252 | void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) |
553c48cf | 253 | { |
7797c6da | 254 | dss_mgr_disable(dssdev->manager); |
553c48cf | 255 | |
7636b3b4 AT |
256 | if (dpi_use_dsi_pll(dssdev)) { |
257 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); | |
a72b64b9 | 258 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 | 259 | dsi_runtime_put(dpi.dsidev); |
7636b3b4 | 260 | } |
553c48cf | 261 | |
4fbafaf3 | 262 | dispc_runtime_put(); |
553c48cf | 263 | |
8a2cfea8 TV |
264 | if (cpu_is_omap34xx()) |
265 | regulator_disable(dpi.vdds_dsi_reg); | |
266 | ||
553c48cf TV |
267 | omap_dss_stop_device(dssdev); |
268 | } | |
37ac60e4 | 269 | EXPORT_SYMBOL(omapdss_dpi_display_disable); |
553c48cf | 270 | |
69b2048f | 271 | void dpi_set_timings(struct omap_dss_device *dssdev, |
553c48cf TV |
272 | struct omap_video_timings *timings) |
273 | { | |
4fbafaf3 TV |
274 | int r; |
275 | ||
553c48cf TV |
276 | DSSDBG("dpi_set_timings\n"); |
277 | dssdev->panel.timings = *timings; | |
278 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
4fbafaf3 | 279 | r = dispc_runtime_get(); |
852f0838 | 280 | if (r) |
4fbafaf3 | 281 | return; |
4fbafaf3 | 282 | |
553c48cf | 283 | dpi_set_mode(dssdev); |
4fbafaf3 TV |
284 | |
285 | dispc_runtime_put(); | |
fcc36619 AT |
286 | } else { |
287 | dss_mgr_set_timings(dssdev->manager, timings); | |
553c48cf TV |
288 | } |
289 | } | |
69b2048f | 290 | EXPORT_SYMBOL(dpi_set_timings); |
553c48cf | 291 | |
69b2048f | 292 | int dpi_check_timings(struct omap_dss_device *dssdev, |
553c48cf TV |
293 | struct omap_video_timings *timings) |
294 | { | |
295 | bool is_tft; | |
296 | int r; | |
297 | int lck_div, pck_div; | |
298 | unsigned long fck; | |
299 | unsigned long pck; | |
7636b3b4 | 300 | struct dispc_clock_info dispc_cinfo; |
553c48cf | 301 | |
b917fa39 | 302 | if (dss_mgr_check_timings(dssdev->manager, timings)) |
553c48cf TV |
303 | return -EINVAL; |
304 | ||
305 | if (timings->pixel_clock == 0) | |
306 | return -EINVAL; | |
307 | ||
308 | is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; | |
309 | ||
7636b3b4 | 310 | if (dpi_use_dsi_pll(dssdev)) { |
553c48cf | 311 | struct dsi_clock_info dsi_cinfo; |
a72b64b9 | 312 | r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, |
553c48cf TV |
313 | timings->pixel_clock * 1000, |
314 | &dsi_cinfo, &dispc_cinfo); | |
315 | ||
316 | if (r) | |
317 | return r; | |
318 | ||
1bb47835 | 319 | fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
7636b3b4 | 320 | } else { |
553c48cf | 321 | struct dss_clock_info dss_cinfo; |
553c48cf TV |
322 | r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000, |
323 | &dss_cinfo, &dispc_cinfo); | |
324 | ||
325 | if (r) | |
326 | return r; | |
327 | ||
328 | fck = dss_cinfo.fck; | |
553c48cf | 329 | } |
7636b3b4 AT |
330 | |
331 | lck_div = dispc_cinfo.lck_div; | |
332 | pck_div = dispc_cinfo.pck_div; | |
553c48cf TV |
333 | |
334 | pck = fck / lck_div / pck_div / 1000; | |
335 | ||
336 | timings->pixel_clock = pck; | |
337 | ||
338 | return 0; | |
339 | } | |
69b2048f | 340 | EXPORT_SYMBOL(dpi_check_timings); |
553c48cf | 341 | |
553c48cf TV |
342 | int dpi_init_display(struct omap_dss_device *dssdev) |
343 | { | |
344 | DSSDBG("init_display\n"); | |
345 | ||
5f42f2ce TV |
346 | if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) { |
347 | struct regulator *vdds_dsi; | |
553c48cf | 348 | |
5f42f2ce TV |
349 | vdds_dsi = dss_get_vdds_dsi(); |
350 | ||
351 | if (IS_ERR(vdds_dsi)) { | |
8a2cfea8 | 352 | DSSERR("can't get VDDS_DSI regulator\n"); |
5f42f2ce | 353 | return PTR_ERR(vdds_dsi); |
8a2cfea8 | 354 | } |
5f42f2ce TV |
355 | |
356 | dpi.vdds_dsi_reg = vdds_dsi; | |
8a2cfea8 TV |
357 | } |
358 | ||
a72b64b9 AT |
359 | if (dpi_use_dsi_pll(dssdev)) { |
360 | enum omap_dss_clk_source dispc_fclk_src = | |
361 | dssdev->clocks.dispc.dispc_fclk_src; | |
362 | dpi.dsidev = dpi_get_dsidev(dispc_fclk_src); | |
363 | } | |
364 | ||
553c48cf TV |
365 | return 0; |
366 | } | |
367 | ||
6e7e8f06 | 368 | static int __init omap_dpi_probe(struct platform_device *pdev) |
5f42f2ce TV |
369 | { |
370 | return 0; | |
371 | } | |
372 | ||
6e7e8f06 | 373 | static int __exit omap_dpi_remove(struct platform_device *pdev) |
553c48cf | 374 | { |
a57dd4fe | 375 | return 0; |
553c48cf TV |
376 | } |
377 | ||
a57dd4fe | 378 | static struct platform_driver omap_dpi_driver = { |
6e7e8f06 | 379 | .remove = __exit_p(omap_dpi_remove), |
a57dd4fe TV |
380 | .driver = { |
381 | .name = "omapdss_dpi", | |
382 | .owner = THIS_MODULE, | |
383 | }, | |
384 | }; | |
385 | ||
6e7e8f06 | 386 | int __init dpi_init_platform_driver(void) |
a57dd4fe | 387 | { |
61055d4b | 388 | return platform_driver_probe(&omap_dpi_driver, omap_dpi_probe); |
a57dd4fe TV |
389 | } |
390 | ||
6e7e8f06 | 391 | void __exit dpi_uninit_platform_driver(void) |
a57dd4fe TV |
392 | { |
393 | platform_driver_unregister(&omap_dpi_driver); | |
394 | } |