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3de7a1dc TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dsi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "DSI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
355b200b | 30 | #include <linux/module.h> |
b9eb5d7d | 31 | #include <linux/semaphore.h> |
3de7a1dc TV |
32 | #include <linux/seq_file.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 35 | #include <linux/wait.h> |
18946f62 | 36 | #include <linux/workqueue.h> |
40885ab3 | 37 | #include <linux/sched.h> |
f1da39d9 | 38 | #include <linux/slab.h> |
5a8b572d | 39 | #include <linux/debugfs.h> |
4fbafaf3 | 40 | #include <linux/pm_runtime.h> |
3de7a1dc | 41 | |
a0b38cc4 | 42 | #include <video/omapdss.h> |
7a7c48f9 | 43 | #include <video/mipi_display.h> |
3de7a1dc TV |
44 | #include <plat/clock.h> |
45 | ||
46 | #include "dss.h" | |
819d807c | 47 | #include "dss_features.h" |
3de7a1dc TV |
48 | |
49 | /*#define VERBOSE_IRQ*/ | |
50 | #define DSI_CATCH_MISSING_TE | |
51 | ||
3de7a1dc TV |
52 | struct dsi_reg { u16 idx; }; |
53 | ||
54 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) | |
55 | ||
56 | #define DSI_SZ_REGS SZ_1K | |
57 | /* DSI Protocol Engine */ | |
58 | ||
59 | #define DSI_REVISION DSI_REG(0x0000) | |
60 | #define DSI_SYSCONFIG DSI_REG(0x0010) | |
61 | #define DSI_SYSSTATUS DSI_REG(0x0014) | |
62 | #define DSI_IRQSTATUS DSI_REG(0x0018) | |
63 | #define DSI_IRQENABLE DSI_REG(0x001C) | |
64 | #define DSI_CTRL DSI_REG(0x0040) | |
75d7247c | 65 | #define DSI_GNQ DSI_REG(0x0044) |
3de7a1dc TV |
66 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
67 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) | |
68 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) | |
69 | #define DSI_CLK_CTRL DSI_REG(0x0054) | |
70 | #define DSI_TIMING1 DSI_REG(0x0058) | |
71 | #define DSI_TIMING2 DSI_REG(0x005C) | |
72 | #define DSI_VM_TIMING1 DSI_REG(0x0060) | |
73 | #define DSI_VM_TIMING2 DSI_REG(0x0064) | |
74 | #define DSI_VM_TIMING3 DSI_REG(0x0068) | |
75 | #define DSI_CLK_TIMING DSI_REG(0x006C) | |
76 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) | |
77 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) | |
78 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) | |
79 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) | |
80 | #define DSI_VM_TIMING4 DSI_REG(0x0080) | |
81 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) | |
82 | #define DSI_VM_TIMING5 DSI_REG(0x0088) | |
83 | #define DSI_VM_TIMING6 DSI_REG(0x008C) | |
84 | #define DSI_VM_TIMING7 DSI_REG(0x0090) | |
85 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) | |
86 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) | |
87 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) | |
88 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) | |
89 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) | |
90 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) | |
91 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) | |
92 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) | |
93 | ||
94 | /* DSIPHY_SCP */ | |
95 | ||
96 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) | |
97 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) | |
98 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) | |
99 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) | |
0a0ee46b | 100 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
3de7a1dc TV |
101 | |
102 | /* DSI_PLL_CTRL_SCP */ | |
103 | ||
104 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) | |
105 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) | |
106 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) | |
107 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) | |
108 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) | |
109 | ||
a72b64b9 AT |
110 | #define REG_GET(dsidev, idx, start, end) \ |
111 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | |
3de7a1dc | 112 | |
a72b64b9 AT |
113 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
114 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) | |
3de7a1dc TV |
115 | |
116 | /* Global interrupts */ | |
117 | #define DSI_IRQ_VC0 (1 << 0) | |
118 | #define DSI_IRQ_VC1 (1 << 1) | |
119 | #define DSI_IRQ_VC2 (1 << 2) | |
120 | #define DSI_IRQ_VC3 (1 << 3) | |
121 | #define DSI_IRQ_WAKEUP (1 << 4) | |
122 | #define DSI_IRQ_RESYNC (1 << 5) | |
123 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
124 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
125 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
126 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
127 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
128 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
129 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
130 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
131 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
132 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
133 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
134 | #define DSI_IRQ_ERROR_MASK \ | |
135 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
8af6ff01 | 136 | DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) |
3de7a1dc TV |
137 | #define DSI_IRQ_CHANNEL_MASK 0xf |
138 | ||
139 | /* Virtual channel interrupts */ | |
140 | #define DSI_VC_IRQ_CS (1 << 0) | |
141 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
142 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
143 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
144 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
145 | #define DSI_VC_IRQ_BTA (1 << 5) | |
146 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
147 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
148 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
149 | #define DSI_VC_IRQ_ERROR_MASK \ | |
150 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
151 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
152 | DSI_VC_IRQ_FIFO_TX_UDF) | |
153 | ||
154 | /* ComplexIO interrupts */ | |
155 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
156 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
157 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
6705615e TV |
158 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
159 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
3de7a1dc TV |
160 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
161 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
162 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
6705615e TV |
163 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
164 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
3de7a1dc TV |
165 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
166 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
167 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
6705615e TV |
168 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
169 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
3de7a1dc TV |
170 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
171 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
172 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
6705615e TV |
173 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
174 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
3de7a1dc TV |
175 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
180 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
6705615e TV |
181 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
182 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
183 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
184 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
3de7a1dc TV |
185 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
186 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
187 | #define DSI_CIO_IRQ_ERROR_MASK \ |
188 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
6705615e TV |
189 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
190 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
191 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
192 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
193 | DSI_CIO_IRQ_ERRESC5 | \ | |
194 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
195 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
196 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
bbecb50b TV |
197 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
198 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
6705615e TV |
199 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
200 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
201 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
3de7a1dc | 202 | |
4ae2dddd TV |
203 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
204 | ||
205 | #define DSI_MAX_NR_ISRS 2 | |
206 | ||
207 | struct dsi_isr_data { | |
208 | omap_dsi_isr_t isr; | |
209 | void *arg; | |
210 | u32 mask; | |
211 | }; | |
212 | ||
3de7a1dc TV |
213 | enum fifo_size { |
214 | DSI_FIFO_SIZE_0 = 0, | |
215 | DSI_FIFO_SIZE_32 = 1, | |
216 | DSI_FIFO_SIZE_64 = 2, | |
217 | DSI_FIFO_SIZE_96 = 3, | |
218 | DSI_FIFO_SIZE_128 = 4, | |
219 | }; | |
220 | ||
d6049144 AT |
221 | enum dsi_vc_source { |
222 | DSI_VC_SOURCE_L4 = 0, | |
223 | DSI_VC_SOURCE_VP, | |
3de7a1dc TV |
224 | }; |
225 | ||
0a0ee46b TV |
226 | enum dsi_lane { |
227 | DSI_CLK_P = 1 << 0, | |
228 | DSI_CLK_N = 1 << 1, | |
229 | DSI_DATA1_P = 1 << 2, | |
230 | DSI_DATA1_N = 1 << 3, | |
231 | DSI_DATA2_P = 1 << 4, | |
232 | DSI_DATA2_N = 1 << 5, | |
75d7247c AT |
233 | DSI_DATA3_P = 1 << 6, |
234 | DSI_DATA3_N = 1 << 7, | |
235 | DSI_DATA4_P = 1 << 8, | |
236 | DSI_DATA4_N = 1 << 9, | |
0a0ee46b TV |
237 | }; |
238 | ||
3de7a1dc | 239 | struct dsi_update_region { |
3de7a1dc TV |
240 | u16 x, y, w, h; |
241 | struct omap_dss_device *device; | |
242 | }; | |
243 | ||
dfc0fd8d TV |
244 | struct dsi_irq_stats { |
245 | unsigned long last_reset; | |
246 | unsigned irq_count; | |
247 | unsigned dsi_irqs[32]; | |
248 | unsigned vc_irqs[4][32]; | |
249 | unsigned cio_irqs[32]; | |
250 | }; | |
251 | ||
4ae2dddd TV |
252 | struct dsi_isr_tables { |
253 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
254 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
255 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
256 | }; | |
257 | ||
f1da39d9 | 258 | struct dsi_data { |
c8aac01b | 259 | struct platform_device *pdev; |
3de7a1dc | 260 | void __iomem *base; |
4fbafaf3 | 261 | |
affe360d | 262 | int irq; |
3de7a1dc | 263 | |
4fbafaf3 TV |
264 | struct clk *dss_clk; |
265 | struct clk *sys_clk; | |
266 | ||
5bc416cb TV |
267 | int (*enable_pads)(int dsi_id, unsigned lane_mask); |
268 | void (*disable_pads)(int dsi_id, unsigned lane_mask); | |
d1f5857e | 269 | |
3de7a1dc TV |
270 | struct dsi_clock_info current_cinfo; |
271 | ||
2a89dc15 | 272 | bool vdds_dsi_enabled; |
3de7a1dc TV |
273 | struct regulator *vdds_dsi_reg; |
274 | ||
275 | struct { | |
d6049144 | 276 | enum dsi_vc_source source; |
3de7a1dc TV |
277 | struct omap_dss_device *dssdev; |
278 | enum fifo_size fifo_size; | |
5ee3c144 | 279 | int vc_id; |
3de7a1dc TV |
280 | } vc[4]; |
281 | ||
282 | struct mutex lock; | |
b9eb5d7d | 283 | struct semaphore bus_lock; |
3de7a1dc TV |
284 | |
285 | unsigned pll_locked; | |
286 | ||
4ae2dddd TV |
287 | spinlock_t irq_lock; |
288 | struct dsi_isr_tables isr_tables; | |
289 | /* space for a copy used by the interrupt handler */ | |
290 | struct dsi_isr_tables isr_tables_copy; | |
291 | ||
18946f62 | 292 | int update_channel; |
3de7a1dc | 293 | struct dsi_update_region update_region; |
3de7a1dc | 294 | |
3de7a1dc | 295 | bool te_enabled; |
40885ab3 | 296 | bool ulps_enabled; |
3de7a1dc | 297 | |
18946f62 TV |
298 | void (*framedone_callback)(int, void *); |
299 | void *framedone_data; | |
300 | ||
301 | struct delayed_work framedone_timeout_work; | |
302 | ||
3de7a1dc TV |
303 | #ifdef DSI_CATCH_MISSING_TE |
304 | struct timer_list te_timer; | |
305 | #endif | |
306 | ||
307 | unsigned long cache_req_pck; | |
308 | unsigned long cache_clk_freq; | |
309 | struct dsi_clock_info cache_cinfo; | |
310 | ||
311 | u32 errors; | |
312 | spinlock_t errors_lock; | |
313 | #ifdef DEBUG | |
314 | ktime_t perf_setup_time; | |
315 | ktime_t perf_start_time; | |
3de7a1dc TV |
316 | #endif |
317 | int debug_read; | |
318 | int debug_write; | |
dfc0fd8d TV |
319 | |
320 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
321 | spinlock_t irq_stats_lock; | |
322 | struct dsi_irq_stats irq_stats; | |
323 | #endif | |
49641116 AT |
324 | /* DSI PLL Parameter Ranges */ |
325 | unsigned long regm_max, regn_max; | |
326 | unsigned long regm_dispc_max, regm_dsi_max; | |
327 | unsigned long fint_min, fint_max; | |
328 | unsigned long lpdiv_max; | |
24c1ae41 | 329 | |
75d7247c AT |
330 | int num_data_lanes; |
331 | ||
24c1ae41 | 332 | unsigned scp_clk_refcount; |
f1da39d9 | 333 | }; |
3de7a1dc | 334 | |
2e868dbe AT |
335 | struct dsi_packet_sent_handler_data { |
336 | struct platform_device *dsidev; | |
337 | struct completion *completion; | |
338 | }; | |
339 | ||
a72b64b9 AT |
340 | static struct platform_device *dsi_pdev_map[MAX_NUM_DSI]; |
341 | ||
3de7a1dc | 342 | #ifdef DEBUG |
90ab5ee9 RR |
343 | static bool dsi_perf; |
344 | module_param(dsi_perf, bool, 0644); | |
3de7a1dc TV |
345 | #endif |
346 | ||
f1da39d9 AT |
347 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
348 | { | |
349 | return dev_get_drvdata(&dsidev->dev); | |
350 | } | |
351 | ||
a72b64b9 AT |
352 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
353 | { | |
354 | return dsi_pdev_map[dssdev->phy.dsi.module]; | |
355 | } | |
356 | ||
357 | struct platform_device *dsi_get_dsidev_from_id(int module) | |
358 | { | |
359 | return dsi_pdev_map[module]; | |
360 | } | |
361 | ||
7c68dd96 | 362 | static inline int dsi_get_dsidev_id(struct platform_device *dsidev) |
f1da39d9 | 363 | { |
7c68dd96 | 364 | return dsidev->id; |
f1da39d9 AT |
365 | } |
366 | ||
a72b64b9 AT |
367 | static inline void dsi_write_reg(struct platform_device *dsidev, |
368 | const struct dsi_reg idx, u32 val) | |
3de7a1dc | 369 | { |
f1da39d9 AT |
370 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
371 | ||
372 | __raw_writel(val, dsi->base + idx.idx); | |
3de7a1dc TV |
373 | } |
374 | ||
a72b64b9 AT |
375 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
376 | const struct dsi_reg idx) | |
3de7a1dc | 377 | { |
f1da39d9 AT |
378 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
379 | ||
380 | return __raw_readl(dsi->base + idx.idx); | |
3de7a1dc TV |
381 | } |
382 | ||
1ffefe75 | 383 | void dsi_bus_lock(struct omap_dss_device *dssdev) |
3de7a1dc | 384 | { |
f1da39d9 AT |
385 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
386 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
387 | ||
388 | down(&dsi->bus_lock); | |
3de7a1dc TV |
389 | } |
390 | EXPORT_SYMBOL(dsi_bus_lock); | |
391 | ||
1ffefe75 | 392 | void dsi_bus_unlock(struct omap_dss_device *dssdev) |
3de7a1dc | 393 | { |
f1da39d9 AT |
394 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
395 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
396 | ||
397 | up(&dsi->bus_lock); | |
3de7a1dc TV |
398 | } |
399 | EXPORT_SYMBOL(dsi_bus_unlock); | |
400 | ||
a72b64b9 | 401 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
4f765023 | 402 | { |
f1da39d9 AT |
403 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
404 | ||
405 | return dsi->bus_lock.count == 0; | |
4f765023 TV |
406 | } |
407 | ||
f36a06e7 TV |
408 | static void dsi_completion_handler(void *data, u32 mask) |
409 | { | |
410 | complete((struct completion *)data); | |
411 | } | |
412 | ||
a72b64b9 AT |
413 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
414 | const struct dsi_reg idx, int bitnum, int value) | |
3de7a1dc TV |
415 | { |
416 | int t = 100000; | |
417 | ||
a72b64b9 | 418 | while (REG_GET(dsidev, idx, bitnum, bitnum) != value) { |
3de7a1dc TV |
419 | if (--t == 0) |
420 | return !value; | |
421 | } | |
422 | ||
423 | return value; | |
424 | } | |
425 | ||
a3b3cc2b AT |
426 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
427 | { | |
428 | switch (fmt) { | |
429 | case OMAP_DSS_DSI_FMT_RGB888: | |
430 | case OMAP_DSS_DSI_FMT_RGB666: | |
431 | return 24; | |
432 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
433 | return 18; | |
434 | case OMAP_DSS_DSI_FMT_RGB565: | |
435 | return 16; | |
436 | default: | |
437 | BUG(); | |
438 | } | |
439 | } | |
440 | ||
3de7a1dc | 441 | #ifdef DEBUG |
a72b64b9 | 442 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
3de7a1dc | 443 | { |
f1da39d9 AT |
444 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
445 | dsi->perf_setup_time = ktime_get(); | |
3de7a1dc TV |
446 | } |
447 | ||
a72b64b9 | 448 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
3de7a1dc | 449 | { |
f1da39d9 AT |
450 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
451 | dsi->perf_start_time = ktime_get(); | |
3de7a1dc TV |
452 | } |
453 | ||
a72b64b9 | 454 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
3de7a1dc | 455 | { |
f1da39d9 | 456 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a3b3cc2b | 457 | struct omap_dss_device *dssdev = dsi->update_region.device; |
3de7a1dc TV |
458 | ktime_t t, setup_time, trans_time; |
459 | u32 total_bytes; | |
460 | u32 setup_us, trans_us, total_us; | |
461 | ||
462 | if (!dsi_perf) | |
463 | return; | |
464 | ||
3de7a1dc TV |
465 | t = ktime_get(); |
466 | ||
f1da39d9 | 467 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
3de7a1dc TV |
468 | setup_us = (u32)ktime_to_us(setup_time); |
469 | if (setup_us == 0) | |
470 | setup_us = 1; | |
471 | ||
f1da39d9 | 472 | trans_time = ktime_sub(t, dsi->perf_start_time); |
3de7a1dc TV |
473 | trans_us = (u32)ktime_to_us(trans_time); |
474 | if (trans_us == 0) | |
475 | trans_us = 1; | |
476 | ||
477 | total_us = setup_us + trans_us; | |
478 | ||
f1da39d9 AT |
479 | total_bytes = dsi->update_region.w * |
480 | dsi->update_region.h * | |
a3b3cc2b | 481 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
3de7a1dc | 482 | |
1bbb275e TV |
483 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
484 | "%u bytes, %u kbytes/sec\n", | |
485 | name, | |
486 | setup_us, | |
487 | trans_us, | |
488 | total_us, | |
489 | 1000*1000 / total_us, | |
490 | total_bytes, | |
491 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
492 | } |
493 | #else | |
4a9a5e39 TV |
494 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
495 | { | |
496 | } | |
497 | ||
498 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) | |
499 | { | |
500 | } | |
501 | ||
502 | static inline void dsi_perf_show(struct platform_device *dsidev, | |
503 | const char *name) | |
504 | { | |
505 | } | |
3de7a1dc TV |
506 | #endif |
507 | ||
508 | static void print_irq_status(u32 status) | |
509 | { | |
d80d499e TV |
510 | if (status == 0) |
511 | return; | |
512 | ||
3de7a1dc TV |
513 | #ifndef VERBOSE_IRQ |
514 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) | |
515 | return; | |
516 | #endif | |
517 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); | |
518 | ||
519 | #define PIS(x) \ | |
520 | if (status & DSI_IRQ_##x) \ | |
521 | printk(#x " "); | |
522 | #ifdef VERBOSE_IRQ | |
523 | PIS(VC0); | |
524 | PIS(VC1); | |
525 | PIS(VC2); | |
526 | PIS(VC3); | |
527 | #endif | |
528 | PIS(WAKEUP); | |
529 | PIS(RESYNC); | |
530 | PIS(PLL_LOCK); | |
531 | PIS(PLL_UNLOCK); | |
532 | PIS(PLL_RECALL); | |
533 | PIS(COMPLEXIO_ERR); | |
534 | PIS(HS_TX_TIMEOUT); | |
535 | PIS(LP_RX_TIMEOUT); | |
536 | PIS(TE_TRIGGER); | |
537 | PIS(ACK_TRIGGER); | |
538 | PIS(SYNC_LOST); | |
539 | PIS(LDO_POWER_GOOD); | |
540 | PIS(TA_TIMEOUT); | |
541 | #undef PIS | |
542 | ||
543 | printk("\n"); | |
544 | } | |
545 | ||
546 | static void print_irq_status_vc(int channel, u32 status) | |
547 | { | |
d80d499e TV |
548 | if (status == 0) |
549 | return; | |
550 | ||
3de7a1dc TV |
551 | #ifndef VERBOSE_IRQ |
552 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) | |
553 | return; | |
554 | #endif | |
555 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); | |
556 | ||
557 | #define PIS(x) \ | |
558 | if (status & DSI_VC_IRQ_##x) \ | |
559 | printk(#x " "); | |
560 | PIS(CS); | |
561 | PIS(ECC_CORR); | |
562 | #ifdef VERBOSE_IRQ | |
563 | PIS(PACKET_SENT); | |
564 | #endif | |
565 | PIS(FIFO_TX_OVF); | |
566 | PIS(FIFO_RX_OVF); | |
567 | PIS(BTA); | |
568 | PIS(ECC_NO_CORR); | |
569 | PIS(FIFO_TX_UDF); | |
570 | PIS(PP_BUSY_CHANGE); | |
571 | #undef PIS | |
572 | printk("\n"); | |
573 | } | |
574 | ||
575 | static void print_irq_status_cio(u32 status) | |
576 | { | |
d80d499e TV |
577 | if (status == 0) |
578 | return; | |
579 | ||
3de7a1dc TV |
580 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
581 | ||
582 | #define PIS(x) \ | |
583 | if (status & DSI_CIO_IRQ_##x) \ | |
584 | printk(#x " "); | |
585 | PIS(ERRSYNCESC1); | |
586 | PIS(ERRSYNCESC2); | |
587 | PIS(ERRSYNCESC3); | |
588 | PIS(ERRESC1); | |
589 | PIS(ERRESC2); | |
590 | PIS(ERRESC3); | |
591 | PIS(ERRCONTROL1); | |
592 | PIS(ERRCONTROL2); | |
593 | PIS(ERRCONTROL3); | |
594 | PIS(STATEULPS1); | |
595 | PIS(STATEULPS2); | |
596 | PIS(STATEULPS3); | |
597 | PIS(ERRCONTENTIONLP0_1); | |
598 | PIS(ERRCONTENTIONLP1_1); | |
599 | PIS(ERRCONTENTIONLP0_2); | |
600 | PIS(ERRCONTENTIONLP1_2); | |
601 | PIS(ERRCONTENTIONLP0_3); | |
602 | PIS(ERRCONTENTIONLP1_3); | |
603 | PIS(ULPSACTIVENOT_ALL0); | |
604 | PIS(ULPSACTIVENOT_ALL1); | |
605 | #undef PIS | |
606 | ||
607 | printk("\n"); | |
608 | } | |
609 | ||
69b281a6 | 610 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
a72b64b9 AT |
611 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
612 | u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 613 | { |
f1da39d9 | 614 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
615 | int i; |
616 | ||
f1da39d9 | 617 | spin_lock(&dsi->irq_stats_lock); |
69b281a6 | 618 | |
f1da39d9 AT |
619 | dsi->irq_stats.irq_count++; |
620 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
69b281a6 TV |
621 | |
622 | for (i = 0; i < 4; ++i) | |
f1da39d9 | 623 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
69b281a6 | 624 | |
f1da39d9 | 625 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
69b281a6 | 626 | |
f1da39d9 | 627 | spin_unlock(&dsi->irq_stats_lock); |
69b281a6 TV |
628 | } |
629 | #else | |
a72b64b9 | 630 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
dfc0fd8d TV |
631 | #endif |
632 | ||
69b281a6 TV |
633 | static int debug_irq; |
634 | ||
a72b64b9 AT |
635 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
636 | u32 *vcstatus, u32 ciostatus) | |
69b281a6 | 637 | { |
f1da39d9 | 638 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
69b281a6 TV |
639 | int i; |
640 | ||
3de7a1dc TV |
641 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
642 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
643 | print_irq_status(irqstatus); | |
f1da39d9 AT |
644 | spin_lock(&dsi->errors_lock); |
645 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
646 | spin_unlock(&dsi->errors_lock); | |
3de7a1dc TV |
647 | } else if (debug_irq) { |
648 | print_irq_status(irqstatus); | |
649 | } | |
650 | ||
3de7a1dc | 651 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
652 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
653 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
654 | i, vcstatus[i]); | |
655 | print_irq_status_vc(i, vcstatus[i]); | |
656 | } else if (debug_irq) { | |
657 | print_irq_status_vc(i, vcstatus[i]); | |
658 | } | |
659 | } | |
3de7a1dc | 660 | |
69b281a6 TV |
661 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
662 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
663 | print_irq_status_cio(ciostatus); | |
664 | } else if (debug_irq) { | |
665 | print_irq_status_cio(ciostatus); | |
666 | } | |
667 | } | |
3de7a1dc | 668 | |
4ae2dddd TV |
669 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
670 | unsigned isr_array_size, u32 irqstatus) | |
671 | { | |
672 | struct dsi_isr_data *isr_data; | |
673 | int i; | |
674 | ||
675 | for (i = 0; i < isr_array_size; i++) { | |
676 | isr_data = &isr_array[i]; | |
677 | if (isr_data->isr && isr_data->mask & irqstatus) | |
678 | isr_data->isr(isr_data->arg, irqstatus); | |
679 | } | |
680 | } | |
681 | ||
682 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
683 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
684 | { | |
685 | int i; | |
686 | ||
687 | dsi_call_isrs(isr_tables->isr_table, | |
688 | ARRAY_SIZE(isr_tables->isr_table), | |
689 | irqstatus); | |
690 | ||
691 | for (i = 0; i < 4; ++i) { | |
692 | if (vcstatus[i] == 0) | |
693 | continue; | |
694 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
695 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
696 | vcstatus[i]); | |
697 | } | |
698 | ||
699 | if (ciostatus != 0) | |
700 | dsi_call_isrs(isr_tables->isr_table_cio, | |
701 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
702 | ciostatus); | |
703 | } | |
704 | ||
69b281a6 TV |
705 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
706 | { | |
a72b64b9 | 707 | struct platform_device *dsidev; |
f1da39d9 | 708 | struct dsi_data *dsi; |
69b281a6 TV |
709 | u32 irqstatus, vcstatus[4], ciostatus; |
710 | int i; | |
dfc0fd8d | 711 | |
a72b64b9 | 712 | dsidev = (struct platform_device *) arg; |
f1da39d9 | 713 | dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 714 | |
f1da39d9 | 715 | spin_lock(&dsi->irq_lock); |
4ae2dddd | 716 | |
a72b64b9 | 717 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
3de7a1dc | 718 | |
69b281a6 | 719 | /* IRQ is not for us */ |
4ae2dddd | 720 | if (!irqstatus) { |
f1da39d9 | 721 | spin_unlock(&dsi->irq_lock); |
69b281a6 | 722 | return IRQ_NONE; |
4ae2dddd | 723 | } |
ab83b14c | 724 | |
a72b64b9 | 725 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
69b281a6 | 726 | /* flush posted write */ |
a72b64b9 | 727 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
69b281a6 TV |
728 | |
729 | for (i = 0; i < 4; ++i) { | |
730 | if ((irqstatus & (1 << i)) == 0) { | |
731 | vcstatus[i] = 0; | |
732 | continue; | |
3de7a1dc TV |
733 | } |
734 | ||
a72b64b9 | 735 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
69b281a6 | 736 | |
a72b64b9 | 737 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
3de7a1dc | 738 | /* flush posted write */ |
a72b64b9 | 739 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
3de7a1dc TV |
740 | } |
741 | ||
742 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
a72b64b9 | 743 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
3de7a1dc | 744 | |
a72b64b9 | 745 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
3de7a1dc | 746 | /* flush posted write */ |
a72b64b9 | 747 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
69b281a6 TV |
748 | } else { |
749 | ciostatus = 0; | |
750 | } | |
3de7a1dc | 751 | |
69b281a6 TV |
752 | #ifdef DSI_CATCH_MISSING_TE |
753 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
f1da39d9 | 754 | del_timer(&dsi->te_timer); |
69b281a6 TV |
755 | #endif |
756 | ||
4ae2dddd TV |
757 | /* make a copy and unlock, so that isrs can unregister |
758 | * themselves */ | |
f1da39d9 AT |
759 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
760 | sizeof(dsi->isr_tables)); | |
4ae2dddd | 761 | |
f1da39d9 | 762 | spin_unlock(&dsi->irq_lock); |
4ae2dddd | 763 | |
f1da39d9 | 764 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
4ae2dddd | 765 | |
a72b64b9 | 766 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
69b281a6 | 767 | |
a72b64b9 | 768 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
dfc0fd8d | 769 | |
affe360d | 770 | return IRQ_HANDLED; |
3de7a1dc TV |
771 | } |
772 | ||
f1da39d9 | 773 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 AT |
774 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
775 | struct dsi_isr_data *isr_array, | |
4ae2dddd TV |
776 | unsigned isr_array_size, u32 default_mask, |
777 | const struct dsi_reg enable_reg, | |
778 | const struct dsi_reg status_reg) | |
3de7a1dc | 779 | { |
4ae2dddd TV |
780 | struct dsi_isr_data *isr_data; |
781 | u32 mask; | |
782 | u32 old_mask; | |
3de7a1dc TV |
783 | int i; |
784 | ||
4ae2dddd | 785 | mask = default_mask; |
3de7a1dc | 786 | |
4ae2dddd TV |
787 | for (i = 0; i < isr_array_size; i++) { |
788 | isr_data = &isr_array[i]; | |
3de7a1dc | 789 | |
4ae2dddd TV |
790 | if (isr_data->isr == NULL) |
791 | continue; | |
792 | ||
793 | mask |= isr_data->mask; | |
3de7a1dc TV |
794 | } |
795 | ||
a72b64b9 | 796 | old_mask = dsi_read_reg(dsidev, enable_reg); |
4ae2dddd | 797 | /* clear the irqstatus for newly enabled irqs */ |
a72b64b9 AT |
798 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
799 | dsi_write_reg(dsidev, enable_reg, mask); | |
4ae2dddd TV |
800 | |
801 | /* flush posted writes */ | |
a72b64b9 AT |
802 | dsi_read_reg(dsidev, enable_reg); |
803 | dsi_read_reg(dsidev, status_reg); | |
4ae2dddd | 804 | } |
3de7a1dc | 805 | |
f1da39d9 | 806 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 807 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
4ae2dddd | 808 | { |
f1da39d9 | 809 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd | 810 | u32 mask = DSI_IRQ_ERROR_MASK; |
3de7a1dc | 811 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 812 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 813 | #endif |
f1da39d9 AT |
814 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
815 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, | |
4ae2dddd TV |
816 | DSI_IRQENABLE, DSI_IRQSTATUS); |
817 | } | |
3de7a1dc | 818 | |
f1da39d9 | 819 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 820 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
4ae2dddd | 821 | { |
f1da39d9 AT |
822 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
823 | ||
824 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], | |
825 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), | |
4ae2dddd TV |
826 | DSI_VC_IRQ_ERROR_MASK, |
827 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
828 | } | |
829 | ||
f1da39d9 | 830 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 831 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
4ae2dddd | 832 | { |
f1da39d9 AT |
833 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
834 | ||
835 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, | |
836 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), | |
4ae2dddd TV |
837 | DSI_CIO_IRQ_ERROR_MASK, |
838 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
839 | } | |
840 | ||
a72b64b9 | 841 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
4ae2dddd | 842 | { |
f1da39d9 | 843 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
844 | unsigned long flags; |
845 | int vc; | |
846 | ||
f1da39d9 | 847 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 848 | |
f1da39d9 | 849 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
4ae2dddd | 850 | |
a72b64b9 | 851 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 852 | for (vc = 0; vc < 4; ++vc) |
a72b64b9 AT |
853 | _omap_dsi_set_irqs_vc(dsidev, vc); |
854 | _omap_dsi_set_irqs_cio(dsidev); | |
4ae2dddd | 855 | |
f1da39d9 | 856 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd | 857 | } |
3de7a1dc | 858 | |
4ae2dddd TV |
859 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
860 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
861 | { | |
862 | struct dsi_isr_data *isr_data; | |
863 | int free_idx; | |
864 | int i; | |
865 | ||
866 | BUG_ON(isr == NULL); | |
867 | ||
868 | /* check for duplicate entry and find a free slot */ | |
869 | free_idx = -1; | |
870 | for (i = 0; i < isr_array_size; i++) { | |
871 | isr_data = &isr_array[i]; | |
872 | ||
873 | if (isr_data->isr == isr && isr_data->arg == arg && | |
874 | isr_data->mask == mask) { | |
875 | return -EINVAL; | |
876 | } | |
877 | ||
878 | if (isr_data->isr == NULL && free_idx == -1) | |
879 | free_idx = i; | |
880 | } | |
881 | ||
882 | if (free_idx == -1) | |
883 | return -EBUSY; | |
884 | ||
885 | isr_data = &isr_array[free_idx]; | |
886 | isr_data->isr = isr; | |
887 | isr_data->arg = arg; | |
888 | isr_data->mask = mask; | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
894 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
895 | { | |
896 | struct dsi_isr_data *isr_data; | |
897 | int i; | |
898 | ||
899 | for (i = 0; i < isr_array_size; i++) { | |
900 | isr_data = &isr_array[i]; | |
901 | if (isr_data->isr != isr || isr_data->arg != arg || | |
902 | isr_data->mask != mask) | |
903 | continue; | |
904 | ||
905 | isr_data->isr = NULL; | |
906 | isr_data->arg = NULL; | |
907 | isr_data->mask = 0; | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | return -EINVAL; | |
913 | } | |
914 | ||
a72b64b9 AT |
915 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
916 | void *arg, u32 mask) | |
4ae2dddd | 917 | { |
f1da39d9 | 918 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
919 | unsigned long flags; |
920 | int r; | |
921 | ||
f1da39d9 | 922 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 923 | |
f1da39d9 AT |
924 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
925 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
926 | |
927 | if (r == 0) | |
a72b64b9 | 928 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 929 | |
f1da39d9 | 930 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
931 | |
932 | return r; | |
933 | } | |
934 | ||
a72b64b9 AT |
935 | static int dsi_unregister_isr(struct platform_device *dsidev, |
936 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 937 | { |
f1da39d9 | 938 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
939 | unsigned long flags; |
940 | int r; | |
941 | ||
f1da39d9 | 942 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 943 | |
f1da39d9 AT |
944 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
945 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
946 | |
947 | if (r == 0) | |
a72b64b9 | 948 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 949 | |
f1da39d9 | 950 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
951 | |
952 | return r; | |
953 | } | |
954 | ||
a72b64b9 AT |
955 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
956 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 957 | { |
f1da39d9 | 958 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
959 | unsigned long flags; |
960 | int r; | |
961 | ||
f1da39d9 | 962 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
963 | |
964 | r = _dsi_register_isr(isr, arg, mask, | |
f1da39d9 AT |
965 | dsi->isr_tables.isr_table_vc[channel], |
966 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
967 | |
968 | if (r == 0) | |
a72b64b9 | 969 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 970 | |
f1da39d9 | 971 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
972 | |
973 | return r; | |
974 | } | |
975 | ||
a72b64b9 AT |
976 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
977 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 978 | { |
f1da39d9 | 979 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
980 | unsigned long flags; |
981 | int r; | |
982 | ||
f1da39d9 | 983 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
984 | |
985 | r = _dsi_unregister_isr(isr, arg, mask, | |
f1da39d9 AT |
986 | dsi->isr_tables.isr_table_vc[channel], |
987 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
988 | |
989 | if (r == 0) | |
a72b64b9 | 990 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 991 | |
f1da39d9 | 992 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
993 | |
994 | return r; | |
995 | } | |
996 | ||
a72b64b9 AT |
997 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
998 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 999 | { |
f1da39d9 | 1000 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1001 | unsigned long flags; |
1002 | int r; | |
1003 | ||
f1da39d9 | 1004 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1005 | |
f1da39d9 AT |
1006 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1007 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1008 | |
1009 | if (r == 0) | |
a72b64b9 | 1010 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1011 | |
f1da39d9 | 1012 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1013 | |
1014 | return r; | |
1015 | } | |
1016 | ||
a72b64b9 AT |
1017 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
1018 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1019 | { |
f1da39d9 | 1020 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1021 | unsigned long flags; |
1022 | int r; | |
1023 | ||
f1da39d9 | 1024 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1025 | |
f1da39d9 AT |
1026 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1027 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1028 | |
1029 | if (r == 0) | |
a72b64b9 | 1030 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1031 | |
f1da39d9 | 1032 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1033 | |
1034 | return r; | |
3de7a1dc TV |
1035 | } |
1036 | ||
a72b64b9 | 1037 | static u32 dsi_get_errors(struct platform_device *dsidev) |
3de7a1dc | 1038 | { |
f1da39d9 | 1039 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1040 | unsigned long flags; |
1041 | u32 e; | |
f1da39d9 AT |
1042 | spin_lock_irqsave(&dsi->errors_lock, flags); |
1043 | e = dsi->errors; | |
1044 | dsi->errors = 0; | |
1045 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
3de7a1dc TV |
1046 | return e; |
1047 | } | |
1048 | ||
4fbafaf3 | 1049 | int dsi_runtime_get(struct platform_device *dsidev) |
3de7a1dc | 1050 | { |
4fbafaf3 TV |
1051 | int r; |
1052 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1053 | ||
1054 | DSSDBG("dsi_runtime_get\n"); | |
1055 | ||
1056 | r = pm_runtime_get_sync(&dsi->pdev->dev); | |
1057 | WARN_ON(r < 0); | |
1058 | return r < 0 ? r : 0; | |
1059 | } | |
1060 | ||
1061 | void dsi_runtime_put(struct platform_device *dsidev) | |
1062 | { | |
1063 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1064 | int r; | |
1065 | ||
1066 | DSSDBG("dsi_runtime_put\n"); | |
1067 | ||
1068 | r = pm_runtime_put(&dsi->pdev->dev); | |
1069 | WARN_ON(r < 0); | |
3de7a1dc TV |
1070 | } |
1071 | ||
1072 | /* source clock for DSI PLL. this could also be PCLKFREE */ | |
a72b64b9 AT |
1073 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
1074 | bool enable) | |
3de7a1dc | 1075 | { |
f1da39d9 AT |
1076 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1077 | ||
3de7a1dc | 1078 | if (enable) |
4fbafaf3 | 1079 | clk_enable(dsi->sys_clk); |
3de7a1dc | 1080 | else |
4fbafaf3 | 1081 | clk_disable(dsi->sys_clk); |
3de7a1dc | 1082 | |
f1da39d9 | 1083 | if (enable && dsi->pll_locked) { |
a72b64b9 | 1084 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
3de7a1dc TV |
1085 | DSSERR("cannot lock PLL when enabling clocks\n"); |
1086 | } | |
1087 | } | |
1088 | ||
1089 | #ifdef DEBUG | |
a72b64b9 | 1090 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
3de7a1dc TV |
1091 | { |
1092 | u32 l; | |
c335cbf9 | 1093 | int b0, b1, b2; |
3de7a1dc TV |
1094 | |
1095 | if (!dss_debug) | |
1096 | return; | |
1097 | ||
1098 | /* A dummy read using the SCP interface to any DSIPHY register is | |
1099 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1100 | * I/O. */ | |
a72b64b9 | 1101 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc TV |
1102 | |
1103 | printk(KERN_DEBUG "DSI resets: "); | |
1104 | ||
a72b64b9 | 1105 | l = dsi_read_reg(dsidev, DSI_PLL_STATUS); |
3de7a1dc TV |
1106 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
1107 | ||
a72b64b9 | 1108 | l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
3de7a1dc TV |
1109 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
1110 | ||
c335cbf9 TV |
1111 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
1112 | b0 = 28; | |
1113 | b1 = 27; | |
1114 | b2 = 26; | |
1115 | } else { | |
1116 | b0 = 24; | |
1117 | b1 = 25; | |
1118 | b2 = 26; | |
1119 | } | |
1120 | ||
a72b64b9 | 1121 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
c335cbf9 TV |
1122 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
1123 | FLD_GET(l, b0, b0), | |
1124 | FLD_GET(l, b1, b1), | |
1125 | FLD_GET(l, b2, b2), | |
3de7a1dc TV |
1126 | FLD_GET(l, 29, 29), |
1127 | FLD_GET(l, 30, 30), | |
1128 | FLD_GET(l, 31, 31)); | |
1129 | } | |
1130 | #else | |
a72b64b9 | 1131 | #define _dsi_print_reset_status(x) |
3de7a1dc TV |
1132 | #endif |
1133 | ||
a72b64b9 | 1134 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
3de7a1dc TV |
1135 | { |
1136 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1137 | ||
1138 | enable = enable ? 1 : 0; | |
a72b64b9 | 1139 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
3de7a1dc | 1140 | |
a72b64b9 | 1141 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
3de7a1dc TV |
1142 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
1143 | return -EIO; | |
1144 | } | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
a72b64b9 | 1149 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
3de7a1dc | 1150 | { |
f1da39d9 AT |
1151 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1152 | ||
1153 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; | |
3de7a1dc TV |
1154 | } |
1155 | ||
a72b64b9 | 1156 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
3de7a1dc | 1157 | { |
f1da39d9 AT |
1158 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1159 | ||
1160 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; | |
3de7a1dc TV |
1161 | } |
1162 | ||
a72b64b9 | 1163 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
3de7a1dc | 1164 | { |
f1da39d9 AT |
1165 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1166 | ||
1167 | return dsi->current_cinfo.clkin4ddr / 16; | |
3de7a1dc TV |
1168 | } |
1169 | ||
a72b64b9 | 1170 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
3de7a1dc TV |
1171 | { |
1172 | unsigned long r; | |
5a8b572d | 1173 | int dsi_module = dsi_get_dsidev_id(dsidev); |
4fbafaf3 | 1174 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc | 1175 | |
5a8b572d | 1176 | if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) { |
1bb47835 | 1177 | /* DSI FCLK source is DSS_CLK_FCK */ |
4fbafaf3 | 1178 | r = clk_get_rate(dsi->dss_clk); |
3de7a1dc | 1179 | } else { |
1bb47835 | 1180 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
a72b64b9 | 1181 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
3de7a1dc TV |
1182 | } |
1183 | ||
1184 | return r; | |
1185 | } | |
1186 | ||
1187 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) | |
1188 | { | |
a72b64b9 | 1189 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 1190 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1191 | unsigned long dsi_fclk; |
1192 | unsigned lp_clk_div; | |
1193 | unsigned long lp_clk; | |
1194 | ||
c6940a3d | 1195 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
3de7a1dc | 1196 | |
f1da39d9 | 1197 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
3de7a1dc TV |
1198 | return -EINVAL; |
1199 | ||
a72b64b9 | 1200 | dsi_fclk = dsi_fclk_rate(dsidev); |
3de7a1dc TV |
1201 | |
1202 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1203 | ||
1204 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
f1da39d9 AT |
1205 | dsi->current_cinfo.lp_clk = lp_clk; |
1206 | dsi->current_cinfo.lp_clk_div = lp_clk_div; | |
3de7a1dc | 1207 | |
a72b64b9 AT |
1208 | /* LP_CLK_DIVISOR */ |
1209 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); | |
3de7a1dc | 1210 | |
a72b64b9 AT |
1211 | /* LP_RX_SYNCHRO_ENABLE */ |
1212 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); | |
3de7a1dc TV |
1213 | |
1214 | return 0; | |
1215 | } | |
1216 | ||
a72b64b9 | 1217 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1218 | { |
f1da39d9 AT |
1219 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1220 | ||
1221 | if (dsi->scp_clk_refcount++ == 0) | |
a72b64b9 | 1222 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 TV |
1223 | } |
1224 | ||
a72b64b9 | 1225 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1226 | { |
f1da39d9 AT |
1227 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1228 | ||
1229 | WARN_ON(dsi->scp_clk_refcount == 0); | |
1230 | if (--dsi->scp_clk_refcount == 0) | |
a72b64b9 | 1231 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 | 1232 | } |
3de7a1dc TV |
1233 | |
1234 | enum dsi_pll_power_state { | |
1235 | DSI_PLL_POWER_OFF = 0x0, | |
1236 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1237 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1238 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1239 | }; | |
1240 | ||
a72b64b9 AT |
1241 | static int dsi_pll_power(struct platform_device *dsidev, |
1242 | enum dsi_pll_power_state state) | |
3de7a1dc TV |
1243 | { |
1244 | int t = 0; | |
1245 | ||
c94dfe05 TV |
1246 | /* DSI-PLL power command 0x3 is not working */ |
1247 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1248 | state == DSI_PLL_POWER_ON_DIV) | |
1249 | state = DSI_PLL_POWER_ON_ALL; | |
1250 | ||
a72b64b9 AT |
1251 | /* PLL_PWR_CMD */ |
1252 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); | |
3de7a1dc TV |
1253 | |
1254 | /* PLL_PWR_STATUS */ | |
a72b64b9 | 1255 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
24be78b3 | 1256 | if (++t > 1000) { |
3de7a1dc TV |
1257 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1258 | state); | |
1259 | return -ENODEV; | |
1260 | } | |
24be78b3 | 1261 | udelay(1); |
3de7a1dc TV |
1262 | } |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | /* calculate clock rates using dividers in cinfo */ | |
ff1b2cde SS |
1268 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
1269 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1270 | { |
f1da39d9 AT |
1271 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
1272 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1273 | ||
1274 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) | |
3de7a1dc TV |
1275 | return -EINVAL; |
1276 | ||
f1da39d9 | 1277 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
3de7a1dc TV |
1278 | return -EINVAL; |
1279 | ||
f1da39d9 | 1280 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
3de7a1dc TV |
1281 | return -EINVAL; |
1282 | ||
f1da39d9 | 1283 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
3de7a1dc TV |
1284 | return -EINVAL; |
1285 | ||
1bb47835 | 1286 | if (cinfo->use_sys_clk) { |
4fbafaf3 | 1287 | cinfo->clkin = clk_get_rate(dsi->sys_clk); |
3de7a1dc | 1288 | /* XXX it is unclear if highfreq should be used |
1bb47835 | 1289 | * with DSS_SYS_CLK source also */ |
3de7a1dc TV |
1290 | cinfo->highfreq = 0; |
1291 | } else { | |
26d9dd0d | 1292 | cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id); |
3de7a1dc TV |
1293 | |
1294 | if (cinfo->clkin < 32000000) | |
1295 | cinfo->highfreq = 0; | |
1296 | else | |
1297 | cinfo->highfreq = 1; | |
1298 | } | |
1299 | ||
1300 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); | |
1301 | ||
f1da39d9 | 1302 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
3de7a1dc TV |
1303 | return -EINVAL; |
1304 | ||
1305 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; | |
1306 | ||
1307 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) | |
1308 | return -EINVAL; | |
1309 | ||
1bb47835 AT |
1310 | if (cinfo->regm_dispc > 0) |
1311 | cinfo->dsi_pll_hsdiv_dispc_clk = | |
1312 | cinfo->clkin4ddr / cinfo->regm_dispc; | |
3de7a1dc | 1313 | else |
1bb47835 | 1314 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
3de7a1dc | 1315 | |
1bb47835 AT |
1316 | if (cinfo->regm_dsi > 0) |
1317 | cinfo->dsi_pll_hsdiv_dsi_clk = | |
1318 | cinfo->clkin4ddr / cinfo->regm_dsi; | |
3de7a1dc | 1319 | else |
1bb47835 | 1320 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
3de7a1dc TV |
1321 | |
1322 | return 0; | |
1323 | } | |
1324 | ||
a72b64b9 AT |
1325 | int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, |
1326 | unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, | |
3de7a1dc TV |
1327 | struct dispc_clock_info *dispc_cinfo) |
1328 | { | |
f1da39d9 | 1329 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1330 | struct dsi_clock_info cur, best; |
1331 | struct dispc_clock_info best_dispc; | |
1332 | int min_fck_per_pck; | |
1333 | int match = 0; | |
1bb47835 | 1334 | unsigned long dss_sys_clk, max_dss_fck; |
3de7a1dc | 1335 | |
4fbafaf3 | 1336 | dss_sys_clk = clk_get_rate(dsi->sys_clk); |
3de7a1dc | 1337 | |
31ef8237 | 1338 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 1339 | |
f1da39d9 AT |
1340 | if (req_pck == dsi->cache_req_pck && |
1341 | dsi->cache_cinfo.clkin == dss_sys_clk) { | |
3de7a1dc | 1342 | DSSDBG("DSI clock info found from cache\n"); |
f1da39d9 | 1343 | *dsi_cinfo = dsi->cache_cinfo; |
1bb47835 AT |
1344 | dispc_find_clk_divs(is_tft, req_pck, |
1345 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); | |
3de7a1dc TV |
1346 | return 0; |
1347 | } | |
1348 | ||
1349 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
1350 | ||
1351 | if (min_fck_per_pck && | |
819d807c | 1352 | req_pck * min_fck_per_pck > max_dss_fck) { |
3de7a1dc TV |
1353 | DSSERR("Requested pixel clock not possible with the current " |
1354 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
1355 | "the constraint off.\n"); | |
1356 | min_fck_per_pck = 0; | |
1357 | } | |
1358 | ||
1359 | DSSDBG("dsi_pll_calc\n"); | |
1360 | ||
1361 | retry: | |
1362 | memset(&best, 0, sizeof(best)); | |
1363 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
1364 | ||
1365 | memset(&cur, 0, sizeof(cur)); | |
1bb47835 AT |
1366 | cur.clkin = dss_sys_clk; |
1367 | cur.use_sys_clk = 1; | |
3de7a1dc TV |
1368 | cur.highfreq = 0; |
1369 | ||
1370 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ | |
1371 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ | |
1372 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ | |
f1da39d9 | 1373 | for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { |
3de7a1dc TV |
1374 | if (cur.highfreq == 0) |
1375 | cur.fint = cur.clkin / cur.regn; | |
1376 | else | |
1377 | cur.fint = cur.clkin / (2 * cur.regn); | |
1378 | ||
f1da39d9 | 1379 | if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) |
3de7a1dc TV |
1380 | continue; |
1381 | ||
1382 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ | |
f1da39d9 | 1383 | for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { |
3de7a1dc TV |
1384 | unsigned long a, b; |
1385 | ||
1386 | a = 2 * cur.regm * (cur.clkin/1000); | |
1387 | b = cur.regn * (cur.highfreq + 1); | |
1388 | cur.clkin4ddr = a / b * 1000; | |
1389 | ||
1390 | if (cur.clkin4ddr > 1800 * 1000 * 1000) | |
1391 | break; | |
1392 | ||
1bb47835 AT |
1393 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
1394 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ | |
f1da39d9 AT |
1395 | for (cur.regm_dispc = 1; cur.regm_dispc < |
1396 | dsi->regm_dispc_max; ++cur.regm_dispc) { | |
3de7a1dc | 1397 | struct dispc_clock_info cur_dispc; |
1bb47835 AT |
1398 | cur.dsi_pll_hsdiv_dispc_clk = |
1399 | cur.clkin4ddr / cur.regm_dispc; | |
3de7a1dc TV |
1400 | |
1401 | /* this will narrow down the search a bit, | |
1402 | * but still give pixclocks below what was | |
1403 | * requested */ | |
1bb47835 | 1404 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
3de7a1dc TV |
1405 | break; |
1406 | ||
1bb47835 | 1407 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
3de7a1dc TV |
1408 | continue; |
1409 | ||
1410 | if (min_fck_per_pck && | |
1bb47835 | 1411 | cur.dsi_pll_hsdiv_dispc_clk < |
3de7a1dc TV |
1412 | req_pck * min_fck_per_pck) |
1413 | continue; | |
1414 | ||
1415 | match = 1; | |
1416 | ||
1417 | dispc_find_clk_divs(is_tft, req_pck, | |
1bb47835 | 1418 | cur.dsi_pll_hsdiv_dispc_clk, |
3de7a1dc TV |
1419 | &cur_dispc); |
1420 | ||
1421 | if (abs(cur_dispc.pck - req_pck) < | |
1422 | abs(best_dispc.pck - req_pck)) { | |
1423 | best = cur; | |
1424 | best_dispc = cur_dispc; | |
1425 | ||
1426 | if (cur_dispc.pck == req_pck) | |
1427 | goto found; | |
1428 | } | |
1429 | } | |
1430 | } | |
1431 | } | |
1432 | found: | |
1433 | if (!match) { | |
1434 | if (min_fck_per_pck) { | |
1435 | DSSERR("Could not find suitable clock settings.\n" | |
1436 | "Turning FCK/PCK constraint off and" | |
1437 | "trying again.\n"); | |
1438 | min_fck_per_pck = 0; | |
1439 | goto retry; | |
1440 | } | |
1441 | ||
1442 | DSSERR("Could not find suitable clock settings.\n"); | |
1443 | ||
1444 | return -EINVAL; | |
1445 | } | |
1446 | ||
1bb47835 AT |
1447 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
1448 | best.regm_dsi = 0; | |
1449 | best.dsi_pll_hsdiv_dsi_clk = 0; | |
3de7a1dc TV |
1450 | |
1451 | if (dsi_cinfo) | |
1452 | *dsi_cinfo = best; | |
1453 | if (dispc_cinfo) | |
1454 | *dispc_cinfo = best_dispc; | |
1455 | ||
f1da39d9 AT |
1456 | dsi->cache_req_pck = req_pck; |
1457 | dsi->cache_clk_freq = 0; | |
1458 | dsi->cache_cinfo = best; | |
3de7a1dc TV |
1459 | |
1460 | return 0; | |
1461 | } | |
1462 | ||
a72b64b9 AT |
1463 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
1464 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1465 | { |
f1da39d9 | 1466 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1467 | int r = 0; |
1468 | u32 l; | |
9613c02b | 1469 | int f = 0; |
49641116 AT |
1470 | u8 regn_start, regn_end, regm_start, regm_end; |
1471 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; | |
3de7a1dc TV |
1472 | |
1473 | DSSDBGF(); | |
1474 | ||
f1da39d9 AT |
1475 | dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk; |
1476 | dsi->current_cinfo.highfreq = cinfo->highfreq; | |
b2765092 | 1477 | |
f1da39d9 AT |
1478 | dsi->current_cinfo.fint = cinfo->fint; |
1479 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; | |
1480 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = | |
1bb47835 | 1481 | cinfo->dsi_pll_hsdiv_dispc_clk; |
f1da39d9 | 1482 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
1bb47835 | 1483 | cinfo->dsi_pll_hsdiv_dsi_clk; |
3de7a1dc | 1484 | |
f1da39d9 AT |
1485 | dsi->current_cinfo.regn = cinfo->regn; |
1486 | dsi->current_cinfo.regm = cinfo->regm; | |
1487 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; | |
1488 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; | |
3de7a1dc TV |
1489 | |
1490 | DSSDBG("DSI Fint %ld\n", cinfo->fint); | |
1491 | ||
1492 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", | |
1bb47835 | 1493 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
3de7a1dc TV |
1494 | cinfo->clkin, |
1495 | cinfo->highfreq); | |
1496 | ||
1497 | /* DSIPHY == CLKIN4DDR */ | |
1498 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", | |
1499 | cinfo->regm, | |
1500 | cinfo->regn, | |
1501 | cinfo->clkin, | |
1502 | cinfo->highfreq + 1, | |
1503 | cinfo->clkin4ddr); | |
1504 | ||
1505 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", | |
1506 | cinfo->clkin4ddr / 1000 / 1000 / 2); | |
1507 | ||
1508 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | |
1509 | ||
1bb47835 | 1510 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
89a35e51 AT |
1511 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1512 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1513 | cinfo->dsi_pll_hsdiv_dispc_clk); |
1514 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, | |
89a35e51 AT |
1515 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
1516 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | |
1bb47835 | 1517 | cinfo->dsi_pll_hsdiv_dsi_clk); |
3de7a1dc | 1518 | |
49641116 AT |
1519 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
1520 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); | |
1521 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, | |
1522 | ®m_dispc_end); | |
1523 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, | |
1524 | ®m_dsi_end); | |
1525 | ||
a72b64b9 AT |
1526 | /* DSI_PLL_AUTOMODE = manual */ |
1527 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); | |
3de7a1dc | 1528 | |
a72b64b9 | 1529 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
3de7a1dc | 1530 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
49641116 AT |
1531 | /* DSI_PLL_REGN */ |
1532 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); | |
1533 | /* DSI_PLL_REGM */ | |
1534 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); | |
1535 | /* DSI_CLOCK_DIV */ | |
1bb47835 | 1536 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
49641116 AT |
1537 | regm_dispc_start, regm_dispc_end); |
1538 | /* DSIPROTO_CLOCK_DIV */ | |
1bb47835 | 1539 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
49641116 | 1540 | regm_dsi_start, regm_dsi_end); |
a72b64b9 | 1541 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
3de7a1dc | 1542 | |
f1da39d9 | 1543 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
9613c02b AT |
1544 | |
1545 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { | |
1546 | f = cinfo->fint < 1000000 ? 0x3 : | |
1547 | cinfo->fint < 1250000 ? 0x4 : | |
1548 | cinfo->fint < 1500000 ? 0x5 : | |
1549 | cinfo->fint < 1750000 ? 0x6 : | |
1550 | 0x7; | |
1551 | } | |
3de7a1dc | 1552 | |
a72b64b9 | 1553 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
9613c02b AT |
1554 | |
1555 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) | |
1556 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ | |
1bb47835 | 1557 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
3de7a1dc TV |
1558 | 11, 11); /* DSI_PLL_CLKSEL */ |
1559 | l = FLD_MOD(l, cinfo->highfreq, | |
1560 | 12, 12); /* DSI_PLL_HIGHFREQ */ | |
1561 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1562 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ | |
1563 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1564 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc | 1565 | |
a72b64b9 | 1566 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
3de7a1dc | 1567 | |
a72b64b9 | 1568 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
3de7a1dc TV |
1569 | DSSERR("dsi pll go bit not going down.\n"); |
1570 | r = -EIO; | |
1571 | goto err; | |
1572 | } | |
1573 | ||
a72b64b9 | 1574 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
3de7a1dc TV |
1575 | DSSERR("cannot lock PLL\n"); |
1576 | r = -EIO; | |
1577 | goto err; | |
1578 | } | |
1579 | ||
f1da39d9 | 1580 | dsi->pll_locked = 1; |
3de7a1dc | 1581 | |
a72b64b9 | 1582 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
3de7a1dc TV |
1583 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
1584 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ | |
1585 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ | |
1586 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ | |
1587 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ | |
1588 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ | |
1589 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1590 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ | |
1591 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ | |
1592 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ | |
1593 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ | |
1594 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ | |
1595 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ | |
1596 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1597 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc TV |
1598 | |
1599 | DSSDBG("PLL config done\n"); | |
1600 | err: | |
1601 | return r; | |
1602 | } | |
1603 | ||
a72b64b9 AT |
1604 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
1605 | bool enable_hsdiv) | |
3de7a1dc | 1606 | { |
f1da39d9 | 1607 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1608 | int r = 0; |
1609 | enum dsi_pll_power_state pwstate; | |
1610 | ||
1611 | DSSDBG("PLL init\n"); | |
1612 | ||
f1da39d9 | 1613 | if (dsi->vdds_dsi_reg == NULL) { |
f2988ab9 TV |
1614 | struct regulator *vdds_dsi; |
1615 | ||
f1da39d9 | 1616 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
f2988ab9 TV |
1617 | |
1618 | if (IS_ERR(vdds_dsi)) { | |
1619 | DSSERR("can't get VDDS_DSI regulator\n"); | |
1620 | return PTR_ERR(vdds_dsi); | |
1621 | } | |
1622 | ||
f1da39d9 | 1623 | dsi->vdds_dsi_reg = vdds_dsi; |
f2988ab9 | 1624 | } |
f2988ab9 | 1625 | |
a72b64b9 | 1626 | dsi_enable_pll_clock(dsidev, 1); |
24c1ae41 TV |
1627 | /* |
1628 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1629 | */ | |
a72b64b9 | 1630 | dsi_enable_scp_clk(dsidev); |
3de7a1dc | 1631 | |
f1da39d9 AT |
1632 | if (!dsi->vdds_dsi_enabled) { |
1633 | r = regulator_enable(dsi->vdds_dsi_reg); | |
2a89dc15 TV |
1634 | if (r) |
1635 | goto err0; | |
f1da39d9 | 1636 | dsi->vdds_dsi_enabled = true; |
2a89dc15 | 1637 | } |
3de7a1dc TV |
1638 | |
1639 | /* XXX PLL does not come out of reset without this... */ | |
1640 | dispc_pck_free_enable(1); | |
1641 | ||
a72b64b9 | 1642 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
3de7a1dc TV |
1643 | DSSERR("PLL not coming out of reset.\n"); |
1644 | r = -ENODEV; | |
481dfa0e | 1645 | dispc_pck_free_enable(0); |
3de7a1dc TV |
1646 | goto err1; |
1647 | } | |
1648 | ||
1649 | /* XXX ... but if left on, we get problems when planes do not | |
1650 | * fill the whole display. No idea about this */ | |
1651 | dispc_pck_free_enable(0); | |
1652 | ||
1653 | if (enable_hsclk && enable_hsdiv) | |
1654 | pwstate = DSI_PLL_POWER_ON_ALL; | |
1655 | else if (enable_hsclk) | |
1656 | pwstate = DSI_PLL_POWER_ON_HSCLK; | |
1657 | else if (enable_hsdiv) | |
1658 | pwstate = DSI_PLL_POWER_ON_DIV; | |
1659 | else | |
1660 | pwstate = DSI_PLL_POWER_OFF; | |
1661 | ||
a72b64b9 | 1662 | r = dsi_pll_power(dsidev, pwstate); |
3de7a1dc TV |
1663 | |
1664 | if (r) | |
1665 | goto err1; | |
1666 | ||
1667 | DSSDBG("PLL init done\n"); | |
1668 | ||
1669 | return 0; | |
1670 | err1: | |
f1da39d9 AT |
1671 | if (dsi->vdds_dsi_enabled) { |
1672 | regulator_disable(dsi->vdds_dsi_reg); | |
1673 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1674 | } |
3de7a1dc | 1675 | err0: |
a72b64b9 | 1676 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1677 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc TV |
1678 | return r; |
1679 | } | |
1680 | ||
a72b64b9 | 1681 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
3de7a1dc | 1682 | { |
f1da39d9 AT |
1683 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1684 | ||
1685 | dsi->pll_locked = 0; | |
a72b64b9 | 1686 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
2a89dc15 | 1687 | if (disconnect_lanes) { |
f1da39d9 AT |
1688 | WARN_ON(!dsi->vdds_dsi_enabled); |
1689 | regulator_disable(dsi->vdds_dsi_reg); | |
1690 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1691 | } |
24c1ae41 | 1692 | |
a72b64b9 | 1693 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1694 | dsi_enable_pll_clock(dsidev, 0); |
24c1ae41 | 1695 | |
3de7a1dc TV |
1696 | DSSDBG("PLL uninit done\n"); |
1697 | } | |
1698 | ||
5a8b572d AT |
1699 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
1700 | struct seq_file *s) | |
3de7a1dc | 1701 | { |
f1da39d9 AT |
1702 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1703 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; | |
89a35e51 | 1704 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
5a8b572d | 1705 | int dsi_module = dsi_get_dsidev_id(dsidev); |
067a57e4 AT |
1706 | |
1707 | dispc_clk_src = dss_get_dispc_clk_source(); | |
5a8b572d | 1708 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
3de7a1dc | 1709 | |
4fbafaf3 TV |
1710 | if (dsi_runtime_get(dsidev)) |
1711 | return; | |
3de7a1dc | 1712 | |
5a8b572d | 1713 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
3de7a1dc TV |
1714 | |
1715 | seq_printf(s, "dsi pll source = %s\n", | |
a9a6500b | 1716 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); |
3de7a1dc TV |
1717 | |
1718 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); | |
1719 | ||
1720 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | |
1721 | cinfo->clkin4ddr, cinfo->regm); | |
1722 | ||
1bb47835 | 1723 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
067a57e4 AT |
1724 | dss_get_generic_clk_source_name(dispc_clk_src), |
1725 | dss_feat_get_clk_source_name(dispc_clk_src), | |
1bb47835 AT |
1726 | cinfo->dsi_pll_hsdiv_dispc_clk, |
1727 | cinfo->regm_dispc, | |
89a35e51 | 1728 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1729 | "off" : "on"); |
3de7a1dc | 1730 | |
1bb47835 | 1731 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
067a57e4 AT |
1732 | dss_get_generic_clk_source_name(dsi_clk_src), |
1733 | dss_feat_get_clk_source_name(dsi_clk_src), | |
1bb47835 AT |
1734 | cinfo->dsi_pll_hsdiv_dsi_clk, |
1735 | cinfo->regm_dsi, | |
89a35e51 | 1736 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1737 | "off" : "on"); |
3de7a1dc | 1738 | |
5a8b572d | 1739 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
3de7a1dc | 1740 | |
067a57e4 AT |
1741 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1742 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1743 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
3de7a1dc | 1744 | |
a72b64b9 | 1745 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
3de7a1dc TV |
1746 | |
1747 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1748 | cinfo->clkin4ddr / 4); | |
1749 | ||
a72b64b9 | 1750 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
3de7a1dc TV |
1751 | |
1752 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); | |
1753 | ||
4fbafaf3 | 1754 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1755 | } |
1756 | ||
5a8b572d AT |
1757 | void dsi_dump_clocks(struct seq_file *s) |
1758 | { | |
1759 | struct platform_device *dsidev; | |
1760 | int i; | |
1761 | ||
1762 | for (i = 0; i < MAX_NUM_DSI; i++) { | |
1763 | dsidev = dsi_get_dsidev_from_id(i); | |
1764 | if (dsidev) | |
1765 | dsi_dump_dsidev_clocks(dsidev, s); | |
1766 | } | |
1767 | } | |
1768 | ||
dfc0fd8d | 1769 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
5a8b572d AT |
1770 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
1771 | struct seq_file *s) | |
dfc0fd8d | 1772 | { |
f1da39d9 | 1773 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
dfc0fd8d TV |
1774 | unsigned long flags; |
1775 | struct dsi_irq_stats stats; | |
5a8b572d | 1776 | int dsi_module = dsi_get_dsidev_id(dsidev); |
dfc0fd8d | 1777 | |
f1da39d9 | 1778 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
dfc0fd8d | 1779 | |
f1da39d9 AT |
1780 | stats = dsi->irq_stats; |
1781 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); | |
1782 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d | 1783 | |
f1da39d9 | 1784 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
dfc0fd8d TV |
1785 | |
1786 | seq_printf(s, "period %u ms\n", | |
1787 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1788 | ||
1789 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1790 | #define PIS(x) \ | |
1791 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1792 | ||
5a8b572d | 1793 | seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1); |
dfc0fd8d TV |
1794 | PIS(VC0); |
1795 | PIS(VC1); | |
1796 | PIS(VC2); | |
1797 | PIS(VC3); | |
1798 | PIS(WAKEUP); | |
1799 | PIS(RESYNC); | |
1800 | PIS(PLL_LOCK); | |
1801 | PIS(PLL_UNLOCK); | |
1802 | PIS(PLL_RECALL); | |
1803 | PIS(COMPLEXIO_ERR); | |
1804 | PIS(HS_TX_TIMEOUT); | |
1805 | PIS(LP_RX_TIMEOUT); | |
1806 | PIS(TE_TRIGGER); | |
1807 | PIS(ACK_TRIGGER); | |
1808 | PIS(SYNC_LOST); | |
1809 | PIS(LDO_POWER_GOOD); | |
1810 | PIS(TA_TIMEOUT); | |
1811 | #undef PIS | |
1812 | ||
1813 | #define PIS(x) \ | |
1814 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1815 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1816 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1817 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1818 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1819 | ||
1820 | seq_printf(s, "-- VC interrupts --\n"); | |
1821 | PIS(CS); | |
1822 | PIS(ECC_CORR); | |
1823 | PIS(PACKET_SENT); | |
1824 | PIS(FIFO_TX_OVF); | |
1825 | PIS(FIFO_RX_OVF); | |
1826 | PIS(BTA); | |
1827 | PIS(ECC_NO_CORR); | |
1828 | PIS(FIFO_TX_UDF); | |
1829 | PIS(PP_BUSY_CHANGE); | |
1830 | #undef PIS | |
1831 | ||
1832 | #define PIS(x) \ | |
1833 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1834 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1835 | ||
1836 | seq_printf(s, "-- CIO interrupts --\n"); | |
1837 | PIS(ERRSYNCESC1); | |
1838 | PIS(ERRSYNCESC2); | |
1839 | PIS(ERRSYNCESC3); | |
1840 | PIS(ERRESC1); | |
1841 | PIS(ERRESC2); | |
1842 | PIS(ERRESC3); | |
1843 | PIS(ERRCONTROL1); | |
1844 | PIS(ERRCONTROL2); | |
1845 | PIS(ERRCONTROL3); | |
1846 | PIS(STATEULPS1); | |
1847 | PIS(STATEULPS2); | |
1848 | PIS(STATEULPS3); | |
1849 | PIS(ERRCONTENTIONLP0_1); | |
1850 | PIS(ERRCONTENTIONLP1_1); | |
1851 | PIS(ERRCONTENTIONLP0_2); | |
1852 | PIS(ERRCONTENTIONLP1_2); | |
1853 | PIS(ERRCONTENTIONLP0_3); | |
1854 | PIS(ERRCONTENTIONLP1_3); | |
1855 | PIS(ULPSACTIVENOT_ALL0); | |
1856 | PIS(ULPSACTIVENOT_ALL1); | |
1857 | #undef PIS | |
1858 | } | |
dfc0fd8d | 1859 | |
5a8b572d | 1860 | static void dsi1_dump_irqs(struct seq_file *s) |
3de7a1dc | 1861 | { |
a72b64b9 AT |
1862 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
1863 | ||
5a8b572d AT |
1864 | dsi_dump_dsidev_irqs(dsidev, s); |
1865 | } | |
1866 | ||
1867 | static void dsi2_dump_irqs(struct seq_file *s) | |
1868 | { | |
1869 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1870 | ||
1871 | dsi_dump_dsidev_irqs(dsidev, s); | |
1872 | } | |
1873 | ||
1874 | void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir, | |
1875 | const struct file_operations *debug_fops) | |
1876 | { | |
1877 | struct platform_device *dsidev; | |
1878 | ||
1879 | dsidev = dsi_get_dsidev_from_id(0); | |
1880 | if (dsidev) | |
1881 | debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir, | |
1882 | &dsi1_dump_irqs, debug_fops); | |
1883 | ||
1884 | dsidev = dsi_get_dsidev_from_id(1); | |
1885 | if (dsidev) | |
1886 | debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir, | |
1887 | &dsi2_dump_irqs, debug_fops); | |
1888 | } | |
1889 | #endif | |
1890 | ||
1891 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, | |
1892 | struct seq_file *s) | |
1893 | { | |
a72b64b9 | 1894 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
3de7a1dc | 1895 | |
4fbafaf3 TV |
1896 | if (dsi_runtime_get(dsidev)) |
1897 | return; | |
a72b64b9 | 1898 | dsi_enable_scp_clk(dsidev); |
3de7a1dc TV |
1899 | |
1900 | DUMPREG(DSI_REVISION); | |
1901 | DUMPREG(DSI_SYSCONFIG); | |
1902 | DUMPREG(DSI_SYSSTATUS); | |
1903 | DUMPREG(DSI_IRQSTATUS); | |
1904 | DUMPREG(DSI_IRQENABLE); | |
1905 | DUMPREG(DSI_CTRL); | |
1906 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1907 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1908 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1909 | DUMPREG(DSI_CLK_CTRL); | |
1910 | DUMPREG(DSI_TIMING1); | |
1911 | DUMPREG(DSI_TIMING2); | |
1912 | DUMPREG(DSI_VM_TIMING1); | |
1913 | DUMPREG(DSI_VM_TIMING2); | |
1914 | DUMPREG(DSI_VM_TIMING3); | |
1915 | DUMPREG(DSI_CLK_TIMING); | |
1916 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1917 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1918 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1919 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1920 | DUMPREG(DSI_VM_TIMING4); | |
1921 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1922 | DUMPREG(DSI_VM_TIMING5); | |
1923 | DUMPREG(DSI_VM_TIMING6); | |
1924 | DUMPREG(DSI_VM_TIMING7); | |
1925 | DUMPREG(DSI_STOPCLK_TIMING); | |
1926 | ||
1927 | DUMPREG(DSI_VC_CTRL(0)); | |
1928 | DUMPREG(DSI_VC_TE(0)); | |
1929 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1930 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1931 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1932 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1933 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1934 | ||
1935 | DUMPREG(DSI_VC_CTRL(1)); | |
1936 | DUMPREG(DSI_VC_TE(1)); | |
1937 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1938 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1939 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1940 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1941 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1942 | ||
1943 | DUMPREG(DSI_VC_CTRL(2)); | |
1944 | DUMPREG(DSI_VC_TE(2)); | |
1945 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1946 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1947 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1948 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1949 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1950 | ||
1951 | DUMPREG(DSI_VC_CTRL(3)); | |
1952 | DUMPREG(DSI_VC_TE(3)); | |
1953 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1954 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1955 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1956 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1957 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1958 | ||
1959 | DUMPREG(DSI_DSIPHY_CFG0); | |
1960 | DUMPREG(DSI_DSIPHY_CFG1); | |
1961 | DUMPREG(DSI_DSIPHY_CFG2); | |
1962 | DUMPREG(DSI_DSIPHY_CFG5); | |
1963 | ||
1964 | DUMPREG(DSI_PLL_CONTROL); | |
1965 | DUMPREG(DSI_PLL_STATUS); | |
1966 | DUMPREG(DSI_PLL_GO); | |
1967 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1968 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
1969 | ||
a72b64b9 | 1970 | dsi_disable_scp_clk(dsidev); |
4fbafaf3 | 1971 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1972 | #undef DUMPREG |
1973 | } | |
1974 | ||
5a8b572d AT |
1975 | static void dsi1_dump_regs(struct seq_file *s) |
1976 | { | |
1977 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
1978 | ||
1979 | dsi_dump_dsidev_regs(dsidev, s); | |
1980 | } | |
1981 | ||
1982 | static void dsi2_dump_regs(struct seq_file *s) | |
1983 | { | |
1984 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1985 | ||
1986 | dsi_dump_dsidev_regs(dsidev, s); | |
1987 | } | |
1988 | ||
1989 | void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir, | |
1990 | const struct file_operations *debug_fops) | |
1991 | { | |
1992 | struct platform_device *dsidev; | |
1993 | ||
1994 | dsidev = dsi_get_dsidev_from_id(0); | |
1995 | if (dsidev) | |
1996 | debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir, | |
1997 | &dsi1_dump_regs, debug_fops); | |
1998 | ||
1999 | dsidev = dsi_get_dsidev_from_id(1); | |
2000 | if (dsidev) | |
2001 | debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir, | |
2002 | &dsi2_dump_regs, debug_fops); | |
2003 | } | |
cc5c1850 | 2004 | enum dsi_cio_power_state { |
3de7a1dc TV |
2005 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
2006 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
2007 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
2008 | }; | |
2009 | ||
a72b64b9 AT |
2010 | static int dsi_cio_power(struct platform_device *dsidev, |
2011 | enum dsi_cio_power_state state) | |
3de7a1dc TV |
2012 | { |
2013 | int t = 0; | |
2014 | ||
2015 | /* PWR_CMD */ | |
a72b64b9 | 2016 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
3de7a1dc TV |
2017 | |
2018 | /* PWR_STATUS */ | |
a72b64b9 AT |
2019 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
2020 | 26, 25) != state) { | |
24be78b3 | 2021 | if (++t > 1000) { |
3de7a1dc TV |
2022 | DSSERR("failed to set complexio power state to " |
2023 | "%d\n", state); | |
2024 | return -ENODEV; | |
2025 | } | |
24be78b3 | 2026 | udelay(1); |
3de7a1dc TV |
2027 | } |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
75d7247c AT |
2032 | /* Number of data lanes present on DSI interface */ |
2033 | static inline int dsi_get_num_data_lanes(struct platform_device *dsidev) | |
2034 | { | |
2035 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number | |
2036 | * of data lanes as 2 by default */ | |
2037 | if (dss_has_feature(FEAT_DSI_GNQ)) | |
2038 | return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */ | |
2039 | else | |
2040 | return 2; | |
2041 | } | |
2042 | ||
2043 | /* Number of data lanes used by the dss device */ | |
2044 | static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev) | |
2045 | { | |
2046 | int num_data_lanes = 0; | |
2047 | ||
2048 | if (dssdev->phy.dsi.data1_lane != 0) | |
2049 | num_data_lanes++; | |
2050 | if (dssdev->phy.dsi.data2_lane != 0) | |
2051 | num_data_lanes++; | |
2052 | if (dssdev->phy.dsi.data3_lane != 0) | |
2053 | num_data_lanes++; | |
2054 | if (dssdev->phy.dsi.data4_lane != 0) | |
2055 | num_data_lanes++; | |
2056 | ||
2057 | return num_data_lanes; | |
2058 | } | |
2059 | ||
0c65622b AT |
2060 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
2061 | { | |
2062 | int val; | |
2063 | ||
2064 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
2065 | /* XXX: for some reason using full buffer size causes | |
2066 | * considerable TX slowdown with update sizes that fill the | |
2067 | * whole buffer */ | |
2068 | if (!dss_has_feature(FEAT_DSI_GNQ)) | |
2069 | return 1023 * 3; | |
2070 | ||
2071 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ | |
2072 | ||
2073 | switch (val) { | |
2074 | case 1: | |
2075 | return 512 * 3; /* 512x24 bits */ | |
2076 | case 2: | |
2077 | return 682 * 3; /* 682x24 bits */ | |
2078 | case 3: | |
2079 | return 853 * 3; /* 853x24 bits */ | |
2080 | case 4: | |
2081 | return 1024 * 3; /* 1024x24 bits */ | |
2082 | case 5: | |
2083 | return 1194 * 3; /* 1194x24 bits */ | |
2084 | case 6: | |
2085 | return 1365 * 3; /* 1365x24 bits */ | |
2086 | default: | |
2087 | BUG(); | |
2088 | } | |
2089 | } | |
2090 | ||
cc5c1850 | 2091 | static void dsi_set_lane_config(struct omap_dss_device *dssdev) |
3de7a1dc | 2092 | { |
a72b64b9 | 2093 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc | 2094 | u32 r; |
75d7247c | 2095 | int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev); |
3de7a1dc TV |
2096 | |
2097 | int clk_lane = dssdev->phy.dsi.clk_lane; | |
2098 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
2099 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
2100 | int clk_pol = dssdev->phy.dsi.clk_pol; | |
2101 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
2102 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
2103 | ||
a72b64b9 | 2104 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
3de7a1dc TV |
2105 | r = FLD_MOD(r, clk_lane, 2, 0); |
2106 | r = FLD_MOD(r, clk_pol, 3, 3); | |
2107 | r = FLD_MOD(r, data1_lane, 6, 4); | |
2108 | r = FLD_MOD(r, data1_pol, 7, 7); | |
2109 | r = FLD_MOD(r, data2_lane, 10, 8); | |
2110 | r = FLD_MOD(r, data2_pol, 11, 11); | |
75d7247c AT |
2111 | if (num_data_lanes_dssdev > 2) { |
2112 | int data3_lane = dssdev->phy.dsi.data3_lane; | |
2113 | int data3_pol = dssdev->phy.dsi.data3_pol; | |
2114 | ||
2115 | r = FLD_MOD(r, data3_lane, 14, 12); | |
2116 | r = FLD_MOD(r, data3_pol, 15, 15); | |
2117 | } | |
2118 | if (num_data_lanes_dssdev > 3) { | |
2119 | int data4_lane = dssdev->phy.dsi.data4_lane; | |
2120 | int data4_pol = dssdev->phy.dsi.data4_pol; | |
2121 | ||
2122 | r = FLD_MOD(r, data4_lane, 18, 16); | |
2123 | r = FLD_MOD(r, data4_pol, 19, 19); | |
2124 | } | |
a72b64b9 | 2125 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
3de7a1dc TV |
2126 | |
2127 | /* The configuration of the DSI complex I/O (number of data lanes, | |
2128 | position, differential order) should not be changed while | |
2129 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for | |
2130 | the hardware to take into account a new configuration of the complex | |
2131 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to | |
2132 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, | |
2133 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set | |
2134 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the | |
2135 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the | |
2136 | DSI complex I/O configuration is unknown. */ | |
2137 | ||
2138 | /* | |
a72b64b9 AT |
2139 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); |
2140 | REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0); | |
2141 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); | |
2142 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); | |
3de7a1dc TV |
2143 | */ |
2144 | } | |
2145 | ||
a72b64b9 | 2146 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
3de7a1dc | 2147 | { |
f1da39d9 AT |
2148 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2149 | ||
3de7a1dc | 2150 | /* convert time in ns to ddr ticks, rounding up */ |
f1da39d9 | 2151 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
3de7a1dc TV |
2152 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
2153 | } | |
2154 | ||
a72b64b9 | 2155 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
3de7a1dc | 2156 | { |
f1da39d9 AT |
2157 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2158 | ||
2159 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; | |
3de7a1dc TV |
2160 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
2161 | } | |
2162 | ||
a72b64b9 | 2163 | static void dsi_cio_timings(struct platform_device *dsidev) |
3de7a1dc TV |
2164 | { |
2165 | u32 r; | |
2166 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
2167 | u32 tlpx_half, tclk_trail, tclk_zero; | |
2168 | u32 tclk_prepare; | |
2169 | ||
2170 | /* calculate timings */ | |
2171 | ||
2172 | /* 1 * DDR_CLK = 2 * UI */ | |
2173 | ||
2174 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
a72b64b9 | 2175 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
3de7a1dc TV |
2176 | |
2177 | /* min 145ns + 10*UI */ | |
a72b64b9 | 2178 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
3de7a1dc TV |
2179 | |
2180 | /* min max(8*UI, 60ns+4*UI) */ | |
a72b64b9 | 2181 | ths_trail = ns2ddr(dsidev, 60) + 5; |
3de7a1dc TV |
2182 | |
2183 | /* min 100ns */ | |
a72b64b9 | 2184 | ths_exit = ns2ddr(dsidev, 145); |
3de7a1dc TV |
2185 | |
2186 | /* tlpx min 50n */ | |
a72b64b9 | 2187 | tlpx_half = ns2ddr(dsidev, 25); |
3de7a1dc TV |
2188 | |
2189 | /* min 60ns */ | |
a72b64b9 | 2190 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
3de7a1dc TV |
2191 | |
2192 | /* min 38ns, max 95ns */ | |
a72b64b9 | 2193 | tclk_prepare = ns2ddr(dsidev, 65); |
3de7a1dc TV |
2194 | |
2195 | /* min tclk-prepare + tclk-zero = 300ns */ | |
a72b64b9 | 2196 | tclk_zero = ns2ddr(dsidev, 260); |
3de7a1dc TV |
2197 | |
2198 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
a72b64b9 AT |
2199 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
2200 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); | |
3de7a1dc | 2201 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
a72b64b9 AT |
2202 | ths_trail, ddr2ns(dsidev, ths_trail), |
2203 | ths_exit, ddr2ns(dsidev, ths_exit)); | |
3de7a1dc TV |
2204 | |
2205 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
2206 | "tclk_zero %u (%uns)\n", | |
a72b64b9 AT |
2207 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
2208 | tclk_trail, ddr2ns(dsidev, tclk_trail), | |
2209 | tclk_zero, ddr2ns(dsidev, tclk_zero)); | |
3de7a1dc | 2210 | DSSDBG("tclk_prepare %u (%uns)\n", |
a72b64b9 | 2211 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
3de7a1dc TV |
2212 | |
2213 | /* program timings */ | |
2214 | ||
a72b64b9 | 2215 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
2216 | r = FLD_MOD(r, ths_prepare, 31, 24); |
2217 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
2218 | r = FLD_MOD(r, ths_trail, 15, 8); | |
2219 | r = FLD_MOD(r, ths_exit, 7, 0); | |
a72b64b9 | 2220 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
3de7a1dc | 2221 | |
a72b64b9 | 2222 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
2223 | r = FLD_MOD(r, tlpx_half, 22, 16); |
2224 | r = FLD_MOD(r, tclk_trail, 15, 8); | |
2225 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
a72b64b9 | 2226 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
3de7a1dc | 2227 | |
a72b64b9 | 2228 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc | 2229 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
a72b64b9 | 2230 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
3de7a1dc TV |
2231 | } |
2232 | ||
cc5c1850 | 2233 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
0a0ee46b TV |
2234 | enum dsi_lane lanes) |
2235 | { | |
a72b64b9 | 2236 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
75d7247c | 2237 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
0a0ee46b TV |
2238 | int clk_lane = dssdev->phy.dsi.clk_lane; |
2239 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
2240 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
75d7247c AT |
2241 | int data3_lane = dssdev->phy.dsi.data3_lane; |
2242 | int data4_lane = dssdev->phy.dsi.data4_lane; | |
0a0ee46b TV |
2243 | int clk_pol = dssdev->phy.dsi.clk_pol; |
2244 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
2245 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
75d7247c AT |
2246 | int data3_pol = dssdev->phy.dsi.data3_pol; |
2247 | int data4_pol = dssdev->phy.dsi.data4_pol; | |
0a0ee46b TV |
2248 | |
2249 | u32 l = 0; | |
75d7247c | 2250 | u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26; |
0a0ee46b TV |
2251 | |
2252 | if (lanes & DSI_CLK_P) | |
2253 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); | |
2254 | if (lanes & DSI_CLK_N) | |
2255 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); | |
2256 | ||
2257 | if (lanes & DSI_DATA1_P) | |
2258 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); | |
2259 | if (lanes & DSI_DATA1_N) | |
2260 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); | |
2261 | ||
2262 | if (lanes & DSI_DATA2_P) | |
2263 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); | |
2264 | if (lanes & DSI_DATA2_N) | |
2265 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); | |
2266 | ||
75d7247c AT |
2267 | if (lanes & DSI_DATA3_P) |
2268 | l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1)); | |
2269 | if (lanes & DSI_DATA3_N) | |
2270 | l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0)); | |
2271 | ||
2272 | if (lanes & DSI_DATA4_P) | |
2273 | l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1)); | |
2274 | if (lanes & DSI_DATA4_N) | |
2275 | l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0)); | |
0a0ee46b TV |
2276 | /* |
2277 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
2278 | * 17: DY0 18: DX0 | |
2279 | * 19: DY1 20: DX1 | |
2280 | * 21: DY2 22: DX2 | |
75d7247c AT |
2281 | * 23: DY3 24: DX3 |
2282 | * 25: DY4 26: DX4 | |
0a0ee46b TV |
2283 | */ |
2284 | ||
2285 | /* Set the lane override configuration */ | |
a72b64b9 AT |
2286 | |
2287 | /* REGLPTXSCPDAT4TO0DXDY */ | |
75d7247c | 2288 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
0a0ee46b TV |
2289 | |
2290 | /* Enable lane override */ | |
a72b64b9 AT |
2291 | |
2292 | /* ENLPTXSCPDAT */ | |
2293 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); | |
0a0ee46b TV |
2294 | } |
2295 | ||
a72b64b9 | 2296 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
0a0ee46b TV |
2297 | { |
2298 | /* Disable lane override */ | |
a72b64b9 | 2299 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
0a0ee46b | 2300 | /* Reset the lane override configuration */ |
a72b64b9 AT |
2301 | /* REGLPTXSCPDAT4TO0DXDY */ |
2302 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); | |
0a0ee46b | 2303 | } |
3de7a1dc | 2304 | |
03329ace TV |
2305 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
2306 | { | |
a72b64b9 | 2307 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
03329ace TV |
2308 | int t; |
2309 | int bits[3]; | |
2310 | bool in_use[3]; | |
2311 | ||
2312 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { | |
2313 | bits[0] = 28; | |
2314 | bits[1] = 27; | |
2315 | bits[2] = 26; | |
2316 | } else { | |
2317 | bits[0] = 24; | |
2318 | bits[1] = 25; | |
2319 | bits[2] = 26; | |
2320 | } | |
2321 | ||
2322 | in_use[0] = false; | |
2323 | in_use[1] = false; | |
2324 | in_use[2] = false; | |
2325 | ||
2326 | if (dssdev->phy.dsi.clk_lane != 0) | |
2327 | in_use[dssdev->phy.dsi.clk_lane - 1] = true; | |
2328 | if (dssdev->phy.dsi.data1_lane != 0) | |
2329 | in_use[dssdev->phy.dsi.data1_lane - 1] = true; | |
2330 | if (dssdev->phy.dsi.data2_lane != 0) | |
2331 | in_use[dssdev->phy.dsi.data2_lane - 1] = true; | |
2332 | ||
2333 | t = 100000; | |
2334 | while (true) { | |
2335 | u32 l; | |
2336 | int i; | |
2337 | int ok; | |
2338 | ||
a72b64b9 | 2339 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
03329ace TV |
2340 | |
2341 | ok = 0; | |
2342 | for (i = 0; i < 3; ++i) { | |
2343 | if (!in_use[i] || (l & (1 << bits[i]))) | |
2344 | ok++; | |
2345 | } | |
2346 | ||
2347 | if (ok == 3) | |
2348 | break; | |
2349 | ||
2350 | if (--t == 0) { | |
2351 | for (i = 0; i < 3; ++i) { | |
2352 | if (!in_use[i] || (l & (1 << bits[i]))) | |
2353 | continue; | |
2354 | ||
2355 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
2356 | "out of reset\n", i); | |
2357 | } | |
2358 | return -EIO; | |
2359 | } | |
2360 | } | |
2361 | ||
2362 | return 0; | |
2363 | } | |
2364 | ||
5bc416cb TV |
2365 | static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev) |
2366 | { | |
2367 | unsigned lanes = 0; | |
2368 | ||
2369 | if (dssdev->phy.dsi.clk_lane != 0) | |
2370 | lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1); | |
2371 | if (dssdev->phy.dsi.data1_lane != 0) | |
2372 | lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1); | |
2373 | if (dssdev->phy.dsi.data2_lane != 0) | |
2374 | lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1); | |
2375 | if (dssdev->phy.dsi.data3_lane != 0) | |
2376 | lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1); | |
2377 | if (dssdev->phy.dsi.data4_lane != 0) | |
2378 | lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1); | |
2379 | ||
2380 | return lanes; | |
2381 | } | |
2382 | ||
cc5c1850 | 2383 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
3de7a1dc | 2384 | { |
a72b64b9 | 2385 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 2386 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
65c62bb9 | 2387 | int r; |
75d7247c | 2388 | int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev); |
40885ab3 | 2389 | u32 l; |
3de7a1dc | 2390 | |
cc5c1850 | 2391 | DSSDBGF(); |
3de7a1dc | 2392 | |
5bc416cb TV |
2393 | r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
2394 | if (r) | |
2395 | return r; | |
d1f5857e | 2396 | |
a72b64b9 | 2397 | dsi_enable_scp_clk(dsidev); |
40885ab3 | 2398 | |
3de7a1dc TV |
2399 | /* A dummy read using the SCP interface to any DSIPHY register is |
2400 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2401 | * I/O. */ | |
a72b64b9 | 2402 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc | 2403 | |
a72b64b9 | 2404 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
65c62bb9 TV |
2405 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
2406 | r = -EIO; | |
2407 | goto err_scp_clk_dom; | |
3de7a1dc TV |
2408 | } |
2409 | ||
cc5c1850 | 2410 | dsi_set_lane_config(dssdev); |
3de7a1dc | 2411 | |
40885ab3 | 2412 | /* set TX STOP MODE timer to maximum for this operation */ |
a72b64b9 | 2413 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
40885ab3 TV |
2414 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
2415 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2416 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2417 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
a72b64b9 | 2418 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
40885ab3 | 2419 | |
f1da39d9 | 2420 | if (dsi->ulps_enabled) { |
75d7247c AT |
2421 | u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P; |
2422 | ||
65c62bb9 TV |
2423 | DSSDBG("manual ulps exit\n"); |
2424 | ||
40885ab3 TV |
2425 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
2426 | * stop state. DSS HW cannot do this via the normal | |
2427 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2428 | * that we are not in ULPS mode, and refuses to send the | |
2429 | * sequence. So we need to send the ULPS exit sequence | |
2430 | * manually. | |
2431 | */ | |
2432 | ||
75d7247c AT |
2433 | if (num_data_lanes_dssdev > 2) |
2434 | lane_mask |= DSI_DATA3_P; | |
2435 | ||
2436 | if (num_data_lanes_dssdev > 3) | |
2437 | lane_mask |= DSI_DATA4_P; | |
2438 | ||
2439 | dsi_cio_enable_lane_override(dssdev, lane_mask); | |
40885ab3 | 2440 | } |
3de7a1dc | 2441 | |
a72b64b9 | 2442 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
3de7a1dc | 2443 | if (r) |
65c62bb9 TV |
2444 | goto err_cio_pwr; |
2445 | ||
a72b64b9 | 2446 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
65c62bb9 TV |
2447 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
2448 | r = -ENODEV; | |
2449 | goto err_cio_pwr_dom; | |
2450 | } | |
2451 | ||
a72b64b9 AT |
2452 | dsi_if_enable(dsidev, true); |
2453 | dsi_if_enable(dsidev, false); | |
2454 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
3de7a1dc | 2455 | |
03329ace TV |
2456 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
2457 | if (r) | |
2458 | goto err_tx_clk_esc_rst; | |
2459 | ||
f1da39d9 | 2460 | if (dsi->ulps_enabled) { |
40885ab3 TV |
2461 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
2462 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2463 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2464 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2465 | ||
2466 | /* Disable the override. The lanes should be set to Mark-11 | |
2467 | * state by the HW */ | |
a72b64b9 | 2468 | dsi_cio_disable_lane_override(dsidev); |
40885ab3 TV |
2469 | } |
2470 | ||
2471 | /* FORCE_TX_STOP_MODE_IO */ | |
a72b64b9 | 2472 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
40885ab3 | 2473 | |
a72b64b9 | 2474 | dsi_cio_timings(dsidev); |
3de7a1dc | 2475 | |
8af6ff01 AT |
2476 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
2477 | /* DDR_CLK_ALWAYS_ON */ | |
2478 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, | |
2479 | dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13); | |
2480 | } | |
2481 | ||
f1da39d9 | 2482 | dsi->ulps_enabled = false; |
3de7a1dc TV |
2483 | |
2484 | DSSDBG("CIO init done\n"); | |
65c62bb9 TV |
2485 | |
2486 | return 0; | |
2487 | ||
03329ace | 2488 | err_tx_clk_esc_rst: |
a72b64b9 | 2489 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
65c62bb9 | 2490 | err_cio_pwr_dom: |
a72b64b9 | 2491 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
65c62bb9 | 2492 | err_cio_pwr: |
f1da39d9 | 2493 | if (dsi->ulps_enabled) |
a72b64b9 | 2494 | dsi_cio_disable_lane_override(dsidev); |
65c62bb9 | 2495 | err_scp_clk_dom: |
a72b64b9 | 2496 | dsi_disable_scp_clk(dsidev); |
5bc416cb | 2497 | dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2498 | return r; |
2499 | } | |
2500 | ||
5bc416cb | 2501 | static void dsi_cio_uninit(struct omap_dss_device *dssdev) |
3de7a1dc | 2502 | { |
5bc416cb | 2503 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 AT |
2504 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2505 | ||
8af6ff01 AT |
2506 | /* DDR_CLK_ALWAYS_ON */ |
2507 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
2508 | ||
a72b64b9 AT |
2509 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
2510 | dsi_disable_scp_clk(dsidev); | |
5bc416cb | 2511 | dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2512 | } |
2513 | ||
a72b64b9 AT |
2514 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
2515 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2516 | enum fifo_size size3, enum fifo_size size4) |
2517 | { | |
f1da39d9 | 2518 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2519 | u32 r = 0; |
2520 | int add = 0; | |
2521 | int i; | |
2522 | ||
f1da39d9 AT |
2523 | dsi->vc[0].fifo_size = size1; |
2524 | dsi->vc[1].fifo_size = size2; | |
2525 | dsi->vc[2].fifo_size = size3; | |
2526 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2527 | |
2528 | for (i = 0; i < 4; i++) { | |
2529 | u8 v; | |
f1da39d9 | 2530 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2531 | |
2532 | if (add + size > 4) { | |
2533 | DSSERR("Illegal FIFO configuration\n"); | |
2534 | BUG(); | |
2535 | } | |
2536 | ||
2537 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2538 | r |= v << (8 * i); | |
2539 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2540 | add += size; | |
2541 | } | |
2542 | ||
a72b64b9 | 2543 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2544 | } |
2545 | ||
a72b64b9 AT |
2546 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
2547 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2548 | enum fifo_size size3, enum fifo_size size4) |
2549 | { | |
f1da39d9 | 2550 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2551 | u32 r = 0; |
2552 | int add = 0; | |
2553 | int i; | |
2554 | ||
f1da39d9 AT |
2555 | dsi->vc[0].fifo_size = size1; |
2556 | dsi->vc[1].fifo_size = size2; | |
2557 | dsi->vc[2].fifo_size = size3; | |
2558 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2559 | |
2560 | for (i = 0; i < 4; i++) { | |
2561 | u8 v; | |
f1da39d9 | 2562 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2563 | |
2564 | if (add + size > 4) { | |
2565 | DSSERR("Illegal FIFO configuration\n"); | |
2566 | BUG(); | |
2567 | } | |
2568 | ||
2569 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2570 | r |= v << (8 * i); | |
2571 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2572 | add += size; | |
2573 | } | |
2574 | ||
a72b64b9 | 2575 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2576 | } |
2577 | ||
a72b64b9 | 2578 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
3de7a1dc TV |
2579 | { |
2580 | u32 r; | |
2581 | ||
a72b64b9 | 2582 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 2583 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
a72b64b9 | 2584 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 2585 | |
a72b64b9 | 2586 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
3de7a1dc TV |
2587 | DSSERR("TX_STOP bit not going down\n"); |
2588 | return -EIO; | |
2589 | } | |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
a72b64b9 | 2594 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
cf398fb3 | 2595 | { |
a72b64b9 | 2596 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
cf398fb3 AT |
2597 | } |
2598 | ||
2599 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2600 | { | |
2e868dbe AT |
2601 | struct dsi_packet_sent_handler_data *vp_data = |
2602 | (struct dsi_packet_sent_handler_data *) data; | |
2603 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); | |
f1da39d9 AT |
2604 | const int channel = dsi->update_channel; |
2605 | u8 bit = dsi->te_enabled ? 30 : 31; | |
cf398fb3 | 2606 | |
2e868dbe AT |
2607 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
2608 | complete(vp_data->completion); | |
cf398fb3 AT |
2609 | } |
2610 | ||
a72b64b9 | 2611 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
cf398fb3 | 2612 | { |
f1da39d9 | 2613 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2e868dbe AT |
2614 | DECLARE_COMPLETION_ONSTACK(completion); |
2615 | struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion }; | |
cf398fb3 AT |
2616 | int r = 0; |
2617 | u8 bit; | |
2618 | ||
f1da39d9 | 2619 | bit = dsi->te_enabled ? 30 : 31; |
cf398fb3 | 2620 | |
a72b64b9 | 2621 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2622 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2623 | if (r) |
2624 | goto err0; | |
2625 | ||
2626 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
a72b64b9 | 2627 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
cf398fb3 AT |
2628 | if (wait_for_completion_timeout(&completion, |
2629 | msecs_to_jiffies(10)) == 0) { | |
2630 | DSSERR("Failed to complete previous frame transfer\n"); | |
2631 | r = -EIO; | |
2632 | goto err1; | |
2633 | } | |
2634 | } | |
2635 | ||
a72b64b9 | 2636 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2637 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2638 | |
2639 | return 0; | |
2640 | err1: | |
a72b64b9 | 2641 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2642 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2643 | err0: |
2644 | return r; | |
2645 | } | |
2646 | ||
2647 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2648 | { | |
2e868dbe AT |
2649 | struct dsi_packet_sent_handler_data *l4_data = |
2650 | (struct dsi_packet_sent_handler_data *) data; | |
2651 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); | |
f1da39d9 | 2652 | const int channel = dsi->update_channel; |
cf398fb3 | 2653 | |
2e868dbe AT |
2654 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
2655 | complete(l4_data->completion); | |
cf398fb3 AT |
2656 | } |
2657 | ||
a72b64b9 | 2658 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
cf398fb3 | 2659 | { |
cf398fb3 | 2660 | DECLARE_COMPLETION_ONSTACK(completion); |
2e868dbe AT |
2661 | struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion }; |
2662 | int r = 0; | |
cf398fb3 | 2663 | |
a72b64b9 | 2664 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2665 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2666 | if (r) |
2667 | goto err0; | |
2668 | ||
2669 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
a72b64b9 | 2670 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
cf398fb3 AT |
2671 | if (wait_for_completion_timeout(&completion, |
2672 | msecs_to_jiffies(10)) == 0) { | |
2673 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2674 | r = -EIO; | |
2675 | goto err1; | |
2676 | } | |
2677 | } | |
2678 | ||
a72b64b9 | 2679 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2680 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2681 | |
2682 | return 0; | |
2683 | err1: | |
a72b64b9 | 2684 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2685 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2686 | err0: |
2687 | return r; | |
2688 | } | |
2689 | ||
a72b64b9 | 2690 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
cf398fb3 | 2691 | { |
f1da39d9 AT |
2692 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2693 | ||
a72b64b9 | 2694 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
cf398fb3 AT |
2695 | |
2696 | WARN_ON(in_interrupt()); | |
2697 | ||
a72b64b9 | 2698 | if (!dsi_vc_is_enabled(dsidev, channel)) |
cf398fb3 AT |
2699 | return 0; |
2700 | ||
d6049144 AT |
2701 | switch (dsi->vc[channel].source) { |
2702 | case DSI_VC_SOURCE_VP: | |
a72b64b9 | 2703 | return dsi_sync_vc_vp(dsidev, channel); |
d6049144 | 2704 | case DSI_VC_SOURCE_L4: |
a72b64b9 | 2705 | return dsi_sync_vc_l4(dsidev, channel); |
cf398fb3 AT |
2706 | default: |
2707 | BUG(); | |
2708 | } | |
2709 | } | |
2710 | ||
a72b64b9 AT |
2711 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
2712 | bool enable) | |
3de7a1dc | 2713 | { |
446f7bff TV |
2714 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2715 | channel, enable); | |
3de7a1dc TV |
2716 | |
2717 | enable = enable ? 1 : 0; | |
2718 | ||
a72b64b9 | 2719 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
3de7a1dc | 2720 | |
a72b64b9 AT |
2721 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
2722 | 0, enable) != enable) { | |
3de7a1dc TV |
2723 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
2724 | return -EIO; | |
2725 | } | |
2726 | ||
2727 | return 0; | |
2728 | } | |
2729 | ||
a72b64b9 | 2730 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
3de7a1dc TV |
2731 | { |
2732 | u32 r; | |
2733 | ||
2734 | DSSDBGF("%d", channel); | |
2735 | ||
a72b64b9 | 2736 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
3de7a1dc TV |
2737 | |
2738 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2739 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2740 | channel); | |
2741 | ||
2742 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2743 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2744 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2745 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2746 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2747 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2748 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
9613c02b AT |
2749 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
2750 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
3de7a1dc TV |
2751 | |
2752 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2753 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2754 | ||
a72b64b9 | 2755 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
3de7a1dc TV |
2756 | } |
2757 | ||
d6049144 AT |
2758 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
2759 | enum dsi_vc_source source) | |
3de7a1dc | 2760 | { |
f1da39d9 AT |
2761 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2762 | ||
d6049144 | 2763 | if (dsi->vc[channel].source == source) |
9ecd9684 | 2764 | return 0; |
3de7a1dc TV |
2765 | |
2766 | DSSDBGF("%d", channel); | |
2767 | ||
a72b64b9 | 2768 | dsi_sync_vc(dsidev, channel); |
cf398fb3 | 2769 | |
a72b64b9 | 2770 | dsi_vc_enable(dsidev, channel, 0); |
3de7a1dc | 2771 | |
9ecd9684 | 2772 | /* VC_BUSY */ |
a72b64b9 | 2773 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
3de7a1dc | 2774 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2775 | return -EIO; |
2776 | } | |
3de7a1dc | 2777 | |
d6049144 AT |
2778 | /* SOURCE, 0 = L4, 1 = video port */ |
2779 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); | |
3de7a1dc | 2780 | |
9613c02b | 2781 | /* DCS_CMD_ENABLE */ |
d6049144 AT |
2782 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
2783 | bool enable = source == DSI_VC_SOURCE_VP; | |
2784 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); | |
2785 | } | |
9613c02b | 2786 | |
a72b64b9 | 2787 | dsi_vc_enable(dsidev, channel, 1); |
3de7a1dc | 2788 | |
d6049144 | 2789 | dsi->vc[channel].source = source; |
9ecd9684 TV |
2790 | |
2791 | return 0; | |
3de7a1dc TV |
2792 | } |
2793 | ||
1ffefe75 AT |
2794 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
2795 | bool enable) | |
3de7a1dc | 2796 | { |
a72b64b9 AT |
2797 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
2798 | ||
3de7a1dc TV |
2799 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
2800 | ||
a72b64b9 | 2801 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
61140c9a | 2802 | |
a72b64b9 AT |
2803 | dsi_vc_enable(dsidev, channel, 0); |
2804 | dsi_if_enable(dsidev, 0); | |
3de7a1dc | 2805 | |
a72b64b9 | 2806 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
3de7a1dc | 2807 | |
a72b64b9 AT |
2808 | dsi_vc_enable(dsidev, channel, 1); |
2809 | dsi_if_enable(dsidev, 1); | |
3de7a1dc | 2810 | |
a72b64b9 | 2811 | dsi_force_tx_stop_mode_io(dsidev); |
8af6ff01 AT |
2812 | |
2813 | /* start the DDR clock by sending a NULL packet */ | |
2814 | if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable) | |
2815 | dsi_vc_send_null(dssdev, channel); | |
3de7a1dc | 2816 | } |
61140c9a | 2817 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
3de7a1dc | 2818 | |
a72b64b9 | 2819 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
3de7a1dc | 2820 | { |
a72b64b9 | 2821 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2822 | u32 val; |
a72b64b9 | 2823 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
3de7a1dc TV |
2824 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
2825 | (val >> 0) & 0xff, | |
2826 | (val >> 8) & 0xff, | |
2827 | (val >> 16) & 0xff, | |
2828 | (val >> 24) & 0xff); | |
2829 | } | |
2830 | } | |
2831 | ||
2832 | static void dsi_show_rx_ack_with_err(u16 err) | |
2833 | { | |
2834 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2835 | if (err & (1 << 0)) | |
2836 | DSSERR("\t\tSoT Error\n"); | |
2837 | if (err & (1 << 1)) | |
2838 | DSSERR("\t\tSoT Sync Error\n"); | |
2839 | if (err & (1 << 2)) | |
2840 | DSSERR("\t\tEoT Sync Error\n"); | |
2841 | if (err & (1 << 3)) | |
2842 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2843 | if (err & (1 << 4)) | |
2844 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2845 | if (err & (1 << 5)) | |
2846 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2847 | if (err & (1 << 6)) | |
2848 | DSSERR("\t\tFalse Control Error\n"); | |
2849 | if (err & (1 << 7)) | |
2850 | DSSERR("\t\t(reserved7)\n"); | |
2851 | if (err & (1 << 8)) | |
2852 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2853 | if (err & (1 << 9)) | |
2854 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2855 | if (err & (1 << 10)) | |
2856 | DSSERR("\t\tChecksum Error\n"); | |
2857 | if (err & (1 << 11)) | |
2858 | DSSERR("\t\tData type not recognized\n"); | |
2859 | if (err & (1 << 12)) | |
2860 | DSSERR("\t\tInvalid VC ID\n"); | |
2861 | if (err & (1 << 13)) | |
2862 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2863 | if (err & (1 << 14)) | |
2864 | DSSERR("\t\t(reserved14)\n"); | |
2865 | if (err & (1 << 15)) | |
2866 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2867 | } | |
2868 | ||
a72b64b9 AT |
2869 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
2870 | int channel) | |
3de7a1dc TV |
2871 | { |
2872 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 2873 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc TV |
2874 | u32 val; |
2875 | u8 dt; | |
a72b64b9 | 2876 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
86a7867e | 2877 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc | 2878 | dt = FLD_GET(val, 5, 0); |
7a7c48f9 | 2879 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2880 | u16 err = FLD_GET(val, 23, 8); |
2881 | dsi_show_rx_ack_with_err(err); | |
7a7c48f9 | 2882 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
86a7867e | 2883 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc | 2884 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2885 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
86a7867e | 2886 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc | 2887 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2888 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
86a7867e | 2889 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc | 2890 | FLD_GET(val, 23, 8)); |
a72b64b9 | 2891 | dsi_vc_flush_long_data(dsidev, channel); |
3de7a1dc TV |
2892 | } else { |
2893 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2894 | } | |
2895 | } | |
2896 | return 0; | |
2897 | } | |
2898 | ||
a72b64b9 | 2899 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
3de7a1dc | 2900 | { |
f1da39d9 AT |
2901 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2902 | ||
2903 | if (dsi->debug_write || dsi->debug_read) | |
3de7a1dc TV |
2904 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2905 | ||
a72b64b9 | 2906 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2907 | |
a72b64b9 AT |
2908 | /* RX_FIFO_NOT_EMPTY */ |
2909 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
3de7a1dc | 2910 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
a72b64b9 | 2911 | dsi_vc_flush_receive_data(dsidev, channel); |
3de7a1dc TV |
2912 | } |
2913 | ||
a72b64b9 | 2914 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
3de7a1dc TV |
2915 | |
2916 | return 0; | |
2917 | } | |
2918 | ||
1ffefe75 | 2919 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2920 | { |
a72b64b9 | 2921 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f36a06e7 | 2922 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2923 | int r = 0; |
2924 | u32 err; | |
2925 | ||
a72b64b9 | 2926 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2927 | &completion, DSI_VC_IRQ_BTA); |
2928 | if (r) | |
2929 | goto err0; | |
3de7a1dc | 2930 | |
a72b64b9 | 2931 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2932 | DSI_IRQ_ERROR_MASK); |
3de7a1dc | 2933 | if (r) |
f36a06e7 | 2934 | goto err1; |
3de7a1dc | 2935 | |
a72b64b9 | 2936 | r = dsi_vc_send_bta(dsidev, channel); |
773b30b2 TV |
2937 | if (r) |
2938 | goto err2; | |
2939 | ||
f36a06e7 | 2940 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2941 | msecs_to_jiffies(500)) == 0) { |
2942 | DSSERR("Failed to receive BTA\n"); | |
2943 | r = -EIO; | |
773b30b2 | 2944 | goto err2; |
3de7a1dc TV |
2945 | } |
2946 | ||
a72b64b9 | 2947 | err = dsi_get_errors(dsidev); |
3de7a1dc TV |
2948 | if (err) { |
2949 | DSSERR("Error while sending BTA: %x\n", err); | |
2950 | r = -EIO; | |
773b30b2 | 2951 | goto err2; |
3de7a1dc | 2952 | } |
773b30b2 | 2953 | err2: |
a72b64b9 | 2954 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2955 | DSI_IRQ_ERROR_MASK); |
f36a06e7 | 2956 | err1: |
a72b64b9 | 2957 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2958 | &completion, DSI_VC_IRQ_BTA); |
2959 | err0: | |
3de7a1dc TV |
2960 | return r; |
2961 | } | |
2962 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); | |
2963 | ||
a72b64b9 AT |
2964 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
2965 | int channel, u8 data_type, u16 len, u8 ecc) | |
3de7a1dc | 2966 | { |
f1da39d9 | 2967 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2968 | u32 val; |
2969 | u8 data_id; | |
2970 | ||
a72b64b9 | 2971 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2972 | |
f1da39d9 | 2973 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2974 | |
2975 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2976 | FLD_VAL(ecc, 31, 24); | |
2977 | ||
a72b64b9 | 2978 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
3de7a1dc TV |
2979 | } |
2980 | ||
a72b64b9 AT |
2981 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
2982 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) | |
3de7a1dc TV |
2983 | { |
2984 | u32 val; | |
2985 | ||
2986 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2987 | ||
2988 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2989 | b1, b2, b3, b4, val); */ | |
2990 | ||
a72b64b9 | 2991 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
3de7a1dc TV |
2992 | } |
2993 | ||
a72b64b9 AT |
2994 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
2995 | u8 data_type, u8 *data, u16 len, u8 ecc) | |
3de7a1dc TV |
2996 | { |
2997 | /*u32 val; */ | |
f1da39d9 | 2998 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2999 | int i; |
3000 | u8 *p; | |
3001 | int r = 0; | |
3002 | u8 b1, b2, b3, b4; | |
3003 | ||
f1da39d9 | 3004 | if (dsi->debug_write) |
3de7a1dc TV |
3005 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
3006 | ||
3007 | /* len + header */ | |
f1da39d9 | 3008 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { |
3de7a1dc TV |
3009 | DSSERR("unable to send long packet: packet too long.\n"); |
3010 | return -EINVAL; | |
3011 | } | |
3012 | ||
d6049144 | 3013 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3014 | |
a72b64b9 | 3015 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
3de7a1dc | 3016 | |
3de7a1dc TV |
3017 | p = data; |
3018 | for (i = 0; i < len >> 2; i++) { | |
f1da39d9 | 3019 | if (dsi->debug_write) |
3de7a1dc | 3020 | DSSDBG("\tsending full packet %d\n", i); |
3de7a1dc TV |
3021 | |
3022 | b1 = *p++; | |
3023 | b2 = *p++; | |
3024 | b3 = *p++; | |
3025 | b4 = *p++; | |
3026 | ||
a72b64b9 | 3027 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
3de7a1dc TV |
3028 | } |
3029 | ||
3030 | i = len % 4; | |
3031 | if (i) { | |
3032 | b1 = 0; b2 = 0; b3 = 0; | |
3033 | ||
f1da39d9 | 3034 | if (dsi->debug_write) |
3de7a1dc TV |
3035 | DSSDBG("\tsending remainder bytes %d\n", i); |
3036 | ||
3037 | switch (i) { | |
3038 | case 3: | |
3039 | b1 = *p++; | |
3040 | b2 = *p++; | |
3041 | b3 = *p++; | |
3042 | break; | |
3043 | case 2: | |
3044 | b1 = *p++; | |
3045 | b2 = *p++; | |
3046 | break; | |
3047 | case 1: | |
3048 | b1 = *p++; | |
3049 | break; | |
3050 | } | |
3051 | ||
a72b64b9 | 3052 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
3de7a1dc TV |
3053 | } |
3054 | ||
3055 | return r; | |
3056 | } | |
3057 | ||
a72b64b9 AT |
3058 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
3059 | u8 data_type, u16 data, u8 ecc) | |
3de7a1dc | 3060 | { |
f1da39d9 | 3061 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3062 | u32 r; |
3063 | u8 data_id; | |
3064 | ||
a72b64b9 | 3065 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 3066 | |
f1da39d9 | 3067 | if (dsi->debug_write) |
3de7a1dc TV |
3068 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
3069 | channel, | |
3070 | data_type, data & 0xff, (data >> 8) & 0xff); | |
3071 | ||
d6049144 | 3072 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3073 | |
a72b64b9 | 3074 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
3de7a1dc TV |
3075 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
3076 | return -EINVAL; | |
3077 | } | |
3078 | ||
f1da39d9 | 3079 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
3080 | |
3081 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
3082 | ||
a72b64b9 | 3083 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
3de7a1dc TV |
3084 | |
3085 | return 0; | |
3086 | } | |
3087 | ||
1ffefe75 | 3088 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 3089 | { |
a72b64b9 | 3090 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
a72b64b9 | 3091 | |
18b7d099 AT |
3092 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, |
3093 | 0, 0); | |
3de7a1dc TV |
3094 | } |
3095 | EXPORT_SYMBOL(dsi_vc_send_null); | |
3096 | ||
6ff8aa31 AT |
3097 | static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev, |
3098 | int channel, u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3099 | { |
a72b64b9 | 3100 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3101 | int r; |
3102 | ||
6ff8aa31 AT |
3103 | if (len == 0) { |
3104 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
7a7c48f9 | 3105 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3106 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
3107 | } else if (len == 1) { | |
3108 | r = dsi_vc_send_short(dsidev, channel, | |
3109 | type == DSS_DSI_CONTENT_GENERIC ? | |
3110 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
7a7c48f9 | 3111 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
3de7a1dc | 3112 | } else if (len == 2) { |
7a7c48f9 | 3113 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3114 | type == DSS_DSI_CONTENT_GENERIC ? |
3115 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
7a7c48f9 | 3116 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
3de7a1dc TV |
3117 | data[0] | (data[1] << 8), 0); |
3118 | } else { | |
6ff8aa31 AT |
3119 | r = dsi_vc_send_long(dsidev, channel, |
3120 | type == DSS_DSI_CONTENT_GENERIC ? | |
3121 | MIPI_DSI_GENERIC_LONG_WRITE : | |
3122 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
3de7a1dc TV |
3123 | } |
3124 | ||
3125 | return r; | |
3126 | } | |
6ff8aa31 AT |
3127 | |
3128 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, | |
3129 | u8 *data, int len) | |
3130 | { | |
3131 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3132 | DSS_DSI_CONTENT_DCS); | |
3133 | } | |
3de7a1dc TV |
3134 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
3135 | ||
6ff8aa31 AT |
3136 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
3137 | u8 *data, int len) | |
3138 | { | |
3139 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3140 | DSS_DSI_CONTENT_GENERIC); | |
3141 | } | |
3142 | EXPORT_SYMBOL(dsi_vc_generic_write_nosync); | |
3143 | ||
3144 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, | |
3145 | u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3146 | { |
a72b64b9 | 3147 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3148 | int r; |
3149 | ||
6ff8aa31 | 3150 | r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type); |
3de7a1dc | 3151 | if (r) |
5d68e032 | 3152 | goto err; |
3de7a1dc | 3153 | |
1ffefe75 | 3154 | r = dsi_vc_send_bta_sync(dssdev, channel); |
5d68e032 TV |
3155 | if (r) |
3156 | goto err; | |
3de7a1dc | 3157 | |
a72b64b9 AT |
3158 | /* RX_FIFO_NOT_EMPTY */ |
3159 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
b63ac1e3 | 3160 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
a72b64b9 | 3161 | dsi_vc_flush_receive_data(dsidev, channel); |
b63ac1e3 TV |
3162 | r = -EIO; |
3163 | goto err; | |
3164 | } | |
3165 | ||
5d68e032 TV |
3166 | return 0; |
3167 | err: | |
6ff8aa31 | 3168 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
5d68e032 | 3169 | channel, data[0], len); |
3de7a1dc TV |
3170 | return r; |
3171 | } | |
6ff8aa31 AT |
3172 | |
3173 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
3174 | int len) | |
3175 | { | |
3176 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3177 | DSS_DSI_CONTENT_DCS); | |
3178 | } | |
3de7a1dc TV |
3179 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
3180 | ||
6ff8aa31 AT |
3181 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
3182 | int len) | |
3183 | { | |
3184 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3185 | DSS_DSI_CONTENT_GENERIC); | |
3186 | } | |
3187 | EXPORT_SYMBOL(dsi_vc_generic_write); | |
3188 | ||
1ffefe75 | 3189 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
828c48f8 | 3190 | { |
1ffefe75 | 3191 | return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1); |
828c48f8 TV |
3192 | } |
3193 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); | |
3194 | ||
6ff8aa31 AT |
3195 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel) |
3196 | { | |
3197 | return dsi_vc_generic_write(dssdev, channel, NULL, 0); | |
3198 | } | |
3199 | EXPORT_SYMBOL(dsi_vc_generic_write_0); | |
3200 | ||
1ffefe75 AT |
3201 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
3202 | u8 param) | |
828c48f8 TV |
3203 | { |
3204 | u8 buf[2]; | |
3205 | buf[0] = dcs_cmd; | |
3206 | buf[1] = param; | |
1ffefe75 | 3207 | return dsi_vc_dcs_write(dssdev, channel, buf, 2); |
828c48f8 TV |
3208 | } |
3209 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); | |
3210 | ||
6ff8aa31 AT |
3211 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
3212 | u8 param) | |
3213 | { | |
3214 | return dsi_vc_generic_write(dssdev, channel, ¶m, 1); | |
3215 | } | |
3216 | EXPORT_SYMBOL(dsi_vc_generic_write_1); | |
3217 | ||
3218 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
3219 | u8 param1, u8 param2) | |
3220 | { | |
3221 | u8 buf[2]; | |
3222 | buf[0] = param1; | |
3223 | buf[1] = param2; | |
3224 | return dsi_vc_generic_write(dssdev, channel, buf, 2); | |
3225 | } | |
3226 | EXPORT_SYMBOL(dsi_vc_generic_write_2); | |
3227 | ||
b850975c AT |
3228 | static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev, |
3229 | int channel, u8 dcs_cmd) | |
3de7a1dc | 3230 | { |
a72b64b9 | 3231 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 3232 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3233 | int r; |
3234 | ||
f1da39d9 | 3235 | if (dsi->debug_read) |
b850975c AT |
3236 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
3237 | channel, dcs_cmd); | |
3de7a1dc | 3238 | |
7a7c48f9 | 3239 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
b850975c AT |
3240 | if (r) { |
3241 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
3242 | " failed\n", channel, dcs_cmd); | |
3243 | return r; | |
3244 | } | |
3de7a1dc | 3245 | |
b850975c AT |
3246 | return 0; |
3247 | } | |
3248 | ||
b3b89c05 AT |
3249 | static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev, |
3250 | int channel, u8 *reqdata, int reqlen) | |
3251 | { | |
3252 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3253 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3254 | u16 data; | |
3255 | u8 data_type; | |
3256 | int r; | |
3257 | ||
3258 | if (dsi->debug_read) | |
3259 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
3260 | channel, reqlen); | |
3261 | ||
3262 | if (reqlen == 0) { | |
3263 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
3264 | data = 0; | |
3265 | } else if (reqlen == 1) { | |
3266 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
3267 | data = reqdata[0]; | |
3268 | } else if (reqlen == 2) { | |
3269 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
3270 | data = reqdata[0] | (reqdata[1] << 8); | |
3271 | } else { | |
3272 | BUG(); | |
3273 | } | |
3274 | ||
3275 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); | |
3276 | if (r) { | |
3277 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
3278 | " failed\n", channel, reqlen); | |
3279 | return r; | |
3280 | } | |
3281 | ||
3282 | return 0; | |
3283 | } | |
3284 | ||
3285 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, | |
3286 | u8 *buf, int buflen, enum dss_dsi_content_type type) | |
b850975c AT |
3287 | { |
3288 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3289 | u32 val; | |
3290 | u8 dt; | |
3291 | int r; | |
3de7a1dc TV |
3292 | |
3293 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 3294 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
3de7a1dc | 3295 | DSSERR("RX fifo empty when trying to read.\n"); |
5d68e032 TV |
3296 | r = -EIO; |
3297 | goto err; | |
3de7a1dc TV |
3298 | } |
3299 | ||
a72b64b9 | 3300 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 3301 | if (dsi->debug_read) |
3de7a1dc TV |
3302 | DSSDBG("\theader: %08x\n", val); |
3303 | dt = FLD_GET(val, 5, 0); | |
7a7c48f9 | 3304 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
3305 | u16 err = FLD_GET(val, 23, 8); |
3306 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
3307 | r = -EIO; |
3308 | goto err; | |
3de7a1dc | 3309 | |
b3b89c05 AT |
3310 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3311 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
3312 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
3de7a1dc | 3313 | u8 data = FLD_GET(val, 15, 8); |
f1da39d9 | 3314 | if (dsi->debug_read) |
b3b89c05 AT |
3315 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
3316 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3317 | "DCS", data); | |
3de7a1dc | 3318 | |
5d68e032 TV |
3319 | if (buflen < 1) { |
3320 | r = -EIO; | |
3321 | goto err; | |
3322 | } | |
3de7a1dc TV |
3323 | |
3324 | buf[0] = data; | |
3325 | ||
3326 | return 1; | |
b3b89c05 AT |
3327 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3328 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
3329 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
3de7a1dc | 3330 | u16 data = FLD_GET(val, 23, 8); |
f1da39d9 | 3331 | if (dsi->debug_read) |
b3b89c05 AT |
3332 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
3333 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3334 | "DCS", data); | |
3de7a1dc | 3335 | |
5d68e032 TV |
3336 | if (buflen < 2) { |
3337 | r = -EIO; | |
3338 | goto err; | |
3339 | } | |
3de7a1dc TV |
3340 | |
3341 | buf[0] = data & 0xff; | |
3342 | buf[1] = (data >> 8) & 0xff; | |
3343 | ||
3344 | return 2; | |
b3b89c05 AT |
3345 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3346 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
3347 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3de7a1dc TV |
3348 | int w; |
3349 | int len = FLD_GET(val, 23, 8); | |
f1da39d9 | 3350 | if (dsi->debug_read) |
b3b89c05 AT |
3351 | DSSDBG("\t%s long response, len %d\n", |
3352 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3353 | "DCS", len); | |
3de7a1dc | 3354 | |
5d68e032 TV |
3355 | if (len > buflen) { |
3356 | r = -EIO; | |
3357 | goto err; | |
3358 | } | |
3de7a1dc TV |
3359 | |
3360 | /* two byte checksum ends the packet, not included in len */ | |
3361 | for (w = 0; w < len + 2;) { | |
3362 | int b; | |
a72b64b9 AT |
3363 | val = dsi_read_reg(dsidev, |
3364 | DSI_VC_SHORT_PACKET_HEADER(channel)); | |
f1da39d9 | 3365 | if (dsi->debug_read) |
3de7a1dc TV |
3366 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
3367 | (val >> 0) & 0xff, | |
3368 | (val >> 8) & 0xff, | |
3369 | (val >> 16) & 0xff, | |
3370 | (val >> 24) & 0xff); | |
3371 | ||
3372 | for (b = 0; b < 4; ++b) { | |
3373 | if (w < len) | |
3374 | buf[w] = (val >> (b * 8)) & 0xff; | |
3375 | /* we discard the 2 byte checksum */ | |
3376 | ++w; | |
3377 | } | |
3378 | } | |
3379 | ||
3380 | return len; | |
3de7a1dc TV |
3381 | } else { |
3382 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
3383 | r = -EIO; |
3384 | goto err; | |
3de7a1dc | 3385 | } |
5d68e032 TV |
3386 | |
3387 | BUG(); | |
3388 | err: | |
b3b89c05 AT |
3389 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
3390 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
b850975c | 3391 | |
5d68e032 | 3392 | return r; |
b850975c AT |
3393 | } |
3394 | ||
3395 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | |
3396 | u8 *buf, int buflen) | |
3397 | { | |
3398 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3399 | int r; | |
3400 | ||
3401 | r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd); | |
3402 | if (r) | |
3403 | goto err; | |
5d68e032 | 3404 | |
b850975c AT |
3405 | r = dsi_vc_send_bta_sync(dssdev, channel); |
3406 | if (r) | |
3407 | goto err; | |
3408 | ||
b3b89c05 AT |
3409 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
3410 | DSS_DSI_CONTENT_DCS); | |
b850975c AT |
3411 | if (r < 0) |
3412 | goto err; | |
3413 | ||
3414 | if (r != buflen) { | |
3415 | r = -EIO; | |
3416 | goto err; | |
3417 | } | |
3418 | ||
3419 | return 0; | |
3420 | err: | |
3421 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3422 | return r; | |
3de7a1dc TV |
3423 | } |
3424 | EXPORT_SYMBOL(dsi_vc_dcs_read); | |
3425 | ||
b3b89c05 AT |
3426 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
3427 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3428 | { | |
3429 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3430 | int r; | |
3431 | ||
3432 | r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen); | |
3433 | if (r) | |
3434 | return r; | |
3435 | ||
3436 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3437 | if (r) | |
3438 | return r; | |
3439 | ||
3440 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3441 | DSS_DSI_CONTENT_GENERIC); | |
3442 | if (r < 0) | |
3443 | return r; | |
3444 | ||
3445 | if (r != buflen) { | |
3446 | r = -EIO; | |
3447 | return r; | |
3448 | } | |
3449 | ||
3450 | return 0; | |
3451 | } | |
3452 | ||
3453 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, | |
3454 | int buflen) | |
3455 | { | |
3456 | int r; | |
3457 | ||
3458 | r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen); | |
3459 | if (r) { | |
3460 | DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel); | |
3461 | return r; | |
3462 | } | |
3463 | ||
3464 | return 0; | |
3465 | } | |
3466 | EXPORT_SYMBOL(dsi_vc_generic_read_0); | |
3467 | ||
3468 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
3469 | u8 *buf, int buflen) | |
3470 | { | |
3471 | int r; | |
3472 | ||
3473 | r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen); | |
3474 | if (r) { | |
3475 | DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel); | |
3476 | return r; | |
3477 | } | |
3478 | ||
3479 | return 0; | |
3480 | } | |
3481 | EXPORT_SYMBOL(dsi_vc_generic_read_1); | |
3482 | ||
3483 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
3484 | u8 param1, u8 param2, u8 *buf, int buflen) | |
3485 | { | |
3486 | int r; | |
3487 | u8 reqdata[2]; | |
3488 | ||
3489 | reqdata[0] = param1; | |
3490 | reqdata[1] = param2; | |
3491 | ||
3492 | r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen); | |
3493 | if (r) { | |
3494 | DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel); | |
3495 | return r; | |
3496 | } | |
3497 | ||
3498 | return 0; | |
3499 | } | |
3500 | EXPORT_SYMBOL(dsi_vc_generic_read_2); | |
3501 | ||
1ffefe75 AT |
3502 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
3503 | u16 len) | |
3de7a1dc | 3504 | { |
a72b64b9 AT |
3505 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3506 | ||
7a7c48f9 AT |
3507 | return dsi_vc_send_short(dsidev, channel, |
3508 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); | |
3de7a1dc TV |
3509 | } |
3510 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); | |
3511 | ||
a72b64b9 | 3512 | static int dsi_enter_ulps(struct platform_device *dsidev) |
40885ab3 | 3513 | { |
f1da39d9 | 3514 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
40885ab3 TV |
3515 | DECLARE_COMPLETION_ONSTACK(completion); |
3516 | int r; | |
3517 | ||
3518 | DSSDBGF(); | |
3519 | ||
a72b64b9 | 3520 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
40885ab3 | 3521 | |
f1da39d9 | 3522 | WARN_ON(dsi->ulps_enabled); |
40885ab3 | 3523 | |
f1da39d9 | 3524 | if (dsi->ulps_enabled) |
40885ab3 TV |
3525 | return 0; |
3526 | ||
a72b64b9 | 3527 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
40885ab3 TV |
3528 | DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n"); |
3529 | return -EIO; | |
3530 | } | |
3531 | ||
a72b64b9 AT |
3532 | dsi_sync_vc(dsidev, 0); |
3533 | dsi_sync_vc(dsidev, 1); | |
3534 | dsi_sync_vc(dsidev, 2); | |
3535 | dsi_sync_vc(dsidev, 3); | |
40885ab3 | 3536 | |
a72b64b9 | 3537 | dsi_force_tx_stop_mode_io(dsidev); |
40885ab3 | 3538 | |
a72b64b9 AT |
3539 | dsi_vc_enable(dsidev, 0, false); |
3540 | dsi_vc_enable(dsidev, 1, false); | |
3541 | dsi_vc_enable(dsidev, 2, false); | |
3542 | dsi_vc_enable(dsidev, 3, false); | |
40885ab3 | 3543 | |
a72b64b9 | 3544 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
40885ab3 TV |
3545 | DSSERR("HS busy when enabling ULPS\n"); |
3546 | return -EIO; | |
3547 | } | |
3548 | ||
a72b64b9 | 3549 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
40885ab3 TV |
3550 | DSSERR("LP busy when enabling ULPS\n"); |
3551 | return -EIO; | |
3552 | } | |
3553 | ||
a72b64b9 | 3554 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3555 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3556 | if (r) | |
3557 | return r; | |
3558 | ||
3559 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ | |
3560 | /* LANEx_ULPS_SIG2 */ | |
a72b64b9 AT |
3561 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2), |
3562 | 7, 5); | |
40885ab3 TV |
3563 | |
3564 | if (wait_for_completion_timeout(&completion, | |
3565 | msecs_to_jiffies(1000)) == 0) { | |
3566 | DSSERR("ULPS enable timeout\n"); | |
3567 | r = -EIO; | |
3568 | goto err; | |
3569 | } | |
3570 | ||
a72b64b9 | 3571 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3572 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3573 | ||
8ef0e614 TV |
3574 | /* Reset LANEx_ULPS_SIG2 */ |
3575 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2), | |
3576 | 7, 5); | |
3577 | ||
a72b64b9 | 3578 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
40885ab3 | 3579 | |
a72b64b9 | 3580 | dsi_if_enable(dsidev, false); |
40885ab3 | 3581 | |
f1da39d9 | 3582 | dsi->ulps_enabled = true; |
40885ab3 TV |
3583 | |
3584 | return 0; | |
3585 | ||
3586 | err: | |
a72b64b9 | 3587 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3588 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3589 | return r; | |
3590 | } | |
3591 | ||
a72b64b9 AT |
3592 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
3593 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3594 | { |
3de7a1dc | 3595 | unsigned long fck; |
4ffa3571 TV |
3596 | unsigned long total_ticks; |
3597 | u32 r; | |
3de7a1dc | 3598 | |
4ffa3571 | 3599 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3600 | |
4ffa3571 | 3601 | /* ticks in DSI_FCK */ |
a72b64b9 | 3602 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3603 | |
a72b64b9 | 3604 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3605 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
4ffa3571 TV |
3606 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
3607 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc | 3608 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
a72b64b9 | 3609 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3610 | |
4ffa3571 TV |
3611 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3612 | ||
3613 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3614 | total_ticks, | |
3615 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3616 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3617 | } |
3618 | ||
a72b64b9 AT |
3619 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
3620 | bool x8, bool x16) | |
3de7a1dc | 3621 | { |
3de7a1dc | 3622 | unsigned long fck; |
4ffa3571 TV |
3623 | unsigned long total_ticks; |
3624 | u32 r; | |
3625 | ||
3626 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
3627 | |
3628 | /* ticks in DSI_FCK */ | |
a72b64b9 | 3629 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3630 | |
a72b64b9 | 3631 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3632 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
4ffa3571 TV |
3633 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
3634 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc | 3635 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
a72b64b9 | 3636 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3637 | |
4ffa3571 TV |
3638 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
3639 | ||
3640 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3641 | total_ticks, | |
3642 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3643 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3644 | } |
3645 | ||
a72b64b9 AT |
3646 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
3647 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3648 | { |
3de7a1dc | 3649 | unsigned long fck; |
4ffa3571 TV |
3650 | unsigned long total_ticks; |
3651 | u32 r; | |
3de7a1dc | 3652 | |
4ffa3571 | 3653 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3654 | |
4ffa3571 | 3655 | /* ticks in DSI_FCK */ |
a72b64b9 | 3656 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3657 | |
a72b64b9 | 3658 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3659 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
4ffa3571 TV |
3660 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
3661 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc | 3662 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
a72b64b9 | 3663 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3664 | |
4ffa3571 TV |
3665 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3666 | ||
3667 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3668 | total_ticks, | |
3669 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3670 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3671 | } |
3672 | ||
a72b64b9 AT |
3673 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
3674 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3675 | { |
3de7a1dc | 3676 | unsigned long fck; |
4ffa3571 TV |
3677 | unsigned long total_ticks; |
3678 | u32 r; | |
3de7a1dc | 3679 | |
4ffa3571 | 3680 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3681 | |
4ffa3571 | 3682 | /* ticks in TxByteClkHS */ |
a72b64b9 | 3683 | fck = dsi_get_txbyteclkhs(dsidev); |
3de7a1dc | 3684 | |
a72b64b9 | 3685 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3686 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
4ffa3571 TV |
3687 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
3688 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc | 3689 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
a72b64b9 | 3690 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3691 | |
4ffa3571 TV |
3692 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3693 | ||
3694 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3695 | total_ticks, | |
3696 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3697 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc | 3698 | } |
8af6ff01 AT |
3699 | |
3700 | static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev) | |
3701 | { | |
3702 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3703 | int num_line_buffers; | |
3704 | ||
3705 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3706 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); | |
3707 | unsigned line_buf_size = dsi_get_line_buf_size(dsidev); | |
3708 | struct omap_video_timings *timings = &dssdev->panel.timings; | |
3709 | /* | |
3710 | * Don't use line buffers if width is greater than the video | |
3711 | * port's line buffer size | |
3712 | */ | |
3713 | if (line_buf_size <= timings->x_res * bpp / 8) | |
3714 | num_line_buffers = 0; | |
3715 | else | |
3716 | num_line_buffers = 2; | |
3717 | } else { | |
3718 | /* Use maximum number of line buffers in command mode */ | |
3719 | num_line_buffers = 2; | |
3720 | } | |
3721 | ||
3722 | /* LINE_BUFFER */ | |
3723 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); | |
3724 | } | |
3725 | ||
3726 | static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev) | |
3727 | { | |
3728 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3729 | int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol; | |
3730 | int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol; | |
3731 | int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol; | |
3732 | bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end; | |
3733 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; | |
3734 | u32 r; | |
3735 | ||
3736 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3737 | r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */ | |
3738 | r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */ | |
3739 | r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */ | |
3740 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ | |
3741 | r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ | |
3742 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ | |
3743 | r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */ | |
3744 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3745 | } | |
3746 | ||
3747 | static void dsi_config_blanking_modes(struct omap_dss_device *dssdev) | |
3748 | { | |
3749 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3750 | int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode; | |
3751 | int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode; | |
3752 | int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode; | |
3753 | int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode; | |
3754 | u32 r; | |
3755 | ||
3756 | /* | |
3757 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods | |
3758 | * 1 = Long blanking packets are sent in corresponding blanking periods | |
3759 | */ | |
3760 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3761 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ | |
3762 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ | |
3763 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ | |
3764 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ | |
3765 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3766 | } | |
3767 | ||
3de7a1dc TV |
3768 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
3769 | { | |
a72b64b9 | 3770 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3771 | u32 r; |
3772 | int buswidth = 0; | |
3773 | ||
a72b64b9 | 3774 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3775 | DSI_FIFO_SIZE_32, |
3776 | DSI_FIFO_SIZE_32, | |
3777 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 3778 | |
a72b64b9 | 3779 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3780 | DSI_FIFO_SIZE_32, |
3781 | DSI_FIFO_SIZE_32, | |
3782 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
3783 | |
3784 | /* XXX what values for the timeouts? */ | |
a72b64b9 AT |
3785 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
3786 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); | |
3787 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); | |
3788 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); | |
3de7a1dc | 3789 | |
a3b3cc2b | 3790 | switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) { |
3de7a1dc TV |
3791 | case 16: |
3792 | buswidth = 0; | |
3793 | break; | |
3794 | case 18: | |
3795 | buswidth = 1; | |
3796 | break; | |
3797 | case 24: | |
3798 | buswidth = 2; | |
3799 | break; | |
3800 | default: | |
3801 | BUG(); | |
3802 | } | |
3803 | ||
a72b64b9 | 3804 | r = dsi_read_reg(dsidev, DSI_CTRL); |
3de7a1dc TV |
3805 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
3806 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3807 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3808 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3809 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3810 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3de7a1dc TV |
3811 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
3812 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
9613c02b AT |
3813 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
3814 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
3815 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3816 | r = FLD_MOD(r, 0, 25, 25); | |
3817 | } | |
3de7a1dc | 3818 | |
a72b64b9 | 3819 | dsi_write_reg(dsidev, DSI_CTRL, r); |
3de7a1dc | 3820 | |
8af6ff01 AT |
3821 | dsi_config_vp_num_line_buffers(dssdev); |
3822 | ||
3823 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3824 | dsi_config_vp_sync_events(dssdev); | |
3825 | dsi_config_blanking_modes(dssdev); | |
3826 | } | |
3827 | ||
a72b64b9 AT |
3828 | dsi_vc_initial_config(dsidev, 0); |
3829 | dsi_vc_initial_config(dsidev, 1); | |
3830 | dsi_vc_initial_config(dsidev, 2); | |
3831 | dsi_vc_initial_config(dsidev, 3); | |
3de7a1dc TV |
3832 | |
3833 | return 0; | |
3834 | } | |
3835 | ||
3836 | static void dsi_proto_timings(struct omap_dss_device *dssdev) | |
3837 | { | |
a72b64b9 | 3838 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3839 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
3840 | unsigned tclk_pre, tclk_post; | |
3841 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3842 | unsigned ths_trail, ths_exit; | |
3843 | unsigned ddr_clk_pre, ddr_clk_post; | |
3844 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
3845 | unsigned ths_eot; | |
8af6ff01 | 3846 | int ndl = dsi_get_num_data_lanes_dssdev(dssdev); |
3de7a1dc TV |
3847 | u32 r; |
3848 | ||
a72b64b9 | 3849 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
3850 | ths_prepare = FLD_GET(r, 31, 24); |
3851 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3852 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3853 | ths_trail = FLD_GET(r, 15, 8); | |
3854 | ths_exit = FLD_GET(r, 7, 0); | |
3855 | ||
a72b64b9 | 3856 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
3857 | tlpx = FLD_GET(r, 22, 16) * 2; |
3858 | tclk_trail = FLD_GET(r, 15, 8); | |
3859 | tclk_zero = FLD_GET(r, 7, 0); | |
3860 | ||
a72b64b9 | 3861 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc TV |
3862 | tclk_prepare = FLD_GET(r, 7, 0); |
3863 | ||
3864 | /* min 8*UI */ | |
3865 | tclk_pre = 20; | |
3866 | /* min 60ns + 52*UI */ | |
a72b64b9 | 3867 | tclk_post = ns2ddr(dsidev, 60) + 26; |
3de7a1dc | 3868 | |
8af6ff01 | 3869 | ths_eot = DIV_ROUND_UP(4, ndl); |
3de7a1dc TV |
3870 | |
3871 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3872 | 4); | |
3873 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3874 | ||
3875 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3876 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3877 | ||
a72b64b9 | 3878 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
3de7a1dc TV |
3879 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
3880 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
a72b64b9 | 3881 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
3de7a1dc TV |
3882 | |
3883 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3884 | ddr_clk_pre, | |
3885 | ddr_clk_post); | |
3886 | ||
3887 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3888 | DIV_ROUND_UP(ths_prepare, 4) + | |
3889 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3890 | ||
3891 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3892 | ||
3893 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3894 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
a72b64b9 | 3895 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
3de7a1dc TV |
3896 | |
3897 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3898 | enter_hs_mode_lat, exit_hs_mode_lat); | |
8af6ff01 AT |
3899 | |
3900 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3901 | /* TODO: Implement a video mode check_timings function */ | |
3902 | int hsa = dssdev->panel.dsi_vm_data.hsa; | |
3903 | int hfp = dssdev->panel.dsi_vm_data.hfp; | |
3904 | int hbp = dssdev->panel.dsi_vm_data.hbp; | |
3905 | int vsa = dssdev->panel.dsi_vm_data.vsa; | |
3906 | int vfp = dssdev->panel.dsi_vm_data.vfp; | |
3907 | int vbp = dssdev->panel.dsi_vm_data.vbp; | |
3908 | int window_sync = dssdev->panel.dsi_vm_data.window_sync; | |
3909 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; | |
3910 | struct omap_video_timings *timings = &dssdev->panel.timings; | |
3911 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); | |
3912 | int tl, t_he, width_bytes; | |
3913 | ||
3914 | t_he = hsync_end ? | |
3915 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; | |
3916 | ||
3917 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
3918 | ||
3919 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ | |
3920 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + | |
3921 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; | |
3922 | ||
3923 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, | |
3924 | hfp, hsync_end ? hsa : 0, tl); | |
3925 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, | |
3926 | vsa, timings->y_res); | |
3927 | ||
3928 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
3929 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ | |
3930 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ | |
3931 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ | |
3932 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); | |
3933 | ||
3934 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); | |
3935 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ | |
3936 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ | |
3937 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ | |
3938 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ | |
3939 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); | |
3940 | ||
3941 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); | |
3942 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ | |
3943 | r = FLD_MOD(r, tl, 31, 16); /* TL */ | |
3944 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); | |
3945 | } | |
3946 | } | |
3947 | ||
3948 | int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel) | |
3949 | { | |
3950 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3951 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); | |
3952 | u8 data_type; | |
3953 | u16 word_count; | |
3954 | ||
3955 | switch (dssdev->panel.dsi_pix_fmt) { | |
3956 | case OMAP_DSS_DSI_FMT_RGB888: | |
3957 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
3958 | break; | |
3959 | case OMAP_DSS_DSI_FMT_RGB666: | |
3960 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
3961 | break; | |
3962 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
3963 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
3964 | break; | |
3965 | case OMAP_DSS_DSI_FMT_RGB565: | |
3966 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
3967 | break; | |
3968 | default: | |
3969 | BUG(); | |
3970 | }; | |
3971 | ||
3972 | dsi_if_enable(dsidev, false); | |
3973 | dsi_vc_enable(dsidev, channel, false); | |
3974 | ||
3975 | /* MODE, 1 = video mode */ | |
3976 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); | |
3977 | ||
3978 | word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8); | |
3979 | ||
3980 | dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0); | |
3981 | ||
3982 | dsi_vc_enable(dsidev, channel, true); | |
3983 | dsi_if_enable(dsidev, true); | |
3984 | ||
3985 | dssdev->manager->enable(dssdev->manager); | |
3986 | ||
3987 | return 0; | |
3988 | } | |
3989 | EXPORT_SYMBOL(dsi_video_mode_enable); | |
3990 | ||
3991 | void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel) | |
3992 | { | |
3993 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3994 | ||
3995 | dsi_if_enable(dsidev, false); | |
3996 | dsi_vc_enable(dsidev, channel, false); | |
3997 | ||
3998 | /* MODE, 0 = command mode */ | |
3999 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); | |
4000 | ||
4001 | dsi_vc_enable(dsidev, channel, true); | |
4002 | dsi_if_enable(dsidev, true); | |
4003 | ||
4004 | dssdev->manager->disable(dssdev->manager); | |
3de7a1dc | 4005 | } |
8af6ff01 | 4006 | EXPORT_SYMBOL(dsi_video_mode_disable); |
3de7a1dc | 4007 | |
3de7a1dc TV |
4008 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
4009 | u16 x, u16 y, u16 w, u16 h) | |
4010 | { | |
a72b64b9 | 4011 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4012 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4013 | unsigned bytespp; |
4014 | unsigned bytespl; | |
4015 | unsigned bytespf; | |
4016 | unsigned total_len; | |
4017 | unsigned packet_payload; | |
4018 | unsigned packet_len; | |
4019 | u32 l; | |
0f16aa0a | 4020 | int r; |
f1da39d9 | 4021 | const unsigned channel = dsi->update_channel; |
0c65622b | 4022 | const unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
3de7a1dc | 4023 | |
446f7bff TV |
4024 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
4025 | x, y, w, h); | |
3de7a1dc | 4026 | |
d6049144 | 4027 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
18946f62 | 4028 | |
a3b3cc2b | 4029 | bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
3de7a1dc TV |
4030 | bytespl = w * bytespp; |
4031 | bytespf = bytespl * h; | |
4032 | ||
4033 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
4034 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
4035 | ||
4036 | if (bytespf < line_buf_size) | |
4037 | packet_payload = bytespf; | |
4038 | else | |
4039 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
4040 | ||
4041 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
4042 | total_len = (bytespf / packet_payload) * packet_len; | |
4043 | ||
4044 | if (bytespf % packet_payload) | |
4045 | total_len += (bytespf % packet_payload) + 1; | |
4046 | ||
3de7a1dc | 4047 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
a72b64b9 | 4048 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc | 4049 | |
7a7c48f9 | 4050 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
a72b64b9 | 4051 | packet_len, 0); |
3de7a1dc | 4052 | |
f1da39d9 | 4053 | if (dsi->te_enabled) |
3de7a1dc TV |
4054 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
4055 | else | |
4056 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
a72b64b9 | 4057 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc TV |
4058 | |
4059 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
4060 | * because DSS interrupts are not capable of waking up the CPU and the | |
4061 | * framedone interrupt could be delayed for quite a long time. I think | |
4062 | * the same goes for any DSS interrupts, but for some reason I have not | |
4063 | * seen the problem anywhere else than here. | |
4064 | */ | |
4065 | dispc_disable_sidle(); | |
4066 | ||
a72b64b9 | 4067 | dsi_perf_mark_start(dsidev); |
18946f62 | 4068 | |
49dbf589 AT |
4069 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
4070 | msecs_to_jiffies(250)); | |
0f16aa0a | 4071 | BUG_ON(r == 0); |
18946f62 | 4072 | |
3de7a1dc TV |
4073 | dss_start_update(dssdev); |
4074 | ||
f1da39d9 | 4075 | if (dsi->te_enabled) { |
3de7a1dc TV |
4076 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
4077 | * for TE is longer than the timer allows */ | |
a72b64b9 | 4078 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
3de7a1dc | 4079 | |
a72b64b9 | 4080 | dsi_vc_send_bta(dsidev, channel); |
3de7a1dc TV |
4081 | |
4082 | #ifdef DSI_CATCH_MISSING_TE | |
f1da39d9 | 4083 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
3de7a1dc TV |
4084 | #endif |
4085 | } | |
4086 | } | |
4087 | ||
4088 | #ifdef DSI_CATCH_MISSING_TE | |
4089 | static void dsi_te_timeout(unsigned long arg) | |
4090 | { | |
4091 | DSSERR("TE not received for 250ms!\n"); | |
4092 | } | |
4093 | #endif | |
4094 | ||
a72b64b9 | 4095 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
3de7a1dc | 4096 | { |
f1da39d9 AT |
4097 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4098 | ||
3de7a1dc TV |
4099 | /* SIDLEMODE back to smart-idle */ |
4100 | dispc_enable_sidle(); | |
4101 | ||
f1da39d9 | 4102 | if (dsi->te_enabled) { |
18946f62 | 4103 | /* enable LP_RX_TO again after the TE */ |
a72b64b9 | 4104 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
3de7a1dc TV |
4105 | } |
4106 | ||
f1da39d9 | 4107 | dsi->framedone_callback(error, dsi->framedone_data); |
ab83b14c TV |
4108 | |
4109 | if (!error) | |
a72b64b9 | 4110 | dsi_perf_show(dsidev, "DISPC"); |
18946f62 | 4111 | } |
3de7a1dc | 4112 | |
ab83b14c | 4113 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 4114 | { |
f1da39d9 AT |
4115 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
4116 | framedone_timeout_work.work); | |
ab83b14c TV |
4117 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
4118 | * 250ms which would conflict with this timeout work. What should be | |
4119 | * done is first cancel the transfer on the HW, and then cancel the | |
4120 | * possibly scheduled framedone work. However, cancelling the transfer | |
4121 | * on the HW is buggy, and would probably require resetting the whole | |
4122 | * DSI */ | |
18946f62 | 4123 | |
ab83b14c | 4124 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 4125 | |
f1da39d9 | 4126 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
3de7a1dc TV |
4127 | } |
4128 | ||
ab83b14c | 4129 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
3de7a1dc | 4130 | { |
a72b64b9 AT |
4131 | struct omap_dss_device *dssdev = (struct omap_dss_device *) data; |
4132 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
f1da39d9 AT |
4133 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4134 | ||
ab83b14c TV |
4135 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
4136 | * turns itself off. However, DSI still has the pixels in its buffers, | |
4137 | * and is sending the data. | |
4138 | */ | |
3de7a1dc | 4139 | |
f1da39d9 | 4140 | __cancel_delayed_work(&dsi->framedone_timeout_work); |
3de7a1dc | 4141 | |
a72b64b9 | 4142 | dsi_handle_framedone(dsidev, 0); |
3de7a1dc | 4143 | |
cf398fb3 AT |
4144 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
4145 | dispc_fake_vsync_irq(); | |
4146 | #endif | |
18946f62 | 4147 | } |
3de7a1dc | 4148 | |
18946f62 | 4149 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
26a8c250 TV |
4150 | u16 *x, u16 *y, u16 *w, u16 *h, |
4151 | bool enlarge_update_area) | |
18946f62 | 4152 | { |
a72b64b9 | 4153 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
18946f62 | 4154 | u16 dw, dh; |
3de7a1dc | 4155 | |
18946f62 | 4156 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
3de7a1dc | 4157 | |
18946f62 TV |
4158 | if (*x > dw || *y > dh) |
4159 | return -EINVAL; | |
3de7a1dc | 4160 | |
18946f62 TV |
4161 | if (*x + *w > dw) |
4162 | return -EINVAL; | |
3de7a1dc | 4163 | |
18946f62 TV |
4164 | if (*y + *h > dh) |
4165 | return -EINVAL; | |
3de7a1dc | 4166 | |
18946f62 TV |
4167 | if (*w == 1) |
4168 | return -EINVAL; | |
3de7a1dc | 4169 | |
18946f62 TV |
4170 | if (*w == 0 || *h == 0) |
4171 | return -EINVAL; | |
3de7a1dc | 4172 | |
a72b64b9 | 4173 | dsi_perf_mark_setup(dsidev); |
3de7a1dc | 4174 | |
4a9e78ab TV |
4175 | dss_setup_partial_planes(dssdev, x, y, w, h, |
4176 | enlarge_update_area); | |
26d9dd0d | 4177 | dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h); |
3de7a1dc | 4178 | |
18946f62 TV |
4179 | return 0; |
4180 | } | |
4181 | EXPORT_SYMBOL(omap_dsi_prepare_update); | |
3de7a1dc | 4182 | |
18946f62 TV |
4183 | int omap_dsi_update(struct omap_dss_device *dssdev, |
4184 | int channel, | |
4185 | u16 x, u16 y, u16 w, u16 h, | |
4186 | void (*callback)(int, void *), void *data) | |
4187 | { | |
a72b64b9 | 4188 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4189 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4190 | |
f1da39d9 | 4191 | dsi->update_channel = channel; |
3de7a1dc | 4192 | |
a602771c TV |
4193 | /* OMAP DSS cannot send updates of odd widths. |
4194 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON | |
4195 | * here to make sure we catch erroneous updates. Otherwise we'll only | |
4196 | * see rather obscure HW error happening, as DSS halts. */ | |
4197 | BUG_ON(x % 2 == 1); | |
4198 | ||
4a9e78ab TV |
4199 | dsi->framedone_callback = callback; |
4200 | dsi->framedone_data = data; | |
e9c31afc | 4201 | |
4a9e78ab TV |
4202 | dsi->update_region.x = x; |
4203 | dsi->update_region.y = y; | |
4204 | dsi->update_region.w = w; | |
4205 | dsi->update_region.h = h; | |
4206 | dsi->update_region.device = dssdev; | |
e9c31afc | 4207 | |
4a9e78ab | 4208 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
3de7a1dc | 4209 | |
3de7a1dc TV |
4210 | return 0; |
4211 | } | |
18946f62 | 4212 | EXPORT_SYMBOL(omap_dsi_update); |
3de7a1dc TV |
4213 | |
4214 | /* Display funcs */ | |
4215 | ||
4216 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) | |
4217 | { | |
4218 | int r; | |
3de7a1dc | 4219 | |
8af6ff01 AT |
4220 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4221 | u32 irq; | |
3de7a1dc TV |
4222 | struct omap_video_timings timings = { |
4223 | .hsw = 1, | |
4224 | .hfp = 1, | |
4225 | .hbp = 1, | |
4226 | .vsw = 1, | |
4227 | .vfp = 0, | |
4228 | .vbp = 0, | |
4229 | }; | |
4230 | ||
8af6ff01 AT |
4231 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? |
4232 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; | |
4233 | ||
4234 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, | |
4235 | (void *) dssdev, irq); | |
4236 | if (r) { | |
4237 | DSSERR("can't get FRAMEDONE irq\n"); | |
4238 | return r; | |
4239 | } | |
4240 | ||
4241 | dispc_mgr_enable_stallmode(dssdev->manager->id, true); | |
4242 | dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1); | |
4243 | ||
26d9dd0d | 4244 | dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings); |
8af6ff01 AT |
4245 | } else { |
4246 | dispc_mgr_enable_stallmode(dssdev->manager->id, false); | |
4247 | dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0); | |
4248 | ||
4249 | dispc_mgr_set_lcd_timings(dssdev->manager->id, | |
4250 | &dssdev->panel.timings); | |
3de7a1dc TV |
4251 | } |
4252 | ||
8af6ff01 AT |
4253 | dispc_mgr_set_lcd_display_type(dssdev->manager->id, |
4254 | OMAP_DSS_LCD_DISPLAY_TFT); | |
4255 | dispc_mgr_set_tft_data_lines(dssdev->manager->id, | |
4256 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)); | |
3de7a1dc TV |
4257 | return 0; |
4258 | } | |
4259 | ||
4260 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) | |
4261 | { | |
8af6ff01 AT |
4262 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4263 | u32 irq; | |
5a8b572d | 4264 | |
8af6ff01 AT |
4265 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? |
4266 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; | |
5a8b572d | 4267 | |
8af6ff01 AT |
4268 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, |
4269 | (void *) dssdev, irq); | |
4270 | } | |
3de7a1dc TV |
4271 | } |
4272 | ||
4273 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) | |
4274 | { | |
a72b64b9 | 4275 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
4276 | struct dsi_clock_info cinfo; |
4277 | int r; | |
4278 | ||
1bb47835 AT |
4279 | /* we always use DSS_CLK_SYSCK as input clock */ |
4280 | cinfo.use_sys_clk = true; | |
c6940a3d TV |
4281 | cinfo.regn = dssdev->clocks.dsi.regn; |
4282 | cinfo.regm = dssdev->clocks.dsi.regm; | |
4283 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; | |
4284 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; | |
ff1b2cde | 4285 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
ebf0a3fe VS |
4286 | if (r) { |
4287 | DSSERR("Failed to calc dsi clocks\n"); | |
3de7a1dc | 4288 | return r; |
ebf0a3fe | 4289 | } |
3de7a1dc | 4290 | |
a72b64b9 | 4291 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
3de7a1dc TV |
4292 | if (r) { |
4293 | DSSERR("Failed to set dsi clocks\n"); | |
4294 | return r; | |
4295 | } | |
4296 | ||
4297 | return 0; | |
4298 | } | |
4299 | ||
4300 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) | |
4301 | { | |
a72b64b9 | 4302 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
4303 | struct dispc_clock_info dispc_cinfo; |
4304 | int r; | |
4305 | unsigned long long fck; | |
4306 | ||
a72b64b9 | 4307 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
3de7a1dc | 4308 | |
e8881662 AT |
4309 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
4310 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; | |
3de7a1dc TV |
4311 | |
4312 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
4313 | if (r) { | |
4314 | DSSERR("Failed to calc dispc clocks\n"); | |
4315 | return r; | |
4316 | } | |
4317 | ||
26d9dd0d | 4318 | r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
3de7a1dc TV |
4319 | if (r) { |
4320 | DSSERR("Failed to set dispc clocks\n"); | |
4321 | return r; | |
4322 | } | |
4323 | ||
4324 | return 0; | |
4325 | } | |
4326 | ||
4327 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) | |
4328 | { | |
a72b64b9 | 4329 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5a8b572d | 4330 | int dsi_module = dsi_get_dsidev_id(dsidev); |
3de7a1dc TV |
4331 | int r; |
4332 | ||
a72b64b9 | 4333 | r = dsi_pll_init(dsidev, true, true); |
3de7a1dc TV |
4334 | if (r) |
4335 | goto err0; | |
4336 | ||
4337 | r = dsi_configure_dsi_clocks(dssdev); | |
4338 | if (r) | |
4339 | goto err1; | |
4340 | ||
e8881662 | 4341 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
5a8b572d | 4342 | dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src); |
9613c02b | 4343 | dss_select_lcd_clk_source(dssdev->manager->id, |
e8881662 | 4344 | dssdev->clocks.dispc.channel.lcd_clk_src); |
3de7a1dc TV |
4345 | |
4346 | DSSDBG("PLL OK\n"); | |
4347 | ||
4348 | r = dsi_configure_dispc_clocks(dssdev); | |
4349 | if (r) | |
4350 | goto err2; | |
4351 | ||
cc5c1850 | 4352 | r = dsi_cio_init(dssdev); |
3de7a1dc TV |
4353 | if (r) |
4354 | goto err2; | |
4355 | ||
a72b64b9 | 4356 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4357 | |
4358 | dsi_proto_timings(dssdev); | |
4359 | dsi_set_lp_clk_divisor(dssdev); | |
4360 | ||
4361 | if (1) | |
a72b64b9 | 4362 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4363 | |
4364 | r = dsi_proto_config(dssdev); | |
4365 | if (r) | |
4366 | goto err3; | |
4367 | ||
4368 | /* enable interface */ | |
a72b64b9 AT |
4369 | dsi_vc_enable(dsidev, 0, 1); |
4370 | dsi_vc_enable(dsidev, 1, 1); | |
4371 | dsi_vc_enable(dsidev, 2, 1); | |
4372 | dsi_vc_enable(dsidev, 3, 1); | |
4373 | dsi_if_enable(dsidev, 1); | |
4374 | dsi_force_tx_stop_mode_io(dsidev); | |
3de7a1dc | 4375 | |
3de7a1dc | 4376 | return 0; |
3de7a1dc | 4377 | err3: |
5bc416cb | 4378 | dsi_cio_uninit(dssdev); |
3de7a1dc | 4379 | err2: |
89a35e51 | 4380 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
5a8b572d | 4381 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
5e785091 TV |
4382 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
4383 | ||
3de7a1dc | 4384 | err1: |
a72b64b9 | 4385 | dsi_pll_uninit(dsidev, true); |
3de7a1dc TV |
4386 | err0: |
4387 | return r; | |
4388 | } | |
4389 | ||
2a89dc15 | 4390 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
22d6d676 | 4391 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4392 | { |
a72b64b9 | 4393 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4394 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5a8b572d | 4395 | int dsi_module = dsi_get_dsidev_id(dsidev); |
a72b64b9 | 4396 | |
f1da39d9 | 4397 | if (enter_ulps && !dsi->ulps_enabled) |
a72b64b9 | 4398 | dsi_enter_ulps(dsidev); |
40885ab3 | 4399 | |
d7370104 | 4400 | /* disable interface */ |
a72b64b9 AT |
4401 | dsi_if_enable(dsidev, 0); |
4402 | dsi_vc_enable(dsidev, 0, 0); | |
4403 | dsi_vc_enable(dsidev, 1, 0); | |
4404 | dsi_vc_enable(dsidev, 2, 0); | |
4405 | dsi_vc_enable(dsidev, 3, 0); | |
d7370104 | 4406 | |
89a35e51 | 4407 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
5a8b572d | 4408 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
5e785091 | 4409 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
5bc416cb | 4410 | dsi_cio_uninit(dssdev); |
a72b64b9 | 4411 | dsi_pll_uninit(dsidev, disconnect_lanes); |
3de7a1dc TV |
4412 | } |
4413 | ||
37ac60e4 | 4414 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc | 4415 | { |
a72b64b9 | 4416 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4417 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4418 | int r = 0; |
4419 | ||
4420 | DSSDBG("dsi_display_enable\n"); | |
4421 | ||
a72b64b9 | 4422 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
37ac60e4 | 4423 | |
f1da39d9 | 4424 | mutex_lock(&dsi->lock); |
3de7a1dc | 4425 | |
05e1d606 TV |
4426 | if (dssdev->manager == NULL) { |
4427 | DSSERR("failed to enable display: no manager\n"); | |
4428 | r = -ENODEV; | |
4429 | goto err_start_dev; | |
4430 | } | |
4431 | ||
3de7a1dc TV |
4432 | r = omap_dss_start_device(dssdev); |
4433 | if (r) { | |
4434 | DSSERR("failed to start device\n"); | |
4fbafaf3 | 4435 | goto err_start_dev; |
3de7a1dc TV |
4436 | } |
4437 | ||
4fbafaf3 | 4438 | r = dsi_runtime_get(dsidev); |
3de7a1dc | 4439 | if (r) |
4fbafaf3 TV |
4440 | goto err_get_dsi; |
4441 | ||
4442 | dsi_enable_pll_clock(dsidev, 1); | |
3de7a1dc | 4443 | |
4fbafaf3 | 4444 | _dsi_initialize_irq(dsidev); |
3de7a1dc TV |
4445 | |
4446 | r = dsi_display_init_dispc(dssdev); | |
4447 | if (r) | |
4fbafaf3 | 4448 | goto err_init_dispc; |
3de7a1dc TV |
4449 | |
4450 | r = dsi_display_init_dsi(dssdev); | |
4451 | if (r) | |
4fbafaf3 | 4452 | goto err_init_dsi; |
3de7a1dc | 4453 | |
f1da39d9 | 4454 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4455 | |
4456 | return 0; | |
4457 | ||
4fbafaf3 | 4458 | err_init_dsi: |
37ac60e4 | 4459 | dsi_display_uninit_dispc(dssdev); |
4fbafaf3 | 4460 | err_init_dispc: |
a72b64b9 | 4461 | dsi_enable_pll_clock(dsidev, 0); |
4fbafaf3 TV |
4462 | dsi_runtime_put(dsidev); |
4463 | err_get_dsi: | |
3de7a1dc | 4464 | omap_dss_stop_device(dssdev); |
4fbafaf3 | 4465 | err_start_dev: |
f1da39d9 | 4466 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4467 | DSSDBG("dsi_display_enable FAILED\n"); |
4468 | return r; | |
4469 | } | |
37ac60e4 | 4470 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
3de7a1dc | 4471 | |
2a89dc15 | 4472 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 4473 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4474 | { |
a72b64b9 | 4475 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4476 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4477 | |
3de7a1dc TV |
4478 | DSSDBG("dsi_display_disable\n"); |
4479 | ||
a72b64b9 | 4480 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 4481 | |
f1da39d9 | 4482 | mutex_lock(&dsi->lock); |
3de7a1dc | 4483 | |
15ffa1da TV |
4484 | dsi_sync_vc(dsidev, 0); |
4485 | dsi_sync_vc(dsidev, 1); | |
4486 | dsi_sync_vc(dsidev, 2); | |
4487 | dsi_sync_vc(dsidev, 3); | |
4488 | ||
3de7a1dc TV |
4489 | dsi_display_uninit_dispc(dssdev); |
4490 | ||
22d6d676 | 4491 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
3de7a1dc | 4492 | |
4fbafaf3 | 4493 | dsi_runtime_put(dsidev); |
a72b64b9 | 4494 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc | 4495 | |
37ac60e4 | 4496 | omap_dss_stop_device(dssdev); |
3de7a1dc | 4497 | |
f1da39d9 | 4498 | mutex_unlock(&dsi->lock); |
3de7a1dc | 4499 | } |
37ac60e4 | 4500 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
3de7a1dc | 4501 | |
225b650d | 4502 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 4503 | { |
f1da39d9 AT |
4504 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4505 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4506 | ||
4507 | dsi->te_enabled = enable; | |
225b650d | 4508 | return 0; |
3de7a1dc | 4509 | } |
225b650d | 4510 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
3de7a1dc | 4511 | |
3de7a1dc | 4512 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
5ed8cf5b | 4513 | u32 fifo_size, u32 burst_size, |
3de7a1dc TV |
4514 | u32 *fifo_low, u32 *fifo_high) |
4515 | { | |
5ed8cf5b TV |
4516 | *fifo_high = fifo_size - burst_size; |
4517 | *fifo_low = fifo_size - burst_size * 2; | |
3de7a1dc TV |
4518 | } |
4519 | ||
4520 | int dsi_init_display(struct omap_dss_device *dssdev) | |
4521 | { | |
f1da39d9 AT |
4522 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4523 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
75d7247c | 4524 | int dsi_module = dsi_get_dsidev_id(dsidev); |
f1da39d9 | 4525 | |
3de7a1dc TV |
4526 | DSSDBG("DSI init\n"); |
4527 | ||
7e951ee9 AT |
4528 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4529 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | | |
4530 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; | |
4531 | } | |
3de7a1dc | 4532 | |
f1da39d9 | 4533 | if (dsi->vdds_dsi_reg == NULL) { |
5f42f2ce TV |
4534 | struct regulator *vdds_dsi; |
4535 | ||
f1da39d9 | 4536 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
5f42f2ce TV |
4537 | |
4538 | if (IS_ERR(vdds_dsi)) { | |
4539 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4540 | return PTR_ERR(vdds_dsi); | |
4541 | } | |
4542 | ||
f1da39d9 | 4543 | dsi->vdds_dsi_reg = vdds_dsi; |
5f42f2ce TV |
4544 | } |
4545 | ||
75d7247c AT |
4546 | if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) { |
4547 | DSSERR("DSI%d can't support more than %d data lanes\n", | |
4548 | dsi_module + 1, dsi->num_data_lanes); | |
4549 | return -EINVAL; | |
4550 | } | |
4551 | ||
3de7a1dc TV |
4552 | return 0; |
4553 | } | |
4554 | ||
5ee3c144 AT |
4555 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
4556 | { | |
f1da39d9 AT |
4557 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4558 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5ee3c144 AT |
4559 | int i; |
4560 | ||
f1da39d9 AT |
4561 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
4562 | if (!dsi->vc[i].dssdev) { | |
4563 | dsi->vc[i].dssdev = dssdev; | |
5ee3c144 AT |
4564 | *channel = i; |
4565 | return 0; | |
4566 | } | |
4567 | } | |
4568 | ||
4569 | DSSERR("cannot get VC for display %s", dssdev->name); | |
4570 | return -ENOSPC; | |
4571 | } | |
4572 | EXPORT_SYMBOL(omap_dsi_request_vc); | |
4573 | ||
4574 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) | |
4575 | { | |
f1da39d9 AT |
4576 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4577 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4578 | ||
5ee3c144 AT |
4579 | if (vc_id < 0 || vc_id > 3) { |
4580 | DSSERR("VC ID out of range\n"); | |
4581 | return -EINVAL; | |
4582 | } | |
4583 | ||
4584 | if (channel < 0 || channel > 3) { | |
4585 | DSSERR("Virtual Channel out of range\n"); | |
4586 | return -EINVAL; | |
4587 | } | |
4588 | ||
f1da39d9 | 4589 | if (dsi->vc[channel].dssdev != dssdev) { |
5ee3c144 AT |
4590 | DSSERR("Virtual Channel not allocated to display %s\n", |
4591 | dssdev->name); | |
4592 | return -EINVAL; | |
4593 | } | |
4594 | ||
f1da39d9 | 4595 | dsi->vc[channel].vc_id = vc_id; |
5ee3c144 AT |
4596 | |
4597 | return 0; | |
4598 | } | |
4599 | EXPORT_SYMBOL(omap_dsi_set_vc_id); | |
4600 | ||
4601 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) | |
4602 | { | |
f1da39d9 AT |
4603 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4604 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4605 | ||
5ee3c144 | 4606 | if ((channel >= 0 && channel <= 3) && |
f1da39d9 AT |
4607 | dsi->vc[channel].dssdev == dssdev) { |
4608 | dsi->vc[channel].dssdev = NULL; | |
4609 | dsi->vc[channel].vc_id = 0; | |
5ee3c144 AT |
4610 | } |
4611 | } | |
4612 | EXPORT_SYMBOL(omap_dsi_release_vc); | |
4613 | ||
a72b64b9 | 4614 | void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) |
e406f907 | 4615 | { |
a72b64b9 | 4616 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1) |
067a57e4 | 4617 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4618 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
4619 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | |
e406f907 TV |
4620 | } |
4621 | ||
a72b64b9 | 4622 | void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) |
e406f907 | 4623 | { |
a72b64b9 | 4624 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1) |
067a57e4 | 4625 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4626 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
4627 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | |
e406f907 TV |
4628 | } |
4629 | ||
a72b64b9 | 4630 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
49641116 | 4631 | { |
f1da39d9 AT |
4632 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4633 | ||
4634 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); | |
4635 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); | |
4636 | dsi->regm_dispc_max = | |
4637 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); | |
4638 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); | |
4639 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); | |
4640 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); | |
4641 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
49641116 AT |
4642 | } |
4643 | ||
4fbafaf3 TV |
4644 | static int dsi_get_clocks(struct platform_device *dsidev) |
4645 | { | |
4646 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4647 | struct clk *clk; | |
4648 | ||
4649 | clk = clk_get(&dsidev->dev, "fck"); | |
4650 | if (IS_ERR(clk)) { | |
4651 | DSSERR("can't get fck\n"); | |
4652 | return PTR_ERR(clk); | |
4653 | } | |
4654 | ||
4655 | dsi->dss_clk = clk; | |
4656 | ||
bfe4f8d3 | 4657 | clk = clk_get(&dsidev->dev, "sys_clk"); |
4fbafaf3 TV |
4658 | if (IS_ERR(clk)) { |
4659 | DSSERR("can't get sys_clk\n"); | |
4660 | clk_put(dsi->dss_clk); | |
4661 | dsi->dss_clk = NULL; | |
4662 | return PTR_ERR(clk); | |
4663 | } | |
4664 | ||
4665 | dsi->sys_clk = clk; | |
4666 | ||
4667 | return 0; | |
4668 | } | |
4669 | ||
4670 | static void dsi_put_clocks(struct platform_device *dsidev) | |
4671 | { | |
4672 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4673 | ||
4674 | if (dsi->dss_clk) | |
4675 | clk_put(dsi->dss_clk); | |
4676 | if (dsi->sys_clk) | |
4677 | clk_put(dsi->sys_clk); | |
4678 | } | |
4679 | ||
b98482ed | 4680 | /* DSI1 HW IP initialisation */ |
7c68dd96 | 4681 | static int omap_dsihw_probe(struct platform_device *dsidev) |
3de7a1dc | 4682 | { |
d1f5857e TV |
4683 | struct omap_display_platform_data *dss_plat_data; |
4684 | struct omap_dss_board_info *board_info; | |
3de7a1dc | 4685 | u32 rev; |
f1da39d9 | 4686 | int r, i, dsi_module = dsi_get_dsidev_id(dsidev); |
ea9da36a | 4687 | struct resource *dsi_mem; |
f1da39d9 AT |
4688 | struct dsi_data *dsi; |
4689 | ||
4690 | dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); | |
4691 | if (!dsi) { | |
4692 | r = -ENOMEM; | |
4fbafaf3 | 4693 | goto err_alloc; |
f1da39d9 | 4694 | } |
3de7a1dc | 4695 | |
f1da39d9 AT |
4696 | dsi->pdev = dsidev; |
4697 | dsi_pdev_map[dsi_module] = dsidev; | |
4698 | dev_set_drvdata(&dsidev->dev, dsi); | |
a72b64b9 AT |
4699 | |
4700 | dss_plat_data = dsidev->dev.platform_data; | |
d1f5857e | 4701 | board_info = dss_plat_data->board_data; |
5bc416cb TV |
4702 | dsi->enable_pads = board_info->dsi_enable_pads; |
4703 | dsi->disable_pads = board_info->dsi_disable_pads; | |
d1f5857e | 4704 | |
f1da39d9 AT |
4705 | spin_lock_init(&dsi->irq_lock); |
4706 | spin_lock_init(&dsi->errors_lock); | |
4707 | dsi->errors = 0; | |
3de7a1dc | 4708 | |
dfc0fd8d | 4709 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f1da39d9 AT |
4710 | spin_lock_init(&dsi->irq_stats_lock); |
4711 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d TV |
4712 | #endif |
4713 | ||
f1da39d9 AT |
4714 | mutex_init(&dsi->lock); |
4715 | sema_init(&dsi->bus_lock, 1); | |
3de7a1dc | 4716 | |
4fbafaf3 TV |
4717 | r = dsi_get_clocks(dsidev); |
4718 | if (r) | |
4719 | goto err_get_clk; | |
4720 | ||
4721 | pm_runtime_enable(&dsidev->dev); | |
4722 | ||
f1da39d9 | 4723 | INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work, |
18946f62 TV |
4724 | dsi_framedone_timeout_work_callback); |
4725 | ||
3de7a1dc | 4726 | #ifdef DSI_CATCH_MISSING_TE |
f1da39d9 AT |
4727 | init_timer(&dsi->te_timer); |
4728 | dsi->te_timer.function = dsi_te_timeout; | |
4729 | dsi->te_timer.data = 0; | |
3de7a1dc | 4730 | #endif |
f1da39d9 | 4731 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); |
ea9da36a SG |
4732 | if (!dsi_mem) { |
4733 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
4734 | r = -EINVAL; | |
4fbafaf3 | 4735 | goto err_ioremap; |
ea9da36a | 4736 | } |
f1da39d9 AT |
4737 | dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem)); |
4738 | if (!dsi->base) { | |
3de7a1dc TV |
4739 | DSSERR("can't ioremap DSI\n"); |
4740 | r = -ENOMEM; | |
4fbafaf3 | 4741 | goto err_ioremap; |
3de7a1dc | 4742 | } |
f1da39d9 AT |
4743 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
4744 | if (dsi->irq < 0) { | |
affe360d AT |
4745 | DSSERR("platform_get_irq failed\n"); |
4746 | r = -ENODEV; | |
4fbafaf3 | 4747 | goto err_get_irq; |
affe360d AT |
4748 | } |
4749 | ||
f1da39d9 AT |
4750 | r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED, |
4751 | dev_name(&dsidev->dev), dsi->pdev); | |
affe360d AT |
4752 | if (r < 0) { |
4753 | DSSERR("request_irq failed\n"); | |
4fbafaf3 | 4754 | goto err_get_irq; |
affe360d | 4755 | } |
3de7a1dc | 4756 | |
5ee3c144 | 4757 | /* DSI VCs initialization */ |
f1da39d9 | 4758 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
d6049144 | 4759 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
f1da39d9 AT |
4760 | dsi->vc[i].dssdev = NULL; |
4761 | dsi->vc[i].vc_id = 0; | |
5ee3c144 AT |
4762 | } |
4763 | ||
a72b64b9 | 4764 | dsi_calc_clock_param_ranges(dsidev); |
49641116 | 4765 | |
4fbafaf3 TV |
4766 | r = dsi_runtime_get(dsidev); |
4767 | if (r) | |
4768 | goto err_get_dsi; | |
3de7a1dc | 4769 | |
a72b64b9 AT |
4770 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
4771 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", | |
3de7a1dc TV |
4772 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
4773 | ||
75d7247c AT |
4774 | dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev); |
4775 | ||
4fbafaf3 | 4776 | dsi_runtime_put(dsidev); |
3de7a1dc | 4777 | |
3de7a1dc | 4778 | return 0; |
4fbafaf3 TV |
4779 | |
4780 | err_get_dsi: | |
4781 | free_irq(dsi->irq, dsi->pdev); | |
4782 | err_get_irq: | |
49dbf589 | 4783 | iounmap(dsi->base); |
4fbafaf3 TV |
4784 | err_ioremap: |
4785 | pm_runtime_disable(&dsidev->dev); | |
4786 | err_get_clk: | |
f1da39d9 | 4787 | kfree(dsi); |
4fbafaf3 | 4788 | err_alloc: |
3de7a1dc TV |
4789 | return r; |
4790 | } | |
4791 | ||
7c68dd96 | 4792 | static int omap_dsihw_remove(struct platform_device *dsidev) |
3de7a1dc | 4793 | { |
f1da39d9 AT |
4794 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4795 | ||
b98482ed TV |
4796 | WARN_ON(dsi->scp_clk_refcount > 0); |
4797 | ||
4fbafaf3 TV |
4798 | pm_runtime_disable(&dsidev->dev); |
4799 | ||
4800 | dsi_put_clocks(dsidev); | |
4801 | ||
f1da39d9 AT |
4802 | if (dsi->vdds_dsi_reg != NULL) { |
4803 | if (dsi->vdds_dsi_enabled) { | |
4804 | regulator_disable(dsi->vdds_dsi_reg); | |
4805 | dsi->vdds_dsi_enabled = false; | |
88257b26 TV |
4806 | } |
4807 | ||
f1da39d9 AT |
4808 | regulator_put(dsi->vdds_dsi_reg); |
4809 | dsi->vdds_dsi_reg = NULL; | |
c8aac01b SG |
4810 | } |
4811 | ||
f1da39d9 AT |
4812 | free_irq(dsi->irq, dsi->pdev); |
4813 | iounmap(dsi->base); | |
3de7a1dc | 4814 | |
f1da39d9 | 4815 | kfree(dsi); |
0f16aa0a | 4816 | |
c8aac01b SG |
4817 | return 0; |
4818 | } | |
4819 | ||
4fbafaf3 TV |
4820 | static int dsi_runtime_suspend(struct device *dev) |
4821 | { | |
4fbafaf3 TV |
4822 | dispc_runtime_put(); |
4823 | dss_runtime_put(); | |
4824 | ||
4825 | return 0; | |
4826 | } | |
4827 | ||
4828 | static int dsi_runtime_resume(struct device *dev) | |
4829 | { | |
4fbafaf3 TV |
4830 | int r; |
4831 | ||
4832 | r = dss_runtime_get(); | |
4833 | if (r) | |
4834 | goto err_get_dss; | |
4835 | ||
4836 | r = dispc_runtime_get(); | |
4837 | if (r) | |
4838 | goto err_get_dispc; | |
4839 | ||
4fbafaf3 TV |
4840 | return 0; |
4841 | ||
4842 | err_get_dispc: | |
4843 | dss_runtime_put(); | |
4844 | err_get_dss: | |
4845 | return r; | |
4846 | } | |
4847 | ||
4848 | static const struct dev_pm_ops dsi_pm_ops = { | |
4849 | .runtime_suspend = dsi_runtime_suspend, | |
4850 | .runtime_resume = dsi_runtime_resume, | |
4851 | }; | |
4852 | ||
7c68dd96 TV |
4853 | static struct platform_driver omap_dsihw_driver = { |
4854 | .probe = omap_dsihw_probe, | |
4855 | .remove = omap_dsihw_remove, | |
c8aac01b | 4856 | .driver = { |
7c68dd96 | 4857 | .name = "omapdss_dsi", |
c8aac01b | 4858 | .owner = THIS_MODULE, |
4fbafaf3 | 4859 | .pm = &dsi_pm_ops, |
c8aac01b SG |
4860 | }, |
4861 | }; | |
4862 | ||
4863 | int dsi_init_platform_driver(void) | |
4864 | { | |
7c68dd96 | 4865 | return platform_driver_register(&omap_dsihw_driver); |
c8aac01b SG |
4866 | } |
4867 | ||
4868 | void dsi_uninit_platform_driver(void) | |
4869 | { | |
7c68dd96 | 4870 | return platform_driver_unregister(&omap_dsihw_driver); |
c8aac01b | 4871 | } |