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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/io.h> | |
a8a35931 | 27 | #include <linux/export.h> |
559d6701 TV |
28 | #include <linux/err.h> |
29 | #include <linux/delay.h> | |
559d6701 TV |
30 | #include <linux/seq_file.h> |
31 | #include <linux/clk.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 | 33 | #include <linux/pm_runtime.h> |
559d6701 | 34 | |
a0b38cc4 | 35 | #include <video/omapdss.h> |
2c799cef TL |
36 | |
37 | #include <plat/cpu.h> | |
8b9cb3a8 | 38 | #include <plat/clock.h> |
2c799cef | 39 | |
559d6701 | 40 | #include "dss.h" |
6ec549e5 | 41 | #include "dss_features.h" |
559d6701 | 42 | |
559d6701 TV |
43 | #define DSS_SZ_REGS SZ_512 |
44 | ||
45 | struct dss_reg { | |
46 | u16 idx; | |
47 | }; | |
48 | ||
49 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
50 | ||
51 | #define DSS_REVISION DSS_REG(0x0000) | |
52 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
53 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
559d6701 TV |
54 | #define DSS_CONTROL DSS_REG(0x0040) |
55 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
56 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
57 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
58 | ||
59 | #define REG_GET(idx, start, end) \ | |
60 | FLD_GET(dss_read_reg(idx), start, end) | |
61 | ||
62 | #define REG_FLD_MOD(idx, val, start, end) \ | |
63 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
64 | ||
852f0838 TV |
65 | static int dss_runtime_get(void); |
66 | static void dss_runtime_put(void); | |
67 | ||
559d6701 | 68 | static struct { |
96c401bc | 69 | struct platform_device *pdev; |
559d6701 | 70 | void __iomem *base; |
4fbafaf3 | 71 | |
559d6701 | 72 | struct clk *dpll4_m4_ck; |
4fbafaf3 | 73 | struct clk *dss_clk; |
559d6701 TV |
74 | |
75 | unsigned long cache_req_pck; | |
76 | unsigned long cache_prate; | |
77 | struct dss_clock_info cache_dss_cinfo; | |
78 | struct dispc_clock_info cache_dispc_cinfo; | |
79 | ||
5a8b572d | 80 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
89a35e51 AT |
81 | enum omap_dss_clk_source dispc_clk_source; |
82 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; | |
2f18c4d8 | 83 | |
69f06054 | 84 | bool ctx_valid; |
559d6701 TV |
85 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
86 | } dss; | |
87 | ||
235e7dba | 88 | static const char * const dss_generic_clk_source_names[] = { |
89a35e51 AT |
89 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
90 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", | |
91 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", | |
067a57e4 AT |
92 | }; |
93 | ||
559d6701 TV |
94 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
95 | { | |
96 | __raw_writel(val, dss.base + idx.idx); | |
97 | } | |
98 | ||
99 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
100 | { | |
101 | return __raw_readl(dss.base + idx.idx); | |
102 | } | |
103 | ||
104 | #define SR(reg) \ | |
105 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
106 | #define RR(reg) \ | |
107 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
108 | ||
4fbafaf3 | 109 | static void dss_save_context(void) |
559d6701 | 110 | { |
4fbafaf3 | 111 | DSSDBG("dss_save_context\n"); |
559d6701 | 112 | |
559d6701 TV |
113 | SR(CONTROL); |
114 | ||
6ec549e5 TV |
115 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
116 | OMAP_DISPLAY_TYPE_SDI) { | |
117 | SR(SDI_CONTROL); | |
118 | SR(PLL_CONTROL); | |
119 | } | |
69f06054 TV |
120 | |
121 | dss.ctx_valid = true; | |
122 | ||
123 | DSSDBG("context saved\n"); | |
559d6701 TV |
124 | } |
125 | ||
4fbafaf3 | 126 | static void dss_restore_context(void) |
559d6701 | 127 | { |
4fbafaf3 | 128 | DSSDBG("dss_restore_context\n"); |
559d6701 | 129 | |
69f06054 TV |
130 | if (!dss.ctx_valid) |
131 | return; | |
132 | ||
559d6701 TV |
133 | RR(CONTROL); |
134 | ||
6ec549e5 TV |
135 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
136 | OMAP_DISPLAY_TYPE_SDI) { | |
137 | RR(SDI_CONTROL); | |
138 | RR(PLL_CONTROL); | |
139 | } | |
69f06054 TV |
140 | |
141 | DSSDBG("context restored\n"); | |
559d6701 TV |
142 | } |
143 | ||
144 | #undef SR | |
145 | #undef RR | |
146 | ||
147 | void dss_sdi_init(u8 datapairs) | |
148 | { | |
149 | u32 l; | |
150 | ||
151 | BUG_ON(datapairs > 3 || datapairs < 1); | |
152 | ||
153 | l = dss_read_reg(DSS_SDI_CONTROL); | |
154 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
155 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
156 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
157 | dss_write_reg(DSS_SDI_CONTROL, l); | |
158 | ||
159 | l = dss_read_reg(DSS_PLL_CONTROL); | |
160 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
161 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
162 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
163 | dss_write_reg(DSS_PLL_CONTROL, l); | |
164 | } | |
165 | ||
166 | int dss_sdi_enable(void) | |
167 | { | |
168 | unsigned long timeout; | |
169 | ||
170 | dispc_pck_free_enable(1); | |
171 | ||
172 | /* Reset SDI PLL */ | |
173 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
174 | udelay(1); /* wait 2x PCLK */ | |
175 | ||
176 | /* Lock SDI PLL */ | |
177 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
178 | ||
179 | /* Waiting for PLL lock request to complete */ | |
180 | timeout = jiffies + msecs_to_jiffies(500); | |
181 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
182 | if (time_after_eq(jiffies, timeout)) { | |
183 | DSSERR("PLL lock request timed out\n"); | |
184 | goto err1; | |
185 | } | |
186 | } | |
187 | ||
188 | /* Clearing PLL_GO bit */ | |
189 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
190 | ||
191 | /* Waiting for PLL to lock */ | |
192 | timeout = jiffies + msecs_to_jiffies(500); | |
193 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
194 | if (time_after_eq(jiffies, timeout)) { | |
195 | DSSERR("PLL lock timed out\n"); | |
196 | goto err1; | |
197 | } | |
198 | } | |
199 | ||
200 | dispc_lcd_enable_signal(1); | |
201 | ||
202 | /* Waiting for SDI reset to complete */ | |
203 | timeout = jiffies + msecs_to_jiffies(500); | |
204 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
205 | if (time_after_eq(jiffies, timeout)) { | |
206 | DSSERR("SDI reset timed out\n"); | |
207 | goto err2; | |
208 | } | |
209 | } | |
210 | ||
211 | return 0; | |
212 | ||
213 | err2: | |
214 | dispc_lcd_enable_signal(0); | |
215 | err1: | |
216 | /* Reset SDI PLL */ | |
217 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
218 | ||
219 | dispc_pck_free_enable(0); | |
220 | ||
221 | return -ETIMEDOUT; | |
222 | } | |
223 | ||
224 | void dss_sdi_disable(void) | |
225 | { | |
226 | dispc_lcd_enable_signal(0); | |
227 | ||
228 | dispc_pck_free_enable(0); | |
229 | ||
230 | /* Reset SDI PLL */ | |
231 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
232 | } | |
233 | ||
89a35e51 | 234 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
067a57e4 | 235 | { |
235e7dba | 236 | return dss_generic_clk_source_names[clk_src]; |
067a57e4 AT |
237 | } |
238 | ||
4fbafaf3 | 239 | |
559d6701 TV |
240 | void dss_dump_clocks(struct seq_file *s) |
241 | { | |
242 | unsigned long dpll4_ck_rate; | |
243 | unsigned long dpll4_m4_ck_rate; | |
0acf659f TV |
244 | const char *fclk_name, *fclk_real_name; |
245 | unsigned long fclk_rate; | |
559d6701 | 246 | |
4fbafaf3 TV |
247 | if (dss_runtime_get()) |
248 | return; | |
559d6701 | 249 | |
559d6701 TV |
250 | seq_printf(s, "- DSS -\n"); |
251 | ||
89a35e51 AT |
252 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
253 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | |
4fbafaf3 | 254 | fclk_rate = clk_get_rate(dss.dss_clk); |
559d6701 | 255 | |
0acf659f TV |
256 | if (dss.dpll4_m4_ck) { |
257 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
258 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); | |
259 | ||
260 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | |
261 | ||
2de11086 | 262 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
0acf659f TV |
263 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
264 | fclk_name, fclk_real_name, | |
265 | dpll4_ck_rate, | |
266 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
267 | fclk_rate); | |
268 | else | |
269 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", | |
270 | fclk_name, fclk_real_name, | |
271 | dpll4_ck_rate, | |
272 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
273 | fclk_rate); | |
274 | } else { | |
275 | seq_printf(s, "%s (%s) = %lu\n", | |
276 | fclk_name, fclk_real_name, | |
277 | fclk_rate); | |
278 | } | |
559d6701 | 279 | |
4fbafaf3 | 280 | dss_runtime_put(); |
559d6701 TV |
281 | } |
282 | ||
e40402cf | 283 | static void dss_dump_regs(struct seq_file *s) |
559d6701 TV |
284 | { |
285 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
286 | ||
4fbafaf3 TV |
287 | if (dss_runtime_get()) |
288 | return; | |
559d6701 TV |
289 | |
290 | DUMPREG(DSS_REVISION); | |
291 | DUMPREG(DSS_SYSCONFIG); | |
292 | DUMPREG(DSS_SYSSTATUS); | |
559d6701 | 293 | DUMPREG(DSS_CONTROL); |
6ec549e5 TV |
294 | |
295 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
296 | OMAP_DISPLAY_TYPE_SDI) { | |
297 | DUMPREG(DSS_SDI_CONTROL); | |
298 | DUMPREG(DSS_PLL_CONTROL); | |
299 | DUMPREG(DSS_SDI_STATUS); | |
300 | } | |
559d6701 | 301 | |
4fbafaf3 | 302 | dss_runtime_put(); |
559d6701 TV |
303 | #undef DUMPREG |
304 | } | |
305 | ||
89a35e51 | 306 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
2f18c4d8 | 307 | { |
a72b64b9 | 308 | struct platform_device *dsidev; |
2f18c4d8 | 309 | int b; |
ea75159e | 310 | u8 start, end; |
2f18c4d8 | 311 | |
66534e8e | 312 | switch (clk_src) { |
89a35e51 | 313 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e AT |
314 | b = 0; |
315 | break; | |
89a35e51 | 316 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
66534e8e | 317 | b = 1; |
a72b64b9 AT |
318 | dsidev = dsi_get_dsidev_from_id(0); |
319 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
66534e8e | 320 | break; |
5a8b572d AT |
321 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
322 | b = 2; | |
323 | dsidev = dsi_get_dsidev_from_id(1); | |
324 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
325 | break; | |
66534e8e AT |
326 | default: |
327 | BUG(); | |
328 | } | |
e406f907 | 329 | |
ea75159e AT |
330 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
331 | ||
332 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ | |
2f18c4d8 TV |
333 | |
334 | dss.dispc_clk_source = clk_src; | |
335 | } | |
336 | ||
5a8b572d AT |
337 | void dss_select_dsi_clk_source(int dsi_module, |
338 | enum omap_dss_clk_source clk_src) | |
559d6701 | 339 | { |
a72b64b9 | 340 | struct platform_device *dsidev; |
a2e5d827 | 341 | int b, pos; |
2f18c4d8 | 342 | |
66534e8e | 343 | switch (clk_src) { |
89a35e51 | 344 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e AT |
345 | b = 0; |
346 | break; | |
89a35e51 | 347 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
5a8b572d | 348 | BUG_ON(dsi_module != 0); |
66534e8e | 349 | b = 1; |
a72b64b9 AT |
350 | dsidev = dsi_get_dsidev_from_id(0); |
351 | dsi_wait_pll_hsdiv_dsi_active(dsidev); | |
66534e8e | 352 | break; |
5a8b572d AT |
353 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
354 | BUG_ON(dsi_module != 1); | |
355 | b = 1; | |
356 | dsidev = dsi_get_dsidev_from_id(1); | |
357 | dsi_wait_pll_hsdiv_dsi_active(dsidev); | |
358 | break; | |
66534e8e AT |
359 | default: |
360 | BUG(); | |
361 | } | |
e406f907 | 362 | |
a2e5d827 AT |
363 | pos = dsi_module == 0 ? 1 : 10; |
364 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ | |
2f18c4d8 | 365 | |
5a8b572d | 366 | dss.dsi_clk_source[dsi_module] = clk_src; |
559d6701 TV |
367 | } |
368 | ||
ea75159e | 369 | void dss_select_lcd_clk_source(enum omap_channel channel, |
89a35e51 | 370 | enum omap_dss_clk_source clk_src) |
ea75159e | 371 | { |
a72b64b9 | 372 | struct platform_device *dsidev; |
ea75159e AT |
373 | int b, ix, pos; |
374 | ||
375 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) | |
376 | return; | |
377 | ||
378 | switch (clk_src) { | |
89a35e51 | 379 | case OMAP_DSS_CLK_SRC_FCK: |
ea75159e AT |
380 | b = 0; |
381 | break; | |
89a35e51 | 382 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
ea75159e AT |
383 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
384 | b = 1; | |
a72b64b9 AT |
385 | dsidev = dsi_get_dsidev_from_id(0); |
386 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
ea75159e | 387 | break; |
5a8b572d AT |
388 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
389 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2); | |
390 | b = 1; | |
391 | dsidev = dsi_get_dsidev_from_id(1); | |
392 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
393 | break; | |
ea75159e AT |
394 | default: |
395 | BUG(); | |
396 | } | |
397 | ||
398 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; | |
399 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ | |
400 | ||
401 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
402 | dss.lcd_clk_source[ix] = clk_src; | |
403 | } | |
404 | ||
89a35e51 | 405 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 406 | { |
2f18c4d8 | 407 | return dss.dispc_clk_source; |
559d6701 TV |
408 | } |
409 | ||
5a8b572d | 410 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
559d6701 | 411 | { |
5a8b572d | 412 | return dss.dsi_clk_source[dsi_module]; |
559d6701 TV |
413 | } |
414 | ||
89a35e51 | 415 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
ea75159e | 416 | { |
89976f29 AT |
417 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
418 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
419 | return dss.lcd_clk_source[ix]; | |
420 | } else { | |
421 | /* LCD_CLK source is the same as DISPC_FCLK source for | |
422 | * OMAP2 and OMAP3 */ | |
423 | return dss.dispc_clk_source; | |
424 | } | |
ea75159e AT |
425 | } |
426 | ||
559d6701 TV |
427 | /* calculate clock rates using dividers in cinfo */ |
428 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) | |
429 | { | |
0acf659f TV |
430 | if (dss.dpll4_m4_ck) { |
431 | unsigned long prate; | |
2de11086 | 432 | u16 fck_div_max = 16; |
559d6701 | 433 | |
2de11086 MR |
434 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
435 | fck_div_max = 32; | |
436 | ||
437 | if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) | |
0acf659f | 438 | return -EINVAL; |
559d6701 | 439 | |
0acf659f | 440 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
559d6701 | 441 | |
0acf659f TV |
442 | cinfo->fck = prate / cinfo->fck_div; |
443 | } else { | |
444 | if (cinfo->fck_div != 0) | |
445 | return -EINVAL; | |
4fbafaf3 | 446 | cinfo->fck = clk_get_rate(dss.dss_clk); |
0acf659f | 447 | } |
559d6701 TV |
448 | |
449 | return 0; | |
450 | } | |
451 | ||
452 | int dss_set_clock_div(struct dss_clock_info *cinfo) | |
453 | { | |
0acf659f TV |
454 | if (dss.dpll4_m4_ck) { |
455 | unsigned long prate; | |
456 | int r; | |
559d6701 | 457 | |
559d6701 TV |
458 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
459 | DSSDBG("dpll4_m4 = %ld\n", prate); | |
460 | ||
461 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); | |
462 | if (r) | |
463 | return r; | |
0acf659f TV |
464 | } else { |
465 | if (cinfo->fck_div != 0) | |
466 | return -EINVAL; | |
559d6701 TV |
467 | } |
468 | ||
469 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | int dss_get_clock_div(struct dss_clock_info *cinfo) | |
475 | { | |
4fbafaf3 | 476 | cinfo->fck = clk_get_rate(dss.dss_clk); |
559d6701 | 477 | |
0acf659f | 478 | if (dss.dpll4_m4_ck) { |
559d6701 | 479 | unsigned long prate; |
0acf659f | 480 | |
559d6701 | 481 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
0acf659f | 482 | |
2de11086 | 483 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
ac01bb7e K |
484 | cinfo->fck_div = prate / (cinfo->fck); |
485 | else | |
486 | cinfo->fck_div = prate / (cinfo->fck / 2); | |
559d6701 TV |
487 | } else { |
488 | cinfo->fck_div = 0; | |
489 | } | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | unsigned long dss_get_dpll4_rate(void) | |
495 | { | |
0acf659f | 496 | if (dss.dpll4_m4_ck) |
559d6701 TV |
497 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
498 | else | |
499 | return 0; | |
500 | } | |
501 | ||
502 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, | |
503 | struct dss_clock_info *dss_cinfo, | |
504 | struct dispc_clock_info *dispc_cinfo) | |
505 | { | |
506 | unsigned long prate; | |
507 | struct dss_clock_info best_dss; | |
508 | struct dispc_clock_info best_dispc; | |
509 | ||
819d807c | 510 | unsigned long fck, max_dss_fck; |
559d6701 | 511 | |
2de11086 | 512 | u16 fck_div, fck_div_max = 16; |
559d6701 TV |
513 | |
514 | int match = 0; | |
515 | int min_fck_per_pck; | |
516 | ||
517 | prate = dss_get_dpll4_rate(); | |
518 | ||
31ef8237 | 519 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 520 | |
4fbafaf3 | 521 | fck = clk_get_rate(dss.dss_clk); |
559d6701 TV |
522 | if (req_pck == dss.cache_req_pck && |
523 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || | |
524 | dss.cache_dss_cinfo.fck == fck)) { | |
525 | DSSDBG("dispc clock info found from cache.\n"); | |
526 | *dss_cinfo = dss.cache_dss_cinfo; | |
527 | *dispc_cinfo = dss.cache_dispc_cinfo; | |
528 | return 0; | |
529 | } | |
530 | ||
531 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
532 | ||
533 | if (min_fck_per_pck && | |
819d807c | 534 | req_pck * min_fck_per_pck > max_dss_fck) { |
559d6701 TV |
535 | DSSERR("Requested pixel clock not possible with the current " |
536 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
537 | "the constraint off.\n"); | |
538 | min_fck_per_pck = 0; | |
539 | } | |
540 | ||
541 | retry: | |
542 | memset(&best_dss, 0, sizeof(best_dss)); | |
543 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
544 | ||
2de11086 | 545 | if (dss.dpll4_m4_ck == NULL) { |
559d6701 TV |
546 | struct dispc_clock_info cur_dispc; |
547 | /* XXX can we change the clock on omap2? */ | |
4fbafaf3 | 548 | fck = clk_get_rate(dss.dss_clk); |
559d6701 TV |
549 | fck_div = 1; |
550 | ||
551 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
552 | match = 1; | |
553 | ||
554 | best_dss.fck = fck; | |
555 | best_dss.fck_div = fck_div; | |
556 | ||
557 | best_dispc = cur_dispc; | |
558 | ||
559 | goto found; | |
2de11086 MR |
560 | } else { |
561 | if (cpu_is_omap3630() || cpu_is_omap44xx()) | |
562 | fck_div_max = 32; | |
563 | ||
564 | for (fck_div = fck_div_max; fck_div > 0; --fck_div) { | |
559d6701 TV |
565 | struct dispc_clock_info cur_dispc; |
566 | ||
2de11086 | 567 | if (fck_div_max == 32) |
ac01bb7e K |
568 | fck = prate / fck_div; |
569 | else | |
570 | fck = prate / fck_div * 2; | |
559d6701 | 571 | |
819d807c | 572 | if (fck > max_dss_fck) |
559d6701 TV |
573 | continue; |
574 | ||
575 | if (min_fck_per_pck && | |
576 | fck < req_pck * min_fck_per_pck) | |
577 | continue; | |
578 | ||
579 | match = 1; | |
580 | ||
581 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
582 | ||
583 | if (abs(cur_dispc.pck - req_pck) < | |
584 | abs(best_dispc.pck - req_pck)) { | |
585 | ||
586 | best_dss.fck = fck; | |
587 | best_dss.fck_div = fck_div; | |
588 | ||
589 | best_dispc = cur_dispc; | |
590 | ||
591 | if (cur_dispc.pck == req_pck) | |
592 | goto found; | |
593 | } | |
594 | } | |
559d6701 TV |
595 | } |
596 | ||
597 | found: | |
598 | if (!match) { | |
599 | if (min_fck_per_pck) { | |
600 | DSSERR("Could not find suitable clock settings.\n" | |
601 | "Turning FCK/PCK constraint off and" | |
602 | "trying again.\n"); | |
603 | min_fck_per_pck = 0; | |
604 | goto retry; | |
605 | } | |
606 | ||
607 | DSSERR("Could not find suitable clock settings.\n"); | |
608 | ||
609 | return -EINVAL; | |
610 | } | |
611 | ||
612 | if (dss_cinfo) | |
613 | *dss_cinfo = best_dss; | |
614 | if (dispc_cinfo) | |
615 | *dispc_cinfo = best_dispc; | |
616 | ||
617 | dss.cache_req_pck = req_pck; | |
618 | dss.cache_prate = prate; | |
619 | dss.cache_dss_cinfo = best_dss; | |
620 | dss.cache_dispc_cinfo = best_dispc; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
559d6701 TV |
625 | void dss_set_venc_output(enum omap_dss_venc_type type) |
626 | { | |
627 | int l = 0; | |
628 | ||
629 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
630 | l = 0; | |
631 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
632 | l = 1; | |
633 | else | |
634 | BUG(); | |
635 | ||
636 | /* venc out selection. 0 = comp, 1 = svideo */ | |
637 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
638 | } | |
639 | ||
640 | void dss_set_dac_pwrdn_bgz(bool enable) | |
641 | { | |
642 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
643 | } | |
644 | ||
7ed024aa M |
645 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) |
646 | { | |
647 | REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ | |
648 | } | |
649 | ||
4a61e267 TV |
650 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) |
651 | { | |
652 | enum omap_display_type displays; | |
653 | ||
654 | displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); | |
655 | if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) | |
656 | return DSS_VENC_TV_CLK; | |
657 | ||
658 | return REG_GET(DSS_CONTROL, 15, 15); | |
659 | } | |
660 | ||
8b9cb3a8 SG |
661 | static int dss_get_clocks(void) |
662 | { | |
4fbafaf3 | 663 | struct clk *clk; |
8b9cb3a8 | 664 | int r; |
8b9cb3a8 | 665 | |
4fbafaf3 TV |
666 | clk = clk_get(&dss.pdev->dev, "fck"); |
667 | if (IS_ERR(clk)) { | |
668 | DSSERR("can't get clock fck\n"); | |
669 | r = PTR_ERR(clk); | |
8b9cb3a8 | 670 | goto err; |
a1a0dcca | 671 | } |
8b9cb3a8 | 672 | |
4fbafaf3 | 673 | dss.dss_clk = clk; |
8b9cb3a8 | 674 | |
94c042ce | 675 | if (cpu_is_omap34xx()) { |
4fbafaf3 TV |
676 | clk = clk_get(NULL, "dpll4_m4_ck"); |
677 | if (IS_ERR(clk)) { | |
94c042ce | 678 | DSSERR("Failed to get dpll4_m4_ck\n"); |
4fbafaf3 | 679 | r = PTR_ERR(clk); |
94c042ce TV |
680 | goto err; |
681 | } | |
682 | } else if (cpu_is_omap44xx()) { | |
4fbafaf3 TV |
683 | clk = clk_get(NULL, "dpll_per_m5x2_ck"); |
684 | if (IS_ERR(clk)) { | |
94c042ce | 685 | DSSERR("Failed to get dpll_per_m5x2_ck\n"); |
4fbafaf3 | 686 | r = PTR_ERR(clk); |
94c042ce TV |
687 | goto err; |
688 | } | |
689 | } else { /* omap24xx */ | |
4fbafaf3 | 690 | clk = NULL; |
94c042ce TV |
691 | } |
692 | ||
4fbafaf3 | 693 | dss.dpll4_m4_ck = clk; |
94c042ce | 694 | |
8b9cb3a8 SG |
695 | return 0; |
696 | ||
697 | err: | |
4fbafaf3 TV |
698 | if (dss.dss_clk) |
699 | clk_put(dss.dss_clk); | |
94c042ce TV |
700 | if (dss.dpll4_m4_ck) |
701 | clk_put(dss.dpll4_m4_ck); | |
8b9cb3a8 SG |
702 | |
703 | return r; | |
704 | } | |
705 | ||
706 | static void dss_put_clocks(void) | |
707 | { | |
94c042ce TV |
708 | if (dss.dpll4_m4_ck) |
709 | clk_put(dss.dpll4_m4_ck); | |
4fbafaf3 | 710 | clk_put(dss.dss_clk); |
8b9cb3a8 SG |
711 | } |
712 | ||
852f0838 | 713 | static int dss_runtime_get(void) |
8b9cb3a8 | 714 | { |
4fbafaf3 | 715 | int r; |
8b9cb3a8 | 716 | |
4fbafaf3 | 717 | DSSDBG("dss_runtime_get\n"); |
8b9cb3a8 | 718 | |
4fbafaf3 TV |
719 | r = pm_runtime_get_sync(&dss.pdev->dev); |
720 | WARN_ON(r < 0); | |
721 | return r < 0 ? r : 0; | |
8b9cb3a8 SG |
722 | } |
723 | ||
852f0838 | 724 | static void dss_runtime_put(void) |
8b9cb3a8 | 725 | { |
4fbafaf3 | 726 | int r; |
8b9cb3a8 | 727 | |
4fbafaf3 | 728 | DSSDBG("dss_runtime_put\n"); |
8b9cb3a8 | 729 | |
0eaf9f52 | 730 | r = pm_runtime_put_sync(&dss.pdev->dev); |
4fbafaf3 | 731 | WARN_ON(r < 0); |
8b9cb3a8 SG |
732 | } |
733 | ||
8b9cb3a8 SG |
734 | /* DEBUGFS */ |
735 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
736 | void dss_debug_dump_clocks(struct seq_file *s) | |
737 | { | |
8b9cb3a8 SG |
738 | dss_dump_clocks(s); |
739 | dispc_dump_clocks(s); | |
740 | #ifdef CONFIG_OMAP2_DSS_DSI | |
741 | dsi_dump_clocks(s); | |
742 | #endif | |
743 | } | |
744 | #endif | |
745 | ||
96c401bc SG |
746 | /* DSS HW IP initialisation */ |
747 | static int omap_dsshw_probe(struct platform_device *pdev) | |
748 | { | |
b98482ed TV |
749 | struct resource *dss_mem; |
750 | u32 rev; | |
96c401bc | 751 | int r; |
96c401bc SG |
752 | |
753 | dss.pdev = pdev; | |
754 | ||
b98482ed TV |
755 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
756 | if (!dss_mem) { | |
757 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
cd3b3449 | 758 | return -EINVAL; |
b98482ed | 759 | } |
cd3b3449 | 760 | |
6e2a14d2 JL |
761 | dss.base = devm_ioremap(&pdev->dev, dss_mem->start, |
762 | resource_size(dss_mem)); | |
b98482ed TV |
763 | if (!dss.base) { |
764 | DSSERR("can't ioremap DSS\n"); | |
cd3b3449 | 765 | return -ENOMEM; |
b98482ed TV |
766 | } |
767 | ||
8b9cb3a8 SG |
768 | r = dss_get_clocks(); |
769 | if (r) | |
cd3b3449 | 770 | return r; |
8b9cb3a8 | 771 | |
4fbafaf3 | 772 | pm_runtime_enable(&pdev->dev); |
b98482ed | 773 | |
4fbafaf3 TV |
774 | r = dss_runtime_get(); |
775 | if (r) | |
776 | goto err_runtime_get; | |
b98482ed TV |
777 | |
778 | /* Select DPLL */ | |
779 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
780 | ||
781 | #ifdef CONFIG_OMAP2_DSS_VENC | |
782 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
783 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
784 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
785 | #endif | |
786 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
787 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
788 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; | |
789 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
790 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
96c401bc | 791 | |
b98482ed TV |
792 | rev = dss_read_reg(DSS_REVISION); |
793 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
794 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
795 | ||
4fbafaf3 | 796 | dss_runtime_put(); |
b98482ed | 797 | |
e40402cf TV |
798 | dss_debugfs_create_file("dss", dss_dump_regs); |
799 | ||
8b9cb3a8 | 800 | return 0; |
a57dd4fe | 801 | |
4fbafaf3 TV |
802 | err_runtime_get: |
803 | pm_runtime_disable(&pdev->dev); | |
8b9cb3a8 | 804 | dss_put_clocks(); |
96c401bc SG |
805 | return r; |
806 | } | |
807 | ||
808 | static int omap_dsshw_remove(struct platform_device *pdev) | |
809 | { | |
4fbafaf3 | 810 | pm_runtime_disable(&pdev->dev); |
8b9cb3a8 SG |
811 | |
812 | dss_put_clocks(); | |
b98482ed | 813 | |
96c401bc SG |
814 | return 0; |
815 | } | |
816 | ||
4fbafaf3 TV |
817 | static int dss_runtime_suspend(struct device *dev) |
818 | { | |
819 | dss_save_context(); | |
a8081d31 | 820 | dss_set_min_bus_tput(dev, 0); |
4fbafaf3 TV |
821 | return 0; |
822 | } | |
823 | ||
824 | static int dss_runtime_resume(struct device *dev) | |
825 | { | |
a8081d31 TV |
826 | int r; |
827 | /* | |
828 | * Set an arbitrarily high tput request to ensure OPP100. | |
829 | * What we should really do is to make a request to stay in OPP100, | |
830 | * without any tput requirements, but that is not currently possible | |
831 | * via the PM layer. | |
832 | */ | |
833 | ||
834 | r = dss_set_min_bus_tput(dev, 1000000000); | |
835 | if (r) | |
836 | return r; | |
837 | ||
39020710 | 838 | dss_restore_context(); |
4fbafaf3 TV |
839 | return 0; |
840 | } | |
841 | ||
842 | static const struct dev_pm_ops dss_pm_ops = { | |
843 | .runtime_suspend = dss_runtime_suspend, | |
844 | .runtime_resume = dss_runtime_resume, | |
845 | }; | |
846 | ||
96c401bc | 847 | static struct platform_driver omap_dsshw_driver = { |
96c401bc SG |
848 | .remove = omap_dsshw_remove, |
849 | .driver = { | |
850 | .name = "omapdss_dss", | |
851 | .owner = THIS_MODULE, | |
4fbafaf3 | 852 | .pm = &dss_pm_ops, |
96c401bc SG |
853 | }, |
854 | }; | |
855 | ||
856 | int dss_init_platform_driver(void) | |
857 | { | |
11436e1d | 858 | return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe); |
96c401bc SG |
859 | } |
860 | ||
861 | void dss_uninit_platform_driver(void) | |
862 | { | |
04c742c3 | 863 | platform_driver_unregister(&omap_dsshw_driver); |
96c401bc | 864 | } |