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Commit | Line | Data |
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c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
cca35017 | 35 | #include <linux/gpio.h> |
a0b38cc4 | 36 | #include <video/omapdss.h> |
c3198a5e | 37 | |
94c52987 | 38 | #include "ti_hdmi.h" |
c3198a5e | 39 | #include "dss.h" |
ad44cc32 | 40 | #include "dss_features.h" |
c3198a5e | 41 | |
95a8aeb6 M |
42 | #define HDMI_WP 0x0 |
43 | #define HDMI_CORE_SYS 0x400 | |
44 | #define HDMI_CORE_AV 0x900 | |
45 | #define HDMI_PLLCTRL 0x200 | |
46 | #define HDMI_PHY 0x300 | |
47 | ||
7c1f1eca M |
48 | /* HDMI EDID Length move this */ |
49 | #define HDMI_EDID_MAX_LENGTH 256 | |
50 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
51 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
52 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
53 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
54 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
55 | ||
b44e4582 | 56 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
57 | #define HDMI_DEFAULT_REGM2 1 |
58 | ||
c3198a5e M |
59 | static struct { |
60 | struct mutex lock; | |
c3198a5e | 61 | struct platform_device *pdev; |
95a8aeb6 | 62 | struct hdmi_ip_data ip_data; |
4fbafaf3 TV |
63 | |
64 | struct clk *sys_clk; | |
cca35017 TV |
65 | |
66 | int ct_cp_hpd_gpio; | |
67 | int ls_oe_gpio; | |
68 | int hpd_gpio; | |
c3198a5e M |
69 | } hdmi; |
70 | ||
71 | /* | |
72 | * Logic for the below structure : | |
73 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
74 | * There is a correspondence between CEA/VESA timing and code, please | |
75 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
76 | * | |
77 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
78 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
79 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
80 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
81 | * is read from the TV, EDID is parsed to find the timing values and then | |
82 | * map it to corresponding CEA or VESA index. | |
83 | */ | |
84 | ||
46095b2d | 85 | static const struct hdmi_config cea_timings[] = { |
cc937e5e AT |
86 | { |
87 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | |
88 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
89 | false, }, | |
90 | { 1, HDMI_HDMI }, | |
91 | }, | |
92 | { | |
93 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | |
94 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
95 | false, }, | |
96 | { 2, HDMI_HDMI }, | |
97 | }, | |
98 | { | |
99 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
100 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
101 | false, }, | |
102 | { 4, HDMI_HDMI }, | |
103 | }, | |
104 | { | |
105 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | |
106 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
107 | true, }, | |
108 | { 5, HDMI_HDMI }, | |
109 | }, | |
110 | { | |
111 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | |
112 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
113 | true, }, | |
114 | { 6, HDMI_HDMI }, | |
115 | }, | |
116 | { | |
117 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | |
118 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
119 | false, }, | |
120 | { 16, HDMI_HDMI }, | |
121 | }, | |
122 | { | |
123 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | |
124 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
125 | false, }, | |
126 | { 17, HDMI_HDMI }, | |
127 | }, | |
128 | { | |
129 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | |
130 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
131 | false, }, | |
132 | { 19, HDMI_HDMI }, | |
133 | }, | |
134 | { | |
135 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | |
136 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
137 | true, }, | |
138 | { 20, HDMI_HDMI }, | |
139 | }, | |
140 | { | |
141 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | |
142 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
143 | true, }, | |
144 | { 21, HDMI_HDMI }, | |
145 | }, | |
146 | { | |
147 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | |
148 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
149 | false, }, | |
150 | { 29, HDMI_HDMI }, | |
151 | }, | |
152 | { | |
153 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | |
154 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
155 | false, }, | |
156 | { 31, HDMI_HDMI }, | |
157 | }, | |
158 | { | |
159 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | |
160 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
161 | false, }, | |
162 | { 32, HDMI_HDMI }, | |
163 | }, | |
164 | { | |
165 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | |
166 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
167 | false, }, | |
168 | { 35, HDMI_HDMI }, | |
169 | }, | |
170 | { | |
171 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | |
172 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
173 | false, }, | |
174 | { 37, HDMI_HDMI }, | |
175 | }, | |
46095b2d | 176 | }; |
cc937e5e | 177 | |
46095b2d | 178 | static const struct hdmi_config vesa_timings[] = { |
a05ce78f | 179 | /* VESA From Here */ |
cc937e5e AT |
180 | { |
181 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | |
182 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
183 | false, }, | |
184 | { 4, HDMI_DVI }, | |
185 | }, | |
186 | { | |
187 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | |
188 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
189 | false, }, | |
190 | { 9, HDMI_DVI }, | |
191 | }, | |
192 | { | |
193 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | |
194 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
195 | false, }, | |
196 | { 0xE, HDMI_DVI }, | |
197 | }, | |
198 | { | |
199 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | |
200 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
201 | false, }, | |
202 | { 0x17, HDMI_DVI }, | |
203 | }, | |
204 | { | |
205 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | |
206 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
207 | false, }, | |
208 | { 0x1C, HDMI_DVI }, | |
209 | }, | |
210 | { | |
211 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | |
212 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
213 | false, }, | |
214 | { 0x27, HDMI_DVI }, | |
215 | }, | |
216 | { | |
217 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | |
218 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
219 | false, }, | |
220 | { 0x20, HDMI_DVI }, | |
221 | }, | |
222 | { | |
223 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | |
224 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
225 | false, }, | |
226 | { 0x23, HDMI_DVI }, | |
227 | }, | |
228 | { | |
229 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | |
230 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
231 | false, }, | |
232 | { 0x10, HDMI_DVI }, | |
233 | }, | |
234 | { | |
235 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | |
236 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
237 | false, }, | |
238 | { 0x2A, HDMI_DVI }, | |
239 | }, | |
240 | { | |
241 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | |
242 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
243 | false, }, | |
244 | { 0x2F, HDMI_DVI }, | |
245 | }, | |
246 | { | |
247 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | |
248 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
249 | false, }, | |
250 | { 0x3A, HDMI_DVI }, | |
251 | }, | |
252 | { | |
253 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | |
254 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
255 | false, }, | |
256 | { 0x51, HDMI_DVI }, | |
257 | }, | |
258 | { | |
259 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | |
260 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
261 | false, }, | |
262 | { 0x52, HDMI_DVI }, | |
263 | }, | |
264 | { | |
265 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | |
266 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
267 | false, }, | |
268 | { 0x16, HDMI_DVI }, | |
269 | }, | |
270 | { | |
271 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | |
272 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
273 | false, }, | |
274 | { 0x29, HDMI_DVI }, | |
275 | }, | |
276 | { | |
277 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | |
278 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
279 | false, }, | |
280 | { 0x39, HDMI_DVI }, | |
281 | }, | |
282 | { | |
283 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | |
284 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
285 | false, }, | |
286 | { 0x1B, HDMI_DVI }, | |
287 | }, | |
288 | { | |
289 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
290 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
291 | false, }, | |
292 | { 0x55, HDMI_DVI }, | |
293 | }, | |
c3198a5e M |
294 | }; |
295 | ||
4fbafaf3 TV |
296 | static int hdmi_runtime_get(void) |
297 | { | |
298 | int r; | |
299 | ||
300 | DSSDBG("hdmi_runtime_get\n"); | |
301 | ||
302 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
303 | WARN_ON(r < 0); | |
a247ce78 | 304 | if (r < 0) |
852f0838 | 305 | return r; |
a247ce78 AT |
306 | |
307 | return 0; | |
4fbafaf3 TV |
308 | } |
309 | ||
310 | static void hdmi_runtime_put(void) | |
311 | { | |
312 | int r; | |
313 | ||
314 | DSSDBG("hdmi_runtime_put\n"); | |
315 | ||
0eaf9f52 | 316 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 317 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
318 | } |
319 | ||
9d8232a7 | 320 | static int __init hdmi_init_display(struct omap_dss_device *dssdev) |
c3198a5e | 321 | { |
cca35017 TV |
322 | int r; |
323 | ||
324 | struct gpio gpios[] = { | |
325 | { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" }, | |
326 | { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" }, | |
327 | { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" }, | |
328 | }; | |
329 | ||
c3198a5e M |
330 | DSSDBG("init_display\n"); |
331 | ||
60634a28 | 332 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
cca35017 TV |
333 | |
334 | r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); | |
335 | if (r) | |
336 | return r; | |
337 | ||
c3198a5e M |
338 | return 0; |
339 | } | |
340 | ||
cca35017 TV |
341 | static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev) |
342 | { | |
343 | DSSDBG("uninit_display\n"); | |
344 | ||
345 | gpio_free(hdmi.ct_cp_hpd_gpio); | |
346 | gpio_free(hdmi.ls_oe_gpio); | |
347 | gpio_free(hdmi.hpd_gpio); | |
348 | } | |
349 | ||
46095b2d M |
350 | static const struct hdmi_config *hdmi_find_timing( |
351 | const struct hdmi_config *timings_arr, | |
352 | int len) | |
c3198a5e | 353 | { |
46095b2d | 354 | int i; |
c3198a5e | 355 | |
46095b2d | 356 | for (i = 0; i < len; i++) { |
9e4ed603 | 357 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
46095b2d M |
358 | return &timings_arr[i]; |
359 | } | |
360 | return NULL; | |
361 | } | |
c3198a5e | 362 | |
46095b2d M |
363 | static const struct hdmi_config *hdmi_get_timings(void) |
364 | { | |
365 | const struct hdmi_config *arr; | |
366 | int len; | |
367 | ||
9e4ed603 | 368 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
46095b2d M |
369 | arr = vesa_timings; |
370 | len = ARRAY_SIZE(vesa_timings); | |
371 | } else { | |
372 | arr = cea_timings; | |
373 | len = ARRAY_SIZE(cea_timings); | |
374 | } | |
375 | ||
376 | return hdmi_find_timing(arr, len); | |
377 | } | |
378 | ||
379 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | |
cc937e5e | 380 | const struct omap_video_timings *timing2) |
46095b2d M |
381 | { |
382 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | |
383 | ||
384 | if ((timing2->pixel_clock == timing1->pixel_clock) && | |
385 | (timing2->x_res == timing1->x_res) && | |
386 | (timing2->y_res == timing1->y_res)) { | |
c3198a5e | 387 | |
46095b2d M |
388 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
389 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | |
390 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
391 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
392 | ||
393 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | |
394 | "timing2_hsync = %d timing2_vsync = %d\n", | |
395 | timing1_hsync, timing1_vsync, | |
396 | timing2_hsync, timing2_vsync); | |
397 | ||
398 | if ((timing1_hsync == timing2_hsync) && | |
399 | (timing1_vsync == timing2_vsync)) { | |
400 | return true; | |
401 | } | |
c3198a5e | 402 | } |
46095b2d | 403 | return false; |
c3198a5e M |
404 | } |
405 | ||
406 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
407 | { | |
46095b2d | 408 | int i; |
c3198a5e M |
409 | struct hdmi_cm cm = {-1}; |
410 | DSSDBG("hdmi_get_code\n"); | |
411 | ||
46095b2d M |
412 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
413 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | |
414 | cm = cea_timings[i].cm; | |
415 | goto end; | |
416 | } | |
417 | } | |
418 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | |
419 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | |
420 | cm = vesa_timings[i].cm; | |
421 | goto end; | |
c3198a5e M |
422 | } |
423 | } | |
424 | ||
46095b2d | 425 | end: return cm; |
c3198a5e | 426 | |
c3198a5e M |
427 | } |
428 | ||
c3dc6a7a AT |
429 | unsigned long hdmi_get_pixel_clock(void) |
430 | { | |
431 | /* HDMI Pixel Clock in Mhz */ | |
a05ce78f | 432 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
c3dc6a7a AT |
433 | } |
434 | ||
6cb07b25 AT |
435 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
436 | struct hdmi_pll_info *pi) | |
c3198a5e | 437 | { |
6cb07b25 | 438 | unsigned long clkin, refclk; |
c3198a5e M |
439 | u32 mf; |
440 | ||
4fbafaf3 | 441 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
442 | /* |
443 | * Input clock is predivided by N + 1 | |
444 | * out put of which is reference clk | |
445 | */ | |
8d88767a TV |
446 | if (dssdev->clocks.hdmi.regn == 0) |
447 | pi->regn = HDMI_DEFAULT_REGN; | |
448 | else | |
449 | pi->regn = dssdev->clocks.hdmi.regn; | |
450 | ||
b44e4582 | 451 | refclk = clkin / pi->regn; |
c3198a5e | 452 | |
8d88767a TV |
453 | if (dssdev->clocks.hdmi.regm2 == 0) |
454 | pi->regm2 = HDMI_DEFAULT_REGM2; | |
455 | else | |
456 | pi->regm2 = dssdev->clocks.hdmi.regm2; | |
c3198a5e | 457 | |
dd2116a3 M |
458 | /* |
459 | * multiplier is pixel_clk/ref_clk | |
460 | * Multiplying by 100 to avoid fractional part removal | |
461 | */ | |
462 | pi->regm = phy * pi->regm2 / refclk; | |
463 | ||
c3198a5e M |
464 | /* |
465 | * fractional multiplier is remainder of the difference between | |
466 | * multiplier and actual phy(required pixel clock thus should be | |
467 | * multiplied by 2^18(262144) divided by the reference clock | |
468 | */ | |
dd2116a3 M |
469 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; |
470 | pi->regmf = pi->regm2 * mf / refclk; | |
c3198a5e M |
471 | |
472 | /* | |
473 | * Dcofreq should be set to 1 if required pixel clock | |
474 | * is greater than 1000MHz | |
475 | */ | |
476 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 477 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 478 | |
7b27da54 M |
479 | /* Set the reference clock to sysclk reference */ |
480 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
481 | ||
c3198a5e M |
482 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
483 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
484 | } | |
485 | ||
c3198a5e M |
486 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
487 | { | |
46095b2d | 488 | int r; |
c3198a5e | 489 | struct omap_video_timings *p; |
6cb07b25 | 490 | unsigned long phy; |
c3198a5e | 491 | |
cca35017 TV |
492 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 1); |
493 | gpio_set_value(hdmi.ls_oe_gpio, 1); | |
494 | ||
a84b2065 TV |
495 | /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */ |
496 | udelay(300); | |
497 | ||
4fbafaf3 TV |
498 | r = hdmi_runtime_get(); |
499 | if (r) | |
cca35017 | 500 | goto err_runtime_get; |
c3198a5e | 501 | |
7797c6da | 502 | dss_mgr_disable(dssdev->manager); |
c3198a5e | 503 | |
7849398f | 504 | p = &hdmi.ip_data.cfg.timings; |
c3198a5e | 505 | |
7849398f | 506 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
c3198a5e | 507 | |
c3198a5e M |
508 | phy = p->pixel_clock; |
509 | ||
7b27da54 | 510 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 511 | |
c0456be3 | 512 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
c3198a5e | 513 | |
95a8aeb6 | 514 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 515 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
516 | if (r) { |
517 | DSSDBG("Failed to lock PLL\n"); | |
cca35017 | 518 | goto err_pll_enable; |
c3198a5e M |
519 | } |
520 | ||
60634a28 | 521 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
522 | if (r) { |
523 | DSSDBG("Failed to start PHY\n"); | |
d3b4aa51 | 524 | goto err_phy_enable; |
c3198a5e M |
525 | } |
526 | ||
60634a28 | 527 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e M |
528 | |
529 | /* Make selection of HDMI in DSS */ | |
530 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
531 | ||
532 | /* Select the dispc clock source as PRCM clock, to ensure that it is not | |
533 | * DSI PLL source as the clock selected by DSI PLL might not be | |
534 | * sufficient for the resolution selected / that can be changed | |
535 | * dynamically by user. This can be moved to single location , say | |
536 | * Boardfile. | |
537 | */ | |
6cb07b25 | 538 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
c3198a5e M |
539 | |
540 | /* bypass TV gamma table */ | |
541 | dispc_enable_gamma_table(0); | |
542 | ||
543 | /* tv size */ | |
7849398f | 544 | dss_mgr_set_timings(dssdev->manager, p); |
c3198a5e | 545 | |
c0456be3 RN |
546 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); |
547 | if (r) | |
548 | goto err_vid_enable; | |
c3198a5e | 549 | |
33ca237f TV |
550 | r = dss_mgr_enable(dssdev->manager); |
551 | if (r) | |
552 | goto err_mgr_enable; | |
3870c909 | 553 | |
c3198a5e | 554 | return 0; |
33ca237f TV |
555 | |
556 | err_mgr_enable: | |
c0456be3 RN |
557 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
558 | err_vid_enable: | |
33ca237f | 559 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
d3b4aa51 | 560 | err_phy_enable: |
33ca237f | 561 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
cca35017 | 562 | err_pll_enable: |
4fbafaf3 | 563 | hdmi_runtime_put(); |
cca35017 TV |
564 | err_runtime_get: |
565 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 0); | |
566 | gpio_set_value(hdmi.ls_oe_gpio, 0); | |
c3198a5e M |
567 | return -EIO; |
568 | } | |
569 | ||
570 | static void hdmi_power_off(struct omap_dss_device *dssdev) | |
571 | { | |
7797c6da | 572 | dss_mgr_disable(dssdev->manager); |
c3198a5e | 573 | |
c0456be3 | 574 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
60634a28 M |
575 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
576 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
4fbafaf3 | 577 | hdmi_runtime_put(); |
cca35017 TV |
578 | |
579 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 0); | |
580 | gpio_set_value(hdmi.ls_oe_gpio, 0); | |
c3198a5e M |
581 | } |
582 | ||
583 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
584 | struct omap_video_timings *timings) | |
585 | { | |
586 | struct hdmi_cm cm; | |
587 | ||
588 | cm = hdmi_get_code(timings); | |
589 | if (cm.code == -1) { | |
c3198a5e M |
590 | return -EINVAL; |
591 | } | |
592 | ||
593 | return 0; | |
594 | ||
595 | } | |
596 | ||
7849398f AT |
597 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev, |
598 | struct omap_video_timings *timings) | |
c3198a5e M |
599 | { |
600 | struct hdmi_cm cm; | |
7849398f | 601 | const struct hdmi_config *t; |
c3198a5e | 602 | |
ed1aa900 AT |
603 | mutex_lock(&hdmi.lock); |
604 | ||
7849398f AT |
605 | cm = hdmi_get_code(timings); |
606 | hdmi.ip_data.cfg.cm = cm; | |
607 | ||
608 | t = hdmi_get_timings(); | |
609 | if (t != NULL) | |
610 | hdmi.ip_data.cfg = *t; | |
fa70dc5f TV |
611 | |
612 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
613 | int r; | |
614 | ||
615 | hdmi_power_off(dssdev); | |
616 | ||
617 | r = hdmi_power_on(dssdev); | |
618 | if (r) | |
619 | DSSERR("failed to power on device\n"); | |
fcc36619 | 620 | } else { |
7849398f | 621 | dss_mgr_set_timings(dssdev->manager, &t->timings); |
fa70dc5f | 622 | } |
ed1aa900 AT |
623 | |
624 | mutex_unlock(&hdmi.lock); | |
c3198a5e M |
625 | } |
626 | ||
e40402cf | 627 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
628 | { |
629 | mutex_lock(&hdmi.lock); | |
630 | ||
631 | if (hdmi_runtime_get()) | |
632 | return; | |
633 | ||
634 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
635 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
636 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
637 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
638 | ||
639 | hdmi_runtime_put(); | |
640 | mutex_unlock(&hdmi.lock); | |
641 | } | |
642 | ||
47024565 TV |
643 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
644 | { | |
645 | int r; | |
646 | ||
647 | mutex_lock(&hdmi.lock); | |
648 | ||
649 | r = hdmi_runtime_get(); | |
650 | BUG_ON(r); | |
651 | ||
652 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
653 | ||
654 | hdmi_runtime_put(); | |
655 | mutex_unlock(&hdmi.lock); | |
656 | ||
657 | return r; | |
658 | } | |
659 | ||
759593ff TV |
660 | bool omapdss_hdmi_detect(void) |
661 | { | |
662 | int r; | |
663 | ||
664 | mutex_lock(&hdmi.lock); | |
665 | ||
666 | r = hdmi_runtime_get(); | |
667 | BUG_ON(r); | |
668 | ||
669 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); | |
670 | ||
671 | hdmi_runtime_put(); | |
672 | mutex_unlock(&hdmi.lock); | |
673 | ||
674 | return r == 1; | |
675 | } | |
676 | ||
c3198a5e M |
677 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
678 | { | |
679 | int r = 0; | |
680 | ||
681 | DSSDBG("ENTER hdmi_display_enable\n"); | |
682 | ||
683 | mutex_lock(&hdmi.lock); | |
684 | ||
05e1d606 TV |
685 | if (dssdev->manager == NULL) { |
686 | DSSERR("failed to enable display: no manager\n"); | |
687 | r = -ENODEV; | |
688 | goto err0; | |
689 | } | |
690 | ||
cca35017 | 691 | hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio; |
c49d005b | 692 | |
c3198a5e M |
693 | r = omap_dss_start_device(dssdev); |
694 | if (r) { | |
695 | DSSERR("failed to start device\n"); | |
696 | goto err0; | |
697 | } | |
698 | ||
c3198a5e M |
699 | r = hdmi_power_on(dssdev); |
700 | if (r) { | |
701 | DSSERR("failed to power on device\n"); | |
cca35017 | 702 | goto err1; |
c3198a5e M |
703 | } |
704 | ||
705 | mutex_unlock(&hdmi.lock); | |
706 | return 0; | |
707 | ||
c3198a5e M |
708 | err1: |
709 | omap_dss_stop_device(dssdev); | |
710 | err0: | |
711 | mutex_unlock(&hdmi.lock); | |
712 | return r; | |
713 | } | |
714 | ||
715 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) | |
716 | { | |
717 | DSSDBG("Enter hdmi_display_disable\n"); | |
718 | ||
719 | mutex_lock(&hdmi.lock); | |
720 | ||
721 | hdmi_power_off(dssdev); | |
722 | ||
c3198a5e M |
723 | omap_dss_stop_device(dssdev); |
724 | ||
725 | mutex_unlock(&hdmi.lock); | |
726 | } | |
727 | ||
4fbafaf3 TV |
728 | static int hdmi_get_clocks(struct platform_device *pdev) |
729 | { | |
730 | struct clk *clk; | |
731 | ||
732 | clk = clk_get(&pdev->dev, "sys_clk"); | |
733 | if (IS_ERR(clk)) { | |
734 | DSSERR("can't get sys_clk\n"); | |
735 | return PTR_ERR(clk); | |
736 | } | |
737 | ||
738 | hdmi.sys_clk = clk; | |
739 | ||
4fbafaf3 TV |
740 | return 0; |
741 | } | |
742 | ||
743 | static void hdmi_put_clocks(void) | |
744 | { | |
745 | if (hdmi.sys_clk) | |
746 | clk_put(hdmi.sys_clk); | |
4fbafaf3 TV |
747 | } |
748 | ||
35547626 RN |
749 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
750 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | |
751 | { | |
752 | u32 deep_color; | |
25a65359 | 753 | bool deep_color_correct = false; |
35547626 RN |
754 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; |
755 | ||
756 | if (n == NULL || cts == NULL) | |
757 | return -EINVAL; | |
758 | ||
759 | /* TODO: When implemented, query deep color mode here. */ | |
760 | deep_color = 100; | |
761 | ||
25a65359 RN |
762 | /* |
763 | * When using deep color, the default N value (as in the HDMI | |
764 | * specification) yields to an non-integer CTS. Hence, we | |
765 | * modify it while keeping the restrictions described in | |
766 | * section 7.2.1 of the HDMI 1.4a specification. | |
767 | */ | |
35547626 RN |
768 | switch (sample_freq) { |
769 | case 32000: | |
25a65359 RN |
770 | case 48000: |
771 | case 96000: | |
772 | case 192000: | |
773 | if (deep_color == 125) | |
774 | if (pclk == 27027 || pclk == 74250) | |
775 | deep_color_correct = true; | |
776 | if (deep_color == 150) | |
777 | if (pclk == 27027) | |
778 | deep_color_correct = true; | |
35547626 RN |
779 | break; |
780 | case 44100: | |
25a65359 RN |
781 | case 88200: |
782 | case 176400: | |
783 | if (deep_color == 125) | |
784 | if (pclk == 27027) | |
785 | deep_color_correct = true; | |
35547626 RN |
786 | break; |
787 | default: | |
35547626 RN |
788 | return -EINVAL; |
789 | } | |
790 | ||
25a65359 RN |
791 | if (deep_color_correct) { |
792 | switch (sample_freq) { | |
793 | case 32000: | |
794 | *n = 8192; | |
795 | break; | |
796 | case 44100: | |
797 | *n = 12544; | |
798 | break; | |
799 | case 48000: | |
800 | *n = 8192; | |
801 | break; | |
802 | case 88200: | |
803 | *n = 25088; | |
804 | break; | |
805 | case 96000: | |
806 | *n = 16384; | |
807 | break; | |
808 | case 176400: | |
809 | *n = 50176; | |
810 | break; | |
811 | case 192000: | |
812 | *n = 32768; | |
813 | break; | |
814 | default: | |
815 | return -EINVAL; | |
816 | } | |
817 | } else { | |
818 | switch (sample_freq) { | |
819 | case 32000: | |
820 | *n = 4096; | |
821 | break; | |
822 | case 44100: | |
823 | *n = 6272; | |
824 | break; | |
825 | case 48000: | |
826 | *n = 6144; | |
827 | break; | |
828 | case 88200: | |
829 | *n = 12544; | |
830 | break; | |
831 | case 96000: | |
832 | *n = 12288; | |
833 | break; | |
834 | case 176400: | |
835 | *n = 25088; | |
836 | break; | |
837 | case 192000: | |
838 | *n = 24576; | |
839 | break; | |
840 | default: | |
841 | return -EINVAL; | |
842 | } | |
843 | } | |
35547626 RN |
844 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
845 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | |
846 | ||
847 | return 0; | |
848 | } | |
f3a97491 RN |
849 | |
850 | int hdmi_audio_enable(void) | |
851 | { | |
852 | DSSDBG("audio_enable\n"); | |
853 | ||
854 | return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | |
855 | } | |
856 | ||
857 | void hdmi_audio_disable(void) | |
858 | { | |
859 | DSSDBG("audio_disable\n"); | |
860 | ||
861 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); | |
862 | } | |
863 | ||
864 | int hdmi_audio_start(void) | |
865 | { | |
866 | DSSDBG("audio_start\n"); | |
867 | ||
868 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | |
869 | } | |
870 | ||
871 | void hdmi_audio_stop(void) | |
872 | { | |
873 | DSSDBG("audio_stop\n"); | |
874 | ||
875 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | |
876 | } | |
877 | ||
878 | bool hdmi_mode_has_audio(void) | |
879 | { | |
880 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | |
881 | return true; | |
882 | else | |
883 | return false; | |
884 | } | |
885 | ||
886 | int hdmi_audio_config(struct omap_dss_audio *audio) | |
887 | { | |
888 | return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | |
889 | } | |
890 | ||
35547626 RN |
891 | #endif |
892 | ||
38f3daf6 TV |
893 | static void __init hdmi_probe_pdata(struct platform_device *pdev) |
894 | { | |
895 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
896 | int r, i; | |
897 | ||
898 | for (i = 0; i < pdata->num_devices; ++i) { | |
899 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
cca35017 | 900 | struct omap_dss_hdmi_data *priv = dssdev->data; |
38f3daf6 TV |
901 | |
902 | if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI) | |
903 | continue; | |
904 | ||
cca35017 TV |
905 | hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio; |
906 | hdmi.ls_oe_gpio = priv->ls_oe_gpio; | |
907 | hdmi.hpd_gpio = priv->hpd_gpio; | |
908 | ||
38f3daf6 TV |
909 | r = hdmi_init_display(dssdev); |
910 | if (r) { | |
911 | DSSERR("device %s init failed: %d\n", dssdev->name, r); | |
912 | continue; | |
913 | } | |
914 | ||
915 | r = omap_dss_register_device(dssdev, &pdev->dev, i); | |
916 | if (r) | |
917 | DSSERR("device %s register failed: %d\n", | |
918 | dssdev->name, r); | |
919 | } | |
920 | } | |
921 | ||
c3198a5e | 922 | /* HDMI HW IP initialisation */ |
6e7e8f06 | 923 | static int __init omapdss_hdmihw_probe(struct platform_device *pdev) |
c3198a5e M |
924 | { |
925 | struct resource *hdmi_mem; | |
38f3daf6 | 926 | int r; |
c3198a5e | 927 | |
c3198a5e M |
928 | hdmi.pdev = pdev; |
929 | ||
930 | mutex_init(&hdmi.lock); | |
931 | ||
932 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | |
933 | if (!hdmi_mem) { | |
934 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); | |
935 | return -EINVAL; | |
936 | } | |
937 | ||
938 | /* Base address taken from platform */ | |
95a8aeb6 M |
939 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
940 | resource_size(hdmi_mem)); | |
941 | if (!hdmi.ip_data.base_wp) { | |
c3198a5e M |
942 | DSSERR("can't ioremap WP\n"); |
943 | return -ENOMEM; | |
944 | } | |
945 | ||
4fbafaf3 TV |
946 | r = hdmi_get_clocks(pdev); |
947 | if (r) { | |
95a8aeb6 | 948 | iounmap(hdmi.ip_data.base_wp); |
4fbafaf3 TV |
949 | return r; |
950 | } | |
951 | ||
952 | pm_runtime_enable(&pdev->dev); | |
953 | ||
95a8aeb6 M |
954 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
955 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
956 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
957 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
7849398f | 958 | |
3a5383a2 | 959 | mutex_init(&hdmi.ip_data.lock); |
95a8aeb6 | 960 | |
c3198a5e M |
961 | hdmi_panel_init(); |
962 | ||
e40402cf TV |
963 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
964 | ||
38f3daf6 | 965 | hdmi_probe_pdata(pdev); |
35deca3d | 966 | |
c3198a5e M |
967 | return 0; |
968 | } | |
969 | ||
cca35017 TV |
970 | static int __exit hdmi_remove_child(struct device *dev, void *data) |
971 | { | |
972 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
973 | hdmi_uninit_display(dssdev); | |
974 | return 0; | |
975 | } | |
976 | ||
6e7e8f06 | 977 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) |
c3198a5e | 978 | { |
cca35017 TV |
979 | device_for_each_child(&pdev->dev, NULL, hdmi_remove_child); |
980 | ||
35deca3d TV |
981 | omap_dss_unregister_child_devices(&pdev->dev); |
982 | ||
c3198a5e M |
983 | hdmi_panel_exit(); |
984 | ||
4fbafaf3 TV |
985 | pm_runtime_disable(&pdev->dev); |
986 | ||
987 | hdmi_put_clocks(); | |
988 | ||
95a8aeb6 | 989 | iounmap(hdmi.ip_data.base_wp); |
c3198a5e M |
990 | |
991 | return 0; | |
992 | } | |
993 | ||
4fbafaf3 TV |
994 | static int hdmi_runtime_suspend(struct device *dev) |
995 | { | |
f11766d1 | 996 | clk_disable_unprepare(hdmi.sys_clk); |
4fbafaf3 TV |
997 | |
998 | dispc_runtime_put(); | |
4fbafaf3 TV |
999 | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static int hdmi_runtime_resume(struct device *dev) | |
1004 | { | |
1005 | int r; | |
1006 | ||
4fbafaf3 TV |
1007 | r = dispc_runtime_get(); |
1008 | if (r < 0) | |
852f0838 | 1009 | return r; |
4fbafaf3 | 1010 | |
f11766d1 | 1011 | clk_prepare_enable(hdmi.sys_clk); |
4fbafaf3 TV |
1012 | |
1013 | return 0; | |
4fbafaf3 TV |
1014 | } |
1015 | ||
1016 | static const struct dev_pm_ops hdmi_pm_ops = { | |
1017 | .runtime_suspend = hdmi_runtime_suspend, | |
1018 | .runtime_resume = hdmi_runtime_resume, | |
1019 | }; | |
1020 | ||
c3198a5e | 1021 | static struct platform_driver omapdss_hdmihw_driver = { |
6e7e8f06 | 1022 | .remove = __exit_p(omapdss_hdmihw_remove), |
c3198a5e M |
1023 | .driver = { |
1024 | .name = "omapdss_hdmi", | |
1025 | .owner = THIS_MODULE, | |
4fbafaf3 | 1026 | .pm = &hdmi_pm_ops, |
c3198a5e M |
1027 | }, |
1028 | }; | |
1029 | ||
6e7e8f06 | 1030 | int __init hdmi_init_platform_driver(void) |
c3198a5e | 1031 | { |
61055d4b | 1032 | return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe); |
c3198a5e M |
1033 | } |
1034 | ||
6e7e8f06 | 1035 | void __exit hdmi_uninit_platform_driver(void) |
c3198a5e | 1036 | { |
04c742c3 | 1037 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 1038 | } |