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5c18adb3 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/rfbi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "RFBI" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
a8a35931 | 27 | #include <linux/export.h> |
5c18adb3 TV |
28 | #include <linux/vmalloc.h> |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/kfifo.h> | |
33 | #include <linux/ktime.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/seq_file.h> | |
773139f1 | 36 | #include <linux/semaphore.h> |
24e6289c | 37 | #include <linux/platform_device.h> |
4fbafaf3 | 38 | #include <linux/pm_runtime.h> |
5c18adb3 | 39 | |
a0b38cc4 | 40 | #include <video/omapdss.h> |
5c18adb3 TV |
41 | #include "dss.h" |
42 | ||
5c18adb3 TV |
43 | struct rfbi_reg { u16 idx; }; |
44 | ||
45 | #define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) | |
46 | ||
47 | #define RFBI_REVISION RFBI_REG(0x0000) | |
48 | #define RFBI_SYSCONFIG RFBI_REG(0x0010) | |
49 | #define RFBI_SYSSTATUS RFBI_REG(0x0014) | |
50 | #define RFBI_CONTROL RFBI_REG(0x0040) | |
51 | #define RFBI_PIXEL_CNT RFBI_REG(0x0044) | |
52 | #define RFBI_LINE_NUMBER RFBI_REG(0x0048) | |
53 | #define RFBI_CMD RFBI_REG(0x004c) | |
54 | #define RFBI_PARAM RFBI_REG(0x0050) | |
55 | #define RFBI_DATA RFBI_REG(0x0054) | |
56 | #define RFBI_READ RFBI_REG(0x0058) | |
57 | #define RFBI_STATUS RFBI_REG(0x005c) | |
58 | ||
59 | #define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18) | |
60 | #define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18) | |
61 | #define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18) | |
62 | #define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18) | |
63 | #define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18) | |
64 | #define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18) | |
65 | ||
66 | #define RFBI_VSYNC_WIDTH RFBI_REG(0x0090) | |
67 | #define RFBI_HSYNC_WIDTH RFBI_REG(0x0094) | |
68 | ||
5c18adb3 TV |
69 | #define REG_FLD_MOD(idx, val, start, end) \ |
70 | rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) | |
71 | ||
5c18adb3 TV |
72 | enum omap_rfbi_cycleformat { |
73 | OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0, | |
74 | OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1, | |
75 | OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2, | |
76 | OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3, | |
77 | }; | |
78 | ||
79 | enum omap_rfbi_datatype { | |
80 | OMAP_DSS_RFBI_DATATYPE_12 = 0, | |
81 | OMAP_DSS_RFBI_DATATYPE_16 = 1, | |
82 | OMAP_DSS_RFBI_DATATYPE_18 = 2, | |
83 | OMAP_DSS_RFBI_DATATYPE_24 = 3, | |
84 | }; | |
85 | ||
86 | enum omap_rfbi_parallelmode { | |
87 | OMAP_DSS_RFBI_PARALLELMODE_8 = 0, | |
88 | OMAP_DSS_RFBI_PARALLELMODE_9 = 1, | |
89 | OMAP_DSS_RFBI_PARALLELMODE_12 = 2, | |
90 | OMAP_DSS_RFBI_PARALLELMODE_16 = 3, | |
91 | }; | |
92 | ||
5c18adb3 TV |
93 | static int rfbi_convert_timings(struct rfbi_timings *t); |
94 | static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); | |
5c18adb3 TV |
95 | |
96 | static struct { | |
3448d500 | 97 | struct platform_device *pdev; |
5c18adb3 TV |
98 | void __iomem *base; |
99 | ||
100 | unsigned long l4_khz; | |
101 | ||
102 | enum omap_rfbi_datatype datatype; | |
103 | enum omap_rfbi_parallelmode parallelmode; | |
104 | ||
105 | enum omap_rfbi_te_mode te_mode; | |
106 | int te_enabled; | |
107 | ||
108 | void (*framedone_callback)(void *data); | |
109 | void *framedone_callback_data; | |
110 | ||
111 | struct omap_dss_device *dssdev[2]; | |
112 | ||
773139f1 | 113 | struct semaphore bus_lock; |
5c18adb3 TV |
114 | } rfbi; |
115 | ||
5c18adb3 TV |
116 | static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val) |
117 | { | |
118 | __raw_writel(val, rfbi.base + idx.idx); | |
119 | } | |
120 | ||
121 | static inline u32 rfbi_read_reg(const struct rfbi_reg idx) | |
122 | { | |
123 | return __raw_readl(rfbi.base + idx.idx); | |
124 | } | |
125 | ||
4fbafaf3 | 126 | static int rfbi_runtime_get(void) |
5c18adb3 | 127 | { |
4fbafaf3 TV |
128 | int r; |
129 | ||
130 | DSSDBG("rfbi_runtime_get\n"); | |
131 | ||
132 | r = pm_runtime_get_sync(&rfbi.pdev->dev); | |
133 | WARN_ON(r < 0); | |
134 | return r < 0 ? r : 0; | |
135 | } | |
136 | ||
137 | static void rfbi_runtime_put(void) | |
138 | { | |
139 | int r; | |
140 | ||
141 | DSSDBG("rfbi_runtime_put\n"); | |
142 | ||
143 | r = pm_runtime_put(&rfbi.pdev->dev); | |
144 | WARN_ON(r < 0); | |
5c18adb3 TV |
145 | } |
146 | ||
773139f1 TV |
147 | void rfbi_bus_lock(void) |
148 | { | |
149 | down(&rfbi.bus_lock); | |
150 | } | |
151 | EXPORT_SYMBOL(rfbi_bus_lock); | |
152 | ||
153 | void rfbi_bus_unlock(void) | |
154 | { | |
155 | up(&rfbi.bus_lock); | |
156 | } | |
157 | EXPORT_SYMBOL(rfbi_bus_unlock); | |
158 | ||
5c18adb3 TV |
159 | void omap_rfbi_write_command(const void *buf, u32 len) |
160 | { | |
5c18adb3 TV |
161 | switch (rfbi.parallelmode) { |
162 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
163 | { | |
164 | const u8 *b = buf; | |
165 | for (; len; len--) | |
166 | rfbi_write_reg(RFBI_CMD, *b++); | |
167 | break; | |
168 | } | |
169 | ||
170 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
171 | { | |
172 | const u16 *w = buf; | |
173 | BUG_ON(len & 1); | |
174 | for (; len; len -= 2) | |
175 | rfbi_write_reg(RFBI_CMD, *w++); | |
176 | break; | |
177 | } | |
178 | ||
179 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
180 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
181 | default: | |
182 | BUG(); | |
183 | } | |
5c18adb3 TV |
184 | } |
185 | EXPORT_SYMBOL(omap_rfbi_write_command); | |
186 | ||
187 | void omap_rfbi_read_data(void *buf, u32 len) | |
188 | { | |
5c18adb3 TV |
189 | switch (rfbi.parallelmode) { |
190 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
191 | { | |
192 | u8 *b = buf; | |
193 | for (; len; len--) { | |
194 | rfbi_write_reg(RFBI_READ, 0); | |
195 | *b++ = rfbi_read_reg(RFBI_READ); | |
196 | } | |
197 | break; | |
198 | } | |
199 | ||
200 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
201 | { | |
202 | u16 *w = buf; | |
203 | BUG_ON(len & ~1); | |
204 | for (; len; len -= 2) { | |
205 | rfbi_write_reg(RFBI_READ, 0); | |
206 | *w++ = rfbi_read_reg(RFBI_READ); | |
207 | } | |
208 | break; | |
209 | } | |
210 | ||
211 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
212 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
213 | default: | |
214 | BUG(); | |
215 | } | |
5c18adb3 TV |
216 | } |
217 | EXPORT_SYMBOL(omap_rfbi_read_data); | |
218 | ||
219 | void omap_rfbi_write_data(const void *buf, u32 len) | |
220 | { | |
5c18adb3 TV |
221 | switch (rfbi.parallelmode) { |
222 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
223 | { | |
224 | const u8 *b = buf; | |
225 | for (; len; len--) | |
226 | rfbi_write_reg(RFBI_PARAM, *b++); | |
227 | break; | |
228 | } | |
229 | ||
230 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
231 | { | |
232 | const u16 *w = buf; | |
233 | BUG_ON(len & 1); | |
234 | for (; len; len -= 2) | |
235 | rfbi_write_reg(RFBI_PARAM, *w++); | |
236 | break; | |
237 | } | |
238 | ||
239 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
240 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
241 | default: | |
242 | BUG(); | |
243 | ||
244 | } | |
5c18adb3 TV |
245 | } |
246 | EXPORT_SYMBOL(omap_rfbi_write_data); | |
247 | ||
248 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
249 | u16 x, u16 y, | |
250 | u16 w, u16 h) | |
251 | { | |
252 | int start_offset = scr_width * y + x; | |
253 | int horiz_offset = scr_width - w; | |
254 | int i; | |
255 | ||
5c18adb3 TV |
256 | if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && |
257 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { | |
258 | const u16 __iomem *pd = buf; | |
259 | pd += start_offset; | |
260 | ||
261 | for (; h; --h) { | |
262 | for (i = 0; i < w; ++i) { | |
263 | const u8 __iomem *b = (const u8 __iomem *)pd; | |
264 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); | |
265 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); | |
266 | ++pd; | |
267 | } | |
268 | pd += horiz_offset; | |
269 | } | |
270 | } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 && | |
271 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { | |
272 | const u32 __iomem *pd = buf; | |
273 | pd += start_offset; | |
274 | ||
275 | for (; h; --h) { | |
276 | for (i = 0; i < w; ++i) { | |
277 | const u8 __iomem *b = (const u8 __iomem *)pd; | |
278 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2)); | |
279 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); | |
280 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); | |
281 | ++pd; | |
282 | } | |
283 | pd += horiz_offset; | |
284 | } | |
285 | } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && | |
286 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) { | |
287 | const u16 __iomem *pd = buf; | |
288 | pd += start_offset; | |
289 | ||
290 | for (; h; --h) { | |
291 | for (i = 0; i < w; ++i) { | |
292 | rfbi_write_reg(RFBI_PARAM, __raw_readw(pd)); | |
293 | ++pd; | |
294 | } | |
295 | pd += horiz_offset; | |
296 | } | |
297 | } else { | |
298 | BUG(); | |
299 | } | |
5c18adb3 TV |
300 | } |
301 | EXPORT_SYMBOL(omap_rfbi_write_pixels); | |
302 | ||
c42ced63 | 303 | static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width, |
64ba4f74 | 304 | u16 height, void (*callback)(void *data), void *data) |
5c18adb3 TV |
305 | { |
306 | u32 l; | |
307 | ||
308 | /*BUG_ON(callback == 0);*/ | |
309 | BUG_ON(rfbi.framedone_callback != NULL); | |
310 | ||
311 | DSSDBG("rfbi_transfer_area %dx%d\n", width, height); | |
312 | ||
26d9dd0d | 313 | dispc_mgr_set_lcd_size(dssdev->manager->id, width, height); |
5c18adb3 | 314 | |
26d9dd0d | 315 | dispc_mgr_enable(dssdev->manager->id, true); |
5c18adb3 TV |
316 | |
317 | rfbi.framedone_callback = callback; | |
318 | rfbi.framedone_callback_data = data; | |
319 | ||
5c18adb3 TV |
320 | rfbi_write_reg(RFBI_PIXEL_CNT, width * height); |
321 | ||
322 | l = rfbi_read_reg(RFBI_CONTROL); | |
323 | l = FLD_MOD(l, 1, 0, 0); /* enable */ | |
324 | if (!rfbi.te_enabled) | |
325 | l = FLD_MOD(l, 1, 4, 4); /* ITE */ | |
326 | ||
5c18adb3 TV |
327 | rfbi_write_reg(RFBI_CONTROL, l); |
328 | } | |
329 | ||
330 | static void framedone_callback(void *data, u32 mask) | |
331 | { | |
332 | void (*callback)(void *data); | |
333 | ||
334 | DSSDBG("FRAMEDONE\n"); | |
335 | ||
5c18adb3 TV |
336 | REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); |
337 | ||
5c18adb3 TV |
338 | callback = rfbi.framedone_callback; |
339 | rfbi.framedone_callback = NULL; | |
340 | ||
18946f62 TV |
341 | if (callback != NULL) |
342 | callback(rfbi.framedone_callback_data); | |
5c18adb3 TV |
343 | } |
344 | ||
345 | #if 1 /* VERBOSE */ | |
346 | static void rfbi_print_timings(void) | |
347 | { | |
348 | u32 l; | |
349 | u32 time; | |
350 | ||
351 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
352 | time = 1000000000 / rfbi.l4_khz; | |
353 | if (l & (1 << 4)) | |
354 | time *= 2; | |
355 | ||
356 | DSSDBG("Tick time %u ps\n", time); | |
357 | l = rfbi_read_reg(RFBI_ONOFF_TIME(0)); | |
358 | DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, " | |
359 | "REONTIME %d, REOFFTIME %d\n", | |
360 | l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f, | |
361 | (l >> 20) & 0x0f, (l >> 24) & 0x3f); | |
362 | ||
363 | l = rfbi_read_reg(RFBI_CYCLE_TIME(0)); | |
364 | DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, " | |
365 | "ACCESSTIME %d\n", | |
366 | (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f, | |
367 | (l >> 22) & 0x3f); | |
368 | } | |
369 | #else | |
370 | static void rfbi_print_timings(void) {} | |
371 | #endif | |
372 | ||
373 | ||
374 | ||
375 | ||
376 | static u32 extif_clk_period; | |
377 | ||
378 | static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) | |
379 | { | |
380 | int bus_tick = extif_clk_period * div; | |
381 | return (ps + bus_tick - 1) / bus_tick * bus_tick; | |
382 | } | |
383 | ||
384 | static int calc_reg_timing(struct rfbi_timings *t, int div) | |
385 | { | |
386 | t->clk_div = div; | |
387 | ||
388 | t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); | |
389 | ||
390 | t->we_on_time = round_to_extif_ticks(t->we_on_time, div); | |
391 | t->we_off_time = round_to_extif_ticks(t->we_off_time, div); | |
392 | t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); | |
393 | ||
394 | t->re_on_time = round_to_extif_ticks(t->re_on_time, div); | |
395 | t->re_off_time = round_to_extif_ticks(t->re_off_time, div); | |
396 | t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); | |
397 | ||
398 | t->access_time = round_to_extif_ticks(t->access_time, div); | |
399 | t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); | |
400 | t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); | |
401 | ||
402 | DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n", | |
403 | t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time); | |
404 | DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n", | |
405 | t->we_on_time, t->we_off_time, t->re_cycle_time, | |
406 | t->we_cycle_time); | |
407 | DSSDBG("[reg]rdaccess %d cspulse %d\n", | |
408 | t->access_time, t->cs_pulse_width); | |
409 | ||
410 | return rfbi_convert_timings(t); | |
411 | } | |
412 | ||
413 | static int calc_extif_timings(struct rfbi_timings *t) | |
414 | { | |
415 | u32 max_clk_div; | |
416 | int div; | |
417 | ||
418 | rfbi_get_clk_info(&extif_clk_period, &max_clk_div); | |
419 | for (div = 1; div <= max_clk_div; div++) { | |
420 | if (calc_reg_timing(t, div) == 0) | |
421 | break; | |
422 | } | |
423 | ||
424 | if (div <= max_clk_div) | |
425 | return 0; | |
426 | ||
427 | DSSERR("can't setup timings\n"); | |
428 | return -1; | |
429 | } | |
430 | ||
431 | ||
c42ced63 | 432 | static void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t) |
5c18adb3 TV |
433 | { |
434 | int r; | |
435 | ||
436 | if (!t->converted) { | |
437 | r = calc_extif_timings(t); | |
438 | if (r < 0) | |
439 | DSSERR("Failed to calc timings\n"); | |
440 | } | |
441 | ||
442 | BUG_ON(!t->converted); | |
443 | ||
5c18adb3 TV |
444 | rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]); |
445 | rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]); | |
446 | ||
447 | /* TIMEGRANULARITY */ | |
448 | REG_FLD_MOD(RFBI_CONFIG(rfbi_module), | |
449 | (t->tim[2] ? 1 : 0), 4, 4); | |
450 | ||
451 | rfbi_print_timings(); | |
5c18adb3 TV |
452 | } |
453 | ||
454 | static int ps_to_rfbi_ticks(int time, int div) | |
455 | { | |
456 | unsigned long tick_ps; | |
457 | int ret; | |
458 | ||
459 | /* Calculate in picosecs to yield more exact results */ | |
460 | tick_ps = 1000000000 / (rfbi.l4_khz) * div; | |
461 | ||
462 | ret = (time + tick_ps - 1) / tick_ps; | |
463 | ||
464 | return ret; | |
465 | } | |
466 | ||
5c18adb3 TV |
467 | static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div) |
468 | { | |
469 | *clk_period = 1000000000 / rfbi.l4_khz; | |
470 | *max_clk_div = 2; | |
471 | } | |
472 | ||
473 | static int rfbi_convert_timings(struct rfbi_timings *t) | |
474 | { | |
475 | u32 l; | |
476 | int reon, reoff, weon, weoff, cson, csoff, cs_pulse; | |
477 | int actim, recyc, wecyc; | |
478 | int div = t->clk_div; | |
479 | ||
480 | if (div <= 0 || div > 2) | |
481 | return -1; | |
482 | ||
483 | /* Make sure that after conversion it still holds that: | |
484 | * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff, | |
485 | * csoff > cson, csoff >= max(weoff, reoff), actim > reon | |
486 | */ | |
487 | weon = ps_to_rfbi_ticks(t->we_on_time, div); | |
488 | weoff = ps_to_rfbi_ticks(t->we_off_time, div); | |
489 | if (weoff <= weon) | |
490 | weoff = weon + 1; | |
491 | if (weon > 0x0f) | |
492 | return -1; | |
493 | if (weoff > 0x3f) | |
494 | return -1; | |
495 | ||
496 | reon = ps_to_rfbi_ticks(t->re_on_time, div); | |
497 | reoff = ps_to_rfbi_ticks(t->re_off_time, div); | |
498 | if (reoff <= reon) | |
499 | reoff = reon + 1; | |
500 | if (reon > 0x0f) | |
501 | return -1; | |
502 | if (reoff > 0x3f) | |
503 | return -1; | |
504 | ||
505 | cson = ps_to_rfbi_ticks(t->cs_on_time, div); | |
506 | csoff = ps_to_rfbi_ticks(t->cs_off_time, div); | |
507 | if (csoff <= cson) | |
508 | csoff = cson + 1; | |
509 | if (csoff < max(weoff, reoff)) | |
510 | csoff = max(weoff, reoff); | |
511 | if (cson > 0x0f) | |
512 | return -1; | |
513 | if (csoff > 0x3f) | |
514 | return -1; | |
515 | ||
516 | l = cson; | |
517 | l |= csoff << 4; | |
518 | l |= weon << 10; | |
519 | l |= weoff << 14; | |
520 | l |= reon << 20; | |
521 | l |= reoff << 24; | |
522 | ||
523 | t->tim[0] = l; | |
524 | ||
525 | actim = ps_to_rfbi_ticks(t->access_time, div); | |
526 | if (actim <= reon) | |
527 | actim = reon + 1; | |
528 | if (actim > 0x3f) | |
529 | return -1; | |
530 | ||
531 | wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); | |
532 | if (wecyc < weoff) | |
533 | wecyc = weoff; | |
534 | if (wecyc > 0x3f) | |
535 | return -1; | |
536 | ||
537 | recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); | |
538 | if (recyc < reoff) | |
539 | recyc = reoff; | |
540 | if (recyc > 0x3f) | |
541 | return -1; | |
542 | ||
543 | cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); | |
544 | if (cs_pulse > 0x3f) | |
545 | return -1; | |
546 | ||
547 | l = wecyc; | |
548 | l |= recyc << 6; | |
549 | l |= cs_pulse << 12; | |
550 | l |= actim << 22; | |
551 | ||
552 | t->tim[1] = l; | |
553 | ||
554 | t->tim[2] = div - 1; | |
555 | ||
556 | t->converted = 1; | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | /* xxx FIX module selection missing */ | |
562 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
563 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
564 | int hs_pol_inv, int vs_pol_inv, int extif_div) | |
565 | { | |
566 | int hs, vs; | |
567 | int min; | |
568 | u32 l; | |
569 | ||
570 | hs = ps_to_rfbi_ticks(hs_pulse_time, 1); | |
571 | vs = ps_to_rfbi_ticks(vs_pulse_time, 1); | |
572 | if (hs < 2) | |
573 | return -EDOM; | |
574 | if (mode == OMAP_DSS_RFBI_TE_MODE_2) | |
575 | min = 2; | |
576 | else /* OMAP_DSS_RFBI_TE_MODE_1 */ | |
577 | min = 4; | |
578 | if (vs < min) | |
579 | return -EDOM; | |
580 | if (vs == hs) | |
581 | return -EINVAL; | |
582 | rfbi.te_mode = mode; | |
583 | DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n", | |
584 | mode, hs, vs, hs_pol_inv, vs_pol_inv); | |
585 | ||
5c18adb3 TV |
586 | rfbi_write_reg(RFBI_HSYNC_WIDTH, hs); |
587 | rfbi_write_reg(RFBI_VSYNC_WIDTH, vs); | |
588 | ||
589 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
590 | if (hs_pol_inv) | |
591 | l &= ~(1 << 21); | |
592 | else | |
593 | l |= 1 << 21; | |
594 | if (vs_pol_inv) | |
595 | l &= ~(1 << 20); | |
596 | else | |
597 | l |= 1 << 20; | |
5c18adb3 TV |
598 | |
599 | return 0; | |
600 | } | |
601 | EXPORT_SYMBOL(omap_rfbi_setup_te); | |
602 | ||
603 | /* xxx FIX module selection missing */ | |
604 | int omap_rfbi_enable_te(bool enable, unsigned line) | |
605 | { | |
606 | u32 l; | |
607 | ||
608 | DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode); | |
609 | if (line > (1 << 11) - 1) | |
610 | return -EINVAL; | |
611 | ||
5c18adb3 TV |
612 | l = rfbi_read_reg(RFBI_CONFIG(0)); |
613 | l &= ~(0x3 << 2); | |
614 | if (enable) { | |
615 | rfbi.te_enabled = 1; | |
616 | l |= rfbi.te_mode << 2; | |
617 | } else | |
618 | rfbi.te_enabled = 0; | |
619 | rfbi_write_reg(RFBI_CONFIG(0), l); | |
620 | rfbi_write_reg(RFBI_LINE_NUMBER, line); | |
5c18adb3 TV |
621 | |
622 | return 0; | |
623 | } | |
624 | EXPORT_SYMBOL(omap_rfbi_enable_te); | |
625 | ||
c42ced63 | 626 | static int rfbi_configure(int rfbi_module, int bpp, int lines) |
5c18adb3 TV |
627 | { |
628 | u32 l; | |
629 | int cycle1 = 0, cycle2 = 0, cycle3 = 0; | |
630 | enum omap_rfbi_cycleformat cycleformat; | |
631 | enum omap_rfbi_datatype datatype; | |
632 | enum omap_rfbi_parallelmode parallelmode; | |
633 | ||
634 | switch (bpp) { | |
635 | case 12: | |
636 | datatype = OMAP_DSS_RFBI_DATATYPE_12; | |
637 | break; | |
638 | case 16: | |
639 | datatype = OMAP_DSS_RFBI_DATATYPE_16; | |
640 | break; | |
641 | case 18: | |
642 | datatype = OMAP_DSS_RFBI_DATATYPE_18; | |
643 | break; | |
644 | case 24: | |
645 | datatype = OMAP_DSS_RFBI_DATATYPE_24; | |
646 | break; | |
647 | default: | |
648 | BUG(); | |
649 | return 1; | |
650 | } | |
651 | rfbi.datatype = datatype; | |
652 | ||
653 | switch (lines) { | |
654 | case 8: | |
655 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8; | |
656 | break; | |
657 | case 9: | |
658 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9; | |
659 | break; | |
660 | case 12: | |
661 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12; | |
662 | break; | |
663 | case 16: | |
664 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16; | |
665 | break; | |
666 | default: | |
667 | BUG(); | |
668 | return 1; | |
669 | } | |
670 | rfbi.parallelmode = parallelmode; | |
671 | ||
672 | if ((bpp % lines) == 0) { | |
673 | switch (bpp / lines) { | |
674 | case 1: | |
675 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1; | |
676 | break; | |
677 | case 2: | |
678 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1; | |
679 | break; | |
680 | case 3: | |
681 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1; | |
682 | break; | |
683 | default: | |
684 | BUG(); | |
685 | return 1; | |
686 | } | |
687 | } else if ((2 * bpp % lines) == 0) { | |
688 | if ((2 * bpp / lines) == 3) | |
689 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2; | |
690 | else { | |
691 | BUG(); | |
692 | return 1; | |
693 | } | |
694 | } else { | |
695 | BUG(); | |
696 | return 1; | |
697 | } | |
698 | ||
699 | switch (cycleformat) { | |
700 | case OMAP_DSS_RFBI_CYCLEFORMAT_1_1: | |
701 | cycle1 = lines; | |
702 | break; | |
703 | ||
704 | case OMAP_DSS_RFBI_CYCLEFORMAT_2_1: | |
705 | cycle1 = lines; | |
706 | cycle2 = lines; | |
707 | break; | |
708 | ||
709 | case OMAP_DSS_RFBI_CYCLEFORMAT_3_1: | |
710 | cycle1 = lines; | |
711 | cycle2 = lines; | |
712 | cycle3 = lines; | |
713 | break; | |
714 | ||
715 | case OMAP_DSS_RFBI_CYCLEFORMAT_3_2: | |
716 | cycle1 = lines; | |
717 | cycle2 = (lines / 2) | ((lines / 2) << 16); | |
718 | cycle3 = (lines << 16); | |
719 | break; | |
720 | } | |
721 | ||
5c18adb3 TV |
722 | REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ |
723 | ||
724 | l = 0; | |
725 | l |= FLD_VAL(parallelmode, 1, 0); | |
726 | l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ | |
727 | l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ | |
728 | l |= FLD_VAL(datatype, 6, 5); | |
729 | /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ | |
730 | l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ | |
731 | l |= FLD_VAL(cycleformat, 10, 9); | |
732 | l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ | |
733 | l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ | |
734 | l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ | |
735 | l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ | |
736 | l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ | |
737 | l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ | |
738 | l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ | |
739 | rfbi_write_reg(RFBI_CONFIG(rfbi_module), l); | |
740 | ||
741 | rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1); | |
742 | rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2); | |
743 | rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3); | |
744 | ||
745 | ||
746 | l = rfbi_read_reg(RFBI_CONTROL); | |
747 | l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ | |
748 | l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ | |
749 | rfbi_write_reg(RFBI_CONTROL, l); | |
750 | ||
751 | ||
752 | DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", | |
753 | bpp, lines, cycle1, cycle2, cycle3); | |
754 | ||
5c18adb3 TV |
755 | return 0; |
756 | } | |
1d5952a8 TV |
757 | |
758 | int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size, | |
759 | int data_lines) | |
760 | { | |
761 | return rfbi_configure(dssdev->phy.rfbi.channel, pixel_size, data_lines); | |
762 | } | |
763 | EXPORT_SYMBOL(omap_rfbi_configure); | |
5c18adb3 | 764 | |
18946f62 TV |
765 | int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, |
766 | u16 *x, u16 *y, u16 *w, u16 *h) | |
5c18adb3 | 767 | { |
18946f62 | 768 | u16 dw, dh; |
5c18adb3 | 769 | |
18946f62 | 770 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
5c18adb3 | 771 | |
18946f62 TV |
772 | if (*x > dw || *y > dh) |
773 | return -EINVAL; | |
5c18adb3 | 774 | |
18946f62 TV |
775 | if (*x + *w > dw) |
776 | return -EINVAL; | |
5c18adb3 | 777 | |
18946f62 TV |
778 | if (*y + *h > dh) |
779 | return -EINVAL; | |
5c18adb3 | 780 | |
18946f62 TV |
781 | if (*w == 1) |
782 | return -EINVAL; | |
5c18adb3 | 783 | |
18946f62 TV |
784 | if (*w == 0 || *h == 0) |
785 | return -EINVAL; | |
5c18adb3 | 786 | |
26d9dd0d | 787 | dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h); |
5c18adb3 | 788 | |
18946f62 TV |
789 | return 0; |
790 | } | |
791 | EXPORT_SYMBOL(omap_rfbi_prepare_update); | |
5c18adb3 | 792 | |
18946f62 TV |
793 | int omap_rfbi_update(struct omap_dss_device *dssdev, |
794 | u16 x, u16 y, u16 w, u16 h, | |
795 | void (*callback)(void *), void *data) | |
796 | { | |
4a9e78ab | 797 | rfbi_transfer_area(dssdev, w, h, callback, data); |
18946f62 | 798 | return 0; |
5c18adb3 | 799 | } |
18946f62 | 800 | EXPORT_SYMBOL(omap_rfbi_update); |
5c18adb3 TV |
801 | |
802 | void rfbi_dump_regs(struct seq_file *s) | |
803 | { | |
804 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) | |
805 | ||
4fbafaf3 TV |
806 | if (rfbi_runtime_get()) |
807 | return; | |
5c18adb3 TV |
808 | |
809 | DUMPREG(RFBI_REVISION); | |
810 | DUMPREG(RFBI_SYSCONFIG); | |
811 | DUMPREG(RFBI_SYSSTATUS); | |
812 | DUMPREG(RFBI_CONTROL); | |
813 | DUMPREG(RFBI_PIXEL_CNT); | |
814 | DUMPREG(RFBI_LINE_NUMBER); | |
815 | DUMPREG(RFBI_CMD); | |
816 | DUMPREG(RFBI_PARAM); | |
817 | DUMPREG(RFBI_DATA); | |
818 | DUMPREG(RFBI_READ); | |
819 | DUMPREG(RFBI_STATUS); | |
820 | ||
821 | DUMPREG(RFBI_CONFIG(0)); | |
822 | DUMPREG(RFBI_ONOFF_TIME(0)); | |
823 | DUMPREG(RFBI_CYCLE_TIME(0)); | |
824 | DUMPREG(RFBI_DATA_CYCLE1(0)); | |
825 | DUMPREG(RFBI_DATA_CYCLE2(0)); | |
826 | DUMPREG(RFBI_DATA_CYCLE3(0)); | |
827 | ||
828 | DUMPREG(RFBI_CONFIG(1)); | |
829 | DUMPREG(RFBI_ONOFF_TIME(1)); | |
830 | DUMPREG(RFBI_CYCLE_TIME(1)); | |
831 | DUMPREG(RFBI_DATA_CYCLE1(1)); | |
832 | DUMPREG(RFBI_DATA_CYCLE2(1)); | |
833 | DUMPREG(RFBI_DATA_CYCLE3(1)); | |
834 | ||
835 | DUMPREG(RFBI_VSYNC_WIDTH); | |
836 | DUMPREG(RFBI_HSYNC_WIDTH); | |
837 | ||
4fbafaf3 | 838 | rfbi_runtime_put(); |
5c18adb3 TV |
839 | #undef DUMPREG |
840 | } | |
841 | ||
37ac60e4 | 842 | int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev) |
5c18adb3 TV |
843 | { |
844 | int r; | |
845 | ||
05e1d606 TV |
846 | if (dssdev->manager == NULL) { |
847 | DSSERR("failed to enable display: no manager\n"); | |
848 | return -ENODEV; | |
849 | } | |
850 | ||
4fbafaf3 TV |
851 | r = rfbi_runtime_get(); |
852 | if (r) | |
853 | return r; | |
5be685fa | 854 | |
5c18adb3 TV |
855 | r = omap_dss_start_device(dssdev); |
856 | if (r) { | |
857 | DSSERR("failed to start device\n"); | |
858 | goto err0; | |
859 | } | |
860 | ||
861 | r = omap_dispc_register_isr(framedone_callback, NULL, | |
862 | DISPC_IRQ_FRAMEDONE); | |
863 | if (r) { | |
864 | DSSERR("can't get FRAMEDONE irq\n"); | |
865 | goto err1; | |
866 | } | |
867 | ||
26d9dd0d | 868 | dispc_mgr_set_lcd_display_type(dssdev->manager->id, |
64ba4f74 | 869 | OMAP_DSS_LCD_DISPLAY_TFT); |
5c18adb3 | 870 | |
569969d6 AT |
871 | dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_RFBI); |
872 | dispc_mgr_enable_stallmode(dssdev->manager->id, true); | |
5c18adb3 | 873 | |
26d9dd0d | 874 | dispc_mgr_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); |
5c18adb3 TV |
875 | |
876 | rfbi_configure(dssdev->phy.rfbi.channel, | |
877 | dssdev->ctrl.pixel_size, | |
878 | dssdev->phy.rfbi.data_lines); | |
879 | ||
880 | rfbi_set_timings(dssdev->phy.rfbi.channel, | |
881 | &dssdev->ctrl.rfbi_timings); | |
882 | ||
883 | ||
5c18adb3 | 884 | return 0; |
5c18adb3 TV |
885 | err1: |
886 | omap_dss_stop_device(dssdev); | |
887 | err0: | |
4fbafaf3 | 888 | rfbi_runtime_put(); |
5c18adb3 TV |
889 | return r; |
890 | } | |
37ac60e4 | 891 | EXPORT_SYMBOL(omapdss_rfbi_display_enable); |
5c18adb3 | 892 | |
37ac60e4 | 893 | void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev) |
5c18adb3 | 894 | { |
5c18adb3 TV |
895 | omap_dispc_unregister_isr(framedone_callback, NULL, |
896 | DISPC_IRQ_FRAMEDONE); | |
897 | omap_dss_stop_device(dssdev); | |
5be685fa | 898 | |
4fbafaf3 | 899 | rfbi_runtime_put(); |
5c18adb3 | 900 | } |
37ac60e4 | 901 | EXPORT_SYMBOL(omapdss_rfbi_display_disable); |
5c18adb3 TV |
902 | |
903 | int rfbi_init_display(struct omap_dss_device *dssdev) | |
904 | { | |
5c18adb3 | 905 | rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; |
5c18adb3 | 906 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; |
5c18adb3 TV |
907 | return 0; |
908 | } | |
3448d500 SG |
909 | |
910 | /* RFBI HW IP initialisation */ | |
911 | static int omap_rfbihw_probe(struct platform_device *pdev) | |
912 | { | |
913 | u32 rev; | |
ea9da36a | 914 | struct resource *rfbi_mem; |
4fbafaf3 TV |
915 | struct clk *clk; |
916 | int r; | |
3448d500 SG |
917 | |
918 | rfbi.pdev = pdev; | |
919 | ||
773139f1 | 920 | sema_init(&rfbi.bus_lock, 1); |
3448d500 | 921 | |
ea9da36a SG |
922 | rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0); |
923 | if (!rfbi_mem) { | |
924 | DSSERR("can't get IORESOURCE_MEM RFBI\n"); | |
4fbafaf3 TV |
925 | r = -EINVAL; |
926 | goto err_ioremap; | |
ea9da36a SG |
927 | } |
928 | rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem)); | |
3448d500 SG |
929 | if (!rfbi.base) { |
930 | DSSERR("can't ioremap RFBI\n"); | |
4fbafaf3 TV |
931 | r = -ENOMEM; |
932 | goto err_ioremap; | |
3448d500 SG |
933 | } |
934 | ||
4fbafaf3 TV |
935 | pm_runtime_enable(&pdev->dev); |
936 | ||
937 | r = rfbi_runtime_get(); | |
938 | if (r) | |
939 | goto err_get_rfbi; | |
3448d500 SG |
940 | |
941 | msleep(10); | |
942 | ||
bfe4f8d3 | 943 | clk = clk_get(&pdev->dev, "ick"); |
4fbafaf3 TV |
944 | if (IS_ERR(clk)) { |
945 | DSSERR("can't get ick\n"); | |
946 | r = PTR_ERR(clk); | |
947 | goto err_get_ick; | |
948 | } | |
949 | ||
950 | rfbi.l4_khz = clk_get_rate(clk) / 1000; | |
3448d500 | 951 | |
4fbafaf3 | 952 | clk_put(clk); |
3448d500 SG |
953 | |
954 | rev = rfbi_read_reg(RFBI_REVISION); | |
a06b62f8 | 955 | dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n", |
3448d500 SG |
956 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
957 | ||
4fbafaf3 | 958 | rfbi_runtime_put(); |
3448d500 SG |
959 | |
960 | return 0; | |
4fbafaf3 TV |
961 | |
962 | err_get_ick: | |
963 | rfbi_runtime_put(); | |
964 | err_get_rfbi: | |
965 | pm_runtime_disable(&pdev->dev); | |
966 | iounmap(rfbi.base); | |
967 | err_ioremap: | |
968 | return r; | |
3448d500 SG |
969 | } |
970 | ||
971 | static int omap_rfbihw_remove(struct platform_device *pdev) | |
972 | { | |
4fbafaf3 | 973 | pm_runtime_disable(&pdev->dev); |
3448d500 SG |
974 | iounmap(rfbi.base); |
975 | return 0; | |
976 | } | |
977 | ||
4fbafaf3 TV |
978 | static int rfbi_runtime_suspend(struct device *dev) |
979 | { | |
980 | dispc_runtime_put(); | |
981 | dss_runtime_put(); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static int rfbi_runtime_resume(struct device *dev) | |
987 | { | |
988 | int r; | |
989 | ||
990 | r = dss_runtime_get(); | |
991 | if (r < 0) | |
992 | goto err_get_dss; | |
993 | ||
994 | r = dispc_runtime_get(); | |
995 | if (r < 0) | |
996 | goto err_get_dispc; | |
997 | ||
998 | return 0; | |
999 | ||
1000 | err_get_dispc: | |
1001 | dss_runtime_put(); | |
1002 | err_get_dss: | |
1003 | return r; | |
1004 | } | |
1005 | ||
1006 | static const struct dev_pm_ops rfbi_pm_ops = { | |
1007 | .runtime_suspend = rfbi_runtime_suspend, | |
1008 | .runtime_resume = rfbi_runtime_resume, | |
1009 | }; | |
1010 | ||
3448d500 SG |
1011 | static struct platform_driver omap_rfbihw_driver = { |
1012 | .probe = omap_rfbihw_probe, | |
1013 | .remove = omap_rfbihw_remove, | |
1014 | .driver = { | |
1015 | .name = "omapdss_rfbi", | |
1016 | .owner = THIS_MODULE, | |
4fbafaf3 | 1017 | .pm = &rfbi_pm_ops, |
3448d500 SG |
1018 | }, |
1019 | }; | |
1020 | ||
1021 | int rfbi_init_platform_driver(void) | |
1022 | { | |
1023 | return platform_driver_register(&omap_rfbihw_driver); | |
1024 | } | |
1025 | ||
1026 | void rfbi_uninit_platform_driver(void) | |
1027 | { | |
1028 | return platform_driver_unregister(&omap_rfbihw_driver); | |
1029 | } |