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OMAPDSS: HDMI: Add an audio configuration function
[mirror_ubuntu-eoan-kernel.git] / drivers / video / omap2 / dss / ti_hdmi_4xxx_ip.c
CommitLineData
7d983f39
M		 1/*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/mutex.h>
28#include <linux/delay.h>
29#include <linux/string.h>
162874d5 30#include <linux/seq_file.h>
c49d005b 31#include <linux/gpio.h>
7e151f7f 32#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
199e7fd6 33#include <sound/asound.h>
6ec355d6 34#include <sound/asoundef.h>
199e7fd6 35#endif
7d983f39
M		 36
37#include "ti_hdmi_4xxx_ip.h"
38#include "dss.h"
6ec355d6 39#include "dss_features.h"
7d983f39
M		 40
41static inline void hdmi_write_reg(void __iomem *base_addr,
31ec732e 42 const u16 idx, u32 val)
7d983f39 43{
31ec732e 44 __raw_writel(val, base_addr + idx);
7d983f39
M		 45}
46
47static inline u32 hdmi_read_reg(void __iomem *base_addr,
31ec732e 48 const u16 idx)
7d983f39 49{
31ec732e 50 return __raw_readl(base_addr + idx);
7d983f39
M		 51}
52
53static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
54{
55 return ip_data->base_wp;
56}
57
58static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
59{
60 return ip_data->base_wp + ip_data->phy_offset;
61}
62
63static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
64{
65 return ip_data->base_wp + ip_data->pll_offset;
66}
67
68static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
69{
70 return ip_data->base_wp + ip_data->core_av_offset;
71}
72
73static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
74{
75 return ip_data->base_wp + ip_data->core_sys_offset;
76}
77
78static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
31ec732e 79 const u16 idx,
7d983f39
M		 80 int b2, int b1, u32 val)
81{
82 u32 t = 0;
83 while (val != REG_GET(base_addr, idx, b2, b1)) {
84 udelay(1);
85 if (t++ > 10000)
86 return !val;
87 }
88 return val;
89}
90
91static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
92{
93 u32 r;
94 void __iomem *pll_base = hdmi_pll_base(ip_data);
95 struct hdmi_pll_info *fmt = &ip_data->pll_data;
96
97 /* PLL start always use manual mode */
98 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
99
100 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
101 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
b44e4582 102 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
7d983f39
M		 103
104 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
105
106 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
107
108 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
109 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
110 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
111 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
112
113 if (fmt->dcofreq) {
114 /* divider programming for frequency beyond 1000Mhz */
115 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
116 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
117 } else {
118 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
119 }
120
121 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
122
123 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
124 r = FLD_MOD(r, fmt->regm2, 24, 18);
125 r = FLD_MOD(r, fmt->regmf, 17, 0);
126
127 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
128
129 /* go now */
130 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
131
132 /* wait for bit change */
133 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
134 0, 0, 1) != 1) {
135 pr_err("PLL GO bit not set\n");
136 return -ETIMEDOUT;
137 }
138
139 /* Wait till the lock bit is set in PLL status */
140 if (hdmi_wait_for_bit_change(pll_base,
141 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
142 pr_err("cannot lock PLL\n");
143 pr_err("CFG1 0x%x\n",
144 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
145 pr_err("CFG2 0x%x\n",
146 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
147 pr_err("CFG4 0x%x\n",
148 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
149 return -ETIMEDOUT;
150 }
151
152 pr_debug("PLL locked!\n");
153
154 return 0;
155}
156
157/* PHY_PWR_CMD */
158static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
159{
160 /* Command for power control of HDMI PHY */
161 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
162
163 /* Status of the power control of HDMI PHY */
164 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
165 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
166 pr_err("Failed to set PHY power mode to %d\n", val);
167 return -ETIMEDOUT;
168 }
169
170 return 0;
171}
172
173/* PLL_PWR_CMD */
176b578b 174static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
7d983f39
M		 175{
176 /* Command for power control of HDMI PLL */
177 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
178
179 /* wait till PHY_PWR_STATUS is set */
180 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
181 1, 0, val) != val) {
182 pr_err("Failed to set PLL_PWR_STATUS\n");
183 return -ETIMEDOUT;
184 }
185
186 return 0;
187}
188
189static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
190{
191 /* SYSRESET controlled by power FSM */
192 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
193
194 /* READ 0x0 reset is in progress */
195 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
196 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
197 pr_err("Failed to sysreset PLL\n");
198 return -ETIMEDOUT;
199 }
200
201 return 0;
202}
203
176b578b 204int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
7d983f39
M		 205{
206 u16 r = 0;
207
208 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
209 if (r)
210 return r;
211
212 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
213 if (r)
214 return r;
215
216 r = hdmi_pll_reset(ip_data);
217 if (r)
218 return r;
219
220 r = hdmi_pll_init(ip_data);
221 if (r)
222 return r;
223
224 return 0;
225}
226
176b578b
M		 227void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
228{
229 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
230}
231
c49d005b
TV		 232static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
233{
234 unsigned long flags;
235 bool hpd;
236 int r;
237 /* this should be in ti_hdmi_4xxx_ip private data */
238 static DEFINE_SPINLOCK(phy_tx_lock);
239
240 spin_lock_irqsave(&phy_tx_lock, flags);
241
242 hpd = gpio_get_value(ip_data->hpd_gpio);
243
244 if (hpd == ip_data->phy_tx_enabled) {
245 spin_unlock_irqrestore(&phy_tx_lock, flags);
246 return 0;
247 }
248
249 if (hpd)
250 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
251 else
252 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
253
254 if (r) {
255 DSSERR("Failed to %s PHY TX power\n",
256 hpd ? "enable" : "disable");
257 goto err;
258 }
259
260 ip_data->phy_tx_enabled = hpd;
261err:
262 spin_unlock_irqrestore(&phy_tx_lock, flags);
263 return r;
264}
265
266static irqreturn_t hpd_irq_handler(int irq, void *data)
267{
268 struct hdmi_ip_data *ip_data = data;
269
270 hdmi_check_hpd_state(ip_data);
271
272 return IRQ_HANDLED;
273}
274
176b578b 275int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
7d983f39
M		 276{
277 u16 r = 0;
278 void __iomem *phy_base = hdmi_phy_base(ip_data);
279
280 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
281 if (r)
282 return r;
283
7d983f39
M		 284 /*
285 * Read address 0 in order to get the SCP reset done completed
286 * Dummy access performed to make sure reset is done
287 */
288 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
289
290 /*
291 * Write to phy address 0 to configure the clock
292 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
293 */
294 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
295
296 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
297 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
298
299 /* Setup max LDO voltage */
300 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
301
302 /* Write to phy address 3 to change the polarity control */
303 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
304
c49d005b
TV		 305 r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
306 NULL, hpd_irq_handler,
307 IRQF_DISABLED | IRQF_TRIGGER_RISING |
308 IRQF_TRIGGER_FALLING, "hpd", ip_data);
309 if (r) {
310 DSSERR("HPD IRQ request failed\n");
311 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
312 return r;
313 }
314
315 r = hdmi_check_hpd_state(ip_data);
316 if (r) {
317 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
318 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
319 return r;
320 }
321
7d983f39
M		 322 return 0;
323}
324
176b578b 325void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
7d983f39 326{
c49d005b
TV		 327 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
328
7d983f39 329 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
c49d005b 330 ip_data->phy_tx_enabled = false;
7d983f39
M		 331}
332
032b8ea5 333static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
7d983f39 334{
032b8ea5 335 void __iomem *base = hdmi_core_sys_base(ip_data);
7d983f39
M		 336
337 /* Turn on CLK for DDC */
032b8ea5
TV		 338 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
339
340 /* IN_PROG */
341 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
342 /* Abort transaction */
343 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
344 /* IN_PROG */
345 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
346 4, 4, 0) != 0) {
347 DSSERR("Timeout aborting DDC transaction\n");
348 return -ETIMEDOUT;
349 }
350 }
7d983f39 351
032b8ea5
TV		 352 /* Clk SCL Devices */
353 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
7d983f39 354
032b8ea5
TV		 355 /* HDMI_CORE_DDC_STATUS_IN_PROG */
356 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
357 4, 4, 0) != 0) {
358 DSSERR("Timeout starting SCL clock\n");
359 return -ETIMEDOUT;
360 }
7d983f39 361
032b8ea5
TV		 362 /* Clear FIFO */
363 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
7d983f39 364
032b8ea5
TV		 365 /* HDMI_CORE_DDC_STATUS_IN_PROG */
366 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
367 4, 4, 0) != 0) {
368 DSSERR("Timeout clearing DDC fifo\n");
369 return -ETIMEDOUT;
370 }
7d983f39 371
032b8ea5
TV		 372 return 0;
373}
7d983f39 374
032b8ea5
TV		 375static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
376 u8 *pedid, int ext)
377{
378 void __iomem *base = hdmi_core_sys_base(ip_data);
937fce13
TV		 379 u32 i;
380 char checksum;
032b8ea5
TV		 381 u32 offset = 0;
382
383 /* HDMI_CORE_DDC_STATUS_IN_PROG */
384 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
385 4, 4, 0) != 0) {
386 DSSERR("Timeout waiting DDC to be ready\n");
387 return -ETIMEDOUT;
7d983f39
M		 388 }
389
032b8ea5
TV		 390 if (ext % 2 != 0)
391 offset = 0x80;
392
7d983f39 393 /* Load Segment Address Register */
032b8ea5 394 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
7d983f39
M		 395
396 /* Load Slave Address Register */
032b8ea5 397 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
7d983f39
M		 398
399 /* Load Offset Address Register */
032b8ea5 400 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
7d983f39
M		 401
402 /* Load Byte Count */
032b8ea5
TV		 403 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
404 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
7d983f39
M		 405
406 /* Set DDC_CMD */
407 if (ext)
032b8ea5 408 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
7d983f39 409 else
032b8ea5 410 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
7d983f39
M		 411
412 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
032b8ea5 413 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
7d983f39
M		 414 pr_err("I2C Bus Low?\n");
415 return -EIO;
416 }
417 /* HDMI_CORE_DDC_STATUS_NO_ACK */
032b8ea5 418 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
7d983f39
M		 419 pr_err("I2C No Ack\n");
420 return -EIO;
421 }
422
937fce13
TV		 423 for (i = 0; i < 0x80; ++i) {
424 int t;
7d983f39 425
937fce13
TV		 426 /* IN_PROG */
427 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
428 DSSERR("operation stopped when reading edid\n");
429 return -EIO;
430 }
431
432 t = 0;
433 /* FIFO_EMPTY */
434 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
435 if (t++ > 10000) {
436 DSSERR("timeout reading edid\n");
437 return -ETIMEDOUT;
438 }
439 udelay(1);
7d983f39 440 }
937fce13
TV		 441
442 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
7d983f39
M		 443 }
444
937fce13
TV		 445 checksum = 0;
446 for (i = 0; i < 0x80; ++i)
447 checksum += pedid[i];
7d983f39
M		 448
449 if (checksum != 0) {
450 pr_err("E-EDID checksum failed!!\n");
451 return -EIO;
452 }
453
454 return 0;
455}
456
176b578b 457int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
937fce13 458 u8 *edid, int len)
7d983f39 459{
937fce13
TV		 460 int r, l;
461
462 if (len < 128)
463 return -EINVAL;
7d983f39 464
032b8ea5
TV		 465 r = hdmi_core_ddc_init(ip_data);
466 if (r)
467 return r;
468
937fce13 469 r = hdmi_core_ddc_edid(ip_data, edid, 0);
47024565 470 if (r)
7d983f39 471 return r;
47024565 472
937fce13 473 l = 128;
47024565 474
937fce13
TV		 475 if (len >= 128 * 2 && edid[0x7e] > 0) {
476 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
47024565
TV		 477 if (r)
478 return r;
937fce13 479 l += 128;
7d983f39 480 }
47024565 481
937fce13 482 return l;
7d983f39
M		 483}
484
759593ff
TV		 485bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
486{
ca888a79 487 return gpio_get_value(ip_data->hpd_gpio);
759593ff
TV		 488}
489
7d983f39
M		 490static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
491 struct hdmi_core_infoframe_avi *avi_cfg,
492 struct hdmi_core_packet_enable_repeat *repeat_cfg)
493{
494 pr_debug("Enter hdmi_core_init\n");
495
496 /* video core */
497 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
498 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
499 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
500 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
501 video_cfg->hdmi_dvi = HDMI_DVI;
502 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
503
504 /* info frame */
505 avi_cfg->db1_format = 0;
506 avi_cfg->db1_active_info = 0;
507 avi_cfg->db1_bar_info_dv = 0;
508 avi_cfg->db1_scan_info = 0;
509 avi_cfg->db2_colorimetry = 0;
510 avi_cfg->db2_aspect_ratio = 0;
511 avi_cfg->db2_active_fmt_ar = 0;
512 avi_cfg->db3_itc = 0;
513 avi_cfg->db3_ec = 0;
514 avi_cfg->db3_q_range = 0;
515 avi_cfg->db3_nup_scaling = 0;
516 avi_cfg->db4_videocode = 0;
517 avi_cfg->db5_pixel_repeat = 0;
518 avi_cfg->db6_7_line_eoftop = 0 ;
519 avi_cfg->db8_9_line_sofbottom = 0;
520 avi_cfg->db10_11_pixel_eofleft = 0;
521 avi_cfg->db12_13_pixel_sofright = 0;
522
523 /* packet enable and repeat */
524 repeat_cfg->audio_pkt = 0;
525 repeat_cfg->audio_pkt_repeat = 0;
526 repeat_cfg->avi_infoframe = 0;
527 repeat_cfg->avi_infoframe_repeat = 0;
528 repeat_cfg->gen_cntrl_pkt = 0;
529 repeat_cfg->gen_cntrl_pkt_repeat = 0;
530 repeat_cfg->generic_pkt = 0;
531 repeat_cfg->generic_pkt_repeat = 0;
532}
533
534static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
535{
536 pr_debug("Enter hdmi_core_powerdown_disable\n");
537 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
538}
539
540static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
541{
542 pr_debug("Enter hdmi_core_swreset_release\n");
543 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
544}
545
546static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
547{
548 pr_debug("Enter hdmi_core_swreset_assert\n");
549 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
550}
551
552/* HDMI_CORE_VIDEO_CONFIG */
553static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
554 struct hdmi_core_video_config *cfg)
555{
556 u32 r = 0;
557 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
558
559 /* sys_ctrl1 default configuration not tunable */
560 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
561 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
562 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
563 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
564 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
565 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
566
567 REG_FLD_MOD(core_sys_base,
568 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
569
570 /* Vid_Mode */
571 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
572
573 /* dither truncation configuration */
574 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
575 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
576 r = FLD_MOD(r, 1, 5, 5);
577 } else {
578 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
579 r = FLD_MOD(r, 0, 5, 5);
580 }
581 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
582
583 /* HDMI_Ctrl */
584 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
585 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
586 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
587 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
588 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
589
590 /* TMDS_CTRL */
591 REG_FLD_MOD(core_sys_base,
592 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
593}
594
da8f14fc 595static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
7d983f39
M		 596{
597 u32 val;
598 char sum = 0, checksum = 0;
599 void __iomem *av_base = hdmi_av_base(ip_data);
da8f14fc 600 struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
7d983f39
M		 601
602 sum += 0x82 + 0x002 + 0x00D;
603 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
604 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
605 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
606
607 val = (info_avi.db1_format << 5) |
608 (info_avi.db1_active_info << 4) |
609 (info_avi.db1_bar_info_dv << 2) |
610 (info_avi.db1_scan_info);
611 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
612 sum += val;
613
614 val = (info_avi.db2_colorimetry << 6) |
615 (info_avi.db2_aspect_ratio << 4) |
616 (info_avi.db2_active_fmt_ar);
617 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
618 sum += val;
619
620 val = (info_avi.db3_itc << 7) |
621 (info_avi.db3_ec << 4) |
622 (info_avi.db3_q_range << 2) |
623 (info_avi.db3_nup_scaling);
624 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
625 sum += val;
626
627 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
628 info_avi.db4_videocode);
629 sum += info_avi.db4_videocode;
630
631 val = info_avi.db5_pixel_repeat;
632 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
633 sum += val;
634
635 val = info_avi.db6_7_line_eoftop & 0x00FF;
636 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
637 sum += val;
638
639 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
640 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
641 sum += val;
642
643 val = info_avi.db8_9_line_sofbottom & 0x00FF;
644 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
645 sum += val;
646
647 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
648 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
649 sum += val;
650
651 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
652 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
653 sum += val;
654
655 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
656 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
657 sum += val;
658
659 val = info_avi.db12_13_pixel_sofright & 0x00FF;
660 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
661 sum += val;
662
663 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
664 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
665 sum += val;
666
667 checksum = 0x100 - sum;
668 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
669}
670
671static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
672 struct hdmi_core_packet_enable_repeat repeat_cfg)
673{
674 /* enable/repeat the infoframe */
675 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
676 (repeat_cfg.audio_pkt << 5) |
677 (repeat_cfg.audio_pkt_repeat << 4) |
678 (repeat_cfg.avi_infoframe << 1) |
679 (repeat_cfg.avi_infoframe_repeat));
680
681 /* enable/repeat the packet */
682 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
683 (repeat_cfg.gen_cntrl_pkt << 3) |
684 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
685 (repeat_cfg.generic_pkt << 1) |
686 (repeat_cfg.generic_pkt_repeat));
687}
688
689static void hdmi_wp_init(struct omap_video_timings *timings,
aeec1a6c 690 struct hdmi_video_format *video_fmt)
7d983f39
M		 691{
692 pr_debug("Enter hdmi_wp_init\n");
693
694 timings->hbp = 0;
695 timings->hfp = 0;
696 timings->hsw = 0;
697 timings->vbp = 0;
698 timings->vfp = 0;
699 timings->vsw = 0;
700
701 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
702 video_fmt->y_res = 0;
703 video_fmt->x_res = 0;
704
7d983f39
M		 705}
706
c0456be3 707int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data)
7d983f39 708{
c0456be3
RN		 709 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31);
710 return 0;
711}
712
713void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data)
714{
715 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31);
7d983f39
M		 716}
717
718static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
719 struct omap_video_timings *timings, struct hdmi_config *param)
720{
721 pr_debug("Enter hdmi_wp_video_init_format\n");
722
a05ce78f
M		 723 video_fmt->y_res = param->timings.y_res;
724 video_fmt->x_res = param->timings.x_res;
7d983f39 725
a05ce78f
M		 726 timings->hbp = param->timings.hbp;
727 timings->hfp = param->timings.hfp;
728 timings->hsw = param->timings.hsw;
729 timings->vbp = param->timings.vbp;
730 timings->vfp = param->timings.vfp;
731 timings->vsw = param->timings.vsw;
7d983f39
M		 732}
733
734static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
735 struct hdmi_video_format *video_fmt)
736{
737 u32 l = 0;
738
739 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
740 video_fmt->packing_mode, 10, 8);
741
742 l |= FLD_VAL(video_fmt->y_res, 31, 16);
743 l |= FLD_VAL(video_fmt->x_res, 15, 0);
744 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
745}
746
aeec1a6c 747static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
7d983f39
M		 748{
749 u32 r;
750 pr_debug("Enter hdmi_wp_video_config_interface\n");
751
752 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
aeec1a6c
M		 753 r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7);
754 r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6);
a05ce78f 755 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
aeec1a6c 756 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
7d983f39
M		 757 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
758}
759
760static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
761 struct omap_video_timings *timings)
762{
763 u32 timing_h = 0;
764 u32 timing_v = 0;
765
766 pr_debug("Enter hdmi_wp_video_config_timing\n");
767
768 timing_h |= FLD_VAL(timings->hbp, 31, 20);
769 timing_h |= FLD_VAL(timings->hfp, 19, 8);
770 timing_h |= FLD_VAL(timings->hsw, 7, 0);
771 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
772
773 timing_v |= FLD_VAL(timings->vbp, 31, 20);
774 timing_v |= FLD_VAL(timings->vfp, 19, 8);
775 timing_v |= FLD_VAL(timings->vsw, 7, 0);
776 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
777}
778
176b578b 779void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
7d983f39
M		 780{
781 /* HDMI */
782 struct omap_video_timings video_timing;
783 struct hdmi_video_format video_format;
7d983f39 784 /* HDMI core */
da8f14fc 785 struct hdmi_core_infoframe_avi avi_cfg = ip_data->avi_cfg;
7d983f39
M		 786 struct hdmi_core_video_config v_core_cfg;
787 struct hdmi_core_packet_enable_repeat repeat_cfg;
788 struct hdmi_config *cfg = &ip_data->cfg;
789
aeec1a6c 790 hdmi_wp_init(&video_timing, &video_format);
7d983f39
M		 791
792 hdmi_core_init(&v_core_cfg,
793 &avi_cfg,
794 &repeat_cfg);
795
796 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
797
798 hdmi_wp_video_config_timing(ip_data, &video_timing);
799
800 /* video config */
801 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
802
803 hdmi_wp_video_config_format(ip_data, &video_format);
804
aeec1a6c 805 hdmi_wp_video_config_interface(ip_data);
7d983f39
M		 806
807 /*
808 * configure core video part
809 * set software reset in the core
810 */
811 hdmi_core_swreset_assert(ip_data);
812
813 /* power down off */
814 hdmi_core_powerdown_disable(ip_data);
815
816 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
817 v_core_cfg.hdmi_dvi = cfg->cm.mode;
818
819 hdmi_core_video_config(ip_data, &v_core_cfg);
820
821 /* release software reset in the core */
822 hdmi_core_swreset_release(ip_data);
823
824 /*
825 * configure packet
826 * info frame video see doc CEA861-D page 65
827 */
828 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
829 avi_cfg.db1_active_info =
830 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
831 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
832 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
833 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
834 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
835 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
836 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
837 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
838 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
839 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
840 avi_cfg.db4_videocode = cfg->cm.code;
841 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
842 avi_cfg.db6_7_line_eoftop = 0;
843 avi_cfg.db8_9_line_sofbottom = 0;
844 avi_cfg.db10_11_pixel_eofleft = 0;
845 avi_cfg.db12_13_pixel_sofright = 0;
846
da8f14fc 847 hdmi_core_aux_infoframe_avi_config(ip_data);
7d983f39
M		 848
849 /* enable/repeat the infoframe */
850 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
851 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
852 /* wakeup */
853 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
854 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
855 hdmi_core_av_packet_config(ip_data, repeat_cfg);
856}
7334167b 857
162874d5
M		 858void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
859{
860#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
861 hdmi_read_reg(hdmi_wp_base(ip_data), r))
862
863 DUMPREG(HDMI_WP_REVISION);
864 DUMPREG(HDMI_WP_SYSCONFIG);
865 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
866 DUMPREG(HDMI_WP_IRQSTATUS);
867 DUMPREG(HDMI_WP_PWR_CTRL);
868 DUMPREG(HDMI_WP_IRQENABLE_SET);
869 DUMPREG(HDMI_WP_VIDEO_CFG);
870 DUMPREG(HDMI_WP_VIDEO_SIZE);
871 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
872 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
873 DUMPREG(HDMI_WP_WP_CLK);
874 DUMPREG(HDMI_WP_AUDIO_CFG);
875 DUMPREG(HDMI_WP_AUDIO_CFG2);
876 DUMPREG(HDMI_WP_AUDIO_CTRL);
877 DUMPREG(HDMI_WP_AUDIO_DATA);
878}
879
880void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
881{
882#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
883 hdmi_read_reg(hdmi_pll_base(ip_data), r))
884
885 DUMPPLL(PLLCTRL_PLL_CONTROL);
886 DUMPPLL(PLLCTRL_PLL_STATUS);
887 DUMPPLL(PLLCTRL_PLL_GO);
888 DUMPPLL(PLLCTRL_CFG1);
889 DUMPPLL(PLLCTRL_CFG2);
890 DUMPPLL(PLLCTRL_CFG3);
891 DUMPPLL(PLLCTRL_CFG4);
892}
893
894void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
895{
896 int i;
897
898#define CORE_REG(i, name) name(i)
899#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
3c7de247
AT		 900 hdmi_read_reg(hdmi_core_sys_base(ip_data), r))
901#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
902 hdmi_read_reg(hdmi_av_base(ip_data), r))
903#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
162874d5 904 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
3c7de247 905 hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r)))
162874d5
M		 906
907 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
908 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
909 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
910 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
911 DUMPCORE(HDMI_CORE_SYS_SRST);
912 DUMPCORE(HDMI_CORE_CTRL1);
913 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
9b9c457b
AT		 914 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
915 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
916 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
917 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
918 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
919 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
920 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
162874d5
M		 921 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
922 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
923 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
924 DUMPCORE(HDMI_CORE_SYS_INTR1);
925 DUMPCORE(HDMI_CORE_SYS_INTR2);
926 DUMPCORE(HDMI_CORE_SYS_INTR3);
927 DUMPCORE(HDMI_CORE_SYS_INTR4);
928 DUMPCORE(HDMI_CORE_SYS_UMASK1);
929 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
162874d5 930
162874d5 931 DUMPCORE(HDMI_CORE_DDC_ADDR);
9b9c457b 932 DUMPCORE(HDMI_CORE_DDC_SEGM);
162874d5
M		 933 DUMPCORE(HDMI_CORE_DDC_OFFSET);
934 DUMPCORE(HDMI_CORE_DDC_COUNT1);
935 DUMPCORE(HDMI_CORE_DDC_COUNT2);
9b9c457b
AT		 936 DUMPCORE(HDMI_CORE_DDC_STATUS);
937 DUMPCORE(HDMI_CORE_DDC_CMD);
162874d5 938 DUMPCORE(HDMI_CORE_DDC_DATA);
3c7de247
AT		 939
940 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
941 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
942 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
943 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
944 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
945 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
946 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
947 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
948 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
949 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
950 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
951 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
952 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
953 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
954 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
955 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
956 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
957 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
958 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
959 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
960 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
961 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
962 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
963 DUMPCOREAV(HDMI_CORE_AV_ASRC);
964 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
965 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
966 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
967 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
968 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
969 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
970 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
971 DUMPCOREAV(HDMI_CORE_AV_DPD);
972 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
973 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
974 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
975 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
976 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
977 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
9b9c457b
AT		 978
979 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
980 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
981
3c7de247
AT		 982 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
983 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
984 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
985 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
9b9c457b
AT		 986
987 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
988 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
989
3c7de247
AT		 990 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
991 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
992 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
993 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
9b9c457b
AT		 994
995 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
996 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
997
3c7de247
AT		 998 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
999 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
1000 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
1001 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
9b9c457b
AT		 1002
1003 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
1004 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
1005
1006 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
1007 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
1008
3c7de247 1009 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
9b9c457b
AT		 1010
1011 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
1012 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
1013
3c7de247 1014 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
162874d5
M		 1015}
1016
1017void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1018{
1019#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1020 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1021
1022 DUMPPHY(HDMI_TXPHY_TX_CTRL);
1023 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1024 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1025 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1026}
1027
7e151f7f 1028#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
6ec355d6 1029static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data,
7334167b
M		 1030 struct hdmi_audio_format *aud_fmt)
1031{
1032 u32 r;
1033
1034 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1035
1036 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1037 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1038 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1039 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1040 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1041 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1042 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1043 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1044 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1045 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1046}
1047
6ec355d6 1048static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
7334167b
M		 1049 struct hdmi_audio_dma *aud_dma)
1050{
1051 u32 r;
1052
1053 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1054
1055 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1056 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1057 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1058 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1059
1060 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1061 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1062 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1063 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1064}
1065
6ec355d6 1066static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data,
7334167b
M		 1067 struct hdmi_core_audio_config *cfg)
1068{
1069 u32 r;
1070 void __iomem *av_base = hdmi_av_base(ip_data);
1071
d8989d96
RN		 1072 /*
1073 * Parameters for generation of Audio Clock Recovery packets
1074 */
7334167b
M		 1075 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1076 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1077 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1078
1079 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1080 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1081 REG_FLD_MOD(av_base,
1082 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1083 REG_FLD_MOD(av_base,
1084 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1085 } else {
7334167b
M		 1086 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1087 cfg->aud_par_busclk, 7, 0);
1088 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1089 (cfg->aud_par_busclk >> 8), 7, 0);
1090 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1091 (cfg->aud_par_busclk >> 16), 7, 0);
1092 }
1093
d8989d96
RN		 1094 /* Set ACR clock divisor */
1095 REG_FLD_MOD(av_base,
1096 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1097
1098 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1099 /*
1100 * Use TMDS clock for ACR packets. For devices that use
1101 * the MCLK, this is the first part of the MCLK initialization.
1102 */
1103 r = FLD_MOD(r, 0, 2, 2);
1104
1105 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1106 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1107 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1108
1109 /* For devices using MCLK, this completes its initialization. */
1110 if (cfg->use_mclk)
1111 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
1112
7334167b
M		 1113 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1114 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1115 cfg->fs_override, 1, 1);
1116
c1164ed8
RN		 1117 /*
1118 * Set IEC-60958-3 channel status word. It is passed to the IP
1119 * just as it is received. The user of the driver is responsible
1120 * for its contents.
1121 */
1122 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
1123 cfg->iec60958_cfg->status[0]);
1124 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
1125 cfg->iec60958_cfg->status[1]);
1126 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
1127 cfg->iec60958_cfg->status[2]);
1128 /* yes, this is correct: status[3] goes to CHST4 register */
1129 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
1130 cfg->iec60958_cfg->status[3]);
1131 /* yes, this is correct: status[4] goes to CHST5 register */
1132 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
1133 cfg->iec60958_cfg->status[4]);
1134
1135 /* set I2S parameters */
7334167b 1136 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
7334167b 1137 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
7334167b 1138 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
7334167b
M		 1139 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1140 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1141 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1142 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1143
7334167b
M		 1144 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1145 cfg->i2s_cfg.in_length_bits, 3, 0);
1146
1147 /* Audio channels and mode parameters */
1148 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1149 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1150 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1151 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1152 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1153 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1154 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1155}
1156
6ec355d6 1157static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data,
199e7fd6 1158 struct snd_cea_861_aud_if *info_aud)
7334167b 1159{
7334167b
M		 1160 u8 sum = 0, checksum = 0;
1161 void __iomem *av_base = hdmi_av_base(ip_data);
1162
1163 /*
1164 * Set audio info frame type, version and length as
1165 * described in HDMI 1.4a Section 8.2.2 specification.
1166 * Checksum calculation is defined in Section 5.3.5.
1167 */
1168 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1169 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1170 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1171 sum += 0x84 + 0x001 + 0x00a;
1172
199e7fd6
RN		 1173 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
1174 info_aud->db1_ct_cc);
1175 sum += info_aud->db1_ct_cc;
7334167b 1176
199e7fd6
RN		 1177 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
1178 info_aud->db2_sf_ss);
1179 sum += info_aud->db2_sf_ss;
7334167b 1180
199e7fd6
RN		 1181 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
1182 sum += info_aud->db3;
7334167b 1183
199e7fd6
RN		 1184 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
1185 sum += info_aud->db4_ca;
7334167b 1186
199e7fd6
RN		 1187 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
1188 info_aud->db5_dminh_lsv);
1189 sum += info_aud->db5_dminh_lsv;
7334167b
M		 1190
1191 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1192 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1193 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1194 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1195 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1196
1197 checksum = 0x100 - sum;
1198 hdmi_write_reg(av_base,
1199 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1200
1201 /*
1202 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1203 * is available.
1204 */
1205}
1206
6ec355d6
RN		 1207int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
1208 struct omap_dss_audio *audio)
1209{
1210 struct hdmi_audio_format audio_format;
1211 struct hdmi_audio_dma audio_dma;
1212 struct hdmi_core_audio_config core;
1213 int err, n, cts, channel_count;
1214 unsigned int fs_nr;
1215 bool word_length_16b = false;
1216
1217 if (!audio || !audio->iec || !audio->cea || !ip_data)
1218 return -EINVAL;
1219
1220 core.iec60958_cfg = audio->iec;
1221 /*
1222 * In the IEC-60958 status word, check if the audio sample word length
1223 * is 16-bit as several optimizations can be performed in such case.
1224 */
1225 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
1226 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
1227 word_length_16b = true;
1228
1229 /* I2S configuration. See Phillips' specification */
1230 if (word_length_16b)
1231 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1232 else
1233 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1234 /*
1235 * The I2S input word length is twice the lenght given in the IEC-60958
1236 * status word. If the word size is greater than
1237 * 20 bits, increment by one.
1238 */
1239 core.i2s_cfg.in_length_bits = audio->iec->status[4]
1240 & IEC958_AES4_CON_WORDLEN;
1241 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
1242 core.i2s_cfg.in_length_bits++;
1243 core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1244 core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1245 core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1246 core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1247
1248 /* convert sample frequency to a number */
1249 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
1250 case IEC958_AES3_CON_FS_32000:
1251 fs_nr = 32000;
1252 break;
1253 case IEC958_AES3_CON_FS_44100:
1254 fs_nr = 44100;
1255 break;
1256 case IEC958_AES3_CON_FS_48000:
1257 fs_nr = 48000;
1258 break;
1259 case IEC958_AES3_CON_FS_88200:
1260 fs_nr = 88200;
1261 break;
1262 case IEC958_AES3_CON_FS_96000:
1263 fs_nr = 96000;
1264 break;
1265 case IEC958_AES3_CON_FS_176400:
1266 fs_nr = 176400;
1267 break;
1268 case IEC958_AES3_CON_FS_192000:
1269 fs_nr = 192000;
1270 break;
1271 default:
1272 return -EINVAL;
1273 }
1274
1275 err = hdmi_compute_acr(fs_nr, &n, &cts);
1276
1277 /* Audio clock regeneration settings */
1278 core.n = n;
1279 core.cts = cts;
1280 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1281 core.aud_par_busclk = 0;
1282 core.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1283 core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
1284 } else {
1285 core.aud_par_busclk = (((128 * 31) - 1) << 8);
1286 core.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1287 core.use_mclk = true;
1288 }
1289
1290 if (core.use_mclk)
1291 core.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1292
1293 /* Audio channels settings */
1294 channel_count = (audio->cea->db1_ct_cc &
1295 CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
1296
1297 switch (channel_count) {
1298 case 2:
1299 audio_format.active_chnnls_msk = 0x03;
1300 break;
1301 case 3:
1302 audio_format.active_chnnls_msk = 0x07;
1303 break;
1304 case 4:
1305 audio_format.active_chnnls_msk = 0x0f;
1306 break;
1307 case 5:
1308 audio_format.active_chnnls_msk = 0x1f;
1309 break;
1310 case 6:
1311 audio_format.active_chnnls_msk = 0x3f;
1312 break;
1313 case 7:
1314 audio_format.active_chnnls_msk = 0x7f;
1315 break;
1316 case 8:
1317 audio_format.active_chnnls_msk = 0xff;
1318 break;
1319 default:
1320 return -EINVAL;
1321 }
1322
1323 /*
1324 * the HDMI IP needs to enable four stereo channels when transmitting
1325 * more than 2 audio channels
1326 */
1327 if (channel_count == 2) {
1328 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1329 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1330 core.layout = HDMI_AUDIO_LAYOUT_2CH;
1331 } else {
1332 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
1333 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
1334 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
1335 HDMI_AUDIO_I2S_SD3_EN;
1336 core.layout = HDMI_AUDIO_LAYOUT_8CH;
1337 }
1338
1339 core.en_spdif = false;
1340 /* use sample frequency from channel status word */
1341 core.fs_override = true;
1342 /* enable ACR packets */
1343 core.en_acr_pkt = true;
1344 /* disable direct streaming digital audio */
1345 core.en_dsd_audio = false;
1346 /* use parallel audio interface */
1347 core.en_parallel_aud_input = true;
1348
1349 /* DMA settings */
1350 if (word_length_16b)
1351 audio_dma.transfer_size = 0x10;
1352 else
1353 audio_dma.transfer_size = 0x20;
1354 audio_dma.block_size = 0xC0;
1355 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1356 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1357
1358 /* audio FIFO format settings */
1359 if (word_length_16b) {
1360 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1361 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1362 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1363 } else {
1364 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1365 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1366 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1367 }
1368 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1369 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1370 /* disable start/stop signals of IEC 60958 blocks */
1371 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
1372
1373 /* configure DMA and audio FIFO format*/
1374 ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma);
1375 ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format);
1376
1377 /* configure the core*/
1378 ti_hdmi_4xxx_core_audio_config(ip_data, &core);
1379
1380 /* configure CEA 861 audio infoframe*/
1381 ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea);
1382
1383 return 0;
1384}
1385
027bdc85 1386int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data)
80a48596 1387{
80a48596 1388 REG_FLD_MOD(hdmi_wp_base(ip_data),
027bdc85 1389 HDMI_WP_AUDIO_CTRL, true, 31, 31);
3df9fb5c
ACG		 1390 return 0;
1391}
1392
1393void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data)
1394{
1395 REG_FLD_MOD(hdmi_wp_base(ip_data),
1396 HDMI_WP_AUDIO_CTRL, false, 31, 31);
1397}
1398
1399int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data)
1400{
1401 REG_FLD_MOD(hdmi_av_base(ip_data),
1402 HDMI_CORE_AV_AUD_MODE, true, 0, 0);
80a48596 1403 REG_FLD_MOD(hdmi_wp_base(ip_data),
027bdc85
RN		 1404 HDMI_WP_AUDIO_CTRL, true, 30, 30);
1405 return 0;
1406}
1407
3df9fb5c 1408void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data)
027bdc85
RN		 1409{
1410 REG_FLD_MOD(hdmi_av_base(ip_data),
1411 HDMI_CORE_AV_AUD_MODE, false, 0, 0);
027bdc85
RN		 1412 REG_FLD_MOD(hdmi_wp_base(ip_data),
1413 HDMI_WP_AUDIO_CTRL, false, 30, 30);
80a48596 1414}
7334167b 1415#endif
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