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1da177e4
LT		 1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41
42#include <video/permedia2.h>
43#include <video/cvisionppc.h>
44
45#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46#error "The endianness of the target host has not been defined."
47#endif
48
49#if !defined(CONFIG_PCI)
50#error "Only generic PCI cards supported."
51#endif
52
53#undef PM2FB_MASTER_DEBUG
54#ifdef PM2FB_MASTER_DEBUG
55#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
56#else
57#define DPRINTK(a,b...)
58#endif
59
60/*
61 * Driver data
62 */
63static char *mode __devinitdata = NULL;
64
65/*
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
73 */
c16c556e
DJ		 74static int lowhsync;
75static int lowvsync;
1da177e4
LT		 76
77/*
78 * The hardware state of the graphics card that isn't part of the
79 * screeninfo.
80 */
81struct pm2fb_par
82{
83 pm2type_t type; /* Board type */
1da177e4
LT		 84 unsigned char __iomem *v_regs;/* virtual address of p_regs */
85 u32 memclock; /* memclock */
86 u32 video; /* video flags before blanking */
87 u32 mem_config; /* MemConfig reg at probe */
88 u32 mem_control; /* MemControl reg at probe */
89 u32 boot_address; /* BootAddress reg at probe */
6772a2ee 90 u32 palette[16];
1da177e4
LT		 91};
92
93/*
94 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
95 * if we don't use modedb.
96 */
97static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
98 .id = "",
99 .type = FB_TYPE_PACKED_PIXELS,
100 .visual = FB_VISUAL_PSEUDOCOLOR,
101 .xpanstep = 1,
102 .ypanstep = 1,
103 .ywrapstep = 0,
87a7cc68 104 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
1da177e4
LT		 105};
106
107/*
108 * Default video mode. In case the modedb doesn't work.
109 */
110static struct fb_var_screeninfo pm2fb_var __devinitdata = {
111 /* "640x480, 8 bpp @ 60 Hz */
112 .xres = 640,
113 .yres = 480,
114 .xres_virtual = 640,
115 .yres_virtual = 480,
116 .bits_per_pixel =8,
117 .red = {0, 8, 0},
118 .blue = {0, 8, 0},
119 .green = {0, 8, 0},
120 .activate = FB_ACTIVATE_NOW,
121 .height = -1,
122 .width = -1,
123 .accel_flags = 0,
124 .pixclock = 39721,
125 .left_margin = 40,
126 .right_margin = 24,
127 .upper_margin = 32,
128 .lower_margin = 11,
129 .hsync_len = 96,
130 .vsync_len = 2,
131 .vmode = FB_VMODE_NONINTERLACED
132};
133
134/*
135 * Utility functions
136 */
137
77933d72 138static inline u32 RD32(unsigned char __iomem *base, s32 off)
1da177e4
LT		 139{
140 return fb_readl(base + off);
141}
142
77933d72 143static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
1da177e4
LT		 144{
145 fb_writel(v, base + off);
146}
147
77933d72 148static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
1da177e4
LT		 149{
150 return RD32(p->v_regs, off);
151}
152
77933d72 153static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
1da177e4
LT		 154{
155 WR32(p->v_regs, off, v);
156}
157
77933d72 158static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
1da177e4
LT		 159{
160 int index = PM2R_RD_INDEXED_DATA;
161 switch (p->type) {
162 case PM2_TYPE_PERMEDIA2:
163 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
164 break;
165 case PM2_TYPE_PERMEDIA2V:
166 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
167 index = PM2VR_RD_INDEXED_DATA;
168 break;
169 }
170 mb();
171 return pm2_RD(p, index);
172}
173
77933d72 174static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 175{
176 int index = PM2R_RD_INDEXED_DATA;
177 switch (p->type) {
178 case PM2_TYPE_PERMEDIA2:
179 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
180 break;
181 case PM2_TYPE_PERMEDIA2V:
182 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
183 index = PM2VR_RD_INDEXED_DATA;
184 break;
185 }
186 mb();
187 pm2_WR(p, index, v);
188}
189
77933d72 190static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 191{
192 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
193 mb();
194 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
195}
196
197#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
198#define WAIT_FIFO(p,a)
199#else
77933d72 200static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
1da177e4
LT		 201{
202 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
203 mb();
204}
205#endif
206
87a7cc68
KH		 207static void wait_pm2(struct pm2fb_par* par) {
208
209 WAIT_FIFO(par, 1);
210 pm2_WR(par, PM2R_SYNC, 0);
211 mb();
212 do {
213 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0);
214 rmb();
215 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
216}
217
1da177e4
LT		 218/*
219 * partial products for the supported horizontal resolutions.
220 */
221#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
222static const struct {
223 u16 width;
224 u16 pp;
225} pp_table[] = {
226 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
227 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
228 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
229 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
230 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
231 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
232 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
233 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
234 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
235 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
236 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
237 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
238 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
239 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
240 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
241 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
242 { 0, 0 } };
243
244static u32 partprod(u32 xres)
245{
246 int i;
247
248 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
249 ;
250 if ( pp_table[i].width == 0 )
251 DPRINTK("invalid width %u\n", xres);
252 return pp_table[i].pp;
253}
254
255static u32 to3264(u32 timing, int bpp, int is64)
256{
257 switch (bpp) {
258 case 8:
259 timing >>= 2 + is64;
260 break;
261 case 16:
262 timing >>= 1 + is64;
263 break;
264 case 24:
265 timing = (timing * 3) >> (2 + is64);
266 break;
267 case 32:
268 if (is64)
269 timing >>= 1;
270 break;
271 }
272 return timing;
273}
274
275static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
276 unsigned char* pp)
277{
278 unsigned char m;
279 unsigned char n;
280 unsigned char p;
281 u32 f;
282 s32 curr;
283 s32 delta = 100000;
284
285 *mm = *nn = *pp = 0;
286 for (n = 2; n < 15; n++) {
287 for (m = 2; m; m++) {
288 f = PM2_REFERENCE_CLOCK * m / n;
289 if (f >= 150000 && f <= 300000) {
290 for ( p = 0; p < 5; p++, f >>= 1) {
291 curr = ( clk > f ) ? clk - f : f - clk;
292 if ( curr < delta ) {
293 delta=curr;
294 *mm=m;
295 *nn=n;
296 *pp=p;
297 }
298 }
299 }
300 }
301 }
302}
303
304static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
305 unsigned char* pp)
306{
307 unsigned char m;
308 unsigned char n;
309 unsigned char p;
310 u32 f;
311 s32 delta = 1000;
312
313 *mm = *nn = *pp = 0;
d4a96b53
KH		 314 for ( m = 1; m < 128; m++) {
315 for (n = 2 * m + 1; n; n++) {
1da177e4 316 for ( p = 0; p < 2; p++) {
d4a96b53 317 f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m;
1da177e4
LT		 318 if ( clk > f - delta && clk < f + delta ) {
319 delta = ( clk > f ) ? clk - f : f - clk;
320 *mm=m;
321 *nn=n;
322 *pp=p;
323 }
324 }
325 }
326 }
327}
328
329static void clear_palette(struct pm2fb_par* p) {
330 int i=256;
331
332 WAIT_FIFO(p, 1);
333 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
334 wmb();
335 while (i--) {
336 WAIT_FIFO(p, 3);
337 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
338 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
339 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
340 }
341}
342
343static void reset_card(struct pm2fb_par* p)
344{
345 if (p->type == PM2_TYPE_PERMEDIA2V)
346 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
347 pm2_WR(p, PM2R_RESET_STATUS, 0);
348 mb();
349 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
350 ;
351 mb();
352#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
353 DPRINTK("FIFO disconnect enabled\n");
354 pm2_WR(p, PM2R_FIFO_DISCON, 1);
355 mb();
356#endif
357
358 /* Restore stashed memory config information from probe */
359 WAIT_FIFO(p, 3);
360 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
361 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
362 wmb();
363 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
364}
365
366static void reset_config(struct pm2fb_par* p)
367{
368 WAIT_FIFO(p, 52);
369 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
370 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
371 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
372 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
373 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
374 pm2_WR(p, PM2R_APERTURE_ONE, 0);
375 pm2_WR(p, PM2R_APERTURE_TWO, 0);
376 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
377 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
378 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
379 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
380 pm2_WR(p, PM2R_LB_READ_MODE, 0);
381 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
382 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
383 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
384 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
385 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
386 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
387 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
388 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
389 pm2_WR(p, PM2R_DITHER_MODE, 0);
390 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
391 pm2_WR(p, PM2R_DEPTH_MODE, 0);
392 pm2_WR(p, PM2R_STENCIL_MODE, 0);
393 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
394 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
395 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
396 pm2_WR(p, PM2R_YUV_MODE, 0);
397 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
398 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
399 pm2_WR(p, PM2R_FOG_MODE, 0);
400 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
401 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
402 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
403 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
404 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
405 switch (p->type) {
406 case PM2_TYPE_PERMEDIA2:
407 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
408 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
409 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
410 break;
411 case PM2_TYPE_PERMEDIA2V:
412 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
413 break;
414 }
415 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
416 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
417 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
418 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
419 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
420}
421
422static void set_aperture(struct pm2fb_par* p, u32 depth)
423{
424 /*
425 * The hardware is little-endian. When used in big-endian
426 * hosts, the on-chip aperture settings are used where
427 * possible to translate from host to card byte order.
428 */
429 WAIT_FIFO(p, 4);
430#ifdef __LITTLE_ENDIAN
431 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
432#else
433 switch (depth) {
434 case 24: /* RGB->BGR */
435 /*
436 * We can't use the aperture to translate host to
437 * card byte order here, so we switch to BGR mode
438 * in pm2fb_set_par().
439 */
440 case 8: /* B->B */
441 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
442 break;
443 case 16: /* HL->LH */
444 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
445 break;
446 case 32: /* RGBA->ABGR */
447 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
448 break;
449 }
450#endif
451
452 // We don't use aperture two, so this may be superflous
453 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
454}
455
456static void set_color(struct pm2fb_par* p, unsigned char regno,
457 unsigned char r, unsigned char g, unsigned char b)
458{
459 WAIT_FIFO(p, 4);
460 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
461 wmb();
462 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
463 wmb();
464 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
465 wmb();
466 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
467}
468
469static void set_memclock(struct pm2fb_par* par, u32 clk)
470{
471 int i;
472 unsigned char m, n, p;
473
e5d809d7
KH		 474 switch (par->type) {
475 case PM2_TYPE_PERMEDIA2V:
476 pm2v_mnp(clk/2, &m, &n, &p);
477 WAIT_FIFO(par, 8);
478 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
479 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
480 wmb();
481 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
482 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
483 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
484 wmb();
485 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
486 rmb();
487 for (i = 256;
488 i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
489 i--)
490 ;
491 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
492 break;
493 case PM2_TYPE_PERMEDIA2:
494 pm2_mnp(clk, &m, &n, &p);
495 WAIT_FIFO(par, 10);
496 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
497 wmb();
498 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
499 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
500 wmb();
501 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
502 wmb();
503 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
504 rmb();
505 for (i = 256;
506 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
507 i--)
508 ;
509 break;
510 }
1da177e4
LT		 511}
512
513static void set_pixclock(struct pm2fb_par* par, u32 clk)
514{
515 int i;
516 unsigned char m, n, p;
517
518 switch (par->type) {
519 case PM2_TYPE_PERMEDIA2:
520 pm2_mnp(clk, &m, &n, &p);
521 WAIT_FIFO(par, 8);
522 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
523 wmb();
524 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
525 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
526 wmb();
527 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
528 wmb();
529 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
530 rmb();
531 for (i = 256;
532 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
533 i--)
534 ;
535 break;
536 case PM2_TYPE_PERMEDIA2V:
537 pm2v_mnp(clk/2, &m, &n, &p);
538 WAIT_FIFO(par, 8);
539 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
540 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
541 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
542 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
543 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
544 break;
545 }
546}
547
548static void set_video(struct pm2fb_par* p, u32 video) {
549 u32 tmp;
550 u32 vsync;
551
552 vsync = video;
553
554 DPRINTK("video = 0x%x\n", video);
555
556 /*
557 * The hardware cursor needs +vsync to recognise vert retrace.
558 * We may not be using the hardware cursor, but the X Glint
559 * driver may well. So always set +hsync/+vsync and then set
560 * the RAMDAC to invert the sync if necessary.
561 */
562 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
563 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
564
565 WAIT_FIFO(p, 5);
566 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
567
568 switch (p->type) {
569 case PM2_TYPE_PERMEDIA2:
570 tmp = PM2F_RD_PALETTE_WIDTH_8;
571 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
572 tmp |= 4; /* invert hsync */
573 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
574 tmp |= 8; /* invert vsync */
575 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
576 break;
577 case PM2_TYPE_PERMEDIA2V:
578 tmp = 0;
579 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
580 tmp |= 1; /* invert hsync */
581 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
582 tmp |= 4; /* invert vsync */
583 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
584 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
585 break;
586 }
587}
588
589/*
590 *
591 */
592
593/**
594 * pm2fb_check_var - Optional function. Validates a var passed in.
595 * @var: frame buffer variable screen structure
596 * @info: frame buffer structure that represents a single frame buffer
597 *
598 * Checks to see if the hardware supports the state requested by
599 * var passed in.
600 *
601 * Returns negative errno on error, or zero on success.
602 */
603static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
604{
605 u32 lpitch;
606
607 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
608 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
609 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
610 return -EINVAL;
611 }
612
613 if (var->xres != var->xres_virtual) {
614 DPRINTK("virtual x resolution != physical x resolution not supported\n");
615 return -EINVAL;
616 }
617
618 if (var->yres > var->yres_virtual) {
619 DPRINTK("virtual y resolution < physical y resolution not possible\n");
620 return -EINVAL;
621 }
622
623 if (var->xoffset) {
624 DPRINTK("xoffset not supported\n");
625 return -EINVAL;
626 }
627
628 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
629 DPRINTK("interlace not supported\n");
630 return -EINVAL;
631 }
632
633 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
634 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
635
636 if (var->xres < 320 || var->xres > 1600) {
637 DPRINTK("width not supported: %u\n", var->xres);
638 return -EINVAL;
639 }
640
641 if (var->yres < 200 || var->yres > 1200) {
642 DPRINTK("height not supported: %u\n", var->yres);
643 return -EINVAL;
644 }
645
646 if (lpitch * var->yres_virtual > info->fix.smem_len) {
647 DPRINTK("no memory for screen (%ux%ux%u)\n",
648 var->xres, var->yres_virtual, var->bits_per_pixel);
649 return -EINVAL;
650 }
651
652 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
653 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
654 return -EINVAL;
655 }
656
76c7d3ff 657 var->transp.offset = 0;
658 var->transp.length = 0;
1da177e4
LT		 659 switch(var->bits_per_pixel) {
660 case 8:
661 var->red.length = var->green.length = var->blue.length = 8;
662 break;
663 case 16:
664 var->red.offset = 11;
665 var->red.length = 5;
666 var->green.offset = 5;
667 var->green.length = 6;
668 var->blue.offset = 0;
669 var->blue.length = 5;
670 break;
671 case 32:
672 var->transp.offset = 24;
673 var->transp.length = 8;
674 var->red.offset = 16;
675 var->green.offset = 8;
676 var->blue.offset = 0;
677 var->red.length = var->green.length = var->blue.length = 8;
678 break;
679 case 24:
680#ifdef __BIG_ENDIAN
681 var->red.offset = 0;
682 var->blue.offset = 16;
683#else
684 var->red.offset = 16;
685 var->blue.offset = 0;
686#endif
687 var->green.offset = 8;
688 var->red.length = var->green.length = var->blue.length = 8;
689 break;
690 }
691 var->height = var->width = -1;
692
693 var->accel_flags = 0; /* Can't mmap if this is on */
694
695 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
696 var->xres, var->yres, var->bits_per_pixel);
697 return 0;
698}
699
700/**
701 * pm2fb_set_par - Alters the hardware state.
702 * @info: frame buffer structure that represents a single frame buffer
703 *
704 * Using the fb_var_screeninfo in fb_info we set the resolution of the
705 * this particular framebuffer.
706 */
707static int pm2fb_set_par(struct fb_info *info)
708{
6772a2ee 709 struct pm2fb_par *par = info->par;
1da177e4
LT		 710 u32 pixclock;
711 u32 width, height, depth;
712 u32 hsstart, hsend, hbend, htotal;
713 u32 vsstart, vsend, vbend, vtotal;
714 u32 stride;
715 u32 base;
716 u32 video = 0;
717 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
718 u32 txtmap = 0;
719 u32 pixsize = 0;
720 u32 clrformat = 0;
721 u32 xres;
722 int data64;
723
724 reset_card(par);
725 reset_config(par);
726 clear_palette(par);
727 if ( par->memclock )
728 set_memclock(par, par->memclock);
729
730 width = (info->var.xres_virtual + 7) & ~7;
731 height = info->var.yres_virtual;
732 depth = (info->var.bits_per_pixel + 7) & ~7;
733 depth = (depth > 32) ? 32 : depth;
734 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
735
736 xres = (info->var.xres + 31) & ~31;
737 pixclock = PICOS2KHZ(info->var.pixclock);
738 if (pixclock > PM2_MAX_PIXCLOCK) {
739 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
740 return -EINVAL;
741 }
742
743 hsstart = to3264(info->var.right_margin, depth, data64);
744 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
745 hbend = hsend + to3264(info->var.left_margin, depth, data64);
746 htotal = to3264(xres, depth, data64) + hbend - 1;
747 vsstart = (info->var.lower_margin)
748 ? info->var.lower_margin - 1
749 : 0; /* FIXME! */
750 vsend = info->var.lower_margin + info->var.vsync_len - 1;
751 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
752 vtotal = info->var.yres + vbend - 1;
753 stride = to3264(width, depth, 1);
754 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
755 if (data64)
756 video |= PM2F_DATA_64_ENABLE;
757
758 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
759 if (lowhsync) {
760 DPRINTK("ignoring +hsync, using -hsync.\n");
761 video |= PM2F_HSYNC_ACT_LOW;
762 } else
763 video |= PM2F_HSYNC_ACT_HIGH;
764 }
765 else
766 video |= PM2F_HSYNC_ACT_LOW;
767 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
768 if (lowvsync) {
769 DPRINTK("ignoring +vsync, using -vsync.\n");
770 video |= PM2F_VSYNC_ACT_LOW;
771 } else
772 video |= PM2F_VSYNC_ACT_HIGH;
773 }
774 else
775 video |= PM2F_VSYNC_ACT_LOW;
776 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
777 DPRINTK("interlaced not supported\n");
778 return -EINVAL;
779 }
780 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
781 video |= PM2F_LINE_DOUBLE;
782 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
783 video |= PM2F_VIDEO_ENABLE;
784 par->video = video;
785
786 info->fix.visual =
787 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
788 info->fix.line_length = info->var.xres * depth / 8;
789 info->cmap.len = 256;
790
791 /*
792 * Settings calculated. Now write them out.
793 */
794 if (par->type == PM2_TYPE_PERMEDIA2V) {
795 WAIT_FIFO(par, 1);
796 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
797 }
798
799 set_aperture(par, depth);
800
801 mb();
802 WAIT_FIFO(par, 19);
803 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
804 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
805 switch (depth) {
806 case 8:
807 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
808 clrformat = 0x0e;
809 break;
810 case 16:
811 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
812 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
813 txtmap = PM2F_TEXTEL_SIZE_16;
814 pixsize = 1;
815 clrformat = 0x70;
816 break;
817 case 32:
818 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
819 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
820 txtmap = PM2F_TEXTEL_SIZE_32;
821 pixsize = 2;
822 clrformat = 0x20;
823 break;
824 case 24:
825 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
826 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
827 txtmap = PM2F_TEXTEL_SIZE_24;
828 pixsize = 4;
829 clrformat = 0x20;
830 break;
831 }
832 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
833 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
834 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
835 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
836 pm2_WR(par, PM2R_H_TOTAL, htotal);
837 pm2_WR(par, PM2R_HS_START, hsstart);
838 pm2_WR(par, PM2R_HS_END, hsend);
839 pm2_WR(par, PM2R_HG_END, hbend);
840 pm2_WR(par, PM2R_HB_END, hbend);
841 pm2_WR(par, PM2R_V_TOTAL, vtotal);
842 pm2_WR(par, PM2R_VS_START, vsstart);
843 pm2_WR(par, PM2R_VS_END, vsend);
844 pm2_WR(par, PM2R_VB_END, vbend);
845 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
846 wmb();
847 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
848 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
849 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
850 wmb();
851 pm2_WR(par, PM2R_SCREEN_BASE, base);
852 wmb();
853 set_video(par, video);
854 WAIT_FIFO(par, 4);
855 switch (par->type) {
856 case PM2_TYPE_PERMEDIA2:
857 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
858 break;
859 case PM2_TYPE_PERMEDIA2V:
860 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
861 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
862 break;
863 }
864 set_pixclock(par, pixclock);
865 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
866 info->var.xres, info->var.yres, info->var.bits_per_pixel);
867 return 0;
868}
869
870/**
871 * pm2fb_setcolreg - Sets a color register.
872 * @regno: boolean, 0 copy local, 1 get_user() function
873 * @red: frame buffer colormap structure
874 * @green: The green value which can be up to 16 bits wide
875 * @blue: The blue value which can be up to 16 bits wide.
876 * @transp: If supported the alpha value which can be up to 16 bits wide.
877 * @info: frame buffer info structure
878 *
879 * Set a single color register. The values supplied have a 16 bit
880 * magnitude which needs to be scaled in this function for the hardware.
881 * Pretty much a direct lift from tdfxfb.c.
882 *
883 * Returns negative errno on error, or zero on success.
884 */
885static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
886 unsigned blue, unsigned transp,
887 struct fb_info *info)
888{
6772a2ee 889 struct pm2fb_par *par = info->par;
1da177e4
LT		 890
891 if (regno >= info->cmap.len) /* no. of hw registers */
892 return 1;
893 /*
894 * Program hardware... do anything you want with transp
895 */
896
897 /* grayscale works only partially under directcolor */
898 if (info->var.grayscale) {
899 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
900 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
901 }
902
903 /* Directcolor:
904 * var->{color}.offset contains start of bitfield
905 * var->{color}.length contains length of bitfield
906 * {hardwarespecific} contains width of DAC
907 * cmap[X] is programmed to
908 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
909 * RAMDAC[X] is programmed to (red, green, blue)
910 *
911 * Pseudocolor:
912 * uses offset = 0 && length = DAC register width.
913 * var->{color}.offset is 0
914 * var->{color}.length contains widht of DAC
915 * cmap is not used
916 * DAC[X] is programmed to (red, green, blue)
917 * Truecolor:
918 * does not use RAMDAC (usually has 3 of them).
919 * var->{color}.offset contains start of bitfield
920 * var->{color}.length contains length of bitfield
921 * cmap is programmed to
922 * (red << red.offset) | (green << green.offset) |
923 * (blue << blue.offset) | (transp << transp.offset)
924 * RAMDAC does not exist
925 */
926#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
927 switch (info->fix.visual) {
928 case FB_VISUAL_TRUECOLOR:
929 case FB_VISUAL_PSEUDOCOLOR:
930 red = CNVT_TOHW(red, info->var.red.length);
931 green = CNVT_TOHW(green, info->var.green.length);
932 blue = CNVT_TOHW(blue, info->var.blue.length);
933 transp = CNVT_TOHW(transp, info->var.transp.length);
934 break;
935 case FB_VISUAL_DIRECTCOLOR:
936 /* example here assumes 8 bit DAC. Might be different
937 * for your hardware */
938 red = CNVT_TOHW(red, 8);
939 green = CNVT_TOHW(green, 8);
940 blue = CNVT_TOHW(blue, 8);
941 /* hey, there is bug in transp handling... */
942 transp = CNVT_TOHW(transp, 8);
943 break;
944 }
945#undef CNVT_TOHW
946 /* Truecolor has hardware independent palette */
947 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
948 u32 v;
949
950 if (regno >= 16)
951 return 1;
952
953 v = (red << info->var.red.offset) |
954 (green << info->var.green.offset) |
955 (blue << info->var.blue.offset) |
956 (transp << info->var.transp.offset);
957
958 switch (info->var.bits_per_pixel) {
959 case 8:
960 break;
961 case 16:
962 case 24:
963 case 32:
6772a2ee 964 par->palette[regno] = v;
1da177e4
LT		 965 break;
966 }
967 return 0;
968 }
969 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
970 set_color(par, regno, red, green, blue);
971
972 return 0;
973}
974
975/**
976 * pm2fb_pan_display - Pans the display.
977 * @var: frame buffer variable screen structure
978 * @info: frame buffer structure that represents a single frame buffer
979 *
980 * Pan (or wrap, depending on the `vmode' field) the display using the
981 * `xoffset' and `yoffset' fields of the `var' structure.
982 * If the values don't fit, return -EINVAL.
983 *
984 * Returns negative errno on error, or zero on success.
985 *
986 */
987static int pm2fb_pan_display(struct fb_var_screeninfo *var,
988 struct fb_info *info)
989{
6772a2ee 990 struct pm2fb_par *p = info->par;
1da177e4
LT		 991 u32 base;
992 u32 depth;
993 u32 xres;
994
995 xres = (var->xres + 31) & ~31;
996 depth = (var->bits_per_pixel + 7) & ~7;
997 depth = (depth > 32) ? 32 : depth;
998 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
999 WAIT_FIFO(p, 1);
1000 pm2_WR(p, PM2R_SCREEN_BASE, base);
1001 return 0;
1002}
1003
1004/**
1005 * pm2fb_blank - Blanks the display.
1006 * @blank_mode: the blank mode we want.
1007 * @info: frame buffer structure that represents a single frame buffer
1008 *
1009 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1010 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1011 * video mode which doesn't support it. Implements VESA suspend
1012 * and powerdown modes on hardware that supports disabling hsync/vsync:
1013 * blank_mode == 2: suspend vsync
1014 * blank_mode == 3: suspend hsync
1015 * blank_mode == 4: powerdown
1016 *
1017 * Returns negative errno on error, or zero on success.
1018 *
1019 */
1020static int pm2fb_blank(int blank_mode, struct fb_info *info)
1021{
6772a2ee 1022 struct pm2fb_par *par = info->par;
1da177e4
LT		 1023 u32 video = par->video;
1024
1025 DPRINTK("blank_mode %d\n", blank_mode);
1026
1027 switch (blank_mode) {
1028 case FB_BLANK_UNBLANK:
1029 /* Screen: On */
1030 video |= PM2F_VIDEO_ENABLE;
1031 break;
1032 case FB_BLANK_NORMAL:
1033 /* Screen: Off */
1034 video &= ~PM2F_VIDEO_ENABLE;
1035 break;
1036 case FB_BLANK_VSYNC_SUSPEND:
1037 /* VSync: Off */
1038 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1039 break;
1040 case FB_BLANK_HSYNC_SUSPEND:
1041 /* HSync: Off */
1042 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1043 break;
1044 case FB_BLANK_POWERDOWN:
1045 /* HSync: Off, VSync: Off */
1046 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1047 break;
1048 }
1049 set_video(par, video);
1050 return 0;
1051}
1052
87a7cc68
KH		 1053/*
1054 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1055 */
1056static void pm2fb_block_op(struct pm2fb_par* par, int copy,
1057 s32 xsrc, s32 ysrc,
1058 s32 x, s32 y, s32 w, s32 h,
1059 u32 color) {
1060
1061 if (!w || !h)
1062 return;
1063 WAIT_FIFO(par, 6);
1064 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1065 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1066 pm2_WR(par, PM2R_FB_PIXEL_OFFSET, 0);
1067 if (copy)
1068 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1069 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff));
1070 else
1071 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1072 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (y << 16) | x);
1073 pm2_WR(par, PM2R_RECTANGLE_SIZE, (h << 16) | w);
1074 wmb();
1075 pm2_WR(par, PM2R_RENDER,PM2F_RENDER_RECTANGLE |
1076 (x<xsrc ? PM2F_INCREASE_X : 0) |
1077 (y<ysrc ? PM2F_INCREASE_Y : 0) |
1078 (copy ? 0 : PM2F_RENDER_FASTFILL));
1079 wait_pm2(par);
1080}
1081
1082static void pm2fb_fillrect (struct fb_info *info,
1083 const struct fb_fillrect *region)
1084{
1085 struct pm2fb_par *par = info->par;
1086 struct fb_fillrect modded;
1087 int vxres, vyres;
1088 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1089 ((u32*)info->pseudo_palette)[region->color] : region->color;
1090
1091 if (info->state != FBINFO_STATE_RUNNING)
1092 return;
1093 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1094 region->rop != ROP_COPY ) {
1095 cfb_fillrect(info, region);
1096 return;
1097 }
1098
1099 vxres = info->var.xres_virtual;
1100 vyres = info->var.yres_virtual;
1101
1102 memcpy(&modded, region, sizeof(struct fb_fillrect));
1103
1104 if(!modded.width || !modded.height ||
1105 modded.dx >= vxres || modded.dy >= vyres)
1106 return;
1107
1108 if(modded.dx + modded.width > vxres)
1109 modded.width = vxres - modded.dx;
1110 if(modded.dy + modded.height > vyres)
1111 modded.height = vyres - modded.dy;
1112
1113 if(info->var.bits_per_pixel == 8)
1114 color |= color << 8;
1115 if(info->var.bits_per_pixel <= 16)
1116 color |= color << 16;
1117
1118 if(info->var.bits_per_pixel != 24)
1119 pm2fb_block_op(par, 0, 0, 0,
1120 modded.dx, modded.dy,
1121 modded.width, modded.height, color);
1122 else
1123 cfb_fillrect(info, region);
1124}
1125
1126static void pm2fb_copyarea(struct fb_info *info,
1127 const struct fb_copyarea *area)
1128{
1129 struct pm2fb_par *par = info->par;
1130 struct fb_copyarea modded;
1131 u32 vxres, vyres;
1132
1133 if (info->state != FBINFO_STATE_RUNNING)
1134 return;
1135 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1136 cfb_copyarea(info, area);
1137 return;
1138 }
1139
1140 memcpy(&modded, area, sizeof(struct fb_copyarea));
1141
1142 vxres = info->var.xres_virtual;
1143 vyres = info->var.yres_virtual;
1144
1145 if(!modded.width || !modded.height ||
1146 modded.sx >= vxres || modded.sy >= vyres ||
1147 modded.dx >= vxres || modded.dy >= vyres)
1148 return;
1149
1150 if(modded.sx + modded.width > vxres)
1151 modded.width = vxres - modded.sx;
1152 if(modded.dx + modded.width > vxres)
1153 modded.width = vxres - modded.dx;
1154 if(modded.sy + modded.height > vyres)
1155 modded.height = vyres - modded.sy;
1156 if(modded.dy + modded.height > vyres)
1157 modded.height = vyres - modded.dy;
1158
1159 pm2fb_block_op(par, 1, modded.sx, modded.sy,
1160 modded.dx, modded.dy,
1161 modded.width, modded.height, 0);
1162}
1163
1da177e4
LT		 1164/* ------------ Hardware Independent Functions ------------ */
1165
1166/*
1167 * Frame buffer operations
1168 */
1169
1170static struct fb_ops pm2fb_ops = {
1171 .owner = THIS_MODULE,
1172 .fb_check_var = pm2fb_check_var,
1173 .fb_set_par = pm2fb_set_par,
1174 .fb_setcolreg = pm2fb_setcolreg,
1175 .fb_blank = pm2fb_blank,
1176 .fb_pan_display = pm2fb_pan_display,
87a7cc68
KH		 1177 .fb_fillrect = pm2fb_fillrect,
1178 .fb_copyarea = pm2fb_copyarea,
1da177e4 1179 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 1180};
1181
1182/*
1183 * PCI stuff
1184 */
1185
1186
1187/**
1188 * Device initialisation
1189 *
1190 * Initialise and allocate resource for PCI device.
1191 *
1192 * @param pdev PCI device.
1193 * @param id PCI device ID.
1194 */
1195static int __devinit pm2fb_probe(struct pci_dev *pdev,
1196 const struct pci_device_id *id)
1197{
1198 struct pm2fb_par *default_par;
1199 struct fb_info *info;
6772a2ee 1200 int err, err_retval = -ENXIO;
1da177e4
LT		 1201
1202 err = pci_enable_device(pdev);
1203 if ( err ) {
1204 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1205 return err;
1206 }
1207
6772a2ee 1208 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1da177e4
LT		 1209 if ( !info )
1210 return -ENOMEM;
6772a2ee 1211 default_par = info->par;
1da177e4
LT		 1212
1213 switch (pdev->device) {
1214 case PCI_DEVICE_ID_TI_TVP4020:
1215 strcpy(pm2fb_fix.id, "TVP4020");
1216 default_par->type = PM2_TYPE_PERMEDIA2;
1217 break;
1218 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1219 strcpy(pm2fb_fix.id, "Permedia2");
1220 default_par->type = PM2_TYPE_PERMEDIA2;
1221 break;
1222 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1223 strcpy(pm2fb_fix.id, "Permedia2v");
1224 default_par->type = PM2_TYPE_PERMEDIA2V;
1225 break;
1226 }
1227
1228 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1229 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1230
1231#if defined(__BIG_ENDIAN)
1232 /*
1233 * PM2 has a 64k register file, mapped twice in 128k. Lower
1234 * map is little-endian, upper map is big-endian.
1235 */
1236 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1237 DPRINTK("Adjusting register base for big-endian.\n");
1238#endif
1239 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1240
1241 /* Registers - request region and map it. */
1242 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1243 "pm2fb regbase") ) {
1244 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1245 goto err_exit_neither;
1246 }
1247 default_par->v_regs =
1248 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1249 if ( !default_par->v_regs ) {
1250 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1251 pm2fb_fix.id);
1252 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1253 goto err_exit_neither;
1254 }
1255
1256 /* Stash away memory register info for use when we reset the board */
1257 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1258 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1259 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1260 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1261 default_par->mem_control, default_par->boot_address,
1262 default_par->mem_config);
1263
9127fa28
PDS		 1264 if(default_par->mem_control == 0 &&
1265 default_par->boot_address == 0x31 &&
f1c15f93 1266 default_par->mem_config == 0x259fffff) {
9a31f0f7 1267 default_par->memclock = CVPPC_MEMCLOCK;
9127fa28
PDS		 1268 default_par->mem_control=0;
1269 default_par->boot_address=0x20;
1270 default_par->mem_config=0xe6002021;
f1c15f93
KH		 1271 if (pdev->subsystem_vendor == 0x1048 &&
1272 pdev->subsystem_device == 0x0a31) {
1273 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1274 pdev->subsystem_vendor, pdev->subsystem_device);
1275 DPRINTK("We have not been initialized by VGA BIOS "
1276 "and are running on an Elsa Winner 2000 Office\n");
1277 DPRINTK("Initializing card timings manually...\n");
1278 default_par->memclock=70000;
1279 }
1280 if (pdev->subsystem_vendor == 0x3d3d &&
1281 pdev->subsystem_device == 0x0100) {
1282 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1283 pdev->subsystem_vendor, pdev->subsystem_device);
1284 DPRINTK("We have not been initialized by VGA BIOS "
1285 "and are running on an 3dlabs reference board\n");
1286 DPRINTK("Initializing card timings manually...\n");
9a31f0f7 1287 default_par->memclock=74894;
f1c15f93 1288 }
9127fa28
PDS		 1289 }
1290
1da177e4
LT		 1291 /* Now work out how big lfb is going to be. */
1292 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1293 case PM2F_MEM_BANKS_1:
4560daaf 1294 pm2fb_fix.smem_len=0x200000;
1da177e4
LT		 1295 break;
1296 case PM2F_MEM_BANKS_2:
4560daaf 1297 pm2fb_fix.smem_len=0x400000;
1da177e4
LT		 1298 break;
1299 case PM2F_MEM_BANKS_3:
4560daaf 1300 pm2fb_fix.smem_len=0x600000;
1da177e4
LT		 1301 break;
1302 case PM2F_MEM_BANKS_4:
4560daaf 1303 pm2fb_fix.smem_len=0x800000;
1da177e4
LT		 1304 break;
1305 }
1da177e4 1306 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1da177e4
LT		 1307
1308 /* Linear frame buffer - request region and map it. */
1309 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1310 "pm2fb smem") ) {
1311 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1312 goto err_exit_mmio;
1313 }
4560daaf 1314 info->screen_base =
1da177e4 1315 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
4560daaf 1316 if ( !info->screen_base ) {
1da177e4
LT		 1317 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1318 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1319 goto err_exit_mmio;
1320 }
1321
1322 info->fbops = &pm2fb_ops;
1323 info->fix = pm2fb_fix;
6772a2ee 1324 info->pseudo_palette = default_par->palette;
1da177e4 1325 info->flags = FBINFO_DEFAULT |
87a7cc68
KH		 1326 FBINFO_HWACCEL_YPAN |
1327 FBINFO_HWACCEL_COPYAREA |
1328 FBINFO_HWACCEL_FILLRECT;
1da177e4
LT		 1329
1330 if (!mode)
1331 mode = "640x480@60";
1332
1333 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1334 if (!err || err == 4)
1335 info->var = pm2fb_var;
1336
1337 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1338 goto err_exit_all;
1339
1340 if (register_framebuffer(info) < 0)
1341 goto err_exit_both;
1342
1343 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
4560daaf 1344 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1da177e4
LT		 1345
1346 /*
1347 * Our driver data
1348 */
1349 pci_set_drvdata(pdev, info);
1350
1351 return 0;
1352
1353 err_exit_all:
1354 fb_dealloc_cmap(&info->cmap);
1355 err_exit_both:
1356 iounmap(info->screen_base);
1357 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1358 err_exit_mmio:
1359 iounmap(default_par->v_regs);
1360 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1361 err_exit_neither:
1362 framebuffer_release(info);
1363 return err_retval;
1364}
1365
1366/**
1367 * Device removal.
1368 *
1369 * Release all device resources.
1370 *
1371 * @param pdev PCI device to clean up.
1372 */
1373static void __devexit pm2fb_remove(struct pci_dev *pdev)
1374{
1375 struct fb_info* info = pci_get_drvdata(pdev);
1376 struct fb_fix_screeninfo* fix = &info->fix;
1377 struct pm2fb_par *par = info->par;
1378
1379 unregister_framebuffer(info);
1380
1381 iounmap(info->screen_base);
1382 release_mem_region(fix->smem_start, fix->smem_len);
1383 iounmap(par->v_regs);
1384 release_mem_region(fix->mmio_start, fix->mmio_len);
1385
1386 pci_set_drvdata(pdev, NULL);
1387 kfree(info);
1388}
1389
1390static struct pci_device_id pm2fb_id_table[] = {
1391 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1392 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1393 0xff0000, 0 },
1394 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1395 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1396 0xff0000, 0 },
1397 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1398 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1399 0xff0000, 0 },
f1c15f93
KH		 1400 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1401 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1402 0xff00, 0 },
1da177e4
LT		 1403 { 0, }
1404};
1405
1406static struct pci_driver pm2fb_driver = {
1407 .name = "pm2fb",
1408 .id_table = pm2fb_id_table,
1409 .probe = pm2fb_probe,
1410 .remove = __devexit_p(pm2fb_remove),
1411};
1412
1413MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1414
1415
1416#ifndef MODULE
1417/**
1418 * Parse user speficied options.
1419 *
1420 * This is, comma-separated options following `video=pm2fb:'.
1421 */
1422static int __init pm2fb_setup(char *options)
1423{
1424 char* this_opt;
1425
1426 if (!options || !*options)
1427 return 0;
1428
1429 while ((this_opt = strsep(&options, ",")) != NULL) {
1430 if (!*this_opt)
1431 continue;
1432 if(!strcmp(this_opt, "lowhsync")) {
1433 lowhsync = 1;
1434 } else if(!strcmp(this_opt, "lowvsync")) {
1435 lowvsync = 1;
1436 } else {
1437 mode = this_opt;
1438 }
1439 }
1440 return 0;
1441}
1442#endif
1443
1444
1445static int __init pm2fb_init(void)
1446{
1447#ifndef MODULE
1448 char *option = NULL;
1449
1450 if (fb_get_options("pm2fb", &option))
1451 return -ENODEV;
1452 pm2fb_setup(option);
1453#endif
1454
1455 return pci_register_driver(&pm2fb_driver);
1456}
1457
1458module_init(pm2fb_init);
1459
1460#ifdef MODULE
1461/*
1462 * Cleanup
1463 */
1464
1465static void __exit pm2fb_exit(void)
1466{
1467 pci_unregister_driver(&pm2fb_driver);
1468}
1469#endif
1470
1471#ifdef MODULE
1472module_exit(pm2fb_exit);
1473
1474module_param(mode, charp, 0);
1475MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1476module_param(lowhsync, bool, 0);
1477MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1478module_param(lowvsync, bool, 0);
1479MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1480
1481MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1482MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1483MODULE_LICENSE("GPL");
1484#endif
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