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1da177e4 LT |
1 | /* |
2 | * Permedia2 framebuffer driver. | |
3 | * | |
4 | * 2.5/2.6 driver: | |
5 | * Copyright (c) 2003 Jim Hague (jim.hague@acm.org) | |
6 | * | |
7 | * based on 2.4 driver: | |
8 | * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) | |
9 | * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com) | |
10 | * | |
11 | * and additional input from James Simmon's port of Hannu Mallat's tdfx | |
12 | * driver. | |
13 | * | |
45f169ec | 14 | * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I |
1da177e4 LT |
15 | * have no access to other pm2fb implementations. Sparc (and thus |
16 | * hopefully other big-endian) devices now work, thanks to a lot of | |
17 | * testing work by Ron Murray. I have no access to CVision hardware, | |
18 | * and therefore for now I am omitting the CVision code. | |
19 | * | |
20 | * Multiple boards support has been on the TODO list for ages. | |
21 | * Don't expect this to change. | |
22 | * | |
23 | * This file is subject to the terms and conditions of the GNU General Public | |
24 | * License. See the file COPYING in the main directory of this archive for | |
25 | * more details. | |
26 | * | |
2f7bb99f | 27 | * |
1da177e4 LT |
28 | */ |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/moduleparam.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/mm.h> | |
1da177e4 LT |
36 | #include <linux/slab.h> |
37 | #include <linux/delay.h> | |
38 | #include <linux/fb.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/pci.h> | |
d5383fcc KH |
41 | #ifdef CONFIG_MTRR |
42 | #include <asm/mtrr.h> | |
43 | #endif | |
1da177e4 LT |
44 | |
45 | #include <video/permedia2.h> | |
46 | #include <video/cvisionppc.h> | |
47 | ||
48 | #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) | |
49 | #error "The endianness of the target host has not been defined." | |
50 | #endif | |
51 | ||
52 | #if !defined(CONFIG_PCI) | |
53 | #error "Only generic PCI cards supported." | |
54 | #endif | |
55 | ||
56 | #undef PM2FB_MASTER_DEBUG | |
57 | #ifdef PM2FB_MASTER_DEBUG | |
3843faa2 KH |
58 | #define DPRINTK(a, b...) \ |
59 | printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b) | |
1da177e4 | 60 | #else |
3843faa2 | 61 | #define DPRINTK(a, b...) |
1da177e4 LT |
62 | #endif |
63 | ||
91b3a6f4 KH |
64 | #define PM2_PIXMAP_SIZE (1600 * 4) |
65 | ||
1da177e4 | 66 | /* |
2f7bb99f | 67 | * Driver data |
1da177e4 | 68 | */ |
3843faa2 | 69 | static char *mode __devinitdata; |
1da177e4 LT |
70 | |
71 | /* | |
72 | * The XFree GLINT driver will (I think to implement hardware cursor | |
73 | * support on TVP4010 and similar where there is no RAMDAC - see | |
74 | * comment in set_video) always request +ve sync regardless of what | |
75 | * the mode requires. This screws me because I have a Sun | |
76 | * fixed-frequency monitor which absolutely has to have -ve sync. So | |
77 | * these flags allow the user to specify that requests for +ve sync | |
78 | * should be silently turned in -ve sync. | |
79 | */ | |
c16c556e DJ |
80 | static int lowhsync; |
81 | static int lowvsync; | |
d5383fcc KH |
82 | static int noaccel __devinitdata; |
83 | /* mtrr option */ | |
84 | #ifdef CONFIG_MTRR | |
85 | static int nomtrr __devinitdata; | |
86 | #endif | |
1da177e4 LT |
87 | |
88 | /* | |
89 | * The hardware state of the graphics card that isn't part of the | |
90 | * screeninfo. | |
91 | */ | |
92 | struct pm2fb_par | |
93 | { | |
94 | pm2type_t type; /* Board type */ | |
1da177e4 | 95 | unsigned char __iomem *v_regs;/* virtual address of p_regs */ |
2f7bb99f | 96 | u32 memclock; /* memclock */ |
1da177e4 LT |
97 | u32 video; /* video flags before blanking */ |
98 | u32 mem_config; /* MemConfig reg at probe */ | |
99 | u32 mem_control; /* MemControl reg at probe */ | |
100 | u32 boot_address; /* BootAddress reg at probe */ | |
2f7bb99f | 101 | u32 palette[16]; |
d5383fcc | 102 | int mtrr_handle; |
1da177e4 LT |
103 | }; |
104 | ||
105 | /* | |
106 | * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo | |
107 | * if we don't use modedb. | |
108 | */ | |
109 | static struct fb_fix_screeninfo pm2fb_fix __devinitdata = { | |
2f7bb99f | 110 | .id = "", |
1da177e4 LT |
111 | .type = FB_TYPE_PACKED_PIXELS, |
112 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
113 | .xpanstep = 1, | |
114 | .ypanstep = 1, | |
2f7bb99f | 115 | .ywrapstep = 0, |
87a7cc68 | 116 | .accel = FB_ACCEL_3DLABS_PERMEDIA2, |
1da177e4 LT |
117 | }; |
118 | ||
119 | /* | |
120 | * Default video mode. In case the modedb doesn't work. | |
121 | */ | |
122 | static struct fb_var_screeninfo pm2fb_var __devinitdata = { | |
123 | /* "640x480, 8 bpp @ 60 Hz */ | |
2f7bb99f KH |
124 | .xres = 640, |
125 | .yres = 480, | |
126 | .xres_virtual = 640, | |
127 | .yres_virtual = 480, | |
128 | .bits_per_pixel = 8, | |
129 | .red = {0, 8, 0}, | |
130 | .blue = {0, 8, 0}, | |
131 | .green = {0, 8, 0}, | |
132 | .activate = FB_ACTIVATE_NOW, | |
133 | .height = -1, | |
134 | .width = -1, | |
135 | .accel_flags = 0, | |
136 | .pixclock = 39721, | |
137 | .left_margin = 40, | |
138 | .right_margin = 24, | |
139 | .upper_margin = 32, | |
140 | .lower_margin = 11, | |
141 | .hsync_len = 96, | |
142 | .vsync_len = 2, | |
143 | .vmode = FB_VMODE_NONINTERLACED | |
1da177e4 LT |
144 | }; |
145 | ||
146 | /* | |
147 | * Utility functions | |
148 | */ | |
149 | ||
3843faa2 | 150 | static inline u32 pm2_RD(struct pm2fb_par *p, s32 off) |
1da177e4 | 151 | { |
45f169ec | 152 | return fb_readl(p->v_regs + off); |
1da177e4 LT |
153 | } |
154 | ||
3843faa2 | 155 | static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v) |
1da177e4 | 156 | { |
45f169ec | 157 | fb_writel(v, p->v_regs + off); |
1da177e4 LT |
158 | } |
159 | ||
3843faa2 | 160 | static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx) |
1da177e4 | 161 | { |
45f169ec | 162 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); |
1da177e4 | 163 | mb(); |
45f169ec KH |
164 | return pm2_RD(p, PM2R_RD_INDEXED_DATA); |
165 | } | |
166 | ||
3843faa2 | 167 | static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx) |
45f169ec KH |
168 | { |
169 | pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); | |
170 | mb(); | |
171 | return pm2_RD(p, PM2VR_RD_INDEXED_DATA); | |
1da177e4 LT |
172 | } |
173 | ||
3843faa2 | 174 | static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) |
1da177e4 | 175 | { |
45f169ec | 176 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); |
11d1a62c | 177 | wmb(); |
45f169ec | 178 | pm2_WR(p, PM2R_RD_INDEXED_DATA, v); |
11d1a62c | 179 | wmb(); |
1da177e4 LT |
180 | } |
181 | ||
3843faa2 | 182 | static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) |
1da177e4 LT |
183 | { |
184 | pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); | |
11d1a62c | 185 | wmb(); |
1da177e4 | 186 | pm2_WR(p, PM2VR_RD_INDEXED_DATA, v); |
11d1a62c | 187 | wmb(); |
1da177e4 LT |
188 | } |
189 | ||
190 | #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT | |
2f7bb99f | 191 | #define WAIT_FIFO(p, a) |
1da177e4 | 192 | #else |
3843faa2 | 193 | static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a) |
1da177e4 | 194 | { |
3843faa2 | 195 | while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a); |
1da177e4 LT |
196 | mb(); |
197 | } | |
198 | #endif | |
199 | ||
200 | /* | |
201 | * partial products for the supported horizontal resolutions. | |
202 | */ | |
2f7bb99f | 203 | #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0)) |
1da177e4 LT |
204 | static const struct { |
205 | u16 width; | |
206 | u16 pp; | |
207 | } pp_table[] = { | |
208 | { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) }, | |
209 | { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) }, | |
210 | { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) }, | |
211 | { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) }, | |
212 | { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) }, | |
213 | { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) }, | |
214 | { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) }, | |
215 | { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) }, | |
216 | { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) }, | |
217 | { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) }, | |
218 | { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) }, | |
219 | { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) }, | |
220 | { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) }, | |
221 | { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) }, | |
222 | { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) }, | |
223 | { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) }, | |
224 | { 0, 0 } }; | |
225 | ||
226 | static u32 partprod(u32 xres) | |
227 | { | |
228 | int i; | |
229 | ||
230 | for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++) | |
231 | ; | |
45f169ec | 232 | if (pp_table[i].width == 0) |
1da177e4 LT |
233 | DPRINTK("invalid width %u\n", xres); |
234 | return pp_table[i].pp; | |
235 | } | |
236 | ||
237 | static u32 to3264(u32 timing, int bpp, int is64) | |
238 | { | |
239 | switch (bpp) { | |
45f169ec KH |
240 | case 24: |
241 | timing *= 3; | |
1da177e4 | 242 | case 8: |
45f169ec | 243 | timing >>= 1; |
1da177e4 | 244 | case 16: |
45f169ec | 245 | timing >>= 1; |
1da177e4 | 246 | case 32: |
1da177e4 LT |
247 | break; |
248 | } | |
45f169ec KH |
249 | if (is64) |
250 | timing >>= 1; | |
1da177e4 LT |
251 | return timing; |
252 | } | |
253 | ||
3843faa2 KH |
254 | static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn, |
255 | unsigned char *pp) | |
1da177e4 LT |
256 | { |
257 | unsigned char m; | |
258 | unsigned char n; | |
259 | unsigned char p; | |
260 | u32 f; | |
261 | s32 curr; | |
262 | s32 delta = 100000; | |
263 | ||
264 | *mm = *nn = *pp = 0; | |
265 | for (n = 2; n < 15; n++) { | |
266 | for (m = 2; m; m++) { | |
267 | f = PM2_REFERENCE_CLOCK * m / n; | |
268 | if (f >= 150000 && f <= 300000) { | |
45f169ec KH |
269 | for (p = 0; p < 5; p++, f >>= 1) { |
270 | curr = (clk > f) ? clk - f : f - clk; | |
271 | if (curr < delta) { | |
272 | delta = curr; | |
273 | *mm = m; | |
274 | *nn = n; | |
275 | *pp = p; | |
1da177e4 LT |
276 | } |
277 | } | |
278 | } | |
279 | } | |
280 | } | |
281 | } | |
282 | ||
3843faa2 KH |
283 | static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn, |
284 | unsigned char *pp) | |
1da177e4 LT |
285 | { |
286 | unsigned char m; | |
287 | unsigned char n; | |
288 | unsigned char p; | |
289 | u32 f; | |
290 | s32 delta = 1000; | |
291 | ||
292 | *mm = *nn = *pp = 0; | |
45f169ec | 293 | for (m = 1; m < 128; m++) { |
d4a96b53 | 294 | for (n = 2 * m + 1; n; n++) { |
45f169ec KH |
295 | for (p = 0; p < 2; p++) { |
296 | f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m; | |
297 | if (clk > f - delta && clk < f + delta) { | |
298 | delta = (clk > f) ? clk - f : f - clk; | |
299 | *mm = m; | |
300 | *nn = n; | |
301 | *pp = p; | |
1da177e4 LT |
302 | } |
303 | } | |
304 | } | |
305 | } | |
306 | } | |
307 | ||
3843faa2 KH |
308 | static void clear_palette(struct pm2fb_par *p) |
309 | { | |
45f169ec | 310 | int i = 256; |
1da177e4 LT |
311 | |
312 | WAIT_FIFO(p, 1); | |
313 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0); | |
314 | wmb(); | |
315 | while (i--) { | |
316 | WAIT_FIFO(p, 3); | |
317 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
318 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
319 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
320 | } | |
321 | } | |
322 | ||
3843faa2 | 323 | static void reset_card(struct pm2fb_par *p) |
1da177e4 LT |
324 | { |
325 | if (p->type == PM2_TYPE_PERMEDIA2V) | |
326 | pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0); | |
327 | pm2_WR(p, PM2R_RESET_STATUS, 0); | |
328 | mb(); | |
329 | while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET) | |
330 | ; | |
331 | mb(); | |
332 | #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT | |
333 | DPRINTK("FIFO disconnect enabled\n"); | |
334 | pm2_WR(p, PM2R_FIFO_DISCON, 1); | |
335 | mb(); | |
336 | #endif | |
337 | ||
338 | /* Restore stashed memory config information from probe */ | |
339 | WAIT_FIFO(p, 3); | |
340 | pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control); | |
341 | pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address); | |
342 | wmb(); | |
343 | pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config); | |
344 | } | |
345 | ||
3843faa2 | 346 | static void reset_config(struct pm2fb_par *p) |
1da177e4 | 347 | { |
138a451c | 348 | WAIT_FIFO(p, 53); |
2f7bb99f | 349 | pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) & |
45f169ec | 350 | ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED)); |
1da177e4 LT |
351 | pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L)); |
352 | pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L)); | |
353 | pm2_WR(p, PM2R_FIFO_CONTROL, 0); | |
354 | pm2_WR(p, PM2R_APERTURE_ONE, 0); | |
355 | pm2_WR(p, PM2R_APERTURE_TWO, 0); | |
356 | pm2_WR(p, PM2R_RASTERIZER_MODE, 0); | |
357 | pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB); | |
358 | pm2_WR(p, PM2R_LB_READ_FORMAT, 0); | |
2f7bb99f | 359 | pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0); |
1da177e4 LT |
360 | pm2_WR(p, PM2R_LB_READ_MODE, 0); |
361 | pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0); | |
362 | pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0); | |
363 | pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0); | |
364 | pm2_WR(p, PM2R_FB_WINDOW_BASE, 0); | |
365 | pm2_WR(p, PM2R_LB_WINDOW_BASE, 0); | |
366 | pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L)); | |
367 | pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L)); | |
368 | pm2_WR(p, PM2R_FB_READ_PIXEL, 0); | |
369 | pm2_WR(p, PM2R_DITHER_MODE, 0); | |
370 | pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0); | |
371 | pm2_WR(p, PM2R_DEPTH_MODE, 0); | |
372 | pm2_WR(p, PM2R_STENCIL_MODE, 0); | |
373 | pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0); | |
374 | pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0); | |
375 | pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0); | |
376 | pm2_WR(p, PM2R_YUV_MODE, 0); | |
377 | pm2_WR(p, PM2R_COLOR_DDA_MODE, 0); | |
378 | pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0); | |
379 | pm2_WR(p, PM2R_FOG_MODE, 0); | |
380 | pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0); | |
381 | pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0); | |
382 | pm2_WR(p, PM2R_STATISTICS_MODE, 0); | |
383 | pm2_WR(p, PM2R_SCISSOR_MODE, 0); | |
384 | pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION); | |
138a451c | 385 | pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff); |
1da177e4 LT |
386 | switch (p->type) { |
387 | case PM2_TYPE_PERMEDIA2: | |
388 | pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */ | |
389 | pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0); | |
390 | pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8); | |
45f169ec KH |
391 | pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0); |
392 | pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0); | |
393 | pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0); | |
394 | pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0); | |
395 | pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0); | |
1da177e4 LT |
396 | break; |
397 | case PM2_TYPE_PERMEDIA2V: | |
398 | pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */ | |
399 | break; | |
400 | } | |
1da177e4 LT |
401 | } |
402 | ||
3843faa2 | 403 | static void set_aperture(struct pm2fb_par *p, u32 depth) |
1da177e4 LT |
404 | { |
405 | /* | |
406 | * The hardware is little-endian. When used in big-endian | |
407 | * hosts, the on-chip aperture settings are used where | |
408 | * possible to translate from host to card byte order. | |
409 | */ | |
45f169ec | 410 | WAIT_FIFO(p, 2); |
1da177e4 LT |
411 | #ifdef __LITTLE_ENDIAN |
412 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); | |
413 | #else | |
414 | switch (depth) { | |
415 | case 24: /* RGB->BGR */ | |
416 | /* | |
417 | * We can't use the aperture to translate host to | |
418 | * card byte order here, so we switch to BGR mode | |
419 | * in pm2fb_set_par(). | |
420 | */ | |
421 | case 8: /* B->B */ | |
422 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); | |
423 | break; | |
424 | case 16: /* HL->LH */ | |
425 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP); | |
426 | break; | |
427 | case 32: /* RGBA->ABGR */ | |
428 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP); | |
429 | break; | |
430 | } | |
431 | #endif | |
432 | ||
3843faa2 | 433 | /* We don't use aperture two, so this may be superflous */ |
1da177e4 LT |
434 | pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD); |
435 | } | |
436 | ||
3843faa2 | 437 | static void set_color(struct pm2fb_par *p, unsigned char regno, |
1da177e4 LT |
438 | unsigned char r, unsigned char g, unsigned char b) |
439 | { | |
440 | WAIT_FIFO(p, 4); | |
441 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno); | |
442 | wmb(); | |
443 | pm2_WR(p, PM2R_RD_PALETTE_DATA, r); | |
444 | wmb(); | |
445 | pm2_WR(p, PM2R_RD_PALETTE_DATA, g); | |
446 | wmb(); | |
447 | pm2_WR(p, PM2R_RD_PALETTE_DATA, b); | |
448 | } | |
449 | ||
3843faa2 | 450 | static void set_memclock(struct pm2fb_par *par, u32 clk) |
1da177e4 LT |
451 | { |
452 | int i; | |
453 | unsigned char m, n, p; | |
454 | ||
e5d809d7 KH |
455 | switch (par->type) { |
456 | case PM2_TYPE_PERMEDIA2V: | |
457 | pm2v_mnp(clk/2, &m, &n, &p); | |
45f169ec | 458 | WAIT_FIFO(par, 12); |
e5d809d7 KH |
459 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); |
460 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); | |
e5d809d7 KH |
461 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); |
462 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); | |
463 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); | |
e5d809d7 KH |
464 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); |
465 | rmb(); | |
45f169ec KH |
466 | for (i = 256; i; i--) |
467 | if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2) | |
468 | break; | |
e5d809d7 KH |
469 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); |
470 | break; | |
471 | case PM2_TYPE_PERMEDIA2: | |
472 | pm2_mnp(clk, &m, &n, &p); | |
473 | WAIT_FIFO(par, 10); | |
474 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); | |
e5d809d7 KH |
475 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); |
476 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); | |
e5d809d7 | 477 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); |
e5d809d7 KH |
478 | pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); |
479 | rmb(); | |
45f169ec KH |
480 | for (i = 256; i; i--) |
481 | if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) | |
482 | break; | |
e5d809d7 KH |
483 | break; |
484 | } | |
1da177e4 LT |
485 | } |
486 | ||
3843faa2 | 487 | static void set_pixclock(struct pm2fb_par *par, u32 clk) |
1da177e4 LT |
488 | { |
489 | int i; | |
490 | unsigned char m, n, p; | |
491 | ||
492 | switch (par->type) { | |
493 | case PM2_TYPE_PERMEDIA2: | |
494 | pm2_mnp(clk, &m, &n, &p); | |
45f169ec | 495 | WAIT_FIFO(par, 10); |
1da177e4 | 496 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0); |
1da177e4 LT |
497 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m); |
498 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n); | |
1da177e4 | 499 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p); |
1da177e4 LT |
500 | pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS); |
501 | rmb(); | |
45f169ec KH |
502 | for (i = 256; i; i--) |
503 | if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) | |
504 | break; | |
1da177e4 LT |
505 | break; |
506 | case PM2_TYPE_PERMEDIA2V: | |
507 | pm2v_mnp(clk/2, &m, &n, &p); | |
508 | WAIT_FIFO(par, 8); | |
509 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8); | |
510 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m); | |
511 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n); | |
512 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p); | |
513 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
514 | break; | |
515 | } | |
516 | } | |
517 | ||
3843faa2 KH |
518 | static void set_video(struct pm2fb_par *p, u32 video) |
519 | { | |
1da177e4 | 520 | u32 tmp; |
45f169ec | 521 | u32 vsync = video; |
1da177e4 LT |
522 | |
523 | DPRINTK("video = 0x%x\n", video); | |
2f7bb99f | 524 | |
1da177e4 LT |
525 | /* |
526 | * The hardware cursor needs +vsync to recognise vert retrace. | |
527 | * We may not be using the hardware cursor, but the X Glint | |
528 | * driver may well. So always set +hsync/+vsync and then set | |
529 | * the RAMDAC to invert the sync if necessary. | |
530 | */ | |
45f169ec KH |
531 | vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK); |
532 | vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH; | |
1da177e4 | 533 | |
138a451c | 534 | WAIT_FIFO(p, 3); |
1da177e4 LT |
535 | pm2_WR(p, PM2R_VIDEO_CONTROL, vsync); |
536 | ||
537 | switch (p->type) { | |
538 | case PM2_TYPE_PERMEDIA2: | |
539 | tmp = PM2F_RD_PALETTE_WIDTH_8; | |
540 | if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) | |
541 | tmp |= 4; /* invert hsync */ | |
542 | if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) | |
543 | tmp |= 8; /* invert vsync */ | |
544 | pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp); | |
545 | break; | |
546 | case PM2_TYPE_PERMEDIA2V: | |
547 | tmp = 0; | |
548 | if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) | |
549 | tmp |= 1; /* invert hsync */ | |
550 | if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) | |
551 | tmp |= 4; /* invert vsync */ | |
552 | pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp); | |
1da177e4 LT |
553 | break; |
554 | } | |
555 | } | |
556 | ||
557 | /* | |
2f7bb99f KH |
558 | * pm2fb_check_var - Optional function. Validates a var passed in. |
559 | * @var: frame buffer variable screen structure | |
560 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
561 | * |
562 | * Checks to see if the hardware supports the state requested by | |
563 | * var passed in. | |
564 | * | |
565 | * Returns negative errno on error, or zero on success. | |
566 | */ | |
567 | static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
568 | { | |
569 | u32 lpitch; | |
570 | ||
571 | if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && | |
572 | var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { | |
573 | DPRINTK("depth not supported: %u\n", var->bits_per_pixel); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | if (var->xres != var->xres_virtual) { | |
3843faa2 KH |
578 | DPRINTK("virtual x resolution != " |
579 | "physical x resolution not supported\n"); | |
1da177e4 LT |
580 | return -EINVAL; |
581 | } | |
582 | ||
583 | if (var->yres > var->yres_virtual) { | |
3843faa2 KH |
584 | DPRINTK("virtual y resolution < " |
585 | "physical y resolution not possible\n"); | |
1da177e4 LT |
586 | return -EINVAL; |
587 | } | |
588 | ||
589 | if (var->xoffset) { | |
590 | DPRINTK("xoffset not supported\n"); | |
591 | return -EINVAL; | |
592 | } | |
593 | ||
594 | if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { | |
595 | DPRINTK("interlace not supported\n"); | |
596 | return -EINVAL; | |
597 | } | |
598 | ||
599 | var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ | |
45f169ec | 600 | lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); |
2f7bb99f | 601 | |
1da177e4 LT |
602 | if (var->xres < 320 || var->xres > 1600) { |
603 | DPRINTK("width not supported: %u\n", var->xres); | |
604 | return -EINVAL; | |
605 | } | |
2f7bb99f | 606 | |
1da177e4 LT |
607 | if (var->yres < 200 || var->yres > 1200) { |
608 | DPRINTK("height not supported: %u\n", var->yres); | |
609 | return -EINVAL; | |
610 | } | |
2f7bb99f | 611 | |
1da177e4 LT |
612 | if (lpitch * var->yres_virtual > info->fix.smem_len) { |
613 | DPRINTK("no memory for screen (%ux%ux%u)\n", | |
614 | var->xres, var->yres_virtual, var->bits_per_pixel); | |
615 | return -EINVAL; | |
616 | } | |
2f7bb99f | 617 | |
1da177e4 | 618 | if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) { |
3843faa2 KH |
619 | DPRINTK("pixclock too high (%ldKHz)\n", |
620 | PICOS2KHZ(var->pixclock)); | |
1da177e4 LT |
621 | return -EINVAL; |
622 | } | |
623 | ||
76c7d3ff | 624 | var->transp.offset = 0; |
625 | var->transp.length = 0; | |
3843faa2 | 626 | switch (var->bits_per_pixel) { |
1da177e4 | 627 | case 8: |
3843faa2 KH |
628 | var->red.length = 8; |
629 | var->green.length = 8; | |
630 | var->blue.length = 8; | |
1da177e4 LT |
631 | break; |
632 | case 16: | |
633 | var->red.offset = 11; | |
634 | var->red.length = 5; | |
635 | var->green.offset = 5; | |
636 | var->green.length = 6; | |
637 | var->blue.offset = 0; | |
638 | var->blue.length = 5; | |
639 | break; | |
640 | case 32: | |
641 | var->transp.offset = 24; | |
642 | var->transp.length = 8; | |
643 | var->red.offset = 16; | |
644 | var->green.offset = 8; | |
645 | var->blue.offset = 0; | |
3843faa2 KH |
646 | var->red.length = 8; |
647 | var->green.length = 8; | |
648 | var->blue.length = 8; | |
1da177e4 LT |
649 | break; |
650 | case 24: | |
651 | #ifdef __BIG_ENDIAN | |
652 | var->red.offset = 0; | |
653 | var->blue.offset = 16; | |
654 | #else | |
655 | var->red.offset = 16; | |
656 | var->blue.offset = 0; | |
657 | #endif | |
658 | var->green.offset = 8; | |
3843faa2 KH |
659 | var->red.length = 8; |
660 | var->green.length = 8; | |
661 | var->blue.length = 8; | |
1da177e4 LT |
662 | break; |
663 | } | |
3843faa2 KH |
664 | var->height = -1; |
665 | var->width = -1; | |
2f7bb99f | 666 | |
1da177e4 | 667 | var->accel_flags = 0; /* Can't mmap if this is on */ |
2f7bb99f | 668 | |
1da177e4 LT |
669 | DPRINTK("Checking graphics mode at %dx%d depth %d\n", |
670 | var->xres, var->yres, var->bits_per_pixel); | |
671 | return 0; | |
672 | } | |
673 | ||
674 | /** | |
2f7bb99f KH |
675 | * pm2fb_set_par - Alters the hardware state. |
676 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
677 | * |
678 | * Using the fb_var_screeninfo in fb_info we set the resolution of the | |
679 | * this particular framebuffer. | |
680 | */ | |
681 | static int pm2fb_set_par(struct fb_info *info) | |
682 | { | |
6772a2ee | 683 | struct pm2fb_par *par = info->par; |
1da177e4 | 684 | u32 pixclock; |
45f169ec KH |
685 | u32 width = (info->var.xres_virtual + 7) & ~7; |
686 | u32 height = info->var.yres_virtual; | |
687 | u32 depth = (info->var.bits_per_pixel + 7) & ~7; | |
1da177e4 LT |
688 | u32 hsstart, hsend, hbend, htotal; |
689 | u32 vsstart, vsend, vbend, vtotal; | |
690 | u32 stride; | |
691 | u32 base; | |
692 | u32 video = 0; | |
693 | u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE; | |
694 | u32 txtmap = 0; | |
695 | u32 pixsize = 0; | |
696 | u32 clrformat = 0; | |
138a451c | 697 | u32 misc = 1; /* 8-bit DAC */ |
45f169ec | 698 | u32 xres = (info->var.xres + 31) & ~31; |
1da177e4 LT |
699 | int data64; |
700 | ||
701 | reset_card(par); | |
702 | reset_config(par); | |
703 | clear_palette(par); | |
45f169ec | 704 | if (par->memclock) |
1da177e4 | 705 | set_memclock(par, par->memclock); |
2f7bb99f | 706 | |
1da177e4 LT |
707 | depth = (depth > 32) ? 32 : depth; |
708 | data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V; | |
709 | ||
1da177e4 LT |
710 | pixclock = PICOS2KHZ(info->var.pixclock); |
711 | if (pixclock > PM2_MAX_PIXCLOCK) { | |
712 | DPRINTK("pixclock too high (%uKHz)\n", pixclock); | |
713 | return -EINVAL; | |
714 | } | |
2f7bb99f | 715 | |
1da177e4 LT |
716 | hsstart = to3264(info->var.right_margin, depth, data64); |
717 | hsend = hsstart + to3264(info->var.hsync_len, depth, data64); | |
718 | hbend = hsend + to3264(info->var.left_margin, depth, data64); | |
719 | htotal = to3264(xres, depth, data64) + hbend - 1; | |
720 | vsstart = (info->var.lower_margin) | |
721 | ? info->var.lower_margin - 1 | |
722 | : 0; /* FIXME! */ | |
723 | vsend = info->var.lower_margin + info->var.vsync_len - 1; | |
3843faa2 KH |
724 | vbend = info->var.lower_margin + info->var.vsync_len + |
725 | info->var.upper_margin; | |
1da177e4 LT |
726 | vtotal = info->var.yres + vbend - 1; |
727 | stride = to3264(width, depth, 1); | |
728 | base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1); | |
729 | if (data64) | |
730 | video |= PM2F_DATA_64_ENABLE; | |
2f7bb99f | 731 | |
1da177e4 LT |
732 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) { |
733 | if (lowhsync) { | |
734 | DPRINTK("ignoring +hsync, using -hsync.\n"); | |
735 | video |= PM2F_HSYNC_ACT_LOW; | |
736 | } else | |
737 | video |= PM2F_HSYNC_ACT_HIGH; | |
3843faa2 | 738 | } else |
1da177e4 | 739 | video |= PM2F_HSYNC_ACT_LOW; |
3843faa2 | 740 | |
1da177e4 LT |
741 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) { |
742 | if (lowvsync) { | |
743 | DPRINTK("ignoring +vsync, using -vsync.\n"); | |
744 | video |= PM2F_VSYNC_ACT_LOW; | |
745 | } else | |
746 | video |= PM2F_VSYNC_ACT_HIGH; | |
3843faa2 | 747 | } else |
1da177e4 | 748 | video |= PM2F_VSYNC_ACT_LOW; |
3843faa2 | 749 | |
45f169ec | 750 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { |
1da177e4 LT |
751 | DPRINTK("interlaced not supported\n"); |
752 | return -EINVAL; | |
753 | } | |
45f169ec | 754 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) |
1da177e4 | 755 | video |= PM2F_LINE_DOUBLE; |
45f169ec | 756 | if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) |
1da177e4 LT |
757 | video |= PM2F_VIDEO_ENABLE; |
758 | par->video = video; | |
759 | ||
760 | info->fix.visual = | |
761 | (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
762 | info->fix.line_length = info->var.xres * depth / 8; | |
763 | info->cmap.len = 256; | |
764 | ||
765 | /* | |
766 | * Settings calculated. Now write them out. | |
767 | */ | |
768 | if (par->type == PM2_TYPE_PERMEDIA2V) { | |
769 | WAIT_FIFO(par, 1); | |
770 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
771 | } | |
2f7bb99f | 772 | |
1da177e4 | 773 | set_aperture(par, depth); |
2f7bb99f | 774 | |
1da177e4 LT |
775 | mb(); |
776 | WAIT_FIFO(par, 19); | |
1da177e4 LT |
777 | switch (depth) { |
778 | case 8: | |
779 | pm2_WR(par, PM2R_FB_READ_PIXEL, 0); | |
138a451c | 780 | clrformat = 0x2e; |
1da177e4 LT |
781 | break; |
782 | case 16: | |
783 | pm2_WR(par, PM2R_FB_READ_PIXEL, 1); | |
784 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565; | |
785 | txtmap = PM2F_TEXTEL_SIZE_16; | |
786 | pixsize = 1; | |
787 | clrformat = 0x70; | |
138a451c | 788 | misc |= 8; |
1da177e4 LT |
789 | break; |
790 | case 32: | |
791 | pm2_WR(par, PM2R_FB_READ_PIXEL, 2); | |
792 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888; | |
793 | txtmap = PM2F_TEXTEL_SIZE_32; | |
794 | pixsize = 2; | |
795 | clrformat = 0x20; | |
138a451c | 796 | misc |= 8; |
1da177e4 LT |
797 | break; |
798 | case 24: | |
799 | pm2_WR(par, PM2R_FB_READ_PIXEL, 4); | |
800 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888; | |
801 | txtmap = PM2F_TEXTEL_SIZE_24; | |
802 | pixsize = 4; | |
803 | clrformat = 0x20; | |
138a451c | 804 | misc |= 8; |
1da177e4 LT |
805 | break; |
806 | } | |
807 | pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE); | |
808 | pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); | |
809 | pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres)); | |
810 | pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres)); | |
811 | pm2_WR(par, PM2R_H_TOTAL, htotal); | |
812 | pm2_WR(par, PM2R_HS_START, hsstart); | |
813 | pm2_WR(par, PM2R_HS_END, hsend); | |
814 | pm2_WR(par, PM2R_HG_END, hbend); | |
815 | pm2_WR(par, PM2R_HB_END, hbend); | |
816 | pm2_WR(par, PM2R_V_TOTAL, vtotal); | |
817 | pm2_WR(par, PM2R_VS_START, vsstart); | |
818 | pm2_WR(par, PM2R_VS_END, vsend); | |
819 | pm2_WR(par, PM2R_VB_END, vbend); | |
820 | pm2_WR(par, PM2R_SCREEN_STRIDE, stride); | |
821 | wmb(); | |
822 | pm2_WR(par, PM2R_WINDOW_ORIGIN, 0); | |
823 | pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width); | |
824 | pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE); | |
825 | wmb(); | |
826 | pm2_WR(par, PM2R_SCREEN_BASE, base); | |
827 | wmb(); | |
828 | set_video(par, video); | |
138a451c | 829 | WAIT_FIFO(par, 10); |
1da177e4 LT |
830 | switch (par->type) { |
831 | case PM2_TYPE_PERMEDIA2: | |
832 | pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode); | |
45f169ec | 833 | pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL, |
3843faa2 | 834 | (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF); |
1da177e4 LT |
835 | break; |
836 | case PM2_TYPE_PERMEDIA2V: | |
138a451c | 837 | pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0); |
1da177e4 LT |
838 | pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize); |
839 | pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat); | |
138a451c KH |
840 | pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc); |
841 | pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0); | |
1da177e4 LT |
842 | break; |
843 | } | |
844 | set_pixclock(par, pixclock); | |
845 | DPRINTK("Setting graphics mode at %dx%d depth %d\n", | |
846 | info->var.xres, info->var.yres, info->var.bits_per_pixel); | |
2f7bb99f | 847 | return 0; |
1da177e4 LT |
848 | } |
849 | ||
850 | /** | |
2f7bb99f KH |
851 | * pm2fb_setcolreg - Sets a color register. |
852 | * @regno: boolean, 0 copy local, 1 get_user() function | |
853 | * @red: frame buffer colormap structure | |
854 | * @green: The green value which can be up to 16 bits wide | |
1da177e4 | 855 | * @blue: The blue value which can be up to 16 bits wide. |
2f7bb99f KH |
856 | * @transp: If supported the alpha value which can be up to 16 bits wide. |
857 | * @info: frame buffer info structure | |
858 | * | |
859 | * Set a single color register. The values supplied have a 16 bit | |
860 | * magnitude which needs to be scaled in this function for the hardware. | |
1da177e4 | 861 | * Pretty much a direct lift from tdfxfb.c. |
2f7bb99f | 862 | * |
1da177e4 LT |
863 | * Returns negative errno on error, or zero on success. |
864 | */ | |
865 | static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
866 | unsigned blue, unsigned transp, | |
867 | struct fb_info *info) | |
868 | { | |
6772a2ee | 869 | struct pm2fb_par *par = info->par; |
1da177e4 LT |
870 | |
871 | if (regno >= info->cmap.len) /* no. of hw registers */ | |
138a451c | 872 | return -EINVAL; |
1da177e4 LT |
873 | /* |
874 | * Program hardware... do anything you want with transp | |
875 | */ | |
876 | ||
877 | /* grayscale works only partially under directcolor */ | |
3843faa2 KH |
878 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ |
879 | if (info->var.grayscale) | |
1da177e4 | 880 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; |
1da177e4 LT |
881 | |
882 | /* Directcolor: | |
883 | * var->{color}.offset contains start of bitfield | |
884 | * var->{color}.length contains length of bitfield | |
885 | * {hardwarespecific} contains width of DAC | |
886 | * cmap[X] is programmed to | |
887 | * (X << red.offset) | (X << green.offset) | (X << blue.offset) | |
888 | * RAMDAC[X] is programmed to (red, green, blue) | |
889 | * | |
890 | * Pseudocolor: | |
891 | * uses offset = 0 && length = DAC register width. | |
892 | * var->{color}.offset is 0 | |
893 | * var->{color}.length contains widht of DAC | |
894 | * cmap is not used | |
895 | * DAC[X] is programmed to (red, green, blue) | |
896 | * Truecolor: | |
897 | * does not use RAMDAC (usually has 3 of them). | |
898 | * var->{color}.offset contains start of bitfield | |
899 | * var->{color}.length contains length of bitfield | |
900 | * cmap is programmed to | |
901 | * (red << red.offset) | (green << green.offset) | | |
902 | * (blue << blue.offset) | (transp << transp.offset) | |
903 | * RAMDAC does not exist | |
904 | */ | |
2f7bb99f | 905 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16) |
1da177e4 LT |
906 | switch (info->fix.visual) { |
907 | case FB_VISUAL_TRUECOLOR: | |
908 | case FB_VISUAL_PSEUDOCOLOR: | |
909 | red = CNVT_TOHW(red, info->var.red.length); | |
910 | green = CNVT_TOHW(green, info->var.green.length); | |
911 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
912 | transp = CNVT_TOHW(transp, info->var.transp.length); | |
913 | break; | |
914 | case FB_VISUAL_DIRECTCOLOR: | |
2f7bb99f KH |
915 | /* example here assumes 8 bit DAC. Might be different |
916 | * for your hardware */ | |
917 | red = CNVT_TOHW(red, 8); | |
1da177e4 LT |
918 | green = CNVT_TOHW(green, 8); |
919 | blue = CNVT_TOHW(blue, 8); | |
920 | /* hey, there is bug in transp handling... */ | |
921 | transp = CNVT_TOHW(transp, 8); | |
922 | break; | |
923 | } | |
924 | #undef CNVT_TOHW | |
925 | /* Truecolor has hardware independent palette */ | |
926 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
927 | u32 v; | |
928 | ||
929 | if (regno >= 16) | |
138a451c | 930 | return -EINVAL; |
1da177e4 LT |
931 | |
932 | v = (red << info->var.red.offset) | | |
933 | (green << info->var.green.offset) | | |
934 | (blue << info->var.blue.offset) | | |
935 | (transp << info->var.transp.offset); | |
936 | ||
937 | switch (info->var.bits_per_pixel) { | |
938 | case 8: | |
2f7bb99f KH |
939 | break; |
940 | case 16: | |
1da177e4 | 941 | case 24: |
2f7bb99f KH |
942 | case 32: |
943 | par->palette[regno] = v; | |
1da177e4 LT |
944 | break; |
945 | } | |
946 | return 0; | |
3843faa2 | 947 | } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) |
1da177e4 LT |
948 | set_color(par, regno, red, green, blue); |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | /** | |
2f7bb99f KH |
954 | * pm2fb_pan_display - Pans the display. |
955 | * @var: frame buffer variable screen structure | |
956 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
957 | * |
958 | * Pan (or wrap, depending on the `vmode' field) the display using the | |
2f7bb99f KH |
959 | * `xoffset' and `yoffset' fields of the `var' structure. |
960 | * If the values don't fit, return -EINVAL. | |
1da177e4 | 961 | * |
2f7bb99f | 962 | * Returns negative errno on error, or zero on success. |
1da177e4 LT |
963 | * |
964 | */ | |
965 | static int pm2fb_pan_display(struct fb_var_screeninfo *var, | |
966 | struct fb_info *info) | |
967 | { | |
6772a2ee | 968 | struct pm2fb_par *p = info->par; |
1da177e4 | 969 | u32 base; |
45f169ec KH |
970 | u32 depth = (var->bits_per_pixel + 7) & ~7; |
971 | u32 xres = (var->xres + 31) & ~31; | |
1da177e4 | 972 | |
1da177e4 LT |
973 | depth = (depth > 32) ? 32 : depth; |
974 | base = to3264(var->yoffset * xres + var->xoffset, depth, 1); | |
975 | WAIT_FIFO(p, 1); | |
2f7bb99f | 976 | pm2_WR(p, PM2R_SCREEN_BASE, base); |
1da177e4 LT |
977 | return 0; |
978 | } | |
979 | ||
980 | /** | |
2f7bb99f KH |
981 | * pm2fb_blank - Blanks the display. |
982 | * @blank_mode: the blank mode we want. | |
983 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 | 984 | * |
2f7bb99f KH |
985 | * Blank the screen if blank_mode != 0, else unblank. Return 0 if |
986 | * blanking succeeded, != 0 if un-/blanking failed due to e.g. a | |
987 | * video mode which doesn't support it. Implements VESA suspend | |
988 | * and powerdown modes on hardware that supports disabling hsync/vsync: | |
989 | * blank_mode == 2: suspend vsync | |
990 | * blank_mode == 3: suspend hsync | |
991 | * blank_mode == 4: powerdown | |
1da177e4 | 992 | * |
2f7bb99f | 993 | * Returns negative errno on error, or zero on success. |
1da177e4 LT |
994 | * |
995 | */ | |
996 | static int pm2fb_blank(int blank_mode, struct fb_info *info) | |
997 | { | |
6772a2ee | 998 | struct pm2fb_par *par = info->par; |
1da177e4 LT |
999 | u32 video = par->video; |
1000 | ||
1001 | DPRINTK("blank_mode %d\n", blank_mode); | |
1002 | ||
1003 | switch (blank_mode) { | |
1004 | case FB_BLANK_UNBLANK: | |
1005 | /* Screen: On */ | |
1006 | video |= PM2F_VIDEO_ENABLE; | |
1007 | break; | |
1008 | case FB_BLANK_NORMAL: | |
1009 | /* Screen: Off */ | |
1010 | video &= ~PM2F_VIDEO_ENABLE; | |
1011 | break; | |
1012 | case FB_BLANK_VSYNC_SUSPEND: | |
1013 | /* VSync: Off */ | |
45f169ec | 1014 | video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1015 | break; |
1016 | case FB_BLANK_HSYNC_SUSPEND: | |
1017 | /* HSync: Off */ | |
45f169ec | 1018 | video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1019 | break; |
1020 | case FB_BLANK_POWERDOWN: | |
1021 | /* HSync: Off, VSync: Off */ | |
3843faa2 | 1022 | video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1023 | break; |
1024 | } | |
1025 | set_video(par, video); | |
1026 | return 0; | |
1027 | } | |
1028 | ||
03b9ae4b AD |
1029 | static int pm2fb_sync(struct fb_info *info) |
1030 | { | |
1031 | struct pm2fb_par *par = info->par; | |
1032 | ||
1033 | WAIT_FIFO(par, 1); | |
1034 | pm2_WR(par, PM2R_SYNC, 0); | |
1035 | mb(); | |
1036 | do { | |
1037 | while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0) | |
1038 | udelay(10); | |
1039 | rmb(); | |
1040 | } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC)); | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
3843faa2 | 1045 | static void pm2fb_fillrect(struct fb_info *info, |
87a7cc68 KH |
1046 | const struct fb_fillrect *region) |
1047 | { | |
3843faa2 | 1048 | struct pm2fb_par *par = info->par; |
87a7cc68 KH |
1049 | struct fb_fillrect modded; |
1050 | int vxres, vyres; | |
1051 | u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? | |
3843faa2 | 1052 | ((u32 *)info->pseudo_palette)[region->color] : region->color; |
87a7cc68 KH |
1053 | |
1054 | if (info->state != FBINFO_STATE_RUNNING) | |
1055 | return; | |
1056 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || | |
1057 | region->rop != ROP_COPY ) { | |
1058 | cfb_fillrect(info, region); | |
1059 | return; | |
1060 | } | |
1061 | ||
1062 | vxres = info->var.xres_virtual; | |
1063 | vyres = info->var.yres_virtual; | |
1064 | ||
1065 | memcpy(&modded, region, sizeof(struct fb_fillrect)); | |
1066 | ||
45f169ec KH |
1067 | if (!modded.width || !modded.height || |
1068 | modded.dx >= vxres || modded.dy >= vyres) | |
87a7cc68 KH |
1069 | return; |
1070 | ||
45f169ec | 1071 | if (modded.dx + modded.width > vxres) |
87a7cc68 | 1072 | modded.width = vxres - modded.dx; |
45f169ec | 1073 | if (modded.dy + modded.height > vyres) |
87a7cc68 KH |
1074 | modded.height = vyres - modded.dy; |
1075 | ||
45f169ec | 1076 | if (info->var.bits_per_pixel == 8) |
87a7cc68 | 1077 | color |= color << 8; |
45f169ec | 1078 | if (info->var.bits_per_pixel <= 16) |
87a7cc68 KH |
1079 | color |= color << 16; |
1080 | ||
45f169ec KH |
1081 | WAIT_FIFO(par, 3); |
1082 | pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE); | |
1083 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); | |
1084 | pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); | |
1085 | if (info->var.bits_per_pixel != 24) { | |
1086 | WAIT_FIFO(par, 2); | |
1087 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, color); | |
1088 | wmb(); | |
1089 | pm2_WR(par, PM2R_RENDER, | |
1090 | PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL); | |
1091 | } else { | |
30dcc909 KH |
1092 | WAIT_FIFO(par, 4); |
1093 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); | |
1094 | pm2_WR(par, PM2R_CONSTANT_COLOR, color); | |
1095 | wmb(); | |
1096 | pm2_WR(par, PM2R_RENDER, | |
3843faa2 KH |
1097 | PM2F_RENDER_RECTANGLE | |
1098 | PM2F_INCREASE_X | PM2F_INCREASE_Y ); | |
30dcc909 | 1099 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); |
45f169ec | 1100 | } |
87a7cc68 KH |
1101 | } |
1102 | ||
1103 | static void pm2fb_copyarea(struct fb_info *info, | |
1104 | const struct fb_copyarea *area) | |
1105 | { | |
45f169ec | 1106 | struct pm2fb_par *par = info->par; |
87a7cc68 KH |
1107 | struct fb_copyarea modded; |
1108 | u32 vxres, vyres; | |
1109 | ||
1110 | if (info->state != FBINFO_STATE_RUNNING) | |
1111 | return; | |
1112 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | |
1113 | cfb_copyarea(info, area); | |
1114 | return; | |
1115 | } | |
1116 | ||
1117 | memcpy(&modded, area, sizeof(struct fb_copyarea)); | |
1118 | ||
1119 | vxres = info->var.xres_virtual; | |
1120 | vyres = info->var.yres_virtual; | |
1121 | ||
45f169ec KH |
1122 | if (!modded.width || !modded.height || |
1123 | modded.sx >= vxres || modded.sy >= vyres || | |
1124 | modded.dx >= vxres || modded.dy >= vyres) | |
87a7cc68 KH |
1125 | return; |
1126 | ||
45f169ec | 1127 | if (modded.sx + modded.width > vxres) |
87a7cc68 | 1128 | modded.width = vxres - modded.sx; |
45f169ec | 1129 | if (modded.dx + modded.width > vxres) |
87a7cc68 | 1130 | modded.width = vxres - modded.dx; |
45f169ec | 1131 | if (modded.sy + modded.height > vyres) |
87a7cc68 | 1132 | modded.height = vyres - modded.sy; |
45f169ec | 1133 | if (modded.dy + modded.height > vyres) |
87a7cc68 KH |
1134 | modded.height = vyres - modded.dy; |
1135 | ||
45f169ec KH |
1136 | WAIT_FIFO(par, 5); |
1137 | pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | | |
1138 | PM2F_CONFIG_FB_READ_SOURCE_ENABLE); | |
1139 | pm2_WR(par, PM2R_FB_SOURCE_DELTA, | |
3843faa2 KH |
1140 | ((modded.sy - modded.dy) & 0xfff) << 16 | |
1141 | ((modded.sx - modded.dx) & 0xfff)); | |
45f169ec KH |
1142 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); |
1143 | pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); | |
1144 | wmb(); | |
1145 | pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE | | |
3843faa2 KH |
1146 | (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) | |
1147 | (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0)); | |
87a7cc68 KH |
1148 | } |
1149 | ||
91b3a6f4 KH |
1150 | static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image) |
1151 | { | |
1152 | struct pm2fb_par *par = info->par; | |
1153 | u32 height = image->height; | |
1154 | u32 fgx, bgx; | |
3843faa2 | 1155 | const u32 *src = (const u32 *)image->data; |
91b3a6f4 KH |
1156 | u32 xres = (info->var.xres + 31) & ~31; |
1157 | ||
1158 | if (info->state != FBINFO_STATE_RUNNING) | |
1159 | return; | |
1160 | if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) { | |
1161 | cfb_imageblit(info, image); | |
1162 | return; | |
1163 | } | |
1164 | switch (info->fix.visual) { | |
45f169ec KH |
1165 | case FB_VISUAL_PSEUDOCOLOR: |
1166 | fgx = image->fg_color; | |
1167 | bgx = image->bg_color; | |
1168 | break; | |
1169 | case FB_VISUAL_TRUECOLOR: | |
1170 | default: | |
1171 | fgx = par->palette[image->fg_color]; | |
1172 | bgx = par->palette[image->bg_color]; | |
1173 | break; | |
91b3a6f4 KH |
1174 | } |
1175 | if (info->var.bits_per_pixel == 8) { | |
1176 | fgx |= fgx << 8; | |
1177 | bgx |= bgx << 8; | |
1178 | } | |
1179 | if (info->var.bits_per_pixel <= 16) { | |
1180 | fgx |= fgx << 16; | |
1181 | bgx |= bgx << 16; | |
1182 | } | |
1183 | ||
1184 | WAIT_FIFO(par, 13); | |
1185 | pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); | |
1186 | pm2_WR(par, PM2R_SCISSOR_MIN_XY, | |
1187 | ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); | |
1188 | pm2_WR(par, PM2R_SCISSOR_MAX_XY, | |
1189 | (((image->dy + image->height) & 0x0fff) << 16) | | |
1190 | ((image->dx + image->width) & 0x0fff)); | |
1191 | pm2_WR(par, PM2R_SCISSOR_MODE, 1); | |
1192 | /* GXcopy & UNIT_ENABLE */ | |
45f169ec | 1193 | pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1); |
91b3a6f4 KH |
1194 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, |
1195 | ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); | |
1196 | pm2_WR(par, PM2R_RECTANGLE_SIZE, | |
1197 | ((image->height & 0x0fff) << 16) | | |
1198 | ((image->width) & 0x0fff)); | |
1199 | if (info->var.bits_per_pixel == 24) { | |
1200 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); | |
1201 | /* clear area */ | |
1202 | pm2_WR(par, PM2R_CONSTANT_COLOR, bgx); | |
1203 | pm2_WR(par, PM2R_RENDER, | |
1204 | PM2F_RENDER_RECTANGLE | | |
45f169ec | 1205 | PM2F_INCREASE_X | PM2F_INCREASE_Y); |
91b3a6f4 KH |
1206 | /* BitMapPackEachScanline & invert bits and byte order*/ |
1207 | /* force background */ | |
45f169ec | 1208 | pm2_WR(par, PM2R_RASTERIZER_MODE, (1 << 9) | 1 | (3 << 7)); |
91b3a6f4 KH |
1209 | pm2_WR(par, PM2R_CONSTANT_COLOR, fgx); |
1210 | pm2_WR(par, PM2R_RENDER, | |
1211 | PM2F_RENDER_RECTANGLE | | |
1212 | PM2F_INCREASE_X | PM2F_INCREASE_Y | | |
1213 | PM2F_RENDER_SYNC_ON_BIT_MASK); | |
1214 | } else { | |
1215 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); | |
1216 | /* clear area */ | |
1217 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx); | |
1218 | pm2_WR(par, PM2R_RENDER, | |
1219 | PM2F_RENDER_RECTANGLE | | |
1220 | PM2F_RENDER_FASTFILL | | |
45f169ec | 1221 | PM2F_INCREASE_X | PM2F_INCREASE_Y); |
91b3a6f4 | 1222 | /* invert bits and byte order*/ |
45f169ec | 1223 | pm2_WR(par, PM2R_RASTERIZER_MODE, 1 | (3 << 7)); |
91b3a6f4 KH |
1224 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx); |
1225 | pm2_WR(par, PM2R_RENDER, | |
1226 | PM2F_RENDER_RECTANGLE | | |
1227 | PM2F_INCREASE_X | PM2F_INCREASE_Y | | |
1228 | PM2F_RENDER_FASTFILL | | |
1229 | PM2F_RENDER_SYNC_ON_BIT_MASK); | |
1230 | } | |
1231 | ||
1232 | while (height--) { | |
1233 | int width = ((image->width + 7) >> 3) | |
1234 | + info->pixmap.scan_align - 1; | |
1235 | width >>= 2; | |
1236 | WAIT_FIFO(par, width); | |
1237 | while (width--) { | |
1238 | pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src); | |
1239 | src++; | |
1240 | } | |
1241 | } | |
1242 | WAIT_FIFO(par, 3); | |
1243 | pm2_WR(par, PM2R_RASTERIZER_MODE, 0); | |
1244 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); | |
1245 | pm2_WR(par, PM2R_SCISSOR_MODE, 0); | |
1246 | } | |
1247 | ||
1da177e4 LT |
1248 | /* ------------ Hardware Independent Functions ------------ */ |
1249 | ||
1250 | /* | |
1251 | * Frame buffer operations | |
1252 | */ | |
1253 | ||
1254 | static struct fb_ops pm2fb_ops = { | |
1255 | .owner = THIS_MODULE, | |
1256 | .fb_check_var = pm2fb_check_var, | |
1257 | .fb_set_par = pm2fb_set_par, | |
1258 | .fb_setcolreg = pm2fb_setcolreg, | |
1259 | .fb_blank = pm2fb_blank, | |
1260 | .fb_pan_display = pm2fb_pan_display, | |
87a7cc68 KH |
1261 | .fb_fillrect = pm2fb_fillrect, |
1262 | .fb_copyarea = pm2fb_copyarea, | |
91b3a6f4 | 1263 | .fb_imageblit = pm2fb_imageblit, |
03b9ae4b | 1264 | .fb_sync = pm2fb_sync, |
1da177e4 LT |
1265 | }; |
1266 | ||
1267 | /* | |
1268 | * PCI stuff | |
1269 | */ | |
1270 | ||
1271 | ||
1272 | /** | |
1273 | * Device initialisation | |
1274 | * | |
1275 | * Initialise and allocate resource for PCI device. | |
1276 | * | |
1277 | * @param pdev PCI device. | |
1278 | * @param id PCI device ID. | |
1279 | */ | |
1280 | static int __devinit pm2fb_probe(struct pci_dev *pdev, | |
1281 | const struct pci_device_id *id) | |
1282 | { | |
1283 | struct pm2fb_par *default_par; | |
1284 | struct fb_info *info; | |
3843faa2 KH |
1285 | int err; |
1286 | int retval = -ENXIO; | |
1da177e4 LT |
1287 | |
1288 | err = pci_enable_device(pdev); | |
45f169ec | 1289 | if (err) { |
1da177e4 LT |
1290 | printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err); |
1291 | return err; | |
1292 | } | |
1293 | ||
6772a2ee | 1294 | info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev); |
45f169ec | 1295 | if (!info) |
1da177e4 | 1296 | return -ENOMEM; |
6772a2ee | 1297 | default_par = info->par; |
1da177e4 LT |
1298 | |
1299 | switch (pdev->device) { | |
1300 | case PCI_DEVICE_ID_TI_TVP4020: | |
1301 | strcpy(pm2fb_fix.id, "TVP4020"); | |
1302 | default_par->type = PM2_TYPE_PERMEDIA2; | |
1303 | break; | |
1304 | case PCI_DEVICE_ID_3DLABS_PERMEDIA2: | |
1305 | strcpy(pm2fb_fix.id, "Permedia2"); | |
1306 | default_par->type = PM2_TYPE_PERMEDIA2; | |
1307 | break; | |
1308 | case PCI_DEVICE_ID_3DLABS_PERMEDIA2V: | |
1309 | strcpy(pm2fb_fix.id, "Permedia2v"); | |
1310 | default_par->type = PM2_TYPE_PERMEDIA2V; | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | pm2fb_fix.mmio_start = pci_resource_start(pdev, 0); | |
1315 | pm2fb_fix.mmio_len = PM2_REGS_SIZE; | |
1316 | ||
1317 | #if defined(__BIG_ENDIAN) | |
1318 | /* | |
1319 | * PM2 has a 64k register file, mapped twice in 128k. Lower | |
1320 | * map is little-endian, upper map is big-endian. | |
1321 | */ | |
1322 | pm2fb_fix.mmio_start += PM2_REGS_SIZE; | |
1323 | DPRINTK("Adjusting register base for big-endian.\n"); | |
1324 | #endif | |
1325 | DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start); | |
2f7bb99f | 1326 | |
1da177e4 | 1327 | /* Registers - request region and map it. */ |
45f169ec KH |
1328 | if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len, |
1329 | "pm2fb regbase")) { | |
1da177e4 LT |
1330 | printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n"); |
1331 | goto err_exit_neither; | |
1332 | } | |
1333 | default_par->v_regs = | |
1334 | ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
45f169ec | 1335 | if (!default_par->v_regs) { |
1da177e4 LT |
1336 | printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n", |
1337 | pm2fb_fix.id); | |
1338 | release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
1339 | goto err_exit_neither; | |
1340 | } | |
1341 | ||
1342 | /* Stash away memory register info for use when we reset the board */ | |
1343 | default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL); | |
1344 | default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS); | |
1345 | default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG); | |
1346 | DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n", | |
1347 | default_par->mem_control, default_par->boot_address, | |
1348 | default_par->mem_config); | |
1349 | ||
45f169ec | 1350 | if (default_par->mem_control == 0 && |
9127fa28 | 1351 | default_par->boot_address == 0x31 && |
f1c15f93 | 1352 | default_par->mem_config == 0x259fffff) { |
9a31f0f7 | 1353 | default_par->memclock = CVPPC_MEMCLOCK; |
45f169ec KH |
1354 | default_par->mem_control = 0; |
1355 | default_par->boot_address = 0x20; | |
1356 | default_par->mem_config = 0xe6002021; | |
f1c15f93 KH |
1357 | if (pdev->subsystem_vendor == 0x1048 && |
1358 | pdev->subsystem_device == 0x0a31) { | |
3843faa2 KH |
1359 | DPRINTK("subsystem_vendor: %04x, " |
1360 | "subsystem_device: %04x\n", | |
f1c15f93 | 1361 | pdev->subsystem_vendor, pdev->subsystem_device); |
3843faa2 KH |
1362 | DPRINTK("We have not been initialized by VGA BIOS and " |
1363 | "are running on an Elsa Winner 2000 Office\n"); | |
f1c15f93 | 1364 | DPRINTK("Initializing card timings manually...\n"); |
138a451c | 1365 | default_par->memclock = 100000; |
f1c15f93 KH |
1366 | } |
1367 | if (pdev->subsystem_vendor == 0x3d3d && | |
1368 | pdev->subsystem_device == 0x0100) { | |
3843faa2 KH |
1369 | DPRINTK("subsystem_vendor: %04x, " |
1370 | "subsystem_device: %04x\n", | |
f1c15f93 | 1371 | pdev->subsystem_vendor, pdev->subsystem_device); |
3843faa2 KH |
1372 | DPRINTK("We have not been initialized by VGA BIOS and " |
1373 | "are running on an 3dlabs reference board\n"); | |
f1c15f93 | 1374 | DPRINTK("Initializing card timings manually...\n"); |
45f169ec | 1375 | default_par->memclock = 74894; |
f1c15f93 | 1376 | } |
9127fa28 PDS |
1377 | } |
1378 | ||
1da177e4 | 1379 | /* Now work out how big lfb is going to be. */ |
3843faa2 | 1380 | switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) { |
1da177e4 | 1381 | case PM2F_MEM_BANKS_1: |
45f169ec | 1382 | pm2fb_fix.smem_len = 0x200000; |
1da177e4 LT |
1383 | break; |
1384 | case PM2F_MEM_BANKS_2: | |
45f169ec | 1385 | pm2fb_fix.smem_len = 0x400000; |
1da177e4 LT |
1386 | break; |
1387 | case PM2F_MEM_BANKS_3: | |
45f169ec | 1388 | pm2fb_fix.smem_len = 0x600000; |
1da177e4 LT |
1389 | break; |
1390 | case PM2F_MEM_BANKS_4: | |
45f169ec | 1391 | pm2fb_fix.smem_len = 0x800000; |
1da177e4 LT |
1392 | break; |
1393 | } | |
1da177e4 | 1394 | pm2fb_fix.smem_start = pci_resource_start(pdev, 1); |
1da177e4 LT |
1395 | |
1396 | /* Linear frame buffer - request region and map it. */ | |
45f169ec KH |
1397 | if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len, |
1398 | "pm2fb smem")) { | |
1da177e4 LT |
1399 | printk(KERN_WARNING "pm2fb: Can't reserve smem.\n"); |
1400 | goto err_exit_mmio; | |
1401 | } | |
4560daaf | 1402 | info->screen_base = |
1da177e4 | 1403 | ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
45f169ec | 1404 | if (!info->screen_base) { |
1da177e4 LT |
1405 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); |
1406 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | |
1407 | goto err_exit_mmio; | |
1408 | } | |
1409 | ||
d5383fcc KH |
1410 | #ifdef CONFIG_MTRR |
1411 | default_par->mtrr_handle = -1; | |
1412 | if (!nomtrr) | |
1413 | default_par->mtrr_handle = | |
1414 | mtrr_add(pm2fb_fix.smem_start, | |
1415 | pm2fb_fix.smem_len, | |
1416 | MTRR_TYPE_WRCOMB, 1); | |
1417 | #endif | |
1418 | ||
1da177e4 | 1419 | info->fbops = &pm2fb_ops; |
2f7bb99f | 1420 | info->fix = pm2fb_fix; |
6772a2ee | 1421 | info->pseudo_palette = default_par->palette; |
1da177e4 | 1422 | info->flags = FBINFO_DEFAULT | |
2f7bb99f KH |
1423 | FBINFO_HWACCEL_YPAN | |
1424 | FBINFO_HWACCEL_COPYAREA | | |
91b3a6f4 | 1425 | FBINFO_HWACCEL_IMAGEBLIT | |
2f7bb99f | 1426 | FBINFO_HWACCEL_FILLRECT; |
1da177e4 | 1427 | |
91b3a6f4 KH |
1428 | info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL); |
1429 | if (!info->pixmap.addr) { | |
3843faa2 | 1430 | retval = -ENOMEM; |
91b3a6f4 KH |
1431 | goto err_exit_pixmap; |
1432 | } | |
1433 | info->pixmap.size = PM2_PIXMAP_SIZE; | |
1434 | info->pixmap.buf_align = 4; | |
1435 | info->pixmap.scan_align = 4; | |
1436 | info->pixmap.access_align = 32; | |
1437 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
1438 | ||
d5383fcc | 1439 | if (noaccel) { |
91b3a6f4 KH |
1440 | printk(KERN_DEBUG "disabling acceleration\n"); |
1441 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1442 | info->pixmap.scan_align = 1; | |
d5383fcc KH |
1443 | } |
1444 | ||
1da177e4 LT |
1445 | if (!mode) |
1446 | mode = "640x480@60"; | |
2f7bb99f KH |
1447 | |
1448 | err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8); | |
1da177e4 LT |
1449 | if (!err || err == 4) |
1450 | info->var = pm2fb_var; | |
1451 | ||
1452 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) | |
435d56fc | 1453 | goto err_exit_both; |
1da177e4 LT |
1454 | |
1455 | if (register_framebuffer(info) < 0) | |
435d56fc | 1456 | goto err_exit_all; |
1da177e4 LT |
1457 | |
1458 | printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n", | |
4560daaf | 1459 | info->node, info->fix.id, pm2fb_fix.smem_len / 1024); |
1da177e4 LT |
1460 | |
1461 | /* | |
1462 | * Our driver data | |
1463 | */ | |
1464 | pci_set_drvdata(pdev, info); | |
1465 | ||
1466 | return 0; | |
1467 | ||
1468 | err_exit_all: | |
2f7bb99f KH |
1469 | fb_dealloc_cmap(&info->cmap); |
1470 | err_exit_both: | |
91b3a6f4 KH |
1471 | kfree(info->pixmap.addr); |
1472 | err_exit_pixmap: | |
1da177e4 LT |
1473 | iounmap(info->screen_base); |
1474 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | |
1475 | err_exit_mmio: | |
1476 | iounmap(default_par->v_regs); | |
1477 | release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
1478 | err_exit_neither: | |
1479 | framebuffer_release(info); | |
3843faa2 | 1480 | return retval; |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | /** | |
1484 | * Device removal. | |
1485 | * | |
1486 | * Release all device resources. | |
1487 | * | |
1488 | * @param pdev PCI device to clean up. | |
1489 | */ | |
1490 | static void __devexit pm2fb_remove(struct pci_dev *pdev) | |
1491 | { | |
3843faa2 KH |
1492 | struct fb_info *info = pci_get_drvdata(pdev); |
1493 | struct fb_fix_screeninfo *fix = &info->fix; | |
1da177e4 LT |
1494 | struct pm2fb_par *par = info->par; |
1495 | ||
1496 | unregister_framebuffer(info); | |
2f7bb99f | 1497 | |
d5383fcc KH |
1498 | #ifdef CONFIG_MTRR |
1499 | if (par->mtrr_handle >= 0) | |
1500 | mtrr_del(par->mtrr_handle, info->fix.smem_start, | |
1501 | info->fix.smem_len); | |
1502 | #endif /* CONFIG_MTRR */ | |
1da177e4 LT |
1503 | iounmap(info->screen_base); |
1504 | release_mem_region(fix->smem_start, fix->smem_len); | |
1505 | iounmap(par->v_regs); | |
1506 | release_mem_region(fix->mmio_start, fix->mmio_len); | |
1507 | ||
1508 | pci_set_drvdata(pdev, NULL); | |
3843faa2 | 1509 | kfree(info->pixmap.addr); |
1da177e4 LT |
1510 | kfree(info); |
1511 | } | |
1512 | ||
1513 | static struct pci_device_id pm2fb_id_table[] = { | |
1514 | { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020, | |
138a451c | 1515 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
1da177e4 | 1516 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2, |
138a451c | 1517 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
f1c15f93 | 1518 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, |
138a451c | 1519 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
1da177e4 LT |
1520 | { 0, } |
1521 | }; | |
1522 | ||
1523 | static struct pci_driver pm2fb_driver = { | |
1524 | .name = "pm2fb", | |
2f7bb99f KH |
1525 | .id_table = pm2fb_id_table, |
1526 | .probe = pm2fb_probe, | |
1527 | .remove = __devexit_p(pm2fb_remove), | |
1da177e4 LT |
1528 | }; |
1529 | ||
1530 | MODULE_DEVICE_TABLE(pci, pm2fb_id_table); | |
1531 | ||
1532 | ||
1533 | #ifndef MODULE | |
1534 | /** | |
1535 | * Parse user speficied options. | |
1536 | * | |
1537 | * This is, comma-separated options following `video=pm2fb:'. | |
1538 | */ | |
1539 | static int __init pm2fb_setup(char *options) | |
1540 | { | |
3843faa2 | 1541 | char *this_opt; |
1da177e4 LT |
1542 | |
1543 | if (!options || !*options) | |
1544 | return 0; | |
1545 | ||
2f7bb99f | 1546 | while ((this_opt = strsep(&options, ",")) != NULL) { |
1da177e4 LT |
1547 | if (!*this_opt) |
1548 | continue; | |
3843faa2 | 1549 | if (!strcmp(this_opt, "lowhsync")) |
1da177e4 | 1550 | lowhsync = 1; |
3843faa2 | 1551 | else if (!strcmp(this_opt, "lowvsync")) |
1da177e4 | 1552 | lowvsync = 1; |
d5383fcc | 1553 | #ifdef CONFIG_MTRR |
3843faa2 | 1554 | else if (!strncmp(this_opt, "nomtrr", 6)) |
d5383fcc KH |
1555 | nomtrr = 1; |
1556 | #endif | |
3843faa2 | 1557 | else if (!strncmp(this_opt, "noaccel", 7)) |
d5383fcc | 1558 | noaccel = 1; |
3843faa2 | 1559 | else |
1da177e4 | 1560 | mode = this_opt; |
1da177e4 LT |
1561 | } |
1562 | return 0; | |
1563 | } | |
1564 | #endif | |
1565 | ||
1566 | ||
1567 | static int __init pm2fb_init(void) | |
1568 | { | |
1569 | #ifndef MODULE | |
1570 | char *option = NULL; | |
1571 | ||
1572 | if (fb_get_options("pm2fb", &option)) | |
1573 | return -ENODEV; | |
1574 | pm2fb_setup(option); | |
1575 | #endif | |
1576 | ||
1577 | return pci_register_driver(&pm2fb_driver); | |
1578 | } | |
1579 | ||
1580 | module_init(pm2fb_init); | |
1581 | ||
1582 | #ifdef MODULE | |
1583 | /* | |
1584 | * Cleanup | |
1585 | */ | |
1586 | ||
1587 | static void __exit pm2fb_exit(void) | |
1588 | { | |
1589 | pci_unregister_driver(&pm2fb_driver); | |
1590 | } | |
1591 | #endif | |
1592 | ||
1593 | #ifdef MODULE | |
1594 | module_exit(pm2fb_exit); | |
1595 | ||
1596 | module_param(mode, charp, 0); | |
1597 | MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'"); | |
1598 | module_param(lowhsync, bool, 0); | |
1599 | MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode"); | |
1600 | module_param(lowvsync, bool, 0); | |
1601 | MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode"); | |
d5383fcc KH |
1602 | module_param(noaccel, bool, 0); |
1603 | MODULE_PARM_DESC(noaccel, "Disable acceleration"); | |
1604 | #ifdef CONFIG_MTRR | |
1605 | module_param(nomtrr, bool, 0); | |
1606 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); | |
1607 | #endif | |
1da177e4 LT |
1608 | |
1609 | MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>"); | |
1610 | MODULE_DESCRIPTION("Permedia2 framebuffer device driver"); | |
1611 | MODULE_LICENSE("GPL"); | |
1612 | #endif |