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[mirror_ubuntu-artful-kernel.git] / drivers / video / pm2fb.c
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1da177e4
LT		 1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
2f7bb99f 27 *
1da177e4
LT		 28 */
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
d5383fcc
KH		 41#ifdef CONFIG_MTRR
42#include <asm/mtrr.h>
43#endif
1da177e4
LT		 44
45#include <video/permedia2.h>
46#include <video/cvisionppc.h>
47
48#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
49#error "The endianness of the target host has not been defined."
50#endif
51
52#if !defined(CONFIG_PCI)
53#error "Only generic PCI cards supported."
54#endif
55
56#undef PM2FB_MASTER_DEBUG
57#ifdef PM2FB_MASTER_DEBUG
58#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
59#else
60#define DPRINTK(a,b...)
61#endif
62
91b3a6f4
KH		 63#define PM2_PIXMAP_SIZE (1600 * 4)
64
1da177e4 65/*
2f7bb99f 66 * Driver data
1da177e4
LT		 67 */
68static char *mode __devinitdata = NULL;
69
70/*
71 * The XFree GLINT driver will (I think to implement hardware cursor
72 * support on TVP4010 and similar where there is no RAMDAC - see
73 * comment in set_video) always request +ve sync regardless of what
74 * the mode requires. This screws me because I have a Sun
75 * fixed-frequency monitor which absolutely has to have -ve sync. So
76 * these flags allow the user to specify that requests for +ve sync
77 * should be silently turned in -ve sync.
78 */
c16c556e
DJ		 79static int lowhsync;
80static int lowvsync;
d5383fcc
KH		 81static int noaccel __devinitdata;
82/* mtrr option */
83#ifdef CONFIG_MTRR
84static int nomtrr __devinitdata;
85#endif
1da177e4
LT		 86
87/*
88 * The hardware state of the graphics card that isn't part of the
89 * screeninfo.
90 */
91struct pm2fb_par
92{
93 pm2type_t type; /* Board type */
1da177e4 94 unsigned char __iomem *v_regs;/* virtual address of p_regs */
2f7bb99f 95 u32 memclock; /* memclock */
1da177e4
LT		 96 u32 video; /* video flags before blanking */
97 u32 mem_config; /* MemConfig reg at probe */
98 u32 mem_control; /* MemControl reg at probe */
99 u32 boot_address; /* BootAddress reg at probe */
2f7bb99f 100 u32 palette[16];
d5383fcc 101 int mtrr_handle;
1da177e4
LT		 102};
103
104/*
105 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
106 * if we don't use modedb.
107 */
108static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
2f7bb99f 109 .id = "",
1da177e4
LT		 110 .type = FB_TYPE_PACKED_PIXELS,
111 .visual = FB_VISUAL_PSEUDOCOLOR,
112 .xpanstep = 1,
113 .ypanstep = 1,
2f7bb99f 114 .ywrapstep = 0,
87a7cc68 115 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
1da177e4
LT		 116};
117
118/*
119 * Default video mode. In case the modedb doesn't work.
120 */
121static struct fb_var_screeninfo pm2fb_var __devinitdata = {
122 /* "640x480, 8 bpp @ 60 Hz */
2f7bb99f
KH		 123 .xres = 640,
124 .yres = 480,
125 .xres_virtual = 640,
126 .yres_virtual = 480,
127 .bits_per_pixel = 8,
128 .red = {0, 8, 0},
129 .blue = {0, 8, 0},
130 .green = {0, 8, 0},
131 .activate = FB_ACTIVATE_NOW,
132 .height = -1,
133 .width = -1,
134 .accel_flags = 0,
135 .pixclock = 39721,
136 .left_margin = 40,
137 .right_margin = 24,
138 .upper_margin = 32,
139 .lower_margin = 11,
140 .hsync_len = 96,
141 .vsync_len = 2,
142 .vmode = FB_VMODE_NONINTERLACED
1da177e4
LT		 143};
144
145/*
146 * Utility functions
147 */
148
77933d72 149static inline u32 RD32(unsigned char __iomem *base, s32 off)
1da177e4
LT		 150{
151 return fb_readl(base + off);
152}
153
77933d72 154static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
1da177e4
LT		 155{
156 fb_writel(v, base + off);
157}
158
77933d72 159static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
1da177e4
LT		 160{
161 return RD32(p->v_regs, off);
162}
163
77933d72 164static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
1da177e4
LT		 165{
166 WR32(p->v_regs, off, v);
167}
168
77933d72 169static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
1da177e4
LT		 170{
171 int index = PM2R_RD_INDEXED_DATA;
172 switch (p->type) {
173 case PM2_TYPE_PERMEDIA2:
174 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
175 break;
176 case PM2_TYPE_PERMEDIA2V:
177 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
178 index = PM2VR_RD_INDEXED_DATA;
179 break;
2f7bb99f 180 }
1da177e4
LT		 181 mb();
182 return pm2_RD(p, index);
183}
184
77933d72 185static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 186{
187 int index = PM2R_RD_INDEXED_DATA;
188 switch (p->type) {
189 case PM2_TYPE_PERMEDIA2:
190 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
191 break;
192 case PM2_TYPE_PERMEDIA2V:
193 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
194 index = PM2VR_RD_INDEXED_DATA;
195 break;
2f7bb99f 196 }
11d1a62c 197 wmb();
1da177e4 198 pm2_WR(p, index, v);
11d1a62c 199 wmb();
1da177e4
LT		 200}
201
77933d72 202static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 203{
204 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
11d1a62c 205 wmb();
1da177e4 206 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
11d1a62c 207 wmb();
1da177e4
LT		 208}
209
210#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
2f7bb99f 211#define WAIT_FIFO(p, a)
1da177e4 212#else
77933d72 213static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
1da177e4
LT		 214{
215 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
216 mb();
217}
218#endif
219
220/*
221 * partial products for the supported horizontal resolutions.
222 */
2f7bb99f 223#define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
1da177e4
LT		 224static const struct {
225 u16 width;
226 u16 pp;
227} pp_table[] = {
228 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
229 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
230 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
231 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
232 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
233 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
234 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
235 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
236 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
237 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
238 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
239 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
240 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
241 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
242 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
243 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
244 { 0, 0 } };
245
246static u32 partprod(u32 xres)
247{
248 int i;
249
250 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
251 ;
252 if ( pp_table[i].width == 0 )
253 DPRINTK("invalid width %u\n", xres);
254 return pp_table[i].pp;
255}
256
257static u32 to3264(u32 timing, int bpp, int is64)
258{
259 switch (bpp) {
260 case 8:
261 timing >>= 2 + is64;
262 break;
263 case 16:
264 timing >>= 1 + is64;
265 break;
266 case 24:
267 timing = (timing * 3) >> (2 + is64);
268 break;
269 case 32:
270 if (is64)
271 timing >>= 1;
272 break;
273 }
274 return timing;
275}
276
277static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
278 unsigned char* pp)
279{
280 unsigned char m;
281 unsigned char n;
282 unsigned char p;
283 u32 f;
284 s32 curr;
285 s32 delta = 100000;
286
287 *mm = *nn = *pp = 0;
288 for (n = 2; n < 15; n++) {
289 for (m = 2; m; m++) {
290 f = PM2_REFERENCE_CLOCK * m / n;
291 if (f >= 150000 && f <= 300000) {
292 for ( p = 0; p < 5; p++, f >>= 1) {
293 curr = ( clk > f ) ? clk - f : f - clk;
294 if ( curr < delta ) {
295 delta=curr;
296 *mm=m;
297 *nn=n;
298 *pp=p;
299 }
300 }
301 }
302 }
303 }
304}
305
306static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
307 unsigned char* pp)
308{
309 unsigned char m;
310 unsigned char n;
311 unsigned char p;
312 u32 f;
313 s32 delta = 1000;
314
315 *mm = *nn = *pp = 0;
d4a96b53
KH		 316 for ( m = 1; m < 128; m++) {
317 for (n = 2 * m + 1; n; n++) {
1da177e4 318 for ( p = 0; p < 2; p++) {
d4a96b53 319 f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m;
1da177e4
LT		 320 if ( clk > f - delta && clk < f + delta ) {
321 delta = ( clk > f ) ? clk - f : f - clk;
322 *mm=m;
323 *nn=n;
324 *pp=p;
325 }
326 }
327 }
328 }
329}
330
331static void clear_palette(struct pm2fb_par* p) {
332 int i=256;
333
334 WAIT_FIFO(p, 1);
335 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
336 wmb();
337 while (i--) {
338 WAIT_FIFO(p, 3);
339 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
340 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
341 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
342 }
343}
344
345static void reset_card(struct pm2fb_par* p)
346{
347 if (p->type == PM2_TYPE_PERMEDIA2V)
348 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
349 pm2_WR(p, PM2R_RESET_STATUS, 0);
350 mb();
351 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
352 ;
353 mb();
354#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
355 DPRINTK("FIFO disconnect enabled\n");
356 pm2_WR(p, PM2R_FIFO_DISCON, 1);
357 mb();
358#endif
359
360 /* Restore stashed memory config information from probe */
361 WAIT_FIFO(p, 3);
362 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
363 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
364 wmb();
365 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
366}
367
368static void reset_config(struct pm2fb_par* p)
369{
370 WAIT_FIFO(p, 52);
2f7bb99f 371 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
1da177e4
LT		 372 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
373 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
374 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
375 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
376 pm2_WR(p, PM2R_APERTURE_ONE, 0);
377 pm2_WR(p, PM2R_APERTURE_TWO, 0);
378 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
379 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
380 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
2f7bb99f 381 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
1da177e4
LT		 382 pm2_WR(p, PM2R_LB_READ_MODE, 0);
383 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
384 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
385 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
386 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
387 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
388 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
389 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
390 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
391 pm2_WR(p, PM2R_DITHER_MODE, 0);
392 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
393 pm2_WR(p, PM2R_DEPTH_MODE, 0);
394 pm2_WR(p, PM2R_STENCIL_MODE, 0);
395 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
396 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
397 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
398 pm2_WR(p, PM2R_YUV_MODE, 0);
399 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
400 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
401 pm2_WR(p, PM2R_FOG_MODE, 0);
402 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
403 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
404 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
405 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
406 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
407 switch (p->type) {
408 case PM2_TYPE_PERMEDIA2:
409 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
410 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
411 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
412 break;
413 case PM2_TYPE_PERMEDIA2V:
414 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
415 break;
416 }
417 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
418 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
419 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
420 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
421 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
422}
423
424static void set_aperture(struct pm2fb_par* p, u32 depth)
425{
426 /*
427 * The hardware is little-endian. When used in big-endian
428 * hosts, the on-chip aperture settings are used where
429 * possible to translate from host to card byte order.
430 */
431 WAIT_FIFO(p, 4);
432#ifdef __LITTLE_ENDIAN
433 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
434#else
435 switch (depth) {
436 case 24: /* RGB->BGR */
437 /*
438 * We can't use the aperture to translate host to
439 * card byte order here, so we switch to BGR mode
440 * in pm2fb_set_par().
441 */
442 case 8: /* B->B */
443 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
444 break;
445 case 16: /* HL->LH */
446 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
447 break;
448 case 32: /* RGBA->ABGR */
449 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
450 break;
451 }
452#endif
453
454 // We don't use aperture two, so this may be superflous
455 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
456}
457
458static void set_color(struct pm2fb_par* p, unsigned char regno,
459 unsigned char r, unsigned char g, unsigned char b)
460{
461 WAIT_FIFO(p, 4);
462 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
463 wmb();
464 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
465 wmb();
466 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
467 wmb();
468 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
469}
470
471static void set_memclock(struct pm2fb_par* par, u32 clk)
472{
473 int i;
474 unsigned char m, n, p;
475
e5d809d7
KH		 476 switch (par->type) {
477 case PM2_TYPE_PERMEDIA2V:
478 pm2v_mnp(clk/2, &m, &n, &p);
479 WAIT_FIFO(par, 8);
480 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
481 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
e5d809d7
KH		 482 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
483 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
484 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
e5d809d7
KH		 485 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
486 rmb();
487 for (i = 256;
488 i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
489 i--)
490 ;
491 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
492 break;
493 case PM2_TYPE_PERMEDIA2:
494 pm2_mnp(clk, &m, &n, &p);
495 WAIT_FIFO(par, 10);
496 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
e5d809d7
KH		 497 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
498 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
e5d809d7 499 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
e5d809d7
KH		 500 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
501 rmb();
502 for (i = 256;
503 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
504 i--)
505 ;
506 break;
507 }
1da177e4
LT		 508}
509
510static void set_pixclock(struct pm2fb_par* par, u32 clk)
511{
512 int i;
513 unsigned char m, n, p;
514
515 switch (par->type) {
516 case PM2_TYPE_PERMEDIA2:
517 pm2_mnp(clk, &m, &n, &p);
518 WAIT_FIFO(par, 8);
519 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
1da177e4
LT		 520 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
521 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
1da177e4 522 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
1da177e4
LT		 523 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
524 rmb();
525 for (i = 256;
526 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
527 i--)
528 ;
529 break;
530 case PM2_TYPE_PERMEDIA2V:
531 pm2v_mnp(clk/2, &m, &n, &p);
532 WAIT_FIFO(par, 8);
533 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
534 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
535 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
536 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
537 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
538 break;
539 }
540}
541
542static void set_video(struct pm2fb_par* p, u32 video) {
543 u32 tmp;
544 u32 vsync;
545
546 vsync = video;
547
548 DPRINTK("video = 0x%x\n", video);
2f7bb99f 549
1da177e4
LT		 550 /*
551 * The hardware cursor needs +vsync to recognise vert retrace.
552 * We may not be using the hardware cursor, but the X Glint
553 * driver may well. So always set +hsync/+vsync and then set
554 * the RAMDAC to invert the sync if necessary.
555 */
556 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
557 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
558
559 WAIT_FIFO(p, 5);
560 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
561
562 switch (p->type) {
563 case PM2_TYPE_PERMEDIA2:
564 tmp = PM2F_RD_PALETTE_WIDTH_8;
565 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
566 tmp |= 4; /* invert hsync */
567 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
568 tmp |= 8; /* invert vsync */
569 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
570 break;
571 case PM2_TYPE_PERMEDIA2V:
572 tmp = 0;
573 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
574 tmp |= 1; /* invert hsync */
575 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
576 tmp |= 4; /* invert vsync */
577 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
578 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
579 break;
580 }
581}
582
583/*
584 *
585 */
586
587/**
2f7bb99f
KH		 588 * pm2fb_check_var - Optional function. Validates a var passed in.
589 * @var: frame buffer variable screen structure
590 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 591 *
592 * Checks to see if the hardware supports the state requested by
593 * var passed in.
594 *
595 * Returns negative errno on error, or zero on success.
596 */
597static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
598{
599 u32 lpitch;
600
601 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
602 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
603 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
604 return -EINVAL;
605 }
606
607 if (var->xres != var->xres_virtual) {
608 DPRINTK("virtual x resolution != physical x resolution not supported\n");
609 return -EINVAL;
610 }
611
612 if (var->yres > var->yres_virtual) {
613 DPRINTK("virtual y resolution < physical y resolution not possible\n");
614 return -EINVAL;
615 }
616
617 if (var->xoffset) {
618 DPRINTK("xoffset not supported\n");
619 return -EINVAL;
620 }
621
622 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
623 DPRINTK("interlace not supported\n");
624 return -EINVAL;
625 }
626
627 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
628 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
2f7bb99f 629
1da177e4
LT		 630 if (var->xres < 320 || var->xres > 1600) {
631 DPRINTK("width not supported: %u\n", var->xres);
632 return -EINVAL;
633 }
2f7bb99f 634
1da177e4
LT		 635 if (var->yres < 200 || var->yres > 1200) {
636 DPRINTK("height not supported: %u\n", var->yres);
637 return -EINVAL;
638 }
2f7bb99f 639
1da177e4
LT		 640 if (lpitch * var->yres_virtual > info->fix.smem_len) {
641 DPRINTK("no memory for screen (%ux%ux%u)\n",
642 var->xres, var->yres_virtual, var->bits_per_pixel);
643 return -EINVAL;
644 }
2f7bb99f 645
1da177e4
LT		 646 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
647 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
648 return -EINVAL;
649 }
650
76c7d3ff 651 var->transp.offset = 0;
652 var->transp.length = 0;
1da177e4
LT		 653 switch(var->bits_per_pixel) {
654 case 8:
655 var->red.length = var->green.length = var->blue.length = 8;
656 break;
657 case 16:
658 var->red.offset = 11;
659 var->red.length = 5;
660 var->green.offset = 5;
661 var->green.length = 6;
662 var->blue.offset = 0;
663 var->blue.length = 5;
664 break;
665 case 32:
666 var->transp.offset = 24;
667 var->transp.length = 8;
668 var->red.offset = 16;
669 var->green.offset = 8;
670 var->blue.offset = 0;
671 var->red.length = var->green.length = var->blue.length = 8;
672 break;
673 case 24:
674#ifdef __BIG_ENDIAN
675 var->red.offset = 0;
676 var->blue.offset = 16;
677#else
678 var->red.offset = 16;
679 var->blue.offset = 0;
680#endif
681 var->green.offset = 8;
682 var->red.length = var->green.length = var->blue.length = 8;
683 break;
684 }
685 var->height = var->width = -1;
2f7bb99f 686
1da177e4 687 var->accel_flags = 0; /* Can't mmap if this is on */
2f7bb99f 688
1da177e4
LT		 689 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
690 var->xres, var->yres, var->bits_per_pixel);
691 return 0;
692}
693
694/**
2f7bb99f
KH		 695 * pm2fb_set_par - Alters the hardware state.
696 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 697 *
698 * Using the fb_var_screeninfo in fb_info we set the resolution of the
699 * this particular framebuffer.
700 */
701static int pm2fb_set_par(struct fb_info *info)
702{
6772a2ee 703 struct pm2fb_par *par = info->par;
1da177e4
LT		 704 u32 pixclock;
705 u32 width, height, depth;
706 u32 hsstart, hsend, hbend, htotal;
707 u32 vsstart, vsend, vbend, vtotal;
708 u32 stride;
709 u32 base;
710 u32 video = 0;
711 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
712 u32 txtmap = 0;
713 u32 pixsize = 0;
714 u32 clrformat = 0;
715 u32 xres;
716 int data64;
717
718 reset_card(par);
719 reset_config(par);
720 clear_palette(par);
721 if ( par->memclock )
722 set_memclock(par, par->memclock);
2f7bb99f 723
1da177e4
LT		 724 width = (info->var.xres_virtual + 7) & ~7;
725 height = info->var.yres_virtual;
726 depth = (info->var.bits_per_pixel + 7) & ~7;
727 depth = (depth > 32) ? 32 : depth;
728 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
729
730 xres = (info->var.xres + 31) & ~31;
731 pixclock = PICOS2KHZ(info->var.pixclock);
732 if (pixclock > PM2_MAX_PIXCLOCK) {
733 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
734 return -EINVAL;
735 }
2f7bb99f 736
1da177e4
LT		 737 hsstart = to3264(info->var.right_margin, depth, data64);
738 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
739 hbend = hsend + to3264(info->var.left_margin, depth, data64);
740 htotal = to3264(xres, depth, data64) + hbend - 1;
741 vsstart = (info->var.lower_margin)
742 ? info->var.lower_margin - 1
743 : 0; /* FIXME! */
744 vsend = info->var.lower_margin + info->var.vsync_len - 1;
745 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
746 vtotal = info->var.yres + vbend - 1;
747 stride = to3264(width, depth, 1);
748 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
749 if (data64)
750 video |= PM2F_DATA_64_ENABLE;
2f7bb99f 751
1da177e4
LT		 752 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
753 if (lowhsync) {
754 DPRINTK("ignoring +hsync, using -hsync.\n");
755 video |= PM2F_HSYNC_ACT_LOW;
756 } else
757 video |= PM2F_HSYNC_ACT_HIGH;
758 }
759 else
760 video |= PM2F_HSYNC_ACT_LOW;
761 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
762 if (lowvsync) {
763 DPRINTK("ignoring +vsync, using -vsync.\n");
764 video |= PM2F_VSYNC_ACT_LOW;
765 } else
766 video |= PM2F_VSYNC_ACT_HIGH;
767 }
768 else
769 video |= PM2F_VSYNC_ACT_LOW;
770 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
771 DPRINTK("interlaced not supported\n");
772 return -EINVAL;
773 }
774 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
775 video |= PM2F_LINE_DOUBLE;
776 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
777 video |= PM2F_VIDEO_ENABLE;
778 par->video = video;
779
780 info->fix.visual =
781 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
782 info->fix.line_length = info->var.xres * depth / 8;
783 info->cmap.len = 256;
784
785 /*
786 * Settings calculated. Now write them out.
787 */
788 if (par->type == PM2_TYPE_PERMEDIA2V) {
789 WAIT_FIFO(par, 1);
790 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
791 }
2f7bb99f 792
1da177e4 793 set_aperture(par, depth);
2f7bb99f 794
1da177e4
LT		 795 mb();
796 WAIT_FIFO(par, 19);
797 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
798 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
799 switch (depth) {
800 case 8:
801 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
802 clrformat = 0x0e;
803 break;
804 case 16:
805 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
806 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
807 txtmap = PM2F_TEXTEL_SIZE_16;
808 pixsize = 1;
809 clrformat = 0x70;
810 break;
811 case 32:
812 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
813 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
814 txtmap = PM2F_TEXTEL_SIZE_32;
815 pixsize = 2;
816 clrformat = 0x20;
817 break;
818 case 24:
819 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
820 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
821 txtmap = PM2F_TEXTEL_SIZE_24;
822 pixsize = 4;
823 clrformat = 0x20;
824 break;
825 }
826 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
827 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
828 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
829 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
830 pm2_WR(par, PM2R_H_TOTAL, htotal);
831 pm2_WR(par, PM2R_HS_START, hsstart);
832 pm2_WR(par, PM2R_HS_END, hsend);
833 pm2_WR(par, PM2R_HG_END, hbend);
834 pm2_WR(par, PM2R_HB_END, hbend);
835 pm2_WR(par, PM2R_V_TOTAL, vtotal);
836 pm2_WR(par, PM2R_VS_START, vsstart);
837 pm2_WR(par, PM2R_VS_END, vsend);
838 pm2_WR(par, PM2R_VB_END, vbend);
839 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
840 wmb();
841 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
842 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
843 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
844 wmb();
845 pm2_WR(par, PM2R_SCREEN_BASE, base);
846 wmb();
847 set_video(par, video);
848 WAIT_FIFO(par, 4);
849 switch (par->type) {
850 case PM2_TYPE_PERMEDIA2:
851 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
852 break;
853 case PM2_TYPE_PERMEDIA2V:
854 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
855 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
856 break;
857 }
858 set_pixclock(par, pixclock);
859 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
860 info->var.xres, info->var.yres, info->var.bits_per_pixel);
2f7bb99f 861 return 0;
1da177e4
LT		 862}
863
864/**
2f7bb99f
KH		 865 * pm2fb_setcolreg - Sets a color register.
866 * @regno: boolean, 0 copy local, 1 get_user() function
867 * @red: frame buffer colormap structure
868 * @green: The green value which can be up to 16 bits wide
1da177e4 869 * @blue: The blue value which can be up to 16 bits wide.
2f7bb99f
KH		 870 * @transp: If supported the alpha value which can be up to 16 bits wide.
871 * @info: frame buffer info structure
872 *
873 * Set a single color register. The values supplied have a 16 bit
874 * magnitude which needs to be scaled in this function for the hardware.
1da177e4 875 * Pretty much a direct lift from tdfxfb.c.
2f7bb99f 876 *
1da177e4
LT		 877 * Returns negative errno on error, or zero on success.
878 */
879static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
880 unsigned blue, unsigned transp,
881 struct fb_info *info)
882{
6772a2ee 883 struct pm2fb_par *par = info->par;
1da177e4
LT		 884
885 if (regno >= info->cmap.len) /* no. of hw registers */
886 return 1;
887 /*
888 * Program hardware... do anything you want with transp
889 */
890
891 /* grayscale works only partially under directcolor */
892 if (info->var.grayscale) {
893 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
894 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
895 }
896
897 /* Directcolor:
898 * var->{color}.offset contains start of bitfield
899 * var->{color}.length contains length of bitfield
900 * {hardwarespecific} contains width of DAC
901 * cmap[X] is programmed to
902 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
903 * RAMDAC[X] is programmed to (red, green, blue)
904 *
905 * Pseudocolor:
906 * uses offset = 0 && length = DAC register width.
907 * var->{color}.offset is 0
908 * var->{color}.length contains widht of DAC
909 * cmap is not used
910 * DAC[X] is programmed to (red, green, blue)
911 * Truecolor:
912 * does not use RAMDAC (usually has 3 of them).
913 * var->{color}.offset contains start of bitfield
914 * var->{color}.length contains length of bitfield
915 * cmap is programmed to
916 * (red << red.offset) | (green << green.offset) |
917 * (blue << blue.offset) | (transp << transp.offset)
918 * RAMDAC does not exist
919 */
2f7bb99f 920#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
1da177e4
LT		 921 switch (info->fix.visual) {
922 case FB_VISUAL_TRUECOLOR:
923 case FB_VISUAL_PSEUDOCOLOR:
924 red = CNVT_TOHW(red, info->var.red.length);
925 green = CNVT_TOHW(green, info->var.green.length);
926 blue = CNVT_TOHW(blue, info->var.blue.length);
927 transp = CNVT_TOHW(transp, info->var.transp.length);
928 break;
929 case FB_VISUAL_DIRECTCOLOR:
2f7bb99f
KH		 930 /* example here assumes 8 bit DAC. Might be different
931 * for your hardware */
932 red = CNVT_TOHW(red, 8);
1da177e4
LT		 933 green = CNVT_TOHW(green, 8);
934 blue = CNVT_TOHW(blue, 8);
935 /* hey, there is bug in transp handling... */
936 transp = CNVT_TOHW(transp, 8);
937 break;
938 }
939#undef CNVT_TOHW
940 /* Truecolor has hardware independent palette */
941 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
942 u32 v;
943
944 if (regno >= 16)
945 return 1;
946
947 v = (red << info->var.red.offset) |
948 (green << info->var.green.offset) |
949 (blue << info->var.blue.offset) |
950 (transp << info->var.transp.offset);
951
952 switch (info->var.bits_per_pixel) {
953 case 8:
2f7bb99f
KH		 954 break;
955 case 16:
1da177e4 956 case 24:
2f7bb99f
KH		 957 case 32:
958 par->palette[regno] = v;
1da177e4
LT		 959 break;
960 }
961 return 0;
962 }
963 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
964 set_color(par, regno, red, green, blue);
965
966 return 0;
967}
968
969/**
2f7bb99f
KH		 970 * pm2fb_pan_display - Pans the display.
971 * @var: frame buffer variable screen structure
972 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 973 *
974 * Pan (or wrap, depending on the `vmode' field) the display using the
2f7bb99f
KH		 975 * `xoffset' and `yoffset' fields of the `var' structure.
976 * If the values don't fit, return -EINVAL.
1da177e4 977 *
2f7bb99f 978 * Returns negative errno on error, or zero on success.
1da177e4
LT		 979 *
980 */
981static int pm2fb_pan_display(struct fb_var_screeninfo *var,
982 struct fb_info *info)
983{
6772a2ee 984 struct pm2fb_par *p = info->par;
1da177e4
LT		 985 u32 base;
986 u32 depth;
987 u32 xres;
988
989 xres = (var->xres + 31) & ~31;
990 depth = (var->bits_per_pixel + 7) & ~7;
991 depth = (depth > 32) ? 32 : depth;
992 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
993 WAIT_FIFO(p, 1);
2f7bb99f 994 pm2_WR(p, PM2R_SCREEN_BASE, base);
1da177e4
LT		 995 return 0;
996}
997
998/**
2f7bb99f
KH		 999 * pm2fb_blank - Blanks the display.
1000 * @blank_mode: the blank mode we want.
1001 * @info: frame buffer structure that represents a single frame buffer
1da177e4 1002 *
2f7bb99f
KH		 1003 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1004 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1005 * video mode which doesn't support it. Implements VESA suspend
1006 * and powerdown modes on hardware that supports disabling hsync/vsync:
1007 * blank_mode == 2: suspend vsync
1008 * blank_mode == 3: suspend hsync
1009 * blank_mode == 4: powerdown
1da177e4 1010 *
2f7bb99f 1011 * Returns negative errno on error, or zero on success.
1da177e4
LT		 1012 *
1013 */
1014static int pm2fb_blank(int blank_mode, struct fb_info *info)
1015{
6772a2ee 1016 struct pm2fb_par *par = info->par;
1da177e4
LT		 1017 u32 video = par->video;
1018
1019 DPRINTK("blank_mode %d\n", blank_mode);
1020
1021 switch (blank_mode) {
1022 case FB_BLANK_UNBLANK:
1023 /* Screen: On */
1024 video |= PM2F_VIDEO_ENABLE;
1025 break;
1026 case FB_BLANK_NORMAL:
1027 /* Screen: Off */
1028 video &= ~PM2F_VIDEO_ENABLE;
1029 break;
1030 case FB_BLANK_VSYNC_SUSPEND:
1031 /* VSync: Off */
1032 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1033 break;
1034 case FB_BLANK_HSYNC_SUSPEND:
1035 /* HSync: Off */
1036 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1037 break;
1038 case FB_BLANK_POWERDOWN:
1039 /* HSync: Off, VSync: Off */
1040 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1041 break;
1042 }
1043 set_video(par, video);
1044 return 0;
1045}
1046
03b9ae4b
AD		 1047static int pm2fb_sync(struct fb_info *info)
1048{
1049 struct pm2fb_par *par = info->par;
1050
1051 WAIT_FIFO(par, 1);
1052 pm2_WR(par, PM2R_SYNC, 0);
1053 mb();
1054 do {
1055 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1056 udelay(10);
1057 rmb();
1058 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1059
1060 return 0;
1061}
1062
87a7cc68
KH		 1063/*
1064 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1065 */
03b9ae4b 1066static void pm2fb_block_op(struct fb_info* info, int copy,
87a7cc68
KH		 1067 s32 xsrc, s32 ysrc,
1068 s32 x, s32 y, s32 w, s32 h,
1069 u32 color) {
03b9ae4b 1070 struct pm2fb_par *par = info->par;
87a7cc68
KH		 1071
1072 if (!w || !h)
1073 return;
11d1a62c 1074 WAIT_FIFO(par, 5);
87a7cc68
KH		 1075 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1076 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
87a7cc68
KH		 1077 if (copy)
1078 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1079 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff));
1080 else
1081 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1082 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (y << 16) | x);
1083 pm2_WR(par, PM2R_RECTANGLE_SIZE, (h << 16) | w);
1084 wmb();
2f7bb99f 1085 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
87a7cc68
KH		 1086 (x<xsrc ? PM2F_INCREASE_X : 0) |
1087 (y<ysrc ? PM2F_INCREASE_Y : 0) |
1088 (copy ? 0 : PM2F_RENDER_FASTFILL));
87a7cc68
KH		 1089}
1090
1091static void pm2fb_fillrect (struct fb_info *info,
1092 const struct fb_fillrect *region)
1093{
87a7cc68
KH		 1094 struct fb_fillrect modded;
1095 int vxres, vyres;
1096 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1097 ((u32*)info->pseudo_palette)[region->color] : region->color;
1098
1099 if (info->state != FBINFO_STATE_RUNNING)
1100 return;
1101 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1102 region->rop != ROP_COPY ) {
1103 cfb_fillrect(info, region);
1104 return;
1105 }
1106
1107 vxres = info->var.xres_virtual;
1108 vyres = info->var.yres_virtual;
1109
1110 memcpy(&modded, region, sizeof(struct fb_fillrect));
1111
1112 if(!modded.width || !modded.height ||
1113 modded.dx >= vxres || modded.dy >= vyres)
1114 return;
1115
1116 if(modded.dx + modded.width > vxres)
1117 modded.width = vxres - modded.dx;
1118 if(modded.dy + modded.height > vyres)
1119 modded.height = vyres - modded.dy;
1120
1121 if(info->var.bits_per_pixel == 8)
1122 color |= color << 8;
1123 if(info->var.bits_per_pixel <= 16)
1124 color |= color << 16;
1125
1126 if(info->var.bits_per_pixel != 24)
03b9ae4b 1127 pm2fb_block_op(info, 0, 0, 0,
87a7cc68
KH		 1128 modded.dx, modded.dy,
1129 modded.width, modded.height, color);
1130 else
1131 cfb_fillrect(info, region);
1132}
1133
1134static void pm2fb_copyarea(struct fb_info *info,
1135 const struct fb_copyarea *area)
1136{
87a7cc68
KH		 1137 struct fb_copyarea modded;
1138 u32 vxres, vyres;
1139
1140 if (info->state != FBINFO_STATE_RUNNING)
1141 return;
1142 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1143 cfb_copyarea(info, area);
1144 return;
1145 }
1146
1147 memcpy(&modded, area, sizeof(struct fb_copyarea));
1148
1149 vxres = info->var.xres_virtual;
1150 vyres = info->var.yres_virtual;
1151
1152 if(!modded.width || !modded.height ||
1153 modded.sx >= vxres || modded.sy >= vyres ||
1154 modded.dx >= vxres || modded.dy >= vyres)
1155 return;
1156
1157 if(modded.sx + modded.width > vxres)
1158 modded.width = vxres - modded.sx;
1159 if(modded.dx + modded.width > vxres)
1160 modded.width = vxres - modded.dx;
1161 if(modded.sy + modded.height > vyres)
1162 modded.height = vyres - modded.sy;
1163 if(modded.dy + modded.height > vyres)
1164 modded.height = vyres - modded.dy;
1165
03b9ae4b 1166 pm2fb_block_op(info, 1, modded.sx, modded.sy,
87a7cc68
KH		 1167 modded.dx, modded.dy,
1168 modded.width, modded.height, 0);
1169}
1170
91b3a6f4
KH		 1171static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1172{
1173 struct pm2fb_par *par = info->par;
1174 u32 height = image->height;
1175 u32 fgx, bgx;
1176 const u32 *src = (const u32*)image->data;
1177 u32 xres = (info->var.xres + 31) & ~31;
1178
1179 if (info->state != FBINFO_STATE_RUNNING)
1180 return;
1181 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1182 cfb_imageblit(info, image);
1183 return;
1184 }
1185 switch (info->fix.visual) {
1186 case FB_VISUAL_PSEUDOCOLOR:
1187 fgx = image->fg_color;
1188 bgx = image->bg_color;
1189 break;
1190 case FB_VISUAL_TRUECOLOR:
1191 default:
1192 fgx = par->palette[image->fg_color];
1193 bgx = par->palette[image->bg_color];
1194 break;
1195 }
1196 if (info->var.bits_per_pixel == 8) {
1197 fgx |= fgx << 8;
1198 bgx |= bgx << 8;
1199 }
1200 if (info->var.bits_per_pixel <= 16) {
1201 fgx |= fgx << 16;
1202 bgx |= bgx << 16;
1203 }
1204
1205 WAIT_FIFO(par, 13);
1206 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1207 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1208 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1209 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1210 (((image->dy + image->height) & 0x0fff) << 16) |
1211 ((image->dx + image->width) & 0x0fff));
1212 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1213 /* GXcopy & UNIT_ENABLE */
1214 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1 );
1215 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1216 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1217 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1218 ((image->height & 0x0fff) << 16) |
1219 ((image->width) & 0x0fff));
1220 if (info->var.bits_per_pixel == 24) {
1221 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1222 /* clear area */
1223 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1224 pm2_WR(par, PM2R_RENDER,
1225 PM2F_RENDER_RECTANGLE |
1226 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1227 /* BitMapPackEachScanline & invert bits and byte order*/
1228 /* force background */
1229 pm2_WR(par, PM2R_RASTERIZER_MODE, (1<<9) | 1 | (3<<7));
1230 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1231 pm2_WR(par, PM2R_RENDER,
1232 PM2F_RENDER_RECTANGLE |
1233 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1234 PM2F_RENDER_SYNC_ON_BIT_MASK);
1235 } else {
1236 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1237 /* clear area */
1238 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1239 pm2_WR(par, PM2R_RENDER,
1240 PM2F_RENDER_RECTANGLE |
1241 PM2F_RENDER_FASTFILL |
1242 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1243 /* invert bits and byte order*/
1244 pm2_WR(par, PM2R_RASTERIZER_MODE, 1 | (3<<7) );
1245 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1246 pm2_WR(par, PM2R_RENDER,
1247 PM2F_RENDER_RECTANGLE |
1248 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1249 PM2F_RENDER_FASTFILL |
1250 PM2F_RENDER_SYNC_ON_BIT_MASK);
1251 }
1252
1253 while (height--) {
1254 int width = ((image->width + 7) >> 3)
1255 + info->pixmap.scan_align - 1;
1256 width >>= 2;
1257 WAIT_FIFO(par, width);
1258 while (width--) {
1259 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1260 src++;
1261 }
1262 }
1263 WAIT_FIFO(par, 3);
1264 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1265 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1266 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1267}
1268
1da177e4
LT		 1269/* ------------ Hardware Independent Functions ------------ */
1270
1271/*
1272 * Frame buffer operations
1273 */
1274
1275static struct fb_ops pm2fb_ops = {
1276 .owner = THIS_MODULE,
1277 .fb_check_var = pm2fb_check_var,
1278 .fb_set_par = pm2fb_set_par,
1279 .fb_setcolreg = pm2fb_setcolreg,
1280 .fb_blank = pm2fb_blank,
1281 .fb_pan_display = pm2fb_pan_display,
87a7cc68
KH		 1282 .fb_fillrect = pm2fb_fillrect,
1283 .fb_copyarea = pm2fb_copyarea,
91b3a6f4 1284 .fb_imageblit = pm2fb_imageblit,
03b9ae4b 1285 .fb_sync = pm2fb_sync,
1da177e4
LT		 1286};
1287
1288/*
1289 * PCI stuff
1290 */
1291
1292
1293/**
1294 * Device initialisation
1295 *
1296 * Initialise and allocate resource for PCI device.
1297 *
1298 * @param pdev PCI device.
1299 * @param id PCI device ID.
1300 */
1301static int __devinit pm2fb_probe(struct pci_dev *pdev,
1302 const struct pci_device_id *id)
1303{
1304 struct pm2fb_par *default_par;
1305 struct fb_info *info;
6772a2ee 1306 int err, err_retval = -ENXIO;
1da177e4
LT		 1307
1308 err = pci_enable_device(pdev);
1309 if ( err ) {
1310 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1311 return err;
1312 }
1313
6772a2ee 1314 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1da177e4
LT		 1315 if ( !info )
1316 return -ENOMEM;
6772a2ee 1317 default_par = info->par;
1da177e4
LT		 1318
1319 switch (pdev->device) {
1320 case PCI_DEVICE_ID_TI_TVP4020:
1321 strcpy(pm2fb_fix.id, "TVP4020");
1322 default_par->type = PM2_TYPE_PERMEDIA2;
1323 break;
1324 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1325 strcpy(pm2fb_fix.id, "Permedia2");
1326 default_par->type = PM2_TYPE_PERMEDIA2;
1327 break;
1328 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1329 strcpy(pm2fb_fix.id, "Permedia2v");
1330 default_par->type = PM2_TYPE_PERMEDIA2V;
1331 break;
1332 }
1333
1334 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1335 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1336
1337#if defined(__BIG_ENDIAN)
1338 /*
1339 * PM2 has a 64k register file, mapped twice in 128k. Lower
1340 * map is little-endian, upper map is big-endian.
1341 */
1342 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1343 DPRINTK("Adjusting register base for big-endian.\n");
1344#endif
1345 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
2f7bb99f 1346
1da177e4
LT		 1347 /* Registers - request region and map it. */
1348 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1349 "pm2fb regbase") ) {
1350 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1351 goto err_exit_neither;
1352 }
1353 default_par->v_regs =
1354 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1355 if ( !default_par->v_regs ) {
1356 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1357 pm2fb_fix.id);
1358 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1359 goto err_exit_neither;
1360 }
1361
1362 /* Stash away memory register info for use when we reset the board */
1363 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1364 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1365 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1366 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1367 default_par->mem_control, default_par->boot_address,
1368 default_par->mem_config);
1369
9127fa28
PDS		 1370 if(default_par->mem_control == 0 &&
1371 default_par->boot_address == 0x31 &&
f1c15f93 1372 default_par->mem_config == 0x259fffff) {
9a31f0f7 1373 default_par->memclock = CVPPC_MEMCLOCK;
9127fa28
PDS		 1374 default_par->mem_control=0;
1375 default_par->boot_address=0x20;
1376 default_par->mem_config=0xe6002021;
f1c15f93
KH		 1377 if (pdev->subsystem_vendor == 0x1048 &&
1378 pdev->subsystem_device == 0x0a31) {
1379 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1380 pdev->subsystem_vendor, pdev->subsystem_device);
1381 DPRINTK("We have not been initialized by VGA BIOS "
1382 "and are running on an Elsa Winner 2000 Office\n");
1383 DPRINTK("Initializing card timings manually...\n");
1384 default_par->memclock=70000;
1385 }
1386 if (pdev->subsystem_vendor == 0x3d3d &&
1387 pdev->subsystem_device == 0x0100) {
1388 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1389 pdev->subsystem_vendor, pdev->subsystem_device);
1390 DPRINTK("We have not been initialized by VGA BIOS "
1391 "and are running on an 3dlabs reference board\n");
1392 DPRINTK("Initializing card timings manually...\n");
9a31f0f7 1393 default_par->memclock=74894;
f1c15f93 1394 }
9127fa28
PDS		 1395 }
1396
1da177e4
LT		 1397 /* Now work out how big lfb is going to be. */
1398 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1399 case PM2F_MEM_BANKS_1:
4560daaf 1400 pm2fb_fix.smem_len=0x200000;
1da177e4
LT		 1401 break;
1402 case PM2F_MEM_BANKS_2:
4560daaf 1403 pm2fb_fix.smem_len=0x400000;
1da177e4
LT		 1404 break;
1405 case PM2F_MEM_BANKS_3:
4560daaf 1406 pm2fb_fix.smem_len=0x600000;
1da177e4
LT		 1407 break;
1408 case PM2F_MEM_BANKS_4:
4560daaf 1409 pm2fb_fix.smem_len=0x800000;
1da177e4
LT		 1410 break;
1411 }
1da177e4 1412 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1da177e4
LT		 1413
1414 /* Linear frame buffer - request region and map it. */
1415 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1416 "pm2fb smem") ) {
1417 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1418 goto err_exit_mmio;
1419 }
4560daaf 1420 info->screen_base =
1da177e4 1421 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
4560daaf 1422 if ( !info->screen_base ) {
1da177e4
LT		 1423 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1424 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1425 goto err_exit_mmio;
1426 }
1427
d5383fcc
KH		 1428#ifdef CONFIG_MTRR
1429 default_par->mtrr_handle = -1;
1430 if (!nomtrr)
1431 default_par->mtrr_handle =
1432 mtrr_add(pm2fb_fix.smem_start,
1433 pm2fb_fix.smem_len,
1434 MTRR_TYPE_WRCOMB, 1);
1435#endif
1436
1da177e4 1437 info->fbops = &pm2fb_ops;
2f7bb99f 1438 info->fix = pm2fb_fix;
6772a2ee 1439 info->pseudo_palette = default_par->palette;
1da177e4 1440 info->flags = FBINFO_DEFAULT |
2f7bb99f
KH		 1441 FBINFO_HWACCEL_YPAN |
1442 FBINFO_HWACCEL_COPYAREA |
91b3a6f4 1443 FBINFO_HWACCEL_IMAGEBLIT |
2f7bb99f 1444 FBINFO_HWACCEL_FILLRECT;
1da177e4 1445
91b3a6f4
KH		 1446 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1447 if (!info->pixmap.addr) {
1448 err_retval = -ENOMEM;
1449 goto err_exit_pixmap;
1450 }
1451 info->pixmap.size = PM2_PIXMAP_SIZE;
1452 info->pixmap.buf_align = 4;
1453 info->pixmap.scan_align = 4;
1454 info->pixmap.access_align = 32;
1455 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1456
d5383fcc 1457 if (noaccel) {
91b3a6f4
KH		 1458 printk(KERN_DEBUG "disabling acceleration\n");
1459 info->flags |= FBINFO_HWACCEL_DISABLED;
1460 info->pixmap.scan_align = 1;
d5383fcc
KH		 1461 }
1462
1da177e4
LT		 1463 if (!mode)
1464 mode = "640x480@60";
2f7bb99f
KH		 1465
1466 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1da177e4
LT		 1467 if (!err || err == 4)
1468 info->var = pm2fb_var;
1469
1470 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
435d56fc 1471 goto err_exit_both;
1da177e4
LT		 1472
1473 if (register_framebuffer(info) < 0)
435d56fc 1474 goto err_exit_all;
1da177e4
LT		 1475
1476 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
4560daaf 1477 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1da177e4
LT		 1478
1479 /*
1480 * Our driver data
1481 */
1482 pci_set_drvdata(pdev, info);
1483
1484 return 0;
1485
1486 err_exit_all:
2f7bb99f
KH		 1487 fb_dealloc_cmap(&info->cmap);
1488 err_exit_both:
91b3a6f4
KH		 1489 kfree(info->pixmap.addr);
1490 err_exit_pixmap:
1da177e4
LT		 1491 iounmap(info->screen_base);
1492 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1493 err_exit_mmio:
1494 iounmap(default_par->v_regs);
1495 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1496 err_exit_neither:
1497 framebuffer_release(info);
1498 return err_retval;
1499}
1500
1501/**
1502 * Device removal.
1503 *
1504 * Release all device resources.
1505 *
1506 * @param pdev PCI device to clean up.
1507 */
1508static void __devexit pm2fb_remove(struct pci_dev *pdev)
1509{
1510 struct fb_info* info = pci_get_drvdata(pdev);
1511 struct fb_fix_screeninfo* fix = &info->fix;
1512 struct pm2fb_par *par = info->par;
1513
1514 unregister_framebuffer(info);
2f7bb99f 1515
d5383fcc
KH		 1516#ifdef CONFIG_MTRR
1517 if (par->mtrr_handle >= 0)
1518 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1519 info->fix.smem_len);
1520#endif /* CONFIG_MTRR */
1da177e4
LT		 1521 iounmap(info->screen_base);
1522 release_mem_region(fix->smem_start, fix->smem_len);
1523 iounmap(par->v_regs);
1524 release_mem_region(fix->mmio_start, fix->mmio_len);
1525
1526 pci_set_drvdata(pdev, NULL);
91b3a6f4
KH		 1527 if (info->pixmap.addr)
1528 kfree(info->pixmap.addr);
1da177e4
LT		 1529 kfree(info);
1530}
1531
1532static struct pci_device_id pm2fb_id_table[] = {
1533 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1534 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1535 0xff0000, 0 },
1536 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1537 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1538 0xff0000, 0 },
1539 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1540 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1541 0xff0000, 0 },
f1c15f93
KH		 1542 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1543 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1544 0xff00, 0 },
1da177e4
LT		 1545 { 0, }
1546};
1547
1548static struct pci_driver pm2fb_driver = {
1549 .name = "pm2fb",
2f7bb99f
KH		 1550 .id_table = pm2fb_id_table,
1551 .probe = pm2fb_probe,
1552 .remove = __devexit_p(pm2fb_remove),
1da177e4
LT		 1553};
1554
1555MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1556
1557
1558#ifndef MODULE
1559/**
1560 * Parse user speficied options.
1561 *
1562 * This is, comma-separated options following `video=pm2fb:'.
1563 */
1564static int __init pm2fb_setup(char *options)
1565{
1566 char* this_opt;
1567
1568 if (!options || !*options)
1569 return 0;
1570
2f7bb99f 1571 while ((this_opt = strsep(&options, ",")) != NULL) {
1da177e4
LT		 1572 if (!*this_opt)
1573 continue;
1574 if(!strcmp(this_opt, "lowhsync")) {
1575 lowhsync = 1;
1576 } else if(!strcmp(this_opt, "lowvsync")) {
1577 lowvsync = 1;
d5383fcc
KH		 1578#ifdef CONFIG_MTRR
1579 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1580 nomtrr = 1;
1581#endif
1582 } else if (!strncmp(this_opt, "noaccel", 7)) {
1583 noaccel = 1;
1da177e4
LT		 1584 } else {
1585 mode = this_opt;
1586 }
1587 }
1588 return 0;
1589}
1590#endif
1591
1592
1593static int __init pm2fb_init(void)
1594{
1595#ifndef MODULE
1596 char *option = NULL;
1597
1598 if (fb_get_options("pm2fb", &option))
1599 return -ENODEV;
1600 pm2fb_setup(option);
1601#endif
1602
1603 return pci_register_driver(&pm2fb_driver);
1604}
1605
1606module_init(pm2fb_init);
1607
1608#ifdef MODULE
1609/*
1610 * Cleanup
1611 */
1612
1613static void __exit pm2fb_exit(void)
1614{
1615 pci_unregister_driver(&pm2fb_driver);
1616}
1617#endif
1618
1619#ifdef MODULE
1620module_exit(pm2fb_exit);
1621
1622module_param(mode, charp, 0);
1623MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1624module_param(lowhsync, bool, 0);
1625MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1626module_param(lowvsync, bool, 0);
1627MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
d5383fcc
KH		 1628module_param(noaccel, bool, 0);
1629MODULE_PARM_DESC(noaccel, "Disable acceleration");
1630#ifdef CONFIG_MTRR
1631module_param(nomtrr, bool, 0);
1632MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1633#endif
1da177e4
LT		 1634
1635MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1636MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1637MODULE_LICENSE("GPL");
1638#endif
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