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1da177e4
LT		 1/* drivers/video/pvr2fb.c
2 *
3 * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
4 * Dreamcast.
5 *
6 * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
7 * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org>
8 *
9 * This file is part of the LinuxDC project (linuxdc.sourceforge.net).
10 *
11 */
12
13/*
14 * This driver is mostly based on the excellent amifb and vfb sources. It uses
15 * an odd scheme for converting hardware values to/from framebuffer values,
16 * here are some hacked-up formulas:
17 *
18 * The Dreamcast has screen offsets from each side of its four borders and
19 * the start offsets of the display window. I used these values to calculate
20 * 'pseudo' values (think of them as placeholders) for the fb video mode, so
21 * that when it came time to convert these values back into their hardware
22 * values, I could just add mode- specific offsets to get the correct mode
23 * settings:
24 *
25 * left_margin = diwstart_h - borderstart_h;
26 * right_margin = borderstop_h - (diwstart_h + xres);
27 * upper_margin = diwstart_v - borderstart_v;
28 * lower_margin = borderstop_v - (diwstart_h + yres);
29 *
30 * hsync_len = borderstart_h + (hsync_total - borderstop_h);
31 * vsync_len = borderstart_v + (vsync_total - borderstop_v);
32 *
33 * Then, when it's time to convert back to hardware settings, the only
34 * constants are the borderstart_* offsets, all other values are derived from
35 * the fb video mode:
36 *
37 * // PAL
38 * borderstart_h = 116;
39 * borderstart_v = 44;
40 * ...
41 * borderstop_h = borderstart_h + hsync_total - hsync_len;
42 * ...
43 * diwstart_v = borderstart_v - upper_margin;
44 *
45 * However, in the current implementation, the borderstart values haven't had
46 * the benefit of being fully researched, so some modes may be broken.
47 */
48
49#undef DEBUG
50
51#include <linux/module.h>
52#include <linux/kernel.h>
53#include <linux/errno.h>
54#include <linux/string.h>
55#include <linux/mm.h>
1da177e4
LT		 56#include <linux/slab.h>
57#include <linux/delay.h>
1da177e4
LT		 58#include <linux/interrupt.h>
59#include <linux/fb.h>
60#include <linux/init.h>
61#include <linux/pci.h>
62
63#ifdef CONFIG_SH_DREAMCAST
64#include <asm/machvec.h>
65#include <asm/mach/sysasic.h>
66#endif
67
68#ifdef CONFIG_SH_DMA
69#include <linux/pagemap.h>
70#include <asm/mach/dma.h>
71#include <asm/dma.h>
72#endif
73
74#ifdef CONFIG_SH_STORE_QUEUES
75#include <asm/uaccess.h>
76#include <asm/cpu/sq.h>
77#endif
78
79#ifndef PCI_DEVICE_ID_NEC_NEON250
80# define PCI_DEVICE_ID_NEC_NEON250 0x0067
81#endif
82
83/* 2D video registers */
84#define DISP_BASE par->mmio_base
85#define DISP_BRDRCOLR (DISP_BASE + 0x40)
86#define DISP_DIWMODE (DISP_BASE + 0x44)
87#define DISP_DIWADDRL (DISP_BASE + 0x50)
88#define DISP_DIWADDRS (DISP_BASE + 0x54)
89#define DISP_DIWSIZE (DISP_BASE + 0x5c)
90#define DISP_SYNCCONF (DISP_BASE + 0xd0)
91#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
92#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
93#define DISP_BRDRVERT (DISP_BASE + 0xdc)
94#define DISP_DIWCONF (DISP_BASE + 0xe8)
95#define DISP_DIWHSTRT (DISP_BASE + 0xec)
96#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
97
98/* Pixel clocks, one for TV output, doubled for VGA output */
99#define TV_CLK 74239
100#define VGA_CLK 37119
101
102/* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
103#define PAL_HTOTAL 863
104#define PAL_VTOTAL 312
105#define NTSC_HTOTAL 857
106#define NTSC_VTOTAL 262
107
108/* Supported cable types */
109enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
110
111/* Supported video output types */
112enum { VO_PAL, VO_NTSC, VO_VGA };
113
114/* Supported palette types */
115enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
116
117struct pvr2_params { unsigned int val; char *name; };
7e7ec0d4 118static struct pvr2_params cables[] __devinitdata = {
1da177e4
LT		 119 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
120};
121
7e7ec0d4 122static struct pvr2_params outputs[] __devinitdata = {
1da177e4
LT		 123 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
124};
125
126/*
127 * This describes the current video mode
128 */
129
130static struct pvr2fb_par {
131 unsigned int hsync_total; /* Clocks/line */
132 unsigned int vsync_total; /* Lines/field */
133 unsigned int borderstart_h;
134 unsigned int borderstop_h;
135 unsigned int borderstart_v;
136 unsigned int borderstop_v;
137 unsigned int diwstart_h; /* Horizontal offset of the display field */
138 unsigned int diwstart_v; /* Vertical offset of the display field, for
139 interlaced modes, this is the long field */
140 unsigned long disp_start; /* Address of image within VRAM */
141 unsigned char is_interlaced; /* Is the display interlaced? */
142 unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
143 unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
144
145 unsigned long mmio_base; /* MMIO base */
146} *currentpar;
147
148static struct fb_info *fb_info;
149
e9705a77 150static struct fb_fix_screeninfo pvr2_fix __devinitdata = {
1da177e4 151 .id = "NEC PowerVR2",
e9705a77
PM		 152 .type = FB_TYPE_PACKED_PIXELS,
153 .visual = FB_VISUAL_TRUECOLOR,
1da177e4
LT		 154 .ypanstep = 1,
155 .ywrapstep = 1,
e9705a77 156 .accel = FB_ACCEL_NONE,
1da177e4
LT		 157};
158
e9705a77 159static struct fb_var_screeninfo pvr2_var __devinitdata = {
1da177e4
LT		 160 .xres = 640,
161 .yres = 480,
162 .xres_virtual = 640,
163 .yres_virtual = 480,
164 .bits_per_pixel =16,
165 .red = { 11, 5, 0 },
166 .green = { 5, 6, 0 },
167 .blue = { 0, 5, 0 },
168 .activate = FB_ACTIVATE_NOW,
169 .height = -1,
170 .width = -1,
171 .vmode = FB_VMODE_NONINTERLACED,
172};
173
174static int cable_type = CT_VGA;
175static int video_output = VO_VGA;
176
177static int nopan = 0;
178static int nowrap = 1;
179
180/*
181 * We do all updating, blanking, etc. during the vertical retrace period
182 */
183static unsigned int do_vmode_full = 0; /* Change the video mode */
184static unsigned int do_vmode_pan = 0; /* Update the video mode */
185static short do_blank = 0; /* (Un)Blank the screen */
186
187static unsigned int is_blanked = 0; /* Is the screen blanked? */
188
189#ifdef CONFIG_SH_STORE_QUEUES
d2b06a8b 190static unsigned long pvr2fb_map;
1da177e4
LT		 191#endif
192
193#ifdef CONFIG_SH_DMA
194static unsigned int shdma = PVR2_CASCADE_CHAN;
195static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
196#endif
197
1da177e4
LT		 198static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
199 unsigned int transp, struct fb_info *info);
200static int pvr2fb_blank(int blank, struct fb_info *info);
201static unsigned long get_line_length(int xres_virtual, int bpp);
202static void set_color_bitfields(struct fb_var_screeninfo *var);
203static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
204static int pvr2fb_set_par(struct fb_info *info);
205static void pvr2_update_display(struct fb_info *info);
206static void pvr2_init_display(struct fb_info *info);
207static void pvr2_do_blank(void);
7d12e780 208static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
1da177e4
LT		 209static int pvr2_init_cable(void);
210static int pvr2_get_param(const struct pvr2_params *p, const char *s,
211 int val, int size);
d2b06a8b 212#ifdef CONFIG_SH_DMA
3f9b0880 213static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4 214 size_t count, loff_t *ppos);
d2b06a8b 215#endif
1da177e4
LT		 216
217static struct fb_ops pvr2fb_ops = {
d2b06a8b
PM		 218 .owner = THIS_MODULE,
219 .fb_setcolreg = pvr2fb_setcolreg,
220 .fb_blank = pvr2fb_blank,
221 .fb_check_var = pvr2fb_check_var,
222 .fb_set_par = pvr2fb_set_par,
1da177e4
LT		 223#ifdef CONFIG_SH_DMA
224 .fb_write = pvr2fb_write,
225#endif
e9705a77 226 .fb_fillrect = cfb_fillrect,
1da177e4
LT		 227 .fb_copyarea = cfb_copyarea,
228 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 229};
230
7e7ec0d4 231static struct fb_videomode pvr2_modedb[] __devinitdata = {
1da177e4
LT		 232 /*
233 * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
234 * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
235 * NTSC, so it shouldn't be a problem (I hope).
236 */
237
238 {
239 /* 640x480 @ 60Hz interlaced (NTSC) */
240 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
241 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
242 }, {
243 /* 640x240 @ 60Hz (NTSC) */
244 /* XXX: Broken! Don't use... */
245 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
246 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
247 }, {
248 /* 640x480 @ 60hz (VGA) */
249 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
250 0, FB_VMODE_YWRAP
e9705a77 251 },
1da177e4
LT		 252};
253
254#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
255
256#define DEFMODE_NTSC 0
257#define DEFMODE_PAL 0
258#define DEFMODE_VGA 2
259
260static int defmode = DEFMODE_NTSC;
7e7ec0d4 261static char *mode_option __devinitdata = NULL;
1da177e4
LT		 262
263static inline void pvr2fb_set_pal_type(unsigned int type)
264{
265 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
266
267 fb_writel(type, par->mmio_base + 0x108);
268}
269
270static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
271 unsigned int regno,
272 unsigned int val)
273{
274 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
275}
276
277static int pvr2fb_blank(int blank, struct fb_info *info)
278{
279 do_blank = blank ? blank : -1;
280 return 0;
281}
282
283static inline unsigned long get_line_length(int xres_virtual, int bpp)
284{
285 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
286}
287
288static void set_color_bitfields(struct fb_var_screeninfo *var)
289{
290 switch (var->bits_per_pixel) {
291 case 16: /* RGB 565 */
e9705a77 292 pvr2fb_set_pal_type(PAL_RGB565);
1da177e4
LT		 293 var->red.offset = 11; var->red.length = 5;
294 var->green.offset = 5; var->green.length = 6;
295 var->blue.offset = 0; var->blue.length = 5;
296 var->transp.offset = 0; var->transp.length = 0;
297 break;
298 case 24: /* RGB 888 */
299 var->red.offset = 16; var->red.length = 8;
300 var->green.offset = 8; var->green.length = 8;
301 var->blue.offset = 0; var->blue.length = 8;
302 var->transp.offset = 0; var->transp.length = 0;
303 break;
304 case 32: /* ARGB 8888 */
e9705a77 305 pvr2fb_set_pal_type(PAL_ARGB8888);
1da177e4
LT		 306 var->red.offset = 16; var->red.length = 8;
307 var->green.offset = 8; var->green.length = 8;
308 var->blue.offset = 0; var->blue.length = 8;
309 var->transp.offset = 24; var->transp.length = 8;
310 break;
311 }
312}
313
314static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
315 unsigned int green, unsigned int blue,
316 unsigned int transp, struct fb_info *info)
317{
318 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
319 unsigned int tmp;
320
321 if (regno > info->cmap.len)
322 return 1;
323
324 /*
325 * We only support the hardware palette for 16 and 32bpp. It's also
326 * expected that the palette format has been set by the time we get
327 * here, so we don't waste time setting it again.
328 */
329 switch (info->var.bits_per_pixel) {
330 case 16: /* RGB 565 */
331 tmp = (red & 0xf800) |
332 ((green & 0xfc00) >> 5) |
333 ((blue & 0xf800) >> 11);
334
335 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 336 break;
337 case 24: /* RGB 888 */
338 red >>= 8; green >>= 8; blue >>= 8;
a66ad56e 339 tmp = (red << 16) | (green << 8) | blue;
1da177e4
LT		 340 break;
341 case 32: /* ARGB 8888 */
342 red >>= 8; green >>= 8; blue >>= 8;
343 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
344
345 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 346 break;
347 default:
348 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
349 return 1;
350 }
351
a66ad56e
AD		 352 if (regno < 16)
353 ((u32*)(info->pseudo_palette))[regno] = tmp;
354
1da177e4
LT		 355 return 0;
356}
357
358static int pvr2fb_set_par(struct fb_info *info)
359{
360 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
361 struct fb_var_screeninfo *var = &info->var;
362 unsigned long line_length;
363 unsigned int vtotal;
364
365 /*
366 * XXX: It's possible that a user could use a VGA box, change the cable
367 * type in hardware (i.e. switch from VGA<->composite), then change
368 * modes (i.e. switching to another VT). If that happens we should
369 * automagically change the output format to cope, but currently I
370 * don't have a VGA box to make sure this works properly.
371 */
372 cable_type = pvr2_init_cable();
373 if (cable_type == CT_VGA && video_output != VO_VGA)
374 video_output = VO_VGA;
375
376 var->vmode &= FB_VMODE_MASK;
377 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
378 par->is_interlaced = 1;
e9705a77 379 /*
1da177e4
LT		 380 * XXX: Need to be more creative with this (i.e. allow doublecan for
381 * PAL/NTSC output).
382 */
383 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
384 par->is_doublescan = 1;
e9705a77 385
1da177e4
LT		 386 par->hsync_total = var->left_margin + var->xres + var->right_margin +
387 var->hsync_len;
388 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
389 var->vsync_len;
390
391 if (var->sync & FB_SYNC_BROADCAST) {
392 vtotal = par->vsync_total;
393 if (par->is_interlaced)
394 vtotal /= 2;
395 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
396 /* XXX: Check for start values here... */
397 /* XXX: Check hardware for PAL-compatibility */
398 par->borderstart_h = 116;
399 par->borderstart_v = 44;
400 } else {
401 /* NTSC video output */
402 par->borderstart_h = 126;
403 par->borderstart_v = 18;
404 }
405 } else {
406 /* VGA mode */
407 /* XXX: What else needs to be checked? */
e9705a77 408 /*
1da177e4
LT		 409 * XXX: We have a little freedom in VGA modes, what ranges
410 * should be here (i.e. hsync/vsync totals, etc.)?
411 */
412 par->borderstart_h = 126;
413 par->borderstart_v = 40;
414 }
415
416 /* Calculate the remainding offsets */
417 par->diwstart_h = par->borderstart_h + var->left_margin;
418 par->diwstart_v = par->borderstart_v + var->upper_margin;
e9705a77
PM		 419 par->borderstop_h = par->diwstart_h + var->xres +
420 var->right_margin;
1da177e4
LT		 421 par->borderstop_v = par->diwstart_v + var->yres +
422 var->lower_margin;
423
424 if (!par->is_interlaced)
425 par->borderstop_v /= 2;
426 if (info->var.xres < 640)
427 par->is_lowres = 1;
428
429 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
430 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
431 info->fix.line_length = line_length;
432 return 0;
433}
434
435static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
436{
437 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
438 unsigned int vtotal, hsync_total;
439 unsigned long line_length;
440
441 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
442 pr_debug("Invalid pixclock value %d\n", var->pixclock);
443 return -EINVAL;
444 }
445
446 if (var->xres < 320)
447 var->xres = 320;
448 if (var->yres < 240)
449 var->yres = 240;
450 if (var->xres_virtual < var->xres)
451 var->xres_virtual = var->xres;
452 if (var->yres_virtual < var->yres)
453 var->yres_virtual = var->yres;
454
455 if (var->bits_per_pixel <= 16)
456 var->bits_per_pixel = 16;
457 else if (var->bits_per_pixel <= 24)
458 var->bits_per_pixel = 24;
459 else if (var->bits_per_pixel <= 32)
460 var->bits_per_pixel = 32;
461
462 set_color_bitfields(var);
463
464 if (var->vmode & FB_VMODE_YWRAP) {
e9705a77 465 if (var->xoffset || var->yoffset < 0 ||
1da177e4
LT		 466 var->yoffset >= var->yres_virtual) {
467 var->xoffset = var->yoffset = 0;
468 } else {
469 if (var->xoffset > var->xres_virtual - var->xres ||
e9705a77 470 var->yoffset > var->yres_virtual - var->yres ||
1da177e4
LT		 471 var->xoffset < 0 || var->yoffset < 0)
472 var->xoffset = var->yoffset = 0;
473 }
474 } else {
475 var->xoffset = var->yoffset = 0;
476 }
477
e9705a77 478 /*
1da177e4
LT		 479 * XXX: Need to be more creative with this (i.e. allow doublecan for
480 * PAL/NTSC output).
481 */
482 if (var->yres < 480 && video_output == VO_VGA)
483 var->vmode |= FB_VMODE_DOUBLE;
484
485 if (video_output != VO_VGA) {
486 var->sync |= FB_SYNC_BROADCAST;
487 var->vmode |= FB_VMODE_INTERLACED;
488 } else {
489 var->sync &= ~FB_SYNC_BROADCAST;
490 var->vmode &= ~FB_VMODE_INTERLACED;
491 var->vmode |= pvr2_var.vmode;
492 }
493
494 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
495 var->right_margin = par->borderstop_h -
496 (par->diwstart_h + var->xres);
497 var->left_margin = par->diwstart_h - par->borderstart_h;
498 var->hsync_len = par->borderstart_h +
499 (par->hsync_total - par->borderstop_h);
500
501 var->upper_margin = par->diwstart_v - par->borderstart_v;
502 var->lower_margin = par->borderstop_v -
503 (par->diwstart_v + var->yres);
504 var->vsync_len = par->borderstop_v +
505 (par->vsync_total - par->borderstop_v);
506 }
e9705a77 507
1da177e4
LT		 508 hsync_total = var->left_margin + var->xres + var->right_margin +
509 var->hsync_len;
510 vtotal = var->upper_margin + var->yres + var->lower_margin +
511 var->vsync_len;
512
513 if (var->sync & FB_SYNC_BROADCAST) {
514 if (var->vmode & FB_VMODE_INTERLACED)
515 vtotal /= 2;
516 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
517 /* PAL video output */
518 /* XXX: Should be using a range here ... ? */
519 if (hsync_total != PAL_HTOTAL) {
520 pr_debug("invalid hsync total for PAL\n");
521 return -EINVAL;
522 }
523 } else {
524 /* NTSC video output */
525 if (hsync_total != NTSC_HTOTAL) {
526 pr_debug("invalid hsync total for NTSC\n");
527 return -EINVAL;
528 }
529 }
530 }
e9705a77 531
1da177e4
LT		 532 /* Check memory sizes */
533 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
534 if (line_length * var->yres_virtual > info->fix.smem_len)
535 return -ENOMEM;
536
537 return 0;
538}
539
540static void pvr2_update_display(struct fb_info *info)
541{
542 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
543 struct fb_var_screeninfo *var = &info->var;
544
545 /* Update the start address of the display image */
546 fb_writel(par->disp_start, DISP_DIWADDRL);
547 fb_writel(par->disp_start +
548 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
549 DISP_DIWADDRS);
550}
551
e9705a77 552/*
1da177e4
LT		 553 * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
554 * very stable. It's probably due to the fact that a lot of the 2D video
555 * registers are still undocumented.
556 */
557
558static void pvr2_init_display(struct fb_info *info)
559{
560 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
561 struct fb_var_screeninfo *var = &info->var;
562 unsigned int diw_height, diw_width, diw_modulo = 1;
563 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
564
565 /* hsync and vsync totals */
566 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
567
568 /* column height, modulo, row width */
569 /* since we're "panning" within vram, we need to offset things based
570 * on the offset from the virtual x start to our real gfx. */
571 if (video_output != VO_VGA && par->is_interlaced)
572 diw_modulo += info->fix.line_length / 4;
573 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
574 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
575 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
576 DISP_DIWSIZE);
577
578 /* display address, long and short fields */
579 fb_writel(par->disp_start, DISP_DIWADDRL);
580 fb_writel(par->disp_start +
581 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
582 DISP_DIWADDRS);
583
584 /* border horizontal, border vertical, border color */
585 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
586 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
587 fb_writel(0, DISP_BRDRCOLR);
588
589 /* display window start position */
590 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
591 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
e9705a77 592
1da177e4
LT		 593 /* misc. settings */
594 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
595
596 /* clock doubler (for VGA), scan doubler, display enable */
e9705a77 597 fb_writel(((video_output == VO_VGA) << 23) |
1da177e4
LT		 598 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
599
600 /* bits per pixel */
601 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
602
e9705a77 603 /* video enable, color sync, interlace,
1da177e4
LT		 604 * hsync and vsync polarity (currently unused) */
605 fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
606}
607
608/* Simulate blanking by making the border cover the entire screen */
609
610#define BLANK_BIT (1<<3)
611
612static void pvr2_do_blank(void)
613{
614 struct pvr2fb_par *par = currentpar;
615 unsigned long diwconf;
616
617 diwconf = fb_readl(DISP_DIWCONF);
618 if (do_blank > 0)
619 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
620 else
621 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
622
623 is_blanked = do_blank > 0 ? do_blank : 0;
624}
625
7d12e780 626static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
1da177e4
LT		 627{
628 struct fb_info *info = dev_id;
629
630 if (do_vmode_pan || do_vmode_full)
631 pvr2_update_display(info);
632 if (do_vmode_full)
633 pvr2_init_display(info);
634 if (do_vmode_pan)
635 do_vmode_pan = 0;
636 if (do_vmode_full)
637 do_vmode_full = 0;
638 if (do_blank) {
639 pvr2_do_blank();
640 do_blank = 0;
641 }
642 return IRQ_HANDLED;
643}
644
645/*
646 * Determine the cable type and initialize the cable output format. Don't do
647 * anything if the cable type has been overidden (via "cable:XX").
648 */
649
650#define PCTRA 0xff80002c
651#define PDTRA 0xff800030
652#define VOUTC 0xa0702c00
653
654static int pvr2_init_cable(void)
655{
656 if (cable_type < 0) {
e9705a77 657 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
1da177e4
LT		 658 PCTRA);
659 cable_type = (fb_readw(PDTRA) >> 8) & 3;
660 }
661
662 /* Now select the output format (either composite or other) */
663 /* XXX: Save the previous val first, as this reg is also AICA
664 related */
665 if (cable_type == CT_COMPOSITE)
666 fb_writel(3 << 8, VOUTC);
667 else
668 fb_writel(0, VOUTC);
669
670 return cable_type;
671}
672
673#ifdef CONFIG_SH_DMA
3f9b0880 674static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4
LT		 675 size_t count, loff_t *ppos)
676{
677 unsigned long dst, start, end, len;
678 unsigned int nr_pages;
679 struct page **pages;
680 int ret, i;
681
682 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
683
684 pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
685 if (!pages)
686 return -ENOMEM;
e9705a77 687
1da177e4
LT		 688 down_read(&current->mm->mmap_sem);
689 ret = get_user_pages(current, current->mm, (unsigned long)buf,
690 nr_pages, WRITE, 0, pages, NULL);
691 up_read(&current->mm->mmap_sem);
692
693 if (ret < nr_pages) {
694 nr_pages = ret;
695 ret = -EINVAL;
696 goto out_unmap;
697 }
698
699 dma_configure_channel(shdma, 0x12c1);
e9705a77 700
1da177e4
LT		 701 dst = (unsigned long)fb_info->screen_base + *ppos;
702 start = (unsigned long)page_address(pages[0]);
703 end = (unsigned long)page_address(pages[nr_pages]);
704 len = nr_pages << PAGE_SHIFT;
705
706 /* Half-assed contig check */
707 if (start + len == end) {
708 /* As we do this in one shot, it's either all or nothing.. */
709 if ((*ppos + len) > fb_info->fix.smem_len) {
710 ret = -ENOSPC;
711 goto out_unmap;
712 }
713
714 dma_write(shdma, start, 0, len);
715 dma_write(pvr2dma, 0, dst, len);
716 dma_wait_for_completion(pvr2dma);
717
718 goto out;
719 }
720
721 /* Not contiguous, writeout per-page instead.. */
722 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
723 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
724 ret = -ENOSPC;
725 goto out_unmap;
726 }
727
728 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
729 dma_write_page(pvr2dma, 0, dst);
730 dma_wait_for_completion(pvr2dma);
731 }
732
733out:
734 *ppos += count;
735 ret = count;
736
737out_unmap:
738 for (i = 0; i < nr_pages; i++)
739 page_cache_release(pages[i]);
740
741 kfree(pages);
742
743 return ret;
e9705a77 744}
1da177e4
LT		 745#endif /* CONFIG_SH_DMA */
746
747/**
748 * pvr2fb_common_init
749 *
750 * Common init code for the PVR2 chips.
751 *
752 * This mostly takes care of the common aspects of the fb setup and
753 * registration. It's expected that the board-specific init code has
754 * already setup pvr2_fix with something meaningful at this point.
755 *
756 * Device info reporting is also done here, as well as picking a sane
757 * default from the modedb. For board-specific modelines, simply define
758 * a per-board modedb.
759 *
760 * Also worth noting is that the cable and video output types are likely
761 * always going to be VGA for the PCI-based PVR2 boards, but we leave this
762 * in for flexibility anyways. Who knows, maybe someone has tv-out on a
763 * PCI-based version of these things ;-)
764 */
7e7ec0d4 765static int __devinit pvr2fb_common_init(void)
1da177e4
LT		 766{
767 struct pvr2fb_par *par = currentpar;
768 unsigned long modememused, rev;
769
770 fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
771 pvr2_fix.smem_len);
e9705a77 772
1da177e4
LT		 773 if (!fb_info->screen_base) {
774 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
775 goto out_err;
776 }
777
778 par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
e9705a77 779 pvr2_fix.mmio_len);
1da177e4
LT		 780 if (!par->mmio_base) {
781 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
782 goto out_err;
783 }
784
d2b06a8b 785 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
1da177e4
LT		 786
787 pvr2_fix.ypanstep = nopan ? 0 : 1;
788 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
789
790 fb_info->fbops = &pvr2fb_ops;
791 fb_info->fix = pvr2_fix;
792 fb_info->par = currentpar;
793 fb_info->pseudo_palette = (void *)(fb_info->par + 1);
794 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
795
796 if (video_output == VO_VGA)
797 defmode = DEFMODE_VGA;
798
799 if (!mode_option)
800 mode_option = "640x480@60";
801
802 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
803 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
804 fb_info->var = pvr2_var;
805
806 fb_alloc_cmap(&fb_info->cmap, 256, 0);
807
808 if (register_framebuffer(fb_info) < 0)
809 goto out_err;
810
811 modememused = get_line_length(fb_info->var.xres_virtual,
812 fb_info->var.bits_per_pixel);
813 modememused *= fb_info->var.yres_virtual;
814
815 rev = fb_readl(par->mmio_base + 0x04);
816
817 printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
818 fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
819 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
e9705a77 820 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
1da177e4 821 fb_info->node, fb_info->var.xres, fb_info->var.yres,
d2b06a8b 822 fb_info->var.bits_per_pixel,
1da177e4
LT		 823 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
824 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
825 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
826
827#ifdef CONFIG_SH_STORE_QUEUES
828 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
829
830 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
d2b06a8b 831 fb_info->fix.id, pgprot_val(PAGE_SHARED));
1da177e4
LT		 832
833 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
d2b06a8b 834 fb_info->node, pvr2fb_map);
1da177e4
LT		 835#endif
836
837 return 0;
838
839out_err:
840 if (fb_info->screen_base)
841 iounmap(fb_info->screen_base);
842 if (par->mmio_base)
843 iounmap((void *)par->mmio_base);
844
845 return -ENXIO;
846}
847
848#ifdef CONFIG_SH_DREAMCAST
849static int __init pvr2fb_dc_init(void)
850{
851 if (!mach_is_dreamcast())
852 return -ENXIO;
853
854 /* Make a guess at the monitor based on the attached cable */
855 if (pvr2_init_cable() == CT_VGA) {
856 fb_info->monspecs.hfmin = 30000;
857 fb_info->monspecs.hfmax = 70000;
858 fb_info->monspecs.vfmin = 60;
859 fb_info->monspecs.vfmax = 60;
860 } else {
861 /* Not VGA, using a TV (taken from acornfb) */
862 fb_info->monspecs.hfmin = 15469;
863 fb_info->monspecs.hfmax = 15781;
864 fb_info->monspecs.vfmin = 49;
865 fb_info->monspecs.vfmax = 51;
866 }
867
868 /*
869 * XXX: This needs to pull default video output via BIOS or other means
870 */
871 if (video_output < 0) {
872 if (cable_type == CT_VGA) {
873 video_output = VO_VGA;
874 } else {
875 video_output = VO_NTSC;
876 }
877 }
e9705a77
PM		 878
879 /*
1da177e4
LT		 880 * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
881 */
882 pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
883 pvr2_fix.smem_len = 8 << 20;
884
885 pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
886 pvr2_fix.mmio_len = 0x2000;
887
888 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, 0,
889 "pvr2 VBL handler", fb_info)) {
890 return -EBUSY;
891 }
892
893#ifdef CONFIG_SH_DMA
894 if (request_dma(pvr2dma, "pvr2") != 0) {
895 free_irq(HW_EVENT_VSYNC, 0);
896 return -EBUSY;
897 }
898#endif
899
900 return pvr2fb_common_init();
901}
902
e9705a77 903static void __exit pvr2fb_dc_exit(void)
1da177e4 904{
295a1b47
AL		 905 if (fb_info->screen_base) {
906 iounmap(fb_info->screen_base);
907 fb_info->screen_base = NULL;
908 }
909 if (currentpar->mmio_base) {
910 iounmap((void *)currentpar->mmio_base);
911 currentpar->mmio_base = 0;
912 }
913
1da177e4
LT		 914 free_irq(HW_EVENT_VSYNC, 0);
915#ifdef CONFIG_SH_DMA
916 free_dma(pvr2dma);
917#endif
918}
919#endif /* CONFIG_SH_DREAMCAST */
920
921#ifdef CONFIG_PCI
922static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev,
923 const struct pci_device_id *ent)
924{
925 int ret;
926
927 ret = pci_enable_device(pdev);
928 if (ret) {
929 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
930 return ret;
931 }
932
933 ret = pci_request_regions(pdev, "pvr2fb");
934 if (ret) {
935 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
936 return ret;
937 }
938
939 /*
940 * Slightly more exciting than the DC PVR2 .. 16MiB!
941 */
942 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
943 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
944
945 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
946 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
947
948 fb_info->device = &pdev->dev;
949
950 return pvr2fb_common_init();
951}
952
953static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev)
954{
295a1b47
AL		 955 if (fb_info->screen_base) {
956 iounmap(fb_info->screen_base);
957 fb_info->screen_base = NULL;
958 }
959 if (currentpar->mmio_base) {
960 iounmap((void *)currentpar->mmio_base);
961 currentpar->mmio_base = 0;
962 }
963
1da177e4
LT		 964 pci_release_regions(pdev);
965}
966
967static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = {
968 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
970 { 0, },
971};
972
973MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
974
975static struct pci_driver pvr2fb_pci_driver = {
976 .name = "pvr2fb",
977 .id_table = pvr2fb_pci_tbl,
978 .probe = pvr2fb_pci_probe,
979 .remove = __devexit_p(pvr2fb_pci_remove),
980};
981
982static int __init pvr2fb_pci_init(void)
983{
984 return pci_register_driver(&pvr2fb_pci_driver);
985}
986
e9705a77 987static void __exit pvr2fb_pci_exit(void)
1da177e4
LT		 988{
989 pci_unregister_driver(&pvr2fb_pci_driver);
990}
991#endif /* CONFIG_PCI */
992
7e7ec0d4 993static int __devinit pvr2_get_param(const struct pvr2_params *p, const char *s,
1da177e4
LT		 994 int val, int size)
995{
996 int i;
997
998 for (i = 0 ; i < size ; i++ ) {
999 if (s != NULL) {
1000 if (!strnicmp(p[i].name, s, strlen(s)))
1001 return p[i].val;
1002 } else {
1003 if (p[i].val == val)
1004 return (int)p[i].name;
1005 }
1006 }
1007 return -1;
1008}
1009
1010/*
1011 * Parse command arguments. Supported arguments are:
1012 * inverse Use inverse color maps
1013 * cable:composite|rgb|vga Override the video cable type
1014 * output:NTSC|PAL|VGA Override the video output format
1015 *
1016 * <xres>x<yres>[-<bpp>][@<refresh>] or,
1017 * <name>[-<bpp>][@<refresh>] Startup using this video mode
1018 */
1019
1020#ifndef MODULE
e9705a77 1021static int __init pvr2fb_setup(char *options)
1da177e4
LT		 1022{
1023 char *this_opt;
1024 char cable_arg[80];
1025 char output_arg[80];
1026
1027 if (!options || !*options)
1028 return 0;
1029
1030 while ((this_opt = strsep(&options, ","))) {
1031 if (!*this_opt)
1032 continue;
1033 if (!strcmp(this_opt, "inverse")) {
1034 fb_invert_cmaps();
1035 } else if (!strncmp(this_opt, "cable:", 6)) {
1036 strcpy(cable_arg, this_opt + 6);
1037 } else if (!strncmp(this_opt, "output:", 7)) {
1038 strcpy(output_arg, this_opt + 7);
1039 } else if (!strncmp(this_opt, "nopan", 5)) {
1040 nopan = 1;
1041 } else if (!strncmp(this_opt, "nowrap", 6)) {
1042 nowrap = 1;
1043 } else {
1044 mode_option = this_opt;
1045 }
1046 }
1047
1048 if (*cable_arg)
1049 cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
1050 if (*output_arg)
1051 video_output = pvr2_get_param(outputs, output_arg, 0, 3);
1052
1053 return 0;
1054}
1055#endif
1056
1057static struct pvr2_board {
1058 int (*init)(void);
1059 void (*exit)(void);
1060 char name[16];
e9705a77 1061} board_driver[] = {
1da177e4
LT		 1062#ifdef CONFIG_SH_DREAMCAST
1063 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1064#endif
1065#ifdef CONFIG_PCI
1066 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1067#endif
1068 { 0, },
1069};
1070
e9705a77 1071static int __init pvr2fb_init(void)
1da177e4
LT		 1072{
1073 int i, ret = -ENODEV;
1074 int size;
1075
1076#ifndef MODULE
1077 char *option = NULL;
1078
1079 if (fb_get_options("pvr2fb", &option))
1080 return -ENODEV;
1081 pvr2fb_setup(option);
1082#endif
1083 size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
1084
dd00cc48 1085 fb_info = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1086 if (!fb_info) {
1087 printk(KERN_ERR "Failed to allocate memory for fb_info\n");
1088 return -ENOMEM;
1089 }
1090
1da177e4
LT		 1091
1092 currentpar = (struct pvr2fb_par *)(fb_info + 1);
1093
e9705a77
PM		 1094 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1095 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1096
1097 if (!pvr_board->init)
1098 continue;
1099
1100 ret = pvr_board->init();
1101
1102 if (ret != 0) {
1103 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1104 pvr_board->name);
1105 kfree(fb_info);
1106 break;
1107 }
1108 }
1109
1110 return ret;
1111}
1112
1113static void __exit pvr2fb_exit(void)
1114{
1115 int i;
1116
e9705a77
PM		 1117 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1118 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1119
1120 if (pvr_board->exit)
1121 pvr_board->exit();
1122 }
e9705a77 1123
1da177e4
LT		 1124#ifdef CONFIG_SH_STORE_QUEUES
1125 sq_unmap(pvr2fb_map);
1126#endif
1127
1128 unregister_framebuffer(fb_info);
1129 kfree(fb_info);
1130}
1131
1132module_init(pvr2fb_init);
1133module_exit(pvr2fb_exit);
1134
1135MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1136MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1137MODULE_LICENSE("GPL");
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