[mirror_ubuntu-artful-kernel.git] / drivers / video / pxa3xx-gcu.c

/*
 *  pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers
 *
 *  This driver needs a DirectFB counterpart in user space, communication
 *  is handled via mmap()ed memory areas and an ioctl.
 *
 *  Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 *  Copyright (c) 2009 Janine Kropp <nin@directfb.org>
 *  Copyright (c) 2009 Denis Oliver Kropp <dok@directfb.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/*
 * WARNING: This controller is attached to System Bus 2 of the PXA which
 * needs its arbiter to be enabled explicitly (CKENB & 1<<9).
 * There is currently no way to do this from Linux, so you need to teach
 * your bootloader for now.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/ioctl.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/fs.h>
#include <linux/io.h>

#include "pxa3xx-gcu.h"

#define DRV_NAME	"pxa3xx-gcu"
#define MISCDEV_MINOR	197

#define REG_GCCR	0x00
#define GCCR_SYNC_CLR	(1 << 9)
#define GCCR_BP_RST	(1 << 8)
#define GCCR_ABORT	(1 << 6)
#define GCCR_STOP	(1 << 4)

#define REG_GCISCR	0x04
#define REG_GCIECR	0x08
#define REG_GCRBBR	0x20
#define REG_GCRBLR	0x24
#define REG_GCRBHR	0x28
#define REG_GCRBTR	0x2C
#define REG_GCRBEXHR	0x30

#define IE_EOB		(1 << 0)
#define IE_EEOB		(1 << 5)
#define IE_ALL		0xff

#define SHARED_SIZE	PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared))

/* #define PXA3XX_GCU_DEBUG */
/* #define PXA3XX_GCU_DEBUG_TIMER */

#ifdef PXA3XX_GCU_DEBUG
#define QDUMP(msg)					\
	do {						\
		QPRINT(priv, KERN_DEBUG, msg);		\
	} while (0)
#else
#define QDUMP(msg)	do {} while (0)
#endif

#define QERROR(msg)					\
	do {						\
		QPRINT(priv, KERN_ERR, msg);		\
	} while (0)

struct pxa3xx_gcu_batch {
	struct pxa3xx_gcu_batch *next;
	u32			*ptr;
	dma_addr_t		 phys;
	unsigned long		 length;
};

struct pxa3xx_gcu_priv {
	void __iomem		 *mmio_base;
	struct clk		 *clk;
	struct pxa3xx_gcu_shared *shared;
	dma_addr_t		  shared_phys;
	struct resource		 *resource_mem;
	struct miscdevice	  misc_dev;
	wait_queue_head_t	  wait_idle;
	wait_queue_head_t	  wait_free;
	spinlock_t		  spinlock;
	struct timeval 		  base_time;

	struct pxa3xx_gcu_batch *free;
	struct pxa3xx_gcu_batch *ready;
	struct pxa3xx_gcu_batch *ready_last;
	struct pxa3xx_gcu_batch *running;
};

static inline unsigned long
gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off)
{
	return __raw_readl(priv->mmio_base + off);
}

static inline void
gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val)
{
	__raw_writel(val, priv->mmio_base + off);
}

#define QPRINT(priv, level, msg)					\
	do {								\
		struct timeval tv;					\
		struct pxa3xx_gcu_shared *shared = priv->shared;	\
		u32 base = gc_readl(priv, REG_GCRBBR);			\
									\
		do_gettimeofday(&tv);					\
									\
		printk(level "%ld.%03ld.%03ld - %-17s: %-21s (%s, "	\
			"STATUS "					\
			"0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, "	\
			"T %5ld)\n",					\
			tv.tv_sec - priv->base_time.tv_sec,		\
			tv.tv_usec / 1000, tv.tv_usec % 1000,		\
			__func__, msg,					\
			shared->hw_running ? "running" : "   idle",	\
			gc_readl(priv, REG_GCISCR),			\
			gc_readl(priv, REG_GCRBBR),			\
			gc_readl(priv, REG_GCRBLR),			\
			(gc_readl(priv, REG_GCRBEXHR) - base) / 4,	\
			(gc_readl(priv, REG_GCRBHR) - base) / 4,	\
			(gc_readl(priv, REG_GCRBTR) - base) / 4);	\
	} while (0)

static void
pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv)
{
	QDUMP("RESET");

	/* disable interrupts */
	gc_writel(priv, REG_GCIECR, 0);

	/* reset hardware */
	gc_writel(priv, REG_GCCR, GCCR_ABORT);
	gc_writel(priv, REG_GCCR, 0);

	memset(priv->shared, 0, SHARED_SIZE);
	priv->shared->buffer_phys = priv->shared_phys;
	priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC;

	do_gettimeofday(&priv->base_time);

	/* set up the ring buffer pointers */
	gc_writel(priv, REG_GCRBLR, 0);
	gc_writel(priv, REG_GCRBBR, priv->shared_phys);
	gc_writel(priv, REG_GCRBTR, priv->shared_phys);

	/* enable all IRQs except EOB */
	gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB);
}

static void
dump_whole_state(struct pxa3xx_gcu_priv *priv)
{
	struct pxa3xx_gcu_shared *sh = priv->shared;
	u32 base = gc_readl(priv, REG_GCRBBR);

	QDUMP("DUMP");

	printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n"
		"%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n",
		sh->hw_running ? "running" : "idle   ",
		gc_readl(priv, REG_GCISCR),
		gc_readl(priv, REG_GCRBBR),
		gc_readl(priv, REG_GCRBLR),
		(gc_readl(priv, REG_GCRBEXHR) - base) / 4,
		(gc_readl(priv, REG_GCRBHR) - base) / 4,
		(gc_readl(priv, REG_GCRBTR) - base) / 4);
}

static void
flush_running(struct pxa3xx_gcu_priv *priv)
{
	struct pxa3xx_gcu_batch *running = priv->running;
	struct pxa3xx_gcu_batch *next;

	while (running) {
		next = running->next;
		running->next = priv->free;
		priv->free = running;
		running = next;
	}

	priv->running = NULL;
}

static void
run_ready(struct pxa3xx_gcu_priv *priv)
{
	unsigned int num = 0;
	struct pxa3xx_gcu_shared *shared = priv->shared;
	struct pxa3xx_gcu_batch	*ready = priv->ready;

	QDUMP("Start");

	BUG_ON(!ready);

	shared->buffer[num++] = 0x05000000;

	while (ready) {
		shared->buffer[num++] = 0x00000001;
		shared->buffer[num++] = ready->phys;
		ready = ready->next;
	}

	shared->buffer[num++] = 0x05000000;
	priv->running = priv->ready;
	priv->ready = priv->ready_last = NULL;
	gc_writel(priv, REG_GCRBLR, 0);
	shared->hw_running = 1;

	/* ring base address */
	gc_writel(priv, REG_GCRBBR, shared->buffer_phys);

	/* ring tail address */
	gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4);

	/* ring length */
	gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4);
}

static irqreturn_t
pxa3xx_gcu_handle_irq(int irq, void *ctx)
{
	struct pxa3xx_gcu_priv *priv = ctx;
	struct pxa3xx_gcu_shared *shared = priv->shared;
	u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL;

	QDUMP("-Interrupt");

	if (!status)
		return IRQ_NONE;

	spin_lock(&priv->spinlock);
	shared->num_interrupts++;

	if (status & IE_EEOB) {
		QDUMP(" [EEOB]");

		flush_running(priv);
		wake_up_all(&priv->wait_free);

		if (priv->ready) {
			run_ready(priv);
		} else {
			/* There is no more data prepared by the userspace.
			 * Set hw_running = 0 and wait for the next userspace
			 * kick-off */
			shared->num_idle++;
			shared->hw_running = 0;

			QDUMP(" '-> Idle.");

			/* set ring buffer length to zero */
			gc_writel(priv, REG_GCRBLR, 0);

			wake_up_all(&priv->wait_idle);
		}

		shared->num_done++;
	} else {
		QERROR(" [???]");
		dump_whole_state(priv);
	}

	/* Clear the interrupt */
	gc_writel(priv, REG_GCISCR, status);
	spin_unlock(&priv->spinlock);

	return IRQ_HANDLED;
}

static int
pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv)
{
	int ret = 0;

	QDUMP("Waiting for idle...");

	/* Does not need to be atomic. There's a lock in user space,
	 * but anyhow, this is just for statistics. */
	priv->shared->num_wait_idle++;

	while (priv->shared->hw_running) {
		int num = priv->shared->num_interrupts;
		u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);

		ret = wait_event_interruptible_timeout(priv->wait_idle,
					!priv->shared->hw_running, HZ*4);

		if (ret != 0)
			break;

		if (gc_readl(priv, REG_GCRBEXHR) == rbexhr &&
		    priv->shared->num_interrupts == num) {
			QERROR("TIMEOUT");
			ret = -ETIMEDOUT;
			break;
		}
	}

	QDUMP("done");

	return ret;
}

static int
pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv)
{
	int ret = 0;

	QDUMP("Waiting for free...");

	/* Does not need to be atomic. There's a lock in user space,
	 * but anyhow, this is just for statistics. */
	priv->shared->num_wait_free++;

	while (!priv->free) {
		u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);

		ret = wait_event_interruptible_timeout(priv->wait_free,
						       priv->free, HZ*4);

		if (ret < 0)
			break;

		if (ret > 0)
			continue;

		if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) {
			QERROR("TIMEOUT");
			ret = -ETIMEDOUT;
			break;
		}
	}

	QDUMP("done");

	return ret;
}

/* Misc device layer */

static inline struct pxa3xx_gcu_priv *to_pxa3xx_gcu_priv(struct file *file)
{
	struct miscdevice *dev = file->private_data;
	return container_of(dev, struct pxa3xx_gcu_priv, misc_dev);
}

static ssize_t
pxa3xx_gcu_write(struct file *file, const char *buff,
		 size_t count, loff_t *offp)
{
	int ret;
	unsigned long flags;
	struct pxa3xx_gcu_batch	*buffer;
	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);

	int words = count / 4;

	/* Does not need to be atomic. There's a lock in user space,
	 * but anyhow, this is just for statistics. */
	priv->shared->num_writes++;
	priv->shared->num_words += words;

	/* Last word reserved for batch buffer end command */
	if (words >= PXA3XX_GCU_BATCH_WORDS)
		return -E2BIG;

	/* Wait for a free buffer */
	if (!priv->free) {
		ret = pxa3xx_gcu_wait_free(priv);
		if (ret < 0)
			return ret;
	}

	/*
	 * Get buffer from free list
	 */
	spin_lock_irqsave(&priv->spinlock, flags);
	buffer = priv->free;
	priv->free = buffer->next;
	spin_unlock_irqrestore(&priv->spinlock, flags);


	/* Copy data from user into buffer */
	ret = copy_from_user(buffer->ptr, buff, words * 4);
	if (ret) {
		spin_lock_irqsave(&priv->spinlock, flags);
		buffer->next = priv->free;
		priv->free = buffer;
		spin_unlock_irqrestore(&priv->spinlock, flags);
		return -EFAULT;
	}

	buffer->length = words;

	/* Append batch buffer end command */
	buffer->ptr[words] = 0x01000000;

	/*
	 * Add buffer to ready list
	 */
	spin_lock_irqsave(&priv->spinlock, flags);

	buffer->next = NULL;

	if (priv->ready) {
		BUG_ON(priv->ready_last == NULL);

		priv->ready_last->next = buffer;
	} else
		priv->ready = buffer;

	priv->ready_last = buffer;

	if (!priv->shared->hw_running)
		run_ready(priv);

	spin_unlock_irqrestore(&priv->spinlock, flags);

	return words * 4;
}


static long
pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
	unsigned long flags;
	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);

	switch (cmd) {
	case PXA3XX_GCU_IOCTL_RESET:
		spin_lock_irqsave(&priv->spinlock, flags);
		pxa3xx_gcu_reset(priv);
		spin_unlock_irqrestore(&priv->spinlock, flags);
		return 0;

	case PXA3XX_GCU_IOCTL_WAIT_IDLE:
		return pxa3xx_gcu_wait_idle(priv);
	}

	return -ENOSYS;
}

static int
pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma)
{
	unsigned int size = vma->vm_end - vma->vm_start;
	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);

	switch (vma->vm_pgoff) {
	case 0:
		/* hand out the shared data area */
		if (size != SHARED_SIZE)
			return -EINVAL;

		return dma_mmap_coherent(NULL, vma,
			priv->shared, priv->shared_phys, size);

	case SHARED_SIZE >> PAGE_SHIFT:
		/* hand out the MMIO base for direct register access
		 * from userspace */
		if (size != resource_size(priv->resource_mem))
			return -EINVAL;

		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

		return io_remap_pfn_range(vma, vma->vm_start,
				priv->resource_mem->start >> PAGE_SHIFT,
				size, vma->vm_page_prot);
	}

	return -EINVAL;
}


#ifdef PXA3XX_GCU_DEBUG_TIMER
static struct timer_list pxa3xx_gcu_debug_timer;

static void pxa3xx_gcu_debug_timedout(unsigned long ptr)
{
	struct pxa3xx_gcu_priv *priv = (struct pxa3xx_gcu_priv *) ptr;

	QERROR("Timer DUMP");

	/* init the timer structure */
	init_timer(&pxa3xx_gcu_debug_timer);
	pxa3xx_gcu_debug_timer.function = pxa3xx_gcu_debug_timedout;
	pxa3xx_gcu_debug_timer.data = ptr;
	pxa3xx_gcu_debug_timer.expires = jiffies + 5*HZ; /* one second */

	add_timer(&pxa3xx_gcu_debug_timer);
}

static void pxa3xx_gcu_init_debug_timer(void)
{
	pxa3xx_gcu_debug_timedout((unsigned long) &pxa3xx_gcu_debug_timer);
}
#else
static inline void pxa3xx_gcu_init_debug_timer(void) {}
#endif

static int
pxa3xx_gcu_add_buffer(struct device *dev,
		      struct pxa3xx_gcu_priv *priv)
{
	struct pxa3xx_gcu_batch *buffer;

	buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL);
	if (!buffer)
		return -ENOMEM;

	buffer->ptr = dma_alloc_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
					 &buffer->phys, GFP_KERNEL);
	if (!buffer->ptr) {
		kfree(buffer);
		return -ENOMEM;
	}

	buffer->next = priv->free;
	priv->free = buffer;

	return 0;
}

static void
pxa3xx_gcu_free_buffers(struct device *dev,
			struct pxa3xx_gcu_priv *priv)
{
	struct pxa3xx_gcu_batch *next, *buffer = priv->free;

	while (buffer) {
		next = buffer->next;

		dma_free_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
				  buffer->ptr, buffer->phys);

		kfree(buffer);
		buffer = next;
	}

	priv->free = NULL;
}

static const struct file_operations pxa3xx_gcu_miscdev_fops = {
	.owner =		THIS_MODULE,
	.write =		pxa3xx_gcu_write,
	.unlocked_ioctl =	pxa3xx_gcu_ioctl,
	.mmap =			pxa3xx_gcu_mmap,
};

static int pxa3xx_gcu_probe(struct platform_device *pdev)
{
	int i, ret, irq;
	struct resource *r;
	struct pxa3xx_gcu_priv *priv;
	struct device *dev = &pdev->dev;

	priv = kzalloc(sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	for (i = 0; i < 8; i++) {
		ret = pxa3xx_gcu_add_buffer(dev, priv);
		if (ret) {
			dev_err(dev, "failed to allocate DMA memory\n");
			goto err_free_priv;
		}
	}

	init_waitqueue_head(&priv->wait_idle);
	init_waitqueue_head(&priv->wait_free);
	spin_lock_init(&priv->spinlock);

	/* we allocate the misc device structure as part of our own allocation,
	 * so we can get a pointer to our priv structure later on with
	 * container_of(). This isn't really necessary as we have a fixed minor
	 * number anyway, but this is to avoid statics. */

	priv->misc_dev.minor	= MISCDEV_MINOR,
	priv->misc_dev.name	= DRV_NAME,
	priv->misc_dev.fops	= &pxa3xx_gcu_miscdev_fops;

	/* register misc device */
	ret = misc_register(&priv->misc_dev);
	if (ret < 0) {
		dev_err(dev, "misc_register() for minor %d failed\n",
			MISCDEV_MINOR);
		goto err_free_priv;
	}

	/* handle IO resources */
	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		dev_err(dev, "no I/O memory resource defined\n");
		ret = -ENODEV;
		goto err_misc_deregister;
	}

	if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
		dev_err(dev, "failed to request I/O memory\n");
		ret = -EBUSY;
		goto err_misc_deregister;
	}

	priv->mmio_base = ioremap_nocache(r->start, resource_size(r));
	if (!priv->mmio_base) {
		dev_err(dev, "failed to map I/O memory\n");
		ret = -EBUSY;
		goto err_free_mem_region;
	}

	/* allocate dma memory */
	priv->shared = dma_alloc_coherent(dev, SHARED_SIZE,
					  &priv->shared_phys, GFP_KERNEL);

	if (!priv->shared) {
		dev_err(dev, "failed to allocate DMA memory\n");
		ret = -ENOMEM;
		goto err_free_io;
	}

	/* enable the clock */
	priv->clk = clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "failed to get clock\n");
		ret = -ENODEV;
		goto err_free_dma;
	}

	ret = clk_enable(priv->clk);
	if (ret < 0) {
		dev_err(dev, "failed to enable clock\n");
		goto err_put_clk;
	}

	/* request the IRQ */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no IRQ defined\n");
		ret = -ENODEV;
		goto err_put_clk;
	}

	ret = request_irq(irq, pxa3xx_gcu_handle_irq,
			  0, DRV_NAME, priv);
	if (ret) {
		dev_err(dev, "request_irq failed\n");
		ret = -EBUSY;
		goto err_put_clk;
	}

	platform_set_drvdata(pdev, priv);
	priv->resource_mem = r;
	pxa3xx_gcu_reset(priv);
	pxa3xx_gcu_init_debug_timer();

	dev_info(dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n",
			(void *) r->start, (void *) priv->shared_phys,
			SHARED_SIZE, irq);
	return 0;

err_put_clk:
	clk_disable(priv->clk);
	clk_put(priv->clk);

err_free_dma:
	dma_free_coherent(dev, SHARED_SIZE,
			priv->shared, priv->shared_phys);

err_free_io:
	iounmap(priv->mmio_base);

err_free_mem_region:
	release_mem_region(r->start, resource_size(r));

err_misc_deregister:
	misc_deregister(&priv->misc_dev);

err_free_priv:
	pxa3xx_gcu_free_buffers(dev, priv);
	kfree(priv);
	return ret;
}

static int pxa3xx_gcu_remove(struct platform_device *pdev)
{
	struct pxa3xx_gcu_priv *priv = platform_get_drvdata(pdev);
	struct resource *r = priv->resource_mem;
	struct device *dev = &pdev->dev;

	pxa3xx_gcu_wait_idle(priv);

	misc_deregister(&priv->misc_dev);
	dma_free_coherent(dev, SHARED_SIZE,
			  priv->shared, priv->shared_phys);
	iounmap(priv->mmio_base);
	release_mem_region(r->start, resource_size(r));
	clk_disable(priv->clk);
	pxa3xx_gcu_free_buffers(dev, priv);
	kfree(priv);

	return 0;
}

static struct platform_driver pxa3xx_gcu_driver = {
	.probe	  = pxa3xx_gcu_probe,
	.remove	 = pxa3xx_gcu_remove,
	.driver	 = {
		.owner  = THIS_MODULE,
		.name   = DRV_NAME,
	},
};

module_platform_driver(pxa3xx_gcu_driver);

MODULE_DESCRIPTION("PXA3xx graphics controller unit driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(MISCDEV_MINOR);
MODULE_AUTHOR("Janine Kropp <nin@directfb.org>, "
		"Denis Oliver Kropp <dok@directfb.org>, "
		"Daniel Mack <daniel@caiaq.de>");
Commit	Line	Data
364dbdf3	1	/*
0b7f1cc7	2	* pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers
364dbdf3 DM	3	*
	4	* This driver needs a DirectFB counterpart in user space, communication
	5	* is handled via mmap()ed memory areas and an ioctl.
	6	*
	7	* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
	8	* Copyright (c) 2009 Janine Kropp <nin@directfb.org>
	9	* Copyright (c) 2009 Denis Oliver Kropp <dok@directfb.org>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*/
	25
	26	/*
	27	* WARNING: This controller is attached to System Bus 2 of the PXA which
25985edc	28	* needs its arbiter to be enabled explicitly (CKENB & 1<<9).
364dbdf3 DM	29	* There is currently no way to do this from Linux, so you need to teach
	30	* your bootloader for now.
	31	*/
	32
	33	#include <linux/module.h>
364dbdf3 DM	34	#include <linux/platform_device.h>
	35	#include <linux/dma-mapping.h>
	36	#include <linux/miscdevice.h>
	37	#include <linux/interrupt.h>
	38	#include <linux/spinlock.h>
	39	#include <linux/uaccess.h>
	40	#include <linux/ioctl.h>
	41	#include <linux/delay.h>
	42	#include <linux/sched.h>
	43	#include <linux/slab.h>
	44	#include <linux/clk.h>
	45	#include <linux/fs.h>
	46	#include <linux/io.h>
	47
	48	#include "pxa3xx-gcu.h"
	49
	50	#define DRV_NAME "pxa3xx-gcu"
	51	#define MISCDEV_MINOR 197
	52
	53	#define REG_GCCR 0x00
	54	#define GCCR_SYNC_CLR (1 << 9)
	55	#define GCCR_BP_RST (1 << 8)
	56	#define GCCR_ABORT (1 << 6)
	57	#define GCCR_STOP (1 << 4)
	58
	59	#define REG_GCISCR 0x04
	60	#define REG_GCIECR 0x08
	61	#define REG_GCRBBR 0x20
	62	#define REG_GCRBLR 0x24
	63	#define REG_GCRBHR 0x28
	64	#define REG_GCRBTR 0x2C
	65	#define REG_GCRBEXHR 0x30
	66
	67	#define IE_EOB (1 << 0)
	68	#define IE_EEOB (1 << 5)
	69	#define IE_ALL 0xff
	70
	71	#define SHARED_SIZE PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared))
	72
	73	/* #define PXA3XX_GCU_DEBUG */
	74	/* #define PXA3XX_GCU_DEBUG_TIMER */
	75
	76	#ifdef PXA3XX_GCU_DEBUG
	77	#define QDUMP(msg) \
	78	do { \
	79	QPRINT(priv, KERN_DEBUG, msg); \
	80	} while (0)
	81	#else
	82	#define QDUMP(msg) do {} while (0)
	83	#endif
	84
	85	#define QERROR(msg) \
	86	do { \
	87	QPRINT(priv, KERN_ERR, msg); \
	88	} while (0)
	89
	90	struct pxa3xx_gcu_batch {
	91	struct pxa3xx_gcu_batch *next;
	92	u32 *ptr;
	93	dma_addr_t phys;
	94	unsigned long length;
	95	};
	96
	97	struct pxa3xx_gcu_priv {
98	void __iomem *mmio_base;
99	struct clk *clk;
100	struct pxa3xx_gcu_shared *shared;
101	dma_addr_t shared_phys;
102	struct resource *resource_mem;
103	struct miscdevice misc_dev;
364dbdf3 DM	104	wait_queue_head_t wait_idle;
	105	wait_queue_head_t wait_free;
	106	spinlock_t spinlock;
	107	struct timeval base_time;
	108
	109	struct pxa3xx_gcu_batch *free;
364dbdf3 DM	110	struct pxa3xx_gcu_batch *ready;
	111	struct pxa3xx_gcu_batch *ready_last;
	112	struct pxa3xx_gcu_batch *running;
	113	};
	114
	115	static inline unsigned long
	116	gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off)
	117	{
	118	return __raw_readl(priv->mmio_base + off);
	119	}
	120
	121	static inline void
	122	gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val)
	123	{
	124	__raw_writel(val, priv->mmio_base + off);
	125	}
	126
	127	#define QPRINT(priv, level, msg) \
	128	do { \
	129	struct timeval tv; \
	130	struct pxa3xx_gcu_shared *shared = priv->shared; \
	131	u32 base = gc_readl(priv, REG_GCRBBR); \
	132	\
	133	do_gettimeofday(&tv); \
	134	\
	135	printk(level "%ld.%03ld.%03ld - %-17s: %-21s (%s, " \
	136	"STATUS " \
	137	"0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, " \
	138	"T %5ld)\n", \
	139	tv.tv_sec - priv->base_time.tv_sec, \
	140	tv.tv_usec / 1000, tv.tv_usec % 1000, \
	141	__func__, msg, \
	142	shared->hw_running ? "running" : " idle", \
	143	gc_readl(priv, REG_GCISCR), \
	144	gc_readl(priv, REG_GCRBBR), \
	145	gc_readl(priv, REG_GCRBLR), \
	146	(gc_readl(priv, REG_GCRBEXHR) - base) / 4, \
	147	(gc_readl(priv, REG_GCRBHR) - base) / 4, \
	148	(gc_readl(priv, REG_GCRBTR) - base) / 4); \
	149	} while (0)
	150
	151	static void
	152	pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv)
	153	{
	154	QDUMP("RESET");
	155
	156	/* disable interrupts */
	157	gc_writel(priv, REG_GCIECR, 0);
	158
	159	/* reset hardware */
	160	gc_writel(priv, REG_GCCR, GCCR_ABORT);
	161	gc_writel(priv, REG_GCCR, 0);
	162
	163	memset(priv->shared, 0, SHARED_SIZE);
	164	priv->shared->buffer_phys = priv->shared_phys;
	165	priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC;
	166
	167	do_gettimeofday(&priv->base_time);
	168
	169	/* set up the ring buffer pointers */
	170	gc_writel(priv, REG_GCRBLR, 0);
	171	gc_writel(priv, REG_GCRBBR, priv->shared_phys);
	172	gc_writel(priv, REG_GCRBTR, priv->shared_phys);
	173
174	/* enable all IRQs except EOB */
175	gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB);
176	}
177
178	static void
179	dump_whole_state(struct pxa3xx_gcu_priv *priv)
180	{
181	struct pxa3xx_gcu_shared *sh = priv->shared;
182	u32 base = gc_readl(priv, REG_GCRBBR);
183
184	QDUMP("DUMP");
185
186	printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n"
187	"%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n",
188	sh->hw_running ? "running" : "idle ",
189	gc_readl(priv, REG_GCISCR),
190	gc_readl(priv, REG_GCRBBR),
191	gc_readl(priv, REG_GCRBLR),
192	(gc_readl(priv, REG_GCRBEXHR) - base) / 4,
193	(gc_readl(priv, REG_GCRBHR) - base) / 4,
194	(gc_readl(priv, REG_GCRBTR) - base) / 4);
195	}
196
197	static void
198	flush_running(struct pxa3xx_gcu_priv *priv)
199	{
200	struct pxa3xx_gcu_batch *running = priv->running;
201	struct pxa3xx_gcu_batch *next;
202
203	while (running) {
204	next = running->next;
205	running->next = priv->free;
206	priv->free = running;
207	running = next;
208	}
209
210	priv->running = NULL;
211	}
212
213	static void
214	run_ready(struct pxa3xx_gcu_priv *priv)
215	{
216	unsigned int num = 0;
217	struct pxa3xx_gcu_shared *shared = priv->shared;
218	struct pxa3xx_gcu_batch *ready = priv->ready;
219
220	QDUMP("Start");
221
222	BUG_ON(!ready);
223
224	shared->buffer[num++] = 0x05000000;
225
226	while (ready) {
227	shared->buffer[num++] = 0x00000001;
228	shared->buffer[num++] = ready->phys;
229	ready = ready->next;
230	}
231
232	shared->buffer[num++] = 0x05000000;
233	priv->running = priv->ready;
234	priv->ready = priv->ready_last = NULL;
235	gc_writel(priv, REG_GCRBLR, 0);
236	shared->hw_running = 1;
237
238	/* ring base address */
239	gc_writel(priv, REG_GCRBBR, shared->buffer_phys);
240
241	/* ring tail address */
242	gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4);
243
244	/* ring length */
245	gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4);
246	}
247
248	static irqreturn_t
249	pxa3xx_gcu_handle_irq(int irq, void *ctx)
250	{
251	struct pxa3xx_gcu_priv *priv = ctx;
252	struct pxa3xx_gcu_shared *shared = priv->shared;
253	u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL;
254
255	QDUMP("-Interrupt");
256
257	if (!status)
258	return IRQ_NONE;
259
260	spin_lock(&priv->spinlock);
261	shared->num_interrupts++;
262
263	if (status & IE_EEOB) {
264	QDUMP(" [EEOB]");
265
266	flush_running(priv);
267	wake_up_all(&priv->wait_free);
268
269	if (priv->ready) {
270	run_ready(priv);
271	} else {
272	/* There is no more data prepared by the userspace.
273	* Set hw_running = 0 and wait for the next userspace
274	* kick-off */
275	shared->num_idle++;
276	shared->hw_running = 0;
277
278	QDUMP(" '-> Idle.");
279
280	/* set ring buffer length to zero */
281	gc_writel(priv, REG_GCRBLR, 0);
282
283	wake_up_all(&priv->wait_idle);
284	}
285
286	shared->num_done++;
287	} else {
288	QERROR(" [???]");
289	dump_whole_state(priv);
290	}
291
292	/* Clear the interrupt */
293	gc_writel(priv, REG_GCISCR, status);
294	spin_unlock(&priv->spinlock);
295
296	return IRQ_HANDLED;
297	}
298
299	static int
300	pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv)
301	{
302	int ret = 0;
303
304	QDUMP("Waiting for idle...");
305
306	/* Does not need to be atomic. There's a lock in user space,
307	* but anyhow, this is just for statistics. */
308	priv->shared->num_wait_idle++;
309
310	while (priv->shared->hw_running) {
311	int num = priv->shared->num_interrupts;
312	u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
313
314	ret = wait_event_interruptible_timeout(priv->wait_idle,
315	!priv->shared->hw_running, HZ*4);
316
688ec344	317	if (ret != 0)
364dbdf3 DM	318	break;
364dbdf3 DM	319
364dbdf3 DM	320	if (gc_readl(priv, REG_GCRBEXHR) == rbexhr &&
	321	priv->shared->num_interrupts == num) {
	322	QERROR("TIMEOUT");
	323	ret = -ETIMEDOUT;
	324	break;
	325	}
	326	}
	327
	328	QDUMP("done");
	329
	330	return ret;
	331	}
	332
	333	static int
	334	pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv)
	335	{
	336	int ret = 0;
	337
	338	QDUMP("Waiting for free...");
	339
	340	/* Does not need to be atomic. There's a lock in user space,
	341	* but anyhow, this is just for statistics. */
	342	priv->shared->num_wait_free++;
	343
	344	while (!priv->free) {
	345	u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
	346
	347	ret = wait_event_interruptible_timeout(priv->wait_free,
	348	priv->free, HZ*4);
	349
	350	if (ret < 0)
	351	break;
	352
	353	if (ret > 0)
	354	continue;
	355
	356	if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) {
	357	QERROR("TIMEOUT");
	358	ret = -ETIMEDOUT;
	359	break;
	360	}
	361	}
	362
	363	QDUMP("done");
	364
	365	return ret;
	366	}
	367
	368	/* Misc device layer */
	369
109393af	370	static inline struct pxa3xx_gcu_priv to_pxa3xx_gcu_priv(struct file file)
996142e6 AV	371	{
	372	struct miscdevice *dev = file->private_data;
	373	return container_of(dev, struct pxa3xx_gcu_priv, misc_dev);
	374	}
	375
364dbdf3	376	static ssize_t
109393af DM	377	pxa3xx_gcu_write(struct file file, const char buff,
109393af DM	378	size_t count, loff_t *offp)
364dbdf3 DM	379	{
	380	int ret;
	381	unsigned long flags;
	382	struct pxa3xx_gcu_batch *buffer;
109393af	383	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
364dbdf3 DM	384
	385	int words = count / 4;
	386
	387	/* Does not need to be atomic. There's a lock in user space,
	388	* but anyhow, this is just for statistics. */
	389	priv->shared->num_writes++;
364dbdf3 DM	390	priv->shared->num_words += words;
	391
	392	/* Last word reserved for batch buffer end command */
	393	if (words >= PXA3XX_GCU_BATCH_WORDS)
	394	return -E2BIG;
	395
	396	/* Wait for a free buffer */
	397	if (!priv->free) {
	398	ret = pxa3xx_gcu_wait_free(priv);
	399	if (ret < 0)
	400	return ret;
	401	}
	402
	403	/*
	404	* Get buffer from free list
	405	*/
	406	spin_lock_irqsave(&priv->spinlock, flags);
364dbdf3 DM	407	buffer = priv->free;
364dbdf3 DM	408	priv->free = buffer->next;
364dbdf3 DM	409	spin_unlock_irqrestore(&priv->spinlock, flags);
	410
	411
	412	/* Copy data from user into buffer */
	413	ret = copy_from_user(buffer->ptr, buff, words * 4);
	414	if (ret) {
	415	spin_lock_irqsave(&priv->spinlock, flags);
	416	buffer->next = priv->free;
	417	priv->free = buffer;
	418	spin_unlock_irqrestore(&priv->spinlock, flags);
0b7f1cc7	419	return -EFAULT;
364dbdf3 DM	420	}
	421
	422	buffer->length = words;
	423
	424	/* Append batch buffer end command */
	425	buffer->ptr[words] = 0x01000000;
	426
	427	/*
	428	* Add buffer to ready list
	429	*/
	430	spin_lock_irqsave(&priv->spinlock, flags);
	431
	432	buffer->next = NULL;
	433
	434	if (priv->ready) {
	435	BUG_ON(priv->ready_last == NULL);
	436
	437	priv->ready_last->next = buffer;
	438	} else
	439	priv->ready = buffer;
	440
	441	priv->ready_last = buffer;
	442
	443	if (!priv->shared->hw_running)
	444	run_ready(priv);
	445
	446	spin_unlock_irqrestore(&priv->spinlock, flags);
	447
	448	return words * 4;
	449	}
	450
	451
	452	static long
109393af	453	pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
364dbdf3 DM	454	{
364dbdf3 DM	455	unsigned long flags;
109393af	456	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
364dbdf3 DM	457
	458	switch (cmd) {
	459	case PXA3XX_GCU_IOCTL_RESET:
	460	spin_lock_irqsave(&priv->spinlock, flags);
	461	pxa3xx_gcu_reset(priv);
	462	spin_unlock_irqrestore(&priv->spinlock, flags);
	463	return 0;
	464
	465	case PXA3XX_GCU_IOCTL_WAIT_IDLE:
	466	return pxa3xx_gcu_wait_idle(priv);
	467	}
	468
	469	return -ENOSYS;
	470	}
	471
	472	static int
109393af	473	pxa3xx_gcu_mmap(struct file file, struct vm_area_struct vma)
364dbdf3 DM	474	{
364dbdf3 DM	475	unsigned int size = vma->vm_end - vma->vm_start;
109393af	476	struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
364dbdf3 DM	477
	478	switch (vma->vm_pgoff) {
	479	case 0:
	480	/* hand out the shared data area */
	481	if (size != SHARED_SIZE)
	482	return -EINVAL;
	483
	484	return dma_mmap_coherent(NULL, vma,
	485	priv->shared, priv->shared_phys, size);
	486
	487	case SHARED_SIZE >> PAGE_SHIFT:
	488	/* hand out the MMIO base for direct register access
	489	* from userspace */
	490	if (size != resource_size(priv->resource_mem))
	491	return -EINVAL;
	492
364dbdf3 DM	493	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	494
	495	return io_remap_pfn_range(vma, vma->vm_start,
	496	priv->resource_mem->start >> PAGE_SHIFT,
	497	size, vma->vm_page_prot);
	498	}
	499
	500	return -EINVAL;
	501	}
	502
	503
	504	#ifdef PXA3XX_GCU_DEBUG_TIMER
	505	static struct timer_list pxa3xx_gcu_debug_timer;
	506
	507	static void pxa3xx_gcu_debug_timedout(unsigned long ptr)
	508	{
	509	struct pxa3xx_gcu_priv priv = (struct pxa3xx_gcu_priv ) ptr;
	510
	511	QERROR("Timer DUMP");
	512
	513	/* init the timer structure */
	514	init_timer(&pxa3xx_gcu_debug_timer);
	515	pxa3xx_gcu_debug_timer.function = pxa3xx_gcu_debug_timedout;
	516	pxa3xx_gcu_debug_timer.data = ptr;
	517	pxa3xx_gcu_debug_timer.expires = jiffies + 5HZ; / one second */
	518
	519	add_timer(&pxa3xx_gcu_debug_timer);
	520	}
	521
	522	static void pxa3xx_gcu_init_debug_timer(void)
	523	{
	524	pxa3xx_gcu_debug_timedout((unsigned long) &pxa3xx_gcu_debug_timer);
	525	}
	526	#else
	527	static inline void pxa3xx_gcu_init_debug_timer(void) {}
	528	#endif
	529
	530	static int
9e4f9675	531	pxa3xx_gcu_add_buffer(struct device *dev,
109393af	532	struct pxa3xx_gcu_priv *priv)
364dbdf3 DM	533	{
	534	struct pxa3xx_gcu_batch *buffer;
	535
	536	buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL);
	537	if (!buffer)
	538	return -ENOMEM;
	539
9e4f9675	540	buffer->ptr = dma_alloc_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
364dbdf3 DM	541	&buffer->phys, GFP_KERNEL);
	542	if (!buffer->ptr) {
	543	kfree(buffer);
	544	return -ENOMEM;
	545	}
	546
	547	buffer->next = priv->free;
364dbdf3 DM	548	priv->free = buffer;
	549
	550	return 0;
	551	}
	552
	553	static void
9e4f9675	554	pxa3xx_gcu_free_buffers(struct device *dev,
109393af	555	struct pxa3xx_gcu_priv *priv)
364dbdf3 DM	556	{
	557	struct pxa3xx_gcu_batch next, buffer = priv->free;
	558
	559	while (buffer) {
	560	next = buffer->next;
	561
9e4f9675	562	dma_free_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
364dbdf3 DM	563	buffer->ptr, buffer->phys);
	564
	565	kfree(buffer);
364dbdf3 DM	566	buffer = next;
	567	}
	568
	569	priv->free = NULL;
	570	}
	571
109393af DM	572	static const struct file_operations pxa3xx_gcu_miscdev_fops = {
	573	.owner = THIS_MODULE,
	574	.write = pxa3xx_gcu_write,
	575	.unlocked_ioctl = pxa3xx_gcu_ioctl,
	576	.mmap = pxa3xx_gcu_mmap,
264bd660 AV	577	};
264bd660 AV	578
9e4f9675	579	static int pxa3xx_gcu_probe(struct platform_device *pdev)
364dbdf3 DM	580	{
	581	int i, ret, irq;
	582	struct resource *r;
	583	struct pxa3xx_gcu_priv *priv;
9e4f9675	584	struct device *dev = &pdev->dev;
364dbdf3 DM	585
	586	priv = kzalloc(sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL);
	587	if (!priv)
	588	return -ENOMEM;
	589
	590	for (i = 0; i < 8; i++) {
109393af	591	ret = pxa3xx_gcu_add_buffer(dev, priv);
364dbdf3	592	if (ret) {
9e4f9675	593	dev_err(dev, "failed to allocate DMA memory\n");
364dbdf3 DM	594	goto err_free_priv;
	595	}
	596	}
	597
	598	init_waitqueue_head(&priv->wait_idle);
	599	init_waitqueue_head(&priv->wait_free);
	600	spin_lock_init(&priv->spinlock);
	601
	602	/* we allocate the misc device structure as part of our own allocation,
	603	* so we can get a pointer to our priv structure later on with
	604	* container_of(). This isn't really necessary as we have a fixed minor
	605	* number anyway, but this is to avoid statics. */
	606
364dbdf3 DM	607	priv->misc_dev.minor = MISCDEV_MINOR,
364dbdf3 DM	608	priv->misc_dev.name = DRV_NAME,
109393af	609	priv->misc_dev.fops = &pxa3xx_gcu_miscdev_fops;
364dbdf3 DM	610
	611	/* register misc device */
	612	ret = misc_register(&priv->misc_dev);
	613	if (ret < 0) {
9e4f9675	614	dev_err(dev, "misc_register() for minor %d failed\n",
364dbdf3 DM	615	MISCDEV_MINOR);
	616	goto err_free_priv;
	617	}
	618
	619	/* handle IO resources */
9e4f9675	620	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364dbdf3	621	if (r == NULL) {
9e4f9675	622	dev_err(dev, "no I/O memory resource defined\n");
364dbdf3 DM	623	ret = -ENODEV;
	624	goto err_misc_deregister;
	625	}
	626
9e4f9675 DM	627	if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
9e4f9675 DM	628	dev_err(dev, "failed to request I/O memory\n");
364dbdf3 DM	629	ret = -EBUSY;
	630	goto err_misc_deregister;
	631	}
	632
	633	priv->mmio_base = ioremap_nocache(r->start, resource_size(r));
	634	if (!priv->mmio_base) {
9e4f9675	635	dev_err(dev, "failed to map I/O memory\n");
364dbdf3 DM	636	ret = -EBUSY;
	637	goto err_free_mem_region;
	638	}
	639
	640	/* allocate dma memory */
9e4f9675	641	priv->shared = dma_alloc_coherent(dev, SHARED_SIZE,
364dbdf3 DM	642	&priv->shared_phys, GFP_KERNEL);
	643
	644	if (!priv->shared) {
9e4f9675	645	dev_err(dev, "failed to allocate DMA memory\n");
364dbdf3 DM	646	ret = -ENOMEM;
	647	goto err_free_io;
	648	}
	649
	650	/* enable the clock */
9e4f9675	651	priv->clk = clk_get(dev, NULL);
364dbdf3	652	if (IS_ERR(priv->clk)) {
9e4f9675	653	dev_err(dev, "failed to get clock\n");
364dbdf3 DM	654	ret = -ENODEV;
	655	goto err_free_dma;
	656	}
	657
	658	ret = clk_enable(priv->clk);
	659	if (ret < 0) {
9e4f9675	660	dev_err(dev, "failed to enable clock\n");
364dbdf3 DM	661	goto err_put_clk;
	662	}
	663
	664	/* request the IRQ */
9e4f9675	665	irq = platform_get_irq(pdev, 0);
364dbdf3	666	if (irq < 0) {
9e4f9675	667	dev_err(dev, "no IRQ defined\n");
364dbdf3 DM	668	ret = -ENODEV;
	669	goto err_put_clk;
	670	}
	671
	672	ret = request_irq(irq, pxa3xx_gcu_handle_irq,
f8798ccb	673	0, DRV_NAME, priv);
364dbdf3	674	if (ret) {
9e4f9675	675	dev_err(dev, "request_irq failed\n");
364dbdf3 DM	676	ret = -EBUSY;
	677	goto err_put_clk;
	678	}
	679
9e4f9675	680	platform_set_drvdata(pdev, priv);
364dbdf3 DM	681	priv->resource_mem = r;
	682	pxa3xx_gcu_reset(priv);
	683	pxa3xx_gcu_init_debug_timer();
	684
9e4f9675	685	dev_info(dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n",
364dbdf3 DM	686	(void ) r->start, (void ) priv->shared_phys,
	687	SHARED_SIZE, irq);
	688	return 0;
	689
	690	err_put_clk:
	691	clk_disable(priv->clk);
	692	clk_put(priv->clk);
	693
	694	err_free_dma:
9e4f9675	695	dma_free_coherent(dev, SHARED_SIZE,
364dbdf3 DM	696	priv->shared, priv->shared_phys);
	697
	698	err_free_io:
	699	iounmap(priv->mmio_base);
	700
	701	err_free_mem_region:
	702	release_mem_region(r->start, resource_size(r));
	703
	704	err_misc_deregister:
	705	misc_deregister(&priv->misc_dev);
	706
	707	err_free_priv:
109393af	708	pxa3xx_gcu_free_buffers(dev, priv);
364dbdf3 DM	709	kfree(priv);
	710	return ret;
	711	}
	712
9e4f9675	713	static int pxa3xx_gcu_remove(struct platform_device *pdev)
364dbdf3	714	{
9e4f9675	715	struct pxa3xx_gcu_priv *priv = platform_get_drvdata(pdev);
364dbdf3	716	struct resource *r = priv->resource_mem;
9e4f9675	717	struct device *dev = &pdev->dev;
364dbdf3 DM	718
	719	pxa3xx_gcu_wait_idle(priv);
	720
	721	misc_deregister(&priv->misc_dev);
9e4f9675 DM	722	dma_free_coherent(dev, SHARED_SIZE,
9e4f9675 DM	723	priv->shared, priv->shared_phys);
364dbdf3 DM	724	iounmap(priv->mmio_base);
364dbdf3 DM	725	release_mem_region(r->start, resource_size(r));
364dbdf3	726	clk_disable(priv->clk);
109393af	727	pxa3xx_gcu_free_buffers(dev, priv);
364dbdf3 DM	728	kfree(priv);
	729
	730	return 0;
	731	}
	732
	733	static struct platform_driver pxa3xx_gcu_driver = {
	734	.probe = pxa3xx_gcu_probe,
48c68c4f	735	.remove = pxa3xx_gcu_remove,
364dbdf3 DM	736	.driver = {
	737	.owner = THIS_MODULE,
	738	.name = DRV_NAME,
	739	},
	740	};
	741
4277f2c4	742	module_platform_driver(pxa3xx_gcu_driver);
364dbdf3 DM	743
	744	MODULE_DESCRIPTION("PXA3xx graphics controller unit driver");
	745	MODULE_LICENSE("GPL");
	746	MODULE_ALIAS_MISCDEV(MISCDEV_MINOR);
	747	MODULE_AUTHOR("Janine Kropp <nin@directfb.org>, "
	748	"Denis Oliver Kropp <dok@directfb.org>, "
	749	"Daniel Mack <daniel@caiaq.de>");