]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/pxafb.c | |
3 | * | |
4 | * Copyright (C) 1999 Eric A. Thomas. | |
5 | * Copyright (C) 2004 Jean-Frederic Clere. | |
6 | * Copyright (C) 2004 Ian Campbell. | |
7 | * Copyright (C) 2004 Jeff Lackey. | |
8 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas | |
9 | * which in turn is | |
10 | * Based on acornfb.c Copyright (C) Russell King. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | * | |
16 | * Intel PXA250/210 LCD Controller Frame Buffer Driver | |
17 | * | |
18 | * Please direct your questions and comments on this driver to the following | |
19 | * email address: | |
20 | * | |
21 | * linux-arm-kernel@lists.arm.linux.org.uk | |
22 | * | |
198fc108 EM |
23 | * Add support for overlay1 and overlay2 based on pxafb_overlay.c: |
24 | * | |
25 | * Copyright (C) 2004, Intel Corporation | |
26 | * | |
27 | * 2003/08/27: <yu.tang@intel.com> | |
28 | * 2004/03/10: <stanley.cai@intel.com> | |
29 | * 2004/10/28: <yan.yin@intel.com> | |
30 | * | |
31 | * Copyright (C) 2006-2008 Marvell International Ltd. | |
32 | * All Rights Reserved | |
1da177e4 LT |
33 | */ |
34 | ||
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/sched.h> | |
39 | #include <linux/errno.h> | |
40 | #include <linux/string.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/slab.h> | |
27ac792c | 43 | #include <linux/mm.h> |
1da177e4 LT |
44 | #include <linux/fb.h> |
45 | #include <linux/delay.h> | |
46 | #include <linux/init.h> | |
47 | #include <linux/ioport.h> | |
48 | #include <linux/cpufreq.h> | |
d052d1be | 49 | #include <linux/platform_device.h> |
1da177e4 | 50 | #include <linux/dma-mapping.h> |
72e3524c RK |
51 | #include <linux/clk.h> |
52 | #include <linux/err.h> | |
2ba162b9 | 53 | #include <linux/completion.h> |
b91dbce5 | 54 | #include <linux/mutex.h> |
3c42a449 EM |
55 | #include <linux/kthread.h> |
56 | #include <linux/freezer.h> | |
1da177e4 | 57 | |
a09e64fb | 58 | #include <mach/hardware.h> |
1da177e4 LT |
59 | #include <asm/io.h> |
60 | #include <asm/irq.h> | |
bf1b8ab6 | 61 | #include <asm/div64.h> |
a09e64fb RK |
62 | #include <mach/bitfield.h> |
63 | #include <mach/pxafb.h> | |
1da177e4 LT |
64 | |
65 | /* | |
66 | * Complain if VAR is out of range. | |
67 | */ | |
68 | #define DEBUG_VAR 1 | |
69 | ||
70 | #include "pxafb.h" | |
71 | ||
72 | /* Bits which should not be set in machine configuration structures */ | |
b0086efb | 73 | #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ |
74 | LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ | |
75 | LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) | |
76 | ||
77 | #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ | |
878f5783 | 78 | LCCR3_PCD | LCCR3_BPP(0xf)) |
1da177e4 | 79 | |
b0086efb | 80 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
81 | struct pxafb_info *); | |
1da177e4 | 82 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); |
448ac479 SN |
83 | static void setup_base_frame(struct pxafb_info *fbi, |
84 | struct fb_var_screeninfo *var, int branch); | |
198fc108 EM |
85 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, |
86 | unsigned long offset, size_t size); | |
1da177e4 | 87 | |
77e19675 | 88 | static unsigned long video_mem_size = 0; |
1da177e4 | 89 | |
a7535ba7 EM |
90 | static inline unsigned long |
91 | lcd_readl(struct pxafb_info *fbi, unsigned int off) | |
92 | { | |
93 | return __raw_readl(fbi->mmio_base + off); | |
94 | } | |
95 | ||
96 | static inline void | |
97 | lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) | |
98 | { | |
99 | __raw_writel(val, fbi->mmio_base + off); | |
100 | } | |
101 | ||
1da177e4 LT |
102 | static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) |
103 | { | |
104 | unsigned long flags; | |
105 | ||
106 | local_irq_save(flags); | |
107 | /* | |
108 | * We need to handle two requests being made at the same time. | |
109 | * There are two important cases: | |
b0086efb | 110 | * 1. When we are changing VT (C_REENABLE) while unblanking |
111 | * (C_ENABLE) We must perform the unblanking, which will | |
112 | * do our REENABLE for us. | |
113 | * 2. When we are blanking, but immediately unblank before | |
114 | * we have blanked. We do the "REENABLE" thing here as | |
115 | * well, just to be sure. | |
1da177e4 LT |
116 | */ |
117 | if (fbi->task_state == C_ENABLE && state == C_REENABLE) | |
118 | state = (u_int) -1; | |
119 | if (fbi->task_state == C_DISABLE && state == C_ENABLE) | |
120 | state = C_REENABLE; | |
121 | ||
122 | if (state != (u_int)-1) { | |
123 | fbi->task_state = state; | |
124 | schedule_work(&fbi->task); | |
125 | } | |
126 | local_irq_restore(flags); | |
127 | } | |
128 | ||
129 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
130 | { | |
131 | chan &= 0xffff; | |
132 | chan >>= 16 - bf->length; | |
133 | return chan << bf->offset; | |
134 | } | |
135 | ||
136 | static int | |
137 | pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, | |
138 | u_int trans, struct fb_info *info) | |
139 | { | |
140 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
9ffa7396 HK |
141 | u_int val; |
142 | ||
143 | if (regno >= fbi->palette_size) | |
144 | return 1; | |
145 | ||
146 | if (fbi->fb.var.grayscale) { | |
147 | fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { | |
152 | case LCCR4_PAL_FOR_0: | |
153 | val = ((red >> 0) & 0xf800); | |
154 | val |= ((green >> 5) & 0x07e0); | |
155 | val |= ((blue >> 11) & 0x001f); | |
1da177e4 | 156 | fbi->palette_cpu[regno] = val; |
9ffa7396 HK |
157 | break; |
158 | case LCCR4_PAL_FOR_1: | |
159 | val = ((red << 8) & 0x00f80000); | |
160 | val |= ((green >> 0) & 0x0000fc00); | |
161 | val |= ((blue >> 8) & 0x000000f8); | |
b0086efb | 162 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 HK |
163 | break; |
164 | case LCCR4_PAL_FOR_2: | |
165 | val = ((red << 8) & 0x00fc0000); | |
166 | val |= ((green >> 0) & 0x0000fc00); | |
167 | val |= ((blue >> 8) & 0x000000fc); | |
b0086efb | 168 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 | 169 | break; |
a0427509 EM |
170 | case LCCR4_PAL_FOR_3: |
171 | val = ((red << 8) & 0x00ff0000); | |
172 | val |= ((green >> 0) & 0x0000ff00); | |
173 | val |= ((blue >> 8) & 0x000000ff); | |
174 | ((u32 *)(fbi->palette_cpu))[regno] = val; | |
175 | break; | |
1da177e4 | 176 | } |
9ffa7396 HK |
177 | |
178 | return 0; | |
1da177e4 LT |
179 | } |
180 | ||
181 | static int | |
182 | pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
183 | u_int trans, struct fb_info *info) | |
184 | { | |
185 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
186 | unsigned int val; | |
187 | int ret = 1; | |
188 | ||
189 | /* | |
190 | * If inverse mode was selected, invert all the colours | |
191 | * rather than the register number. The register number | |
192 | * is what you poke into the framebuffer to produce the | |
193 | * colour you requested. | |
194 | */ | |
195 | if (fbi->cmap_inverse) { | |
196 | red = 0xffff - red; | |
197 | green = 0xffff - green; | |
198 | blue = 0xffff - blue; | |
199 | } | |
200 | ||
201 | /* | |
202 | * If greyscale is true, then we convert the RGB value | |
203 | * to greyscale no matter what visual we are using. | |
204 | */ | |
205 | if (fbi->fb.var.grayscale) | |
206 | red = green = blue = (19595 * red + 38470 * green + | |
207 | 7471 * blue) >> 16; | |
208 | ||
209 | switch (fbi->fb.fix.visual) { | |
210 | case FB_VISUAL_TRUECOLOR: | |
211 | /* | |
212 | * 16-bit True Colour. We encode the RGB value | |
213 | * according to the RGB bitfield information. | |
214 | */ | |
215 | if (regno < 16) { | |
216 | u32 *pal = fbi->fb.pseudo_palette; | |
217 | ||
218 | val = chan_to_field(red, &fbi->fb.var.red); | |
219 | val |= chan_to_field(green, &fbi->fb.var.green); | |
220 | val |= chan_to_field(blue, &fbi->fb.var.blue); | |
221 | ||
222 | pal[regno] = val; | |
223 | ret = 0; | |
224 | } | |
225 | break; | |
226 | ||
227 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
228 | case FB_VISUAL_PSEUDOCOLOR: | |
229 | ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); | |
230 | break; | |
231 | } | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
878f5783 EM |
236 | /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ |
237 | static inline int var_to_depth(struct fb_var_screeninfo *var) | |
1da177e4 | 238 | { |
878f5783 EM |
239 | return var->red.length + var->green.length + |
240 | var->blue.length + var->transp.length; | |
241 | } | |
242 | ||
243 | /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */ | |
244 | static int pxafb_var_to_bpp(struct fb_var_screeninfo *var) | |
245 | { | |
246 | int bpp = -EINVAL; | |
247 | ||
b0086efb | 248 | switch (var->bits_per_pixel) { |
878f5783 EM |
249 | case 1: bpp = 0; break; |
250 | case 2: bpp = 1; break; | |
251 | case 4: bpp = 2; break; | |
252 | case 8: bpp = 3; break; | |
253 | case 16: bpp = 4; break; | |
c1450f15 | 254 | case 24: |
878f5783 EM |
255 | switch (var_to_depth(var)) { |
256 | case 18: bpp = 6; break; /* 18-bits/pixel packed */ | |
257 | case 19: bpp = 8; break; /* 19-bits/pixel packed */ | |
258 | case 24: bpp = 9; break; | |
c1450f15 SS |
259 | } |
260 | break; | |
261 | case 32: | |
878f5783 EM |
262 | switch (var_to_depth(var)) { |
263 | case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ | |
264 | case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ | |
265 | case 25: bpp = 10; break; | |
c1450f15 SS |
266 | } |
267 | break; | |
b0086efb | 268 | } |
878f5783 EM |
269 | return bpp; |
270 | } | |
271 | ||
272 | /* | |
273 | * pxafb_var_to_lccr3(): | |
274 | * Convert a bits per pixel value to the correct bit pattern for LCCR3 | |
275 | * | |
276 | * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an | |
277 | * implication of the acutal use of transparency bit, which we handle it | |
278 | * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel | |
279 | * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP. | |
280 | * | |
281 | * Transparency for palette pixel formats is not supported at the moment. | |
282 | */ | |
283 | static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) | |
284 | { | |
285 | int bpp = pxafb_var_to_bpp(var); | |
286 | uint32_t lccr3; | |
287 | ||
288 | if (bpp < 0) | |
289 | return 0; | |
290 | ||
291 | lccr3 = LCCR3_BPP(bpp); | |
292 | ||
293 | switch (var_to_depth(var)) { | |
294 | case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break; | |
295 | case 18: lccr3 |= LCCR3_PDFOR_3; break; | |
296 | case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3; | |
297 | break; | |
298 | case 19: | |
299 | case 25: lccr3 |= LCCR3_PDFOR_0; break; | |
300 | } | |
301 | return lccr3; | |
302 | } | |
303 | ||
304 | #define SET_PIXFMT(v, r, g, b, t) \ | |
305 | ({ \ | |
306 | (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \ | |
307 | (v)->transp.length = (t) ? (t) : 0; \ | |
308 | (v)->blue.length = (b); (v)->blue.offset = 0; \ | |
309 | (v)->green.length = (g); (v)->green.offset = (b); \ | |
310 | (v)->red.length = (r); (v)->red.offset = (b) + (g); \ | |
311 | }) | |
312 | ||
313 | /* set the RGBT bitfields of fb_var_screeninf according to | |
314 | * var->bits_per_pixel and given depth | |
315 | */ | |
316 | static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth) | |
317 | { | |
318 | if (depth == 0) | |
319 | depth = var->bits_per_pixel; | |
320 | ||
321 | if (var->bits_per_pixel < 16) { | |
322 | /* indexed pixel formats */ | |
323 | var->red.offset = 0; var->red.length = 8; | |
324 | var->green.offset = 0; var->green.length = 8; | |
325 | var->blue.offset = 0; var->blue.length = 8; | |
326 | var->transp.offset = 0; var->transp.length = 8; | |
327 | } | |
328 | ||
329 | switch (depth) { | |
330 | case 16: var->transp.length ? | |
331 | SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */ | |
332 | SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */ | |
333 | case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */ | |
334 | case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */ | |
335 | case 24: var->transp.length ? | |
336 | SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */ | |
337 | SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */ | |
338 | case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */ | |
339 | } | |
1da177e4 LT |
340 | } |
341 | ||
342 | #ifdef CONFIG_CPU_FREQ | |
343 | /* | |
344 | * pxafb_display_dma_period() | |
345 | * Calculate the minimum period (in picoseconds) between two DMA | |
346 | * requests for the LCD controller. If we hit this, it means we're | |
347 | * doing nothing but LCD DMA. | |
348 | */ | |
349 | static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) | |
350 | { | |
b0086efb | 351 | /* |
352 | * Period = pixclock * bits_per_byte * bytes_per_transfer | |
353 | * / memory_bits_per_pixel; | |
354 | */ | |
355 | return var->pixclock * 8 * 16 / var->bits_per_pixel; | |
1da177e4 | 356 | } |
1da177e4 LT |
357 | #endif |
358 | ||
d14b272b RP |
359 | /* |
360 | * Select the smallest mode that allows the desired resolution to be | |
361 | * displayed. If desired parameters can be rounded up. | |
362 | */ | |
b0086efb | 363 | static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, |
364 | struct fb_var_screeninfo *var) | |
d14b272b RP |
365 | { |
366 | struct pxafb_mode_info *mode = NULL; | |
367 | struct pxafb_mode_info *modelist = mach->modes; | |
368 | unsigned int best_x = 0xffffffff, best_y = 0xffffffff; | |
369 | unsigned int i; | |
370 | ||
b0086efb | 371 | for (i = 0; i < mach->num_modes; i++) { |
372 | if (modelist[i].xres >= var->xres && | |
373 | modelist[i].yres >= var->yres && | |
374 | modelist[i].xres < best_x && | |
375 | modelist[i].yres < best_y && | |
376 | modelist[i].bpp >= var->bits_per_pixel) { | |
d14b272b RP |
377 | best_x = modelist[i].xres; |
378 | best_y = modelist[i].yres; | |
379 | mode = &modelist[i]; | |
380 | } | |
381 | } | |
382 | ||
383 | return mode; | |
384 | } | |
385 | ||
b0086efb | 386 | static void pxafb_setmode(struct fb_var_screeninfo *var, |
387 | struct pxafb_mode_info *mode) | |
d14b272b RP |
388 | { |
389 | var->xres = mode->xres; | |
390 | var->yres = mode->yres; | |
391 | var->bits_per_pixel = mode->bpp; | |
392 | var->pixclock = mode->pixclock; | |
393 | var->hsync_len = mode->hsync_len; | |
394 | var->left_margin = mode->left_margin; | |
395 | var->right_margin = mode->right_margin; | |
396 | var->vsync_len = mode->vsync_len; | |
397 | var->upper_margin = mode->upper_margin; | |
398 | var->lower_margin = mode->lower_margin; | |
399 | var->sync = mode->sync; | |
400 | var->grayscale = mode->cmap_greyscale; | |
049ad833 | 401 | var->transp.length = mode->transparency; |
878f5783 EM |
402 | |
403 | /* set the initial RGBA bitfields */ | |
404 | pxafb_set_pixfmt(var, mode->depth); | |
d14b272b RP |
405 | } |
406 | ||
3f16ff60 EM |
407 | static int pxafb_adjust_timing(struct pxafb_info *fbi, |
408 | struct fb_var_screeninfo *var) | |
409 | { | |
410 | int line_length; | |
411 | ||
412 | var->xres = max_t(int, var->xres, MIN_XRES); | |
413 | var->yres = max_t(int, var->yres, MIN_YRES); | |
414 | ||
415 | if (!(fbi->lccr0 & LCCR0_LCDT)) { | |
416 | clamp_val(var->hsync_len, 1, 64); | |
417 | clamp_val(var->vsync_len, 1, 64); | |
418 | clamp_val(var->left_margin, 1, 255); | |
419 | clamp_val(var->right_margin, 1, 255); | |
420 | clamp_val(var->upper_margin, 1, 255); | |
421 | clamp_val(var->lower_margin, 1, 255); | |
422 | } | |
423 | ||
424 | /* make sure each line is aligned on word boundary */ | |
425 | line_length = var->xres * var->bits_per_pixel / 8; | |
426 | line_length = ALIGN(line_length, 4); | |
427 | var->xres = line_length * 8 / var->bits_per_pixel; | |
428 | ||
429 | /* we don't support xpan, force xres_virtual to be equal to xres */ | |
430 | var->xres_virtual = var->xres; | |
431 | ||
432 | if (var->accel_flags & FB_ACCELF_TEXT) | |
433 | var->yres_virtual = fbi->fb.fix.smem_len / line_length; | |
434 | else | |
435 | var->yres_virtual = max(var->yres_virtual, var->yres); | |
436 | ||
437 | /* check for limits */ | |
438 | if (var->xres > MAX_XRES || var->yres > MAX_YRES) | |
439 | return -EINVAL; | |
440 | ||
441 | if (var->yres > var->yres_virtual) | |
442 | return -EINVAL; | |
443 | ||
444 | return 0; | |
d14b272b RP |
445 | } |
446 | ||
1da177e4 LT |
447 | /* |
448 | * pxafb_check_var(): | |
449 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
450 | * if it's too big, return -EINVAL. | |
451 | * | |
452 | * Round up in the following order: bits_per_pixel, xres, | |
453 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
454 | * bitfields, horizontal timing, vertical timing. | |
455 | */ | |
456 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
457 | { | |
458 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
d14b272b | 459 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
878f5783 | 460 | int err; |
d14b272b RP |
461 | |
462 | if (inf->fixed_modes) { | |
463 | struct pxafb_mode_info *mode; | |
464 | ||
465 | mode = pxafb_getmode(inf, var); | |
466 | if (!mode) | |
467 | return -EINVAL; | |
468 | pxafb_setmode(var, mode); | |
d14b272b RP |
469 | } |
470 | ||
878f5783 EM |
471 | /* do a test conversion to BPP fields to check the color formats */ |
472 | err = pxafb_var_to_bpp(var); | |
473 | if (err < 0) | |
474 | return err; | |
1da177e4 | 475 | |
878f5783 | 476 | pxafb_set_pixfmt(var, var_to_depth(var)); |
c1450f15 | 477 | |
3f16ff60 EM |
478 | err = pxafb_adjust_timing(fbi, var); |
479 | if (err) | |
480 | return err; | |
1da177e4 LT |
481 | |
482 | #ifdef CONFIG_CPU_FREQ | |
78d3cfd3 RK |
483 | pr_debug("pxafb: dma period = %d ps\n", |
484 | pxafb_display_dma_period(var)); | |
1da177e4 LT |
485 | #endif |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
1da177e4 LT |
490 | /* |
491 | * pxafb_set_par(): | |
492 | * Set the user defined part of the display for the specified console | |
493 | */ | |
494 | static int pxafb_set_par(struct fb_info *info) | |
495 | { | |
496 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
497 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 | 498 | |
c1450f15 | 499 | if (var->bits_per_pixel >= 16) |
1da177e4 LT |
500 | fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; |
501 | else if (!fbi->cmap_static) | |
502 | fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
503 | else { | |
504 | /* | |
505 | * Some people have weird ideas about wanting static | |
506 | * pseudocolor maps. I suspect their user space | |
507 | * applications are broken. | |
508 | */ | |
509 | fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
510 | } | |
511 | ||
512 | fbi->fb.fix.line_length = var->xres_virtual * | |
513 | var->bits_per_pixel / 8; | |
c1450f15 | 514 | if (var->bits_per_pixel >= 16) |
1da177e4 LT |
515 | fbi->palette_size = 0; |
516 | else | |
b0086efb | 517 | fbi->palette_size = var->bits_per_pixel == 1 ? |
518 | 4 : 1 << var->bits_per_pixel; | |
1da177e4 | 519 | |
2c42dd8e | 520 | fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; |
1da177e4 | 521 | |
c1450f15 | 522 | if (fbi->fb.var.bits_per_pixel >= 16) |
1da177e4 LT |
523 | fb_dealloc_cmap(&fbi->fb.cmap); |
524 | else | |
525 | fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); | |
526 | ||
527 | pxafb_activate_var(var, fbi); | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
6e354846 EM |
532 | static int pxafb_pan_display(struct fb_var_screeninfo *var, |
533 | struct fb_info *info) | |
534 | { | |
535 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
448ac479 | 536 | struct fb_var_screeninfo newvar; |
6e354846 EM |
537 | int dma = DMA_MAX + DMA_BASE; |
538 | ||
539 | if (fbi->state != C_ENABLE) | |
540 | return 0; | |
541 | ||
448ac479 SN |
542 | /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what |
543 | * was passed in and copy the rest from the old screeninfo. | |
544 | */ | |
545 | memcpy(&newvar, &fbi->fb.var, sizeof(newvar)); | |
546 | newvar.xoffset = var->xoffset; | |
547 | newvar.yoffset = var->yoffset; | |
548 | newvar.vmode &= ~FB_VMODE_YWRAP; | |
549 | newvar.vmode |= var->vmode & FB_VMODE_YWRAP; | |
550 | ||
551 | setup_base_frame(fbi, &newvar, 1); | |
6e354846 EM |
552 | |
553 | if (fbi->lccr0 & LCCR0_SDS) | |
554 | lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); | |
555 | ||
556 | lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1); | |
557 | return 0; | |
558 | } | |
559 | ||
1da177e4 LT |
560 | /* |
561 | * pxafb_blank(): | |
562 | * Blank the display by setting all palette values to zero. Note, the | |
563 | * 16 bpp mode does not really use the palette, so this will not | |
564 | * blank the display in all modes. | |
565 | */ | |
566 | static int pxafb_blank(int blank, struct fb_info *info) | |
567 | { | |
568 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
569 | int i; | |
570 | ||
1da177e4 LT |
571 | switch (blank) { |
572 | case FB_BLANK_POWERDOWN: | |
573 | case FB_BLANK_VSYNC_SUSPEND: | |
574 | case FB_BLANK_HSYNC_SUSPEND: | |
575 | case FB_BLANK_NORMAL: | |
576 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
577 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
578 | for (i = 0; i < fbi->palette_size; i++) | |
579 | pxafb_setpalettereg(i, 0, 0, 0, 0, info); | |
580 | ||
581 | pxafb_schedule_work(fbi, C_DISABLE); | |
b0086efb | 582 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
583 | break; |
584 | ||
585 | case FB_BLANK_UNBLANK: | |
b0086efb | 586 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
587 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || |
588 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
589 | fb_set_cmap(&fbi->fb.cmap, info); | |
590 | pxafb_schedule_work(fbi, C_ENABLE); | |
591 | } | |
592 | return 0; | |
593 | } | |
594 | ||
1da177e4 LT |
595 | static struct fb_ops pxafb_ops = { |
596 | .owner = THIS_MODULE, | |
597 | .fb_check_var = pxafb_check_var, | |
598 | .fb_set_par = pxafb_set_par, | |
6e354846 | 599 | .fb_pan_display = pxafb_pan_display, |
1da177e4 LT |
600 | .fb_setcolreg = pxafb_setcolreg, |
601 | .fb_fillrect = cfb_fillrect, | |
602 | .fb_copyarea = cfb_copyarea, | |
603 | .fb_imageblit = cfb_imageblit, | |
604 | .fb_blank = pxafb_blank, | |
1da177e4 LT |
605 | }; |
606 | ||
198fc108 EM |
607 | #ifdef CONFIG_FB_PXA_OVERLAY |
608 | static void overlay1fb_setup(struct pxafb_layer *ofb) | |
609 | { | |
610 | int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; | |
611 | unsigned long start = ofb->video_mem_phys; | |
612 | setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size); | |
613 | } | |
614 | ||
615 | /* Depending on the enable status of overlay1/2, the DMA should be | |
616 | * updated from FDADRx (when disabled) or FBRx (when enabled). | |
617 | */ | |
618 | static void overlay1fb_enable(struct pxafb_layer *ofb) | |
619 | { | |
620 | int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN; | |
621 | uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); | |
622 | ||
623 | lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1); | |
624 | lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]); | |
625 | lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN); | |
626 | } | |
627 | ||
628 | static void overlay1fb_disable(struct pxafb_layer *ofb) | |
629 | { | |
1b98d7c4 VK |
630 | uint32_t lccr5; |
631 | ||
632 | if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN)) | |
633 | return; | |
634 | ||
635 | lccr5 = lcd_readl(ofb->fbi, LCCR5); | |
198fc108 EM |
636 | |
637 | lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN); | |
638 | ||
639 | lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1)); | |
640 | lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1)); | |
641 | lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3); | |
642 | ||
643 | if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) | |
644 | pr_warning("%s: timeout disabling overlay1\n", __func__); | |
645 | ||
646 | lcd_writel(ofb->fbi, LCCR5, lccr5); | |
647 | } | |
648 | ||
649 | static void overlay2fb_setup(struct pxafb_layer *ofb) | |
650 | { | |
651 | int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); | |
652 | unsigned long start[3] = { ofb->video_mem_phys, 0, 0 }; | |
653 | ||
654 | if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) { | |
655 | size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; | |
656 | setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); | |
657 | } else { | |
658 | size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual; | |
659 | switch (pfor) { | |
660 | case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break; | |
661 | case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break; | |
662 | case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break; | |
663 | } | |
664 | start[1] = start[0] + size; | |
665 | start[2] = start[1] + size / div; | |
666 | setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); | |
667 | setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div); | |
668 | setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div); | |
669 | } | |
670 | } | |
671 | ||
672 | static void overlay2fb_enable(struct pxafb_layer *ofb) | |
673 | { | |
674 | int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); | |
675 | int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN; | |
676 | uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); | |
677 | uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); | |
678 | uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); | |
679 | ||
680 | if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) | |
681 | lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); | |
682 | else { | |
683 | lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); | |
684 | lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3); | |
685 | lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4); | |
686 | } | |
687 | lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]); | |
688 | lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN); | |
689 | } | |
690 | ||
691 | static void overlay2fb_disable(struct pxafb_layer *ofb) | |
692 | { | |
1b98d7c4 VK |
693 | uint32_t lccr5; |
694 | ||
695 | if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN)) | |
696 | return; | |
697 | ||
698 | lccr5 = lcd_readl(ofb->fbi, LCCR5); | |
198fc108 EM |
699 | |
700 | lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN); | |
701 | ||
702 | lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2)); | |
703 | lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2)); | |
704 | lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3); | |
705 | lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3); | |
706 | lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3); | |
707 | ||
708 | if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) | |
709 | pr_warning("%s: timeout disabling overlay2\n", __func__); | |
710 | } | |
711 | ||
712 | static struct pxafb_layer_ops ofb_ops[] = { | |
713 | [0] = { | |
714 | .enable = overlay1fb_enable, | |
715 | .disable = overlay1fb_disable, | |
716 | .setup = overlay1fb_setup, | |
717 | }, | |
718 | [1] = { | |
719 | .enable = overlay2fb_enable, | |
720 | .disable = overlay2fb_disable, | |
721 | .setup = overlay2fb_setup, | |
722 | }, | |
723 | }; | |
724 | ||
725 | static int overlayfb_open(struct fb_info *info, int user) | |
726 | { | |
727 | struct pxafb_layer *ofb = (struct pxafb_layer *)info; | |
728 | ||
729 | /* no support for framebuffer console on overlay */ | |
730 | if (user == 0) | |
731 | return -ENODEV; | |
732 | ||
1b98d7c4 VK |
733 | if (ofb->usage++ == 0) |
734 | /* unblank the base framebuffer */ | |
735 | fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK); | |
198fc108 | 736 | |
198fc108 EM |
737 | return 0; |
738 | } | |
739 | ||
740 | static int overlayfb_release(struct fb_info *info, int user) | |
741 | { | |
742 | struct pxafb_layer *ofb = (struct pxafb_layer*) info; | |
743 | ||
1b98d7c4 VK |
744 | if (ofb->usage == 1) { |
745 | ofb->ops->disable(ofb); | |
746 | ofb->fb.var.height = -1; | |
747 | ofb->fb.var.width = -1; | |
748 | ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0; | |
749 | ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0; | |
198fc108 | 750 | |
1b98d7c4 VK |
751 | ofb->usage--; |
752 | } | |
198fc108 EM |
753 | return 0; |
754 | } | |
755 | ||
756 | static int overlayfb_check_var(struct fb_var_screeninfo *var, | |
757 | struct fb_info *info) | |
758 | { | |
759 | struct pxafb_layer *ofb = (struct pxafb_layer *)info; | |
760 | struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var; | |
761 | int xpos, ypos, pfor, bpp; | |
762 | ||
763 | xpos = NONSTD_TO_XPOS(var->nonstd); | |
dcf8eee9 | 764 | ypos = NONSTD_TO_YPOS(var->nonstd); |
198fc108 EM |
765 | pfor = NONSTD_TO_PFOR(var->nonstd); |
766 | ||
767 | bpp = pxafb_var_to_bpp(var); | |
768 | if (bpp < 0) | |
769 | return -EINVAL; | |
770 | ||
771 | /* no support for YUV format on overlay1 */ | |
772 | if (ofb->id == OVERLAY1 && pfor != 0) | |
773 | return -EINVAL; | |
774 | ||
775 | /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ | |
776 | switch (pfor) { | |
777 | case OVERLAY_FORMAT_RGB: | |
778 | bpp = pxafb_var_to_bpp(var); | |
779 | if (bpp < 0) | |
780 | return -EINVAL; | |
781 | ||
782 | pxafb_set_pixfmt(var, var_to_depth(var)); | |
783 | break; | |
784 | case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; | |
785 | case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; | |
786 | case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; | |
787 | case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; | |
788 | default: | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | /* each line must start at a 32-bit word boundary */ | |
793 | if ((xpos * bpp) % 32) | |
794 | return -EINVAL; | |
795 | ||
796 | /* xres must align on 32-bit word boundary */ | |
797 | var->xres = roundup(var->xres * bpp, 32) / bpp; | |
798 | ||
799 | if ((xpos + var->xres > base_var->xres) || | |
800 | (ypos + var->yres > base_var->yres)) | |
801 | return -EINVAL; | |
802 | ||
803 | var->xres_virtual = var->xres; | |
804 | var->yres_virtual = max(var->yres, var->yres_virtual); | |
805 | return 0; | |
806 | } | |
807 | ||
1b98d7c4 | 808 | static int overlayfb_check_video_memory(struct pxafb_layer *ofb) |
198fc108 EM |
809 | { |
810 | struct fb_var_screeninfo *var = &ofb->fb.var; | |
811 | int pfor = NONSTD_TO_PFOR(var->nonstd); | |
812 | int size, bpp = 0; | |
813 | ||
814 | switch (pfor) { | |
815 | case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; | |
816 | case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; | |
817 | case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; | |
818 | case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; | |
819 | case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; | |
820 | } | |
821 | ||
822 | ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; | |
823 | ||
824 | size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual); | |
825 | ||
198fc108 EM |
826 | if (ofb->video_mem) { |
827 | if (ofb->video_mem_size >= size) | |
828 | return 0; | |
198fc108 | 829 | } |
1b98d7c4 | 830 | return -EINVAL; |
198fc108 EM |
831 | } |
832 | ||
833 | static int overlayfb_set_par(struct fb_info *info) | |
834 | { | |
835 | struct pxafb_layer *ofb = (struct pxafb_layer *)info; | |
836 | struct fb_var_screeninfo *var = &info->var; | |
837 | int xpos, ypos, pfor, bpp, ret; | |
838 | ||
1b98d7c4 | 839 | ret = overlayfb_check_video_memory(ofb); |
198fc108 EM |
840 | if (ret) |
841 | return ret; | |
842 | ||
843 | bpp = pxafb_var_to_bpp(var); | |
844 | xpos = NONSTD_TO_XPOS(var->nonstd); | |
dcf8eee9 | 845 | ypos = NONSTD_TO_YPOS(var->nonstd); |
198fc108 EM |
846 | pfor = NONSTD_TO_PFOR(var->nonstd); |
847 | ||
848 | ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) | | |
849 | OVLxC1_BPP(bpp); | |
850 | ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos); | |
851 | ||
852 | if (ofb->id == OVERLAY2) | |
853 | ofb->control[1] |= OVL2C2_PFOR(pfor); | |
854 | ||
855 | ofb->ops->setup(ofb); | |
856 | ofb->ops->enable(ofb); | |
857 | return 0; | |
858 | } | |
859 | ||
860 | static struct fb_ops overlay_fb_ops = { | |
861 | .owner = THIS_MODULE, | |
862 | .fb_open = overlayfb_open, | |
863 | .fb_release = overlayfb_release, | |
864 | .fb_check_var = overlayfb_check_var, | |
865 | .fb_set_par = overlayfb_set_par, | |
866 | }; | |
867 | ||
868 | static void __devinit init_pxafb_overlay(struct pxafb_info *fbi, | |
869 | struct pxafb_layer *ofb, int id) | |
870 | { | |
871 | sprintf(ofb->fb.fix.id, "overlay%d", id + 1); | |
872 | ||
873 | ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
874 | ofb->fb.fix.xpanstep = 0; | |
875 | ofb->fb.fix.ypanstep = 1; | |
876 | ||
877 | ofb->fb.var.activate = FB_ACTIVATE_NOW; | |
878 | ofb->fb.var.height = -1; | |
879 | ofb->fb.var.width = -1; | |
880 | ofb->fb.var.vmode = FB_VMODE_NONINTERLACED; | |
881 | ||
882 | ofb->fb.fbops = &overlay_fb_ops; | |
883 | ofb->fb.flags = FBINFO_FLAG_DEFAULT; | |
884 | ofb->fb.node = -1; | |
885 | ofb->fb.pseudo_palette = NULL; | |
886 | ||
887 | ofb->id = id; | |
888 | ofb->ops = &ofb_ops[id]; | |
1b98d7c4 | 889 | ofb->usage = 0; |
198fc108 EM |
890 | ofb->fbi = fbi; |
891 | init_completion(&ofb->branch_done); | |
892 | } | |
893 | ||
782385ae EM |
894 | static inline int pxafb_overlay_supported(void) |
895 | { | |
896 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) | |
897 | return 1; | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
1b98d7c4 VK |
902 | static int __devinit pxafb_overlay_map_video_memory(struct pxafb_info *pxafb, |
903 | struct pxafb_layer *ofb) | |
904 | { | |
905 | /* We assume that user will use at most video_mem_size for overlay fb, | |
906 | * anyway, it's useless to use 16bpp main plane and 24bpp overlay | |
907 | */ | |
908 | ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size), | |
909 | GFP_KERNEL | __GFP_ZERO); | |
910 | if (ofb->video_mem == NULL) | |
911 | return -ENOMEM; | |
912 | ||
913 | ofb->video_mem_phys = virt_to_phys(ofb->video_mem); | |
914 | ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size); | |
915 | ||
916 | mutex_lock(&ofb->fb.mm_lock); | |
917 | ofb->fb.fix.smem_start = ofb->video_mem_phys; | |
918 | ofb->fb.fix.smem_len = pxafb->video_mem_size; | |
919 | mutex_unlock(&ofb->fb.mm_lock); | |
920 | ||
921 | ofb->fb.screen_base = ofb->video_mem; | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static void __devinit pxafb_overlay_init(struct pxafb_info *fbi) | |
198fc108 EM |
927 | { |
928 | int i, ret; | |
929 | ||
782385ae | 930 | if (!pxafb_overlay_supported()) |
1b98d7c4 | 931 | return; |
782385ae | 932 | |
198fc108 | 933 | for (i = 0; i < 2; i++) { |
1b98d7c4 VK |
934 | struct pxafb_layer *ofb = &fbi->overlay[i]; |
935 | init_pxafb_overlay(fbi, ofb, i); | |
936 | ret = register_framebuffer(&ofb->fb); | |
198fc108 EM |
937 | if (ret) { |
938 | dev_err(fbi->dev, "failed to register overlay %d\n", i); | |
1b98d7c4 VK |
939 | continue; |
940 | } | |
941 | ret = pxafb_overlay_map_video_memory(fbi, ofb); | |
942 | if (ret) { | |
943 | dev_err(fbi->dev, | |
944 | "failed to map video memory for overlay %d\n", | |
945 | i); | |
946 | unregister_framebuffer(&ofb->fb); | |
947 | continue; | |
198fc108 | 948 | } |
1b98d7c4 | 949 | ofb->registered = 1; |
198fc108 EM |
950 | } |
951 | ||
952 | /* mask all IU/BS/EOF/SOF interrupts */ | |
953 | lcd_writel(fbi, LCCR5, ~0); | |
954 | ||
198fc108 | 955 | pr_info("PXA Overlay driver loaded successfully!\n"); |
198fc108 EM |
956 | } |
957 | ||
958 | static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi) | |
959 | { | |
960 | int i; | |
961 | ||
782385ae EM |
962 | if (!pxafb_overlay_supported()) |
963 | return; | |
964 | ||
1b98d7c4 VK |
965 | for (i = 0; i < 2; i++) { |
966 | struct pxafb_layer *ofb = &fbi->overlay[i]; | |
967 | if (ofb->registered) { | |
968 | if (ofb->video_mem) | |
969 | free_pages_exact(ofb->video_mem, | |
970 | ofb->video_mem_size); | |
971 | unregister_framebuffer(&ofb->fb); | |
972 | } | |
973 | } | |
198fc108 EM |
974 | } |
975 | #else | |
976 | static inline void pxafb_overlay_init(struct pxafb_info *fbi) {} | |
977 | static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {} | |
978 | #endif /* CONFIG_FB_PXA_OVERLAY */ | |
979 | ||
1da177e4 LT |
980 | /* |
981 | * Calculate the PCD value from the clock rate (in picoseconds). | |
982 | * We take account of the PPCR clock setting. | |
983 | * From PXA Developer's Manual: | |
984 | * | |
985 | * PixelClock = LCLK | |
986 | * ------------- | |
987 | * 2 ( PCD + 1 ) | |
988 | * | |
989 | * PCD = LCLK | |
990 | * ------------- - 1 | |
991 | * 2(PixelClock) | |
992 | * | |
993 | * Where: | |
994 | * LCLK = LCD/Memory Clock | |
995 | * PCD = LCCR3[7:0] | |
996 | * | |
997 | * PixelClock here is in Hz while the pixclock argument given is the | |
998 | * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) | |
999 | * | |
1000 | * The function get_lclk_frequency_10khz returns LCLK in units of | |
1001 | * 10khz. Calling the result of this function lclk gives us the | |
1002 | * following | |
1003 | * | |
1004 | * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) | |
1005 | * -------------------------------------- - 1 | |
1006 | * 2 | |
1007 | * | |
1008 | * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. | |
1009 | */ | |
b0086efb | 1010 | static inline unsigned int get_pcd(struct pxafb_info *fbi, |
1011 | unsigned int pixclock) | |
1da177e4 LT |
1012 | { |
1013 | unsigned long long pcd; | |
1014 | ||
1015 | /* FIXME: Need to take into account Double Pixel Clock mode | |
72e3524c RK |
1016 | * (DPC) bit? or perhaps set it based on the various clock |
1017 | * speeds */ | |
1018 | pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); | |
1019 | pcd *= pixclock; | |
bf1b8ab6 | 1020 | do_div(pcd, 100000000 * 2); |
1da177e4 LT |
1021 | /* no need for this, since we should subtract 1 anyway. they cancel */ |
1022 | /* pcd += 1; */ /* make up for integer math truncations */ | |
1023 | return (unsigned int)pcd; | |
1024 | } | |
1025 | ||
ba44cd2d RP |
1026 | /* |
1027 | * Some touchscreens need hsync information from the video driver to | |
72e3524c RK |
1028 | * function correctly. We export it here. Note that 'hsync_time' and |
1029 | * the value returned from pxafb_get_hsync_time() is the *reciprocal* | |
1030 | * of the hsync period in seconds. | |
ba44cd2d RP |
1031 | */ |
1032 | static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) | |
1033 | { | |
72e3524c | 1034 | unsigned long htime; |
ba44cd2d RP |
1035 | |
1036 | if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { | |
b0086efb | 1037 | fbi->hsync_time = 0; |
ba44cd2d RP |
1038 | return; |
1039 | } | |
1040 | ||
72e3524c RK |
1041 | htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); |
1042 | ||
ba44cd2d RP |
1043 | fbi->hsync_time = htime; |
1044 | } | |
1045 | ||
1046 | unsigned long pxafb_get_hsync_time(struct device *dev) | |
1047 | { | |
1048 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
1049 | ||
1050 | /* If display is blanked/suspended, hsync isn't active */ | |
1051 | if (!fbi || (fbi->state != C_ENABLE)) | |
1052 | return 0; | |
1053 | ||
1054 | return fbi->hsync_time; | |
1055 | } | |
1056 | EXPORT_SYMBOL(pxafb_get_hsync_time); | |
1057 | ||
2c42dd8e | 1058 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, |
198fc108 | 1059 | unsigned long start, size_t size) |
2c42dd8e | 1060 | { |
1061 | struct pxafb_dma_descriptor *dma_desc, *pal_desc; | |
1062 | unsigned int dma_desc_off, pal_desc_off; | |
1063 | ||
6e354846 | 1064 | if (dma < 0 || dma >= DMA_MAX * 2) |
2c42dd8e | 1065 | return -EINVAL; |
1066 | ||
1067 | dma_desc = &fbi->dma_buff->dma_desc[dma]; | |
1068 | dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); | |
1069 | ||
198fc108 | 1070 | dma_desc->fsadr = start; |
2c42dd8e | 1071 | dma_desc->fidr = 0; |
1072 | dma_desc->ldcmd = size; | |
1073 | ||
6e354846 | 1074 | if (pal < 0 || pal >= PAL_MAX * 2) { |
2c42dd8e | 1075 | dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; |
1076 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
1077 | } else { | |
62cfcf4f JS |
1078 | pal_desc = &fbi->dma_buff->pal_desc[pal]; |
1079 | pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); | |
2c42dd8e | 1080 | |
1081 | pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; | |
1082 | pal_desc->fidr = 0; | |
1083 | ||
1084 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) | |
1085 | pal_desc->ldcmd = fbi->palette_size * sizeof(u16); | |
1086 | else | |
1087 | pal_desc->ldcmd = fbi->palette_size * sizeof(u32); | |
1088 | ||
1089 | pal_desc->ldcmd |= LDCMD_PAL; | |
1090 | ||
1091 | /* flip back and forth between palette and frame buffer */ | |
1092 | pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
1093 | dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; | |
1094 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
1095 | } | |
1096 | ||
1097 | return 0; | |
1098 | } | |
1099 | ||
448ac479 SN |
1100 | static void setup_base_frame(struct pxafb_info *fbi, |
1101 | struct fb_var_screeninfo *var, | |
1102 | int branch) | |
6e354846 | 1103 | { |
6e354846 | 1104 | struct fb_fix_screeninfo *fix = &fbi->fb.fix; |
198fc108 EM |
1105 | int nbytes, dma, pal, bpp = var->bits_per_pixel; |
1106 | unsigned long offset; | |
6e354846 EM |
1107 | |
1108 | dma = DMA_BASE + (branch ? DMA_MAX : 0); | |
1109 | pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); | |
1110 | ||
1111 | nbytes = fix->line_length * var->yres; | |
198fc108 | 1112 | offset = fix->line_length * var->yoffset + fbi->video_mem_phys; |
6e354846 EM |
1113 | |
1114 | if (fbi->lccr0 & LCCR0_SDS) { | |
1115 | nbytes = nbytes / 2; | |
1116 | setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes); | |
1117 | } | |
1118 | ||
1119 | setup_frame_dma(fbi, dma, pal, offset, nbytes); | |
1120 | } | |
1121 | ||
3c42a449 EM |
1122 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1123 | static int setup_smart_dma(struct pxafb_info *fbi) | |
1124 | { | |
1125 | struct pxafb_dma_descriptor *dma_desc; | |
1126 | unsigned long dma_desc_off, cmd_buff_off; | |
1127 | ||
1128 | dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD]; | |
1129 | dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]); | |
1130 | cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff); | |
1131 | ||
1132 | dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
1133 | dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off; | |
1134 | dma_desc->fidr = 0; | |
1135 | dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t); | |
1136 | ||
1137 | fbi->fdadr[DMA_CMD] = dma_desc->fdadr; | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | int pxafb_smart_flush(struct fb_info *info) | |
1142 | { | |
1143 | struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); | |
1144 | uint32_t prsr; | |
1145 | int ret = 0; | |
1146 | ||
1147 | /* disable controller until all registers are set up */ | |
1148 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
1149 | ||
1150 | /* 1. make it an even number of commands to align on 32-bit boundary | |
1151 | * 2. add the interrupt command to the end of the chain so we can | |
1152 | * keep track of the end of the transfer | |
1153 | */ | |
1154 | ||
1155 | while (fbi->n_smart_cmds & 1) | |
1156 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP; | |
1157 | ||
1158 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT; | |
1159 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC; | |
1160 | setup_smart_dma(fbi); | |
1161 | ||
1162 | /* continue to execute next command */ | |
1163 | prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT; | |
1164 | lcd_writel(fbi, PRSR, prsr); | |
1165 | ||
1166 | /* stop the processor in case it executed "wait for sync" cmd */ | |
1167 | lcd_writel(fbi, CMDCR, 0x0001); | |
1168 | ||
1169 | /* don't send interrupts for fifo underruns on channel 6 */ | |
1170 | lcd_writel(fbi, LCCR5, LCCR5_IUM(6)); | |
1171 | ||
1172 | lcd_writel(fbi, LCCR1, fbi->reg_lccr1); | |
1173 | lcd_writel(fbi, LCCR2, fbi->reg_lccr2); | |
1174 | lcd_writel(fbi, LCCR3, fbi->reg_lccr3); | |
a0427509 | 1175 | lcd_writel(fbi, LCCR4, fbi->reg_lccr4); |
3c42a449 EM |
1176 | lcd_writel(fbi, FDADR0, fbi->fdadr[0]); |
1177 | lcd_writel(fbi, FDADR6, fbi->fdadr[6]); | |
1178 | ||
1179 | /* begin sending */ | |
1180 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); | |
1181 | ||
1182 | if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) { | |
1183 | pr_warning("%s: timeout waiting for command done\n", | |
1184 | __func__); | |
1185 | ret = -ETIMEDOUT; | |
1186 | } | |
1187 | ||
1188 | /* quick disable */ | |
1189 | prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT); | |
1190 | lcd_writel(fbi, PRSR, prsr); | |
1191 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
1192 | lcd_writel(fbi, FDADR6, 0); | |
1193 | fbi->n_smart_cmds = 0; | |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) | |
1198 | { | |
1199 | int i; | |
1200 | struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); | |
1201 | ||
69bdea70 EM |
1202 | for (i = 0; i < n_cmds; i++, cmds++) { |
1203 | /* if it is a software delay, flush and delay */ | |
1204 | if ((*cmds & 0xff00) == SMART_CMD_DELAY) { | |
1205 | pxafb_smart_flush(info); | |
1206 | mdelay(*cmds & 0xff); | |
1207 | continue; | |
1208 | } | |
1209 | ||
1210 | /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ | |
3c42a449 EM |
1211 | if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) |
1212 | pxafb_smart_flush(info); | |
1213 | ||
69bdea70 | 1214 | fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds; |
3c42a449 EM |
1215 | } |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) | |
1221 | { | |
1222 | unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000); | |
1223 | return (t == 0) ? 1 : t; | |
1224 | } | |
1225 | ||
1226 | static void setup_smart_timing(struct pxafb_info *fbi, | |
1227 | struct fb_var_screeninfo *var) | |
1228 | { | |
1229 | struct pxafb_mach_info *inf = fbi->dev->platform_data; | |
1230 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
1231 | unsigned long lclk = clk_get_rate(fbi->clk); | |
1232 | unsigned t1, t2, t3, t4; | |
1233 | ||
1234 | t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld); | |
1235 | t2 = max(mode->rd_pulse_width, mode->wr_pulse_width); | |
1236 | t3 = mode->op_hold_time; | |
1237 | t4 = mode->cmd_inh_time; | |
1238 | ||
1239 | fbi->reg_lccr1 = | |
1240 | LCCR1_DisWdth(var->xres) | | |
1241 | LCCR1_BegLnDel(__smart_timing(t1, lclk)) | | |
1242 | LCCR1_EndLnDel(__smart_timing(t2, lclk)) | | |
1243 | LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); | |
1244 | ||
1245 | fbi->reg_lccr2 = LCCR2_DisHght(var->yres); | |
c1f99c21 EM |
1246 | fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); |
1247 | fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; | |
1248 | fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; | |
3c42a449 EM |
1249 | |
1250 | /* FIXME: make this configurable */ | |
1251 | fbi->reg_cmdcr = 1; | |
1252 | } | |
1253 | ||
1254 | static int pxafb_smart_thread(void *arg) | |
1255 | { | |
7f1133cb | 1256 | struct pxafb_info *fbi = arg; |
da2c3f0e | 1257 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
3c42a449 | 1258 | |
da2c3f0e | 1259 | if (!inf->smart_update) { |
3c42a449 EM |
1260 | pr_err("%s: not properly initialized, thread terminated\n", |
1261 | __func__); | |
1262 | return -EINVAL; | |
1263 | } | |
d2a34c13 | 1264 | inf = fbi->dev->platform_data; |
3c42a449 EM |
1265 | |
1266 | pr_debug("%s(): task starting\n", __func__); | |
1267 | ||
1268 | set_freezable(); | |
1269 | while (!kthread_should_stop()) { | |
1270 | ||
1271 | if (try_to_freeze()) | |
1272 | continue; | |
1273 | ||
07f651c7 EM |
1274 | mutex_lock(&fbi->ctrlr_lock); |
1275 | ||
3c42a449 EM |
1276 | if (fbi->state == C_ENABLE) { |
1277 | inf->smart_update(&fbi->fb); | |
1278 | complete(&fbi->refresh_done); | |
1279 | } | |
1280 | ||
07f651c7 EM |
1281 | mutex_unlock(&fbi->ctrlr_lock); |
1282 | ||
3c42a449 EM |
1283 | set_current_state(TASK_INTERRUPTIBLE); |
1284 | schedule_timeout(30 * HZ / 1000); | |
1285 | } | |
1286 | ||
1287 | pr_debug("%s(): task ending\n", __func__); | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static int pxafb_smart_init(struct pxafb_info *fbi) | |
1292 | { | |
07df1c4f | 1293 | if (!(fbi->lccr0 & LCCR0_LCDT)) |
6cc4abe4 EM |
1294 | return 0; |
1295 | ||
07df1c4f EM |
1296 | fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; |
1297 | fbi->n_smart_cmds = 0; | |
1298 | ||
1299 | init_completion(&fbi->command_done); | |
1300 | init_completion(&fbi->refresh_done); | |
1301 | ||
3c42a449 EM |
1302 | fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, |
1303 | "lcd_refresh"); | |
1304 | if (IS_ERR(fbi->smart_thread)) { | |
07df1c4f | 1305 | pr_err("%s: unable to create kernel thread\n", __func__); |
3c42a449 EM |
1306 | return PTR_ERR(fbi->smart_thread); |
1307 | } | |
a5718a14 | 1308 | |
3c42a449 EM |
1309 | return 0; |
1310 | } | |
1311 | #else | |
1312 | int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) | |
1313 | { | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | int pxafb_smart_flush(struct fb_info *info) | |
1318 | { | |
1319 | return 0; | |
1320 | } | |
07df1c4f EM |
1321 | |
1322 | static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } | |
1323 | #endif /* CONFIG_FB_PXA_SMARTPANEL */ | |
3c42a449 | 1324 | |
90eabbf0 EM |
1325 | static void setup_parallel_timing(struct pxafb_info *fbi, |
1326 | struct fb_var_screeninfo *var) | |
1327 | { | |
1328 | unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); | |
1329 | ||
1330 | fbi->reg_lccr1 = | |
1331 | LCCR1_DisWdth(var->xres) + | |
1332 | LCCR1_HorSnchWdth(var->hsync_len) + | |
1333 | LCCR1_BegLnDel(var->left_margin) + | |
1334 | LCCR1_EndLnDel(var->right_margin); | |
1335 | ||
1336 | /* | |
1337 | * If we have a dual scan LCD, we need to halve | |
1338 | * the YRES parameter. | |
1339 | */ | |
1340 | lines_per_panel = var->yres; | |
1341 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
1342 | lines_per_panel /= 2; | |
1343 | ||
1344 | fbi->reg_lccr2 = | |
1345 | LCCR2_DisHght(lines_per_panel) + | |
1346 | LCCR2_VrtSnchWdth(var->vsync_len) + | |
1347 | LCCR2_BegFrmDel(var->upper_margin) + | |
1348 | LCCR2_EndFrmDel(var->lower_margin); | |
1349 | ||
1350 | fbi->reg_lccr3 = fbi->lccr3 | | |
1351 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? | |
1352 | LCCR3_HorSnchH : LCCR3_HorSnchL) | | |
1353 | (var->sync & FB_SYNC_VERT_HIGH_ACT ? | |
1354 | LCCR3_VrtSnchH : LCCR3_VrtSnchL); | |
1355 | ||
1356 | if (pcd) { | |
1357 | fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd); | |
1358 | set_hsync_time(fbi, pcd); | |
1359 | } | |
1360 | } | |
1361 | ||
1da177e4 LT |
1362 | /* |
1363 | * pxafb_activate_var(): | |
b0086efb | 1364 | * Configures LCD Controller based on entries in var parameter. |
1365 | * Settings are only written to the controller if changes were made. | |
1da177e4 | 1366 | */ |
b0086efb | 1367 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
1368 | struct pxafb_info *fbi) | |
1da177e4 | 1369 | { |
1da177e4 | 1370 | u_long flags; |
1da177e4 | 1371 | |
90eabbf0 EM |
1372 | /* Update shadow copy atomically */ |
1373 | local_irq_save(flags); | |
1da177e4 | 1374 | |
3c42a449 EM |
1375 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1376 | if (fbi->lccr0 & LCCR0_LCDT) | |
1377 | setup_smart_timing(fbi, var); | |
1378 | else | |
1379 | #endif | |
1380 | setup_parallel_timing(fbi, var); | |
90eabbf0 | 1381 | |
448ac479 | 1382 | setup_base_frame(fbi, var, 0); |
6e354846 | 1383 | |
90eabbf0 | 1384 | fbi->reg_lccr0 = fbi->lccr0 | |
1da177e4 | 1385 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | |
b0086efb | 1386 | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); |
1da177e4 | 1387 | |
878f5783 | 1388 | fbi->reg_lccr3 |= pxafb_var_to_lccr3(var); |
1da177e4 | 1389 | |
a7535ba7 | 1390 | fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; |
9ffa7396 | 1391 | fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); |
1da177e4 LT |
1392 | local_irq_restore(flags); |
1393 | ||
1394 | /* | |
1395 | * Only update the registers if the controller is enabled | |
1396 | * and something has changed. | |
1397 | */ | |
a7535ba7 EM |
1398 | if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || |
1399 | (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || | |
1400 | (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || | |
1401 | (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || | |
a0427509 | 1402 | (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) || |
a7535ba7 | 1403 | (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || |
1b98d7c4 VK |
1404 | ((fbi->lccr0 & LCCR0_SDS) && |
1405 | (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))) | |
1da177e4 LT |
1406 | pxafb_schedule_work(fbi, C_REENABLE); |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | /* | |
1412 | * NOTE! The following functions are purely helpers for set_ctrlr_state. | |
1413 | * Do not call them directly; set_ctrlr_state does the correct serialisation | |
1414 | * to ensure that things happen in the right way 100% of time time. | |
1415 | * -- rmk | |
1416 | */ | |
1417 | static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) | |
1418 | { | |
ca5da710 | 1419 | pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); |
1da177e4 | 1420 | |
a5718a14 EM |
1421 | if (fbi->backlight_power) |
1422 | fbi->backlight_power(on); | |
1da177e4 LT |
1423 | } |
1424 | ||
1425 | static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) | |
1426 | { | |
ca5da710 | 1427 | pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); |
1da177e4 | 1428 | |
a5718a14 EM |
1429 | if (fbi->lcd_power) |
1430 | fbi->lcd_power(on, &fbi->fb.var); | |
1da177e4 LT |
1431 | } |
1432 | ||
1da177e4 LT |
1433 | static void pxafb_enable_controller(struct pxafb_info *fbi) |
1434 | { | |
ca5da710 | 1435 | pr_debug("pxafb: Enabling LCD controller\n"); |
2c42dd8e | 1436 | pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); |
1437 | pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); | |
ca5da710 RK |
1438 | pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); |
1439 | pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); | |
1440 | pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); | |
1441 | pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); | |
1da177e4 | 1442 | |
8d372266 | 1443 | /* enable LCD controller clock */ |
72e3524c | 1444 | clk_enable(fbi->clk); |
8d372266 | 1445 | |
3c42a449 EM |
1446 | if (fbi->lccr0 & LCCR0_LCDT) |
1447 | return; | |
1448 | ||
1da177e4 | 1449 | /* Sequence from 11.7.10 */ |
a0427509 | 1450 | lcd_writel(fbi, LCCR4, fbi->reg_lccr4); |
a7535ba7 EM |
1451 | lcd_writel(fbi, LCCR3, fbi->reg_lccr3); |
1452 | lcd_writel(fbi, LCCR2, fbi->reg_lccr2); | |
1453 | lcd_writel(fbi, LCCR1, fbi->reg_lccr1); | |
1454 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
1455 | ||
1456 | lcd_writel(fbi, FDADR0, fbi->fdadr[0]); | |
1b98d7c4 VK |
1457 | if (fbi->lccr0 & LCCR0_SDS) |
1458 | lcd_writel(fbi, FDADR1, fbi->fdadr[1]); | |
a7535ba7 | 1459 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); |
1da177e4 LT |
1460 | } |
1461 | ||
1462 | static void pxafb_disable_controller(struct pxafb_info *fbi) | |
1463 | { | |
ce4fb7b8 | 1464 | uint32_t lccr0; |
1465 | ||
3c42a449 EM |
1466 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1467 | if (fbi->lccr0 & LCCR0_LCDT) { | |
1468 | wait_for_completion_timeout(&fbi->refresh_done, | |
1469 | 200 * HZ / 1000); | |
1470 | return; | |
1471 | } | |
1472 | #endif | |
1473 | ||
ce4fb7b8 | 1474 | /* Clear LCD Status Register */ |
a7535ba7 | 1475 | lcd_writel(fbi, LCSR, 0xffffffff); |
ce4fb7b8 | 1476 | |
a7535ba7 EM |
1477 | lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; |
1478 | lcd_writel(fbi, LCCR0, lccr0); | |
1479 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); | |
1da177e4 | 1480 | |
2ba162b9 | 1481 | wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000); |
8d372266 NP |
1482 | |
1483 | /* disable LCD controller clock */ | |
72e3524c | 1484 | clk_disable(fbi->clk); |
1da177e4 LT |
1485 | } |
1486 | ||
1487 | /* | |
1488 | * pxafb_handle_irq: Handle 'LCD DONE' interrupts. | |
1489 | */ | |
7d12e780 | 1490 | static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) |
1da177e4 LT |
1491 | { |
1492 | struct pxafb_info *fbi = dev_id; | |
ff14ed5d | 1493 | unsigned int lccr0, lcsr; |
1da177e4 | 1494 | |
198fc108 | 1495 | lcsr = lcd_readl(fbi, LCSR); |
1da177e4 | 1496 | if (lcsr & LCSR_LDD) { |
a7535ba7 EM |
1497 | lccr0 = lcd_readl(fbi, LCCR0); |
1498 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); | |
2ba162b9 | 1499 | complete(&fbi->disable_done); |
1da177e4 LT |
1500 | } |
1501 | ||
3c42a449 EM |
1502 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1503 | if (lcsr & LCSR_CMD_INT) | |
1504 | complete(&fbi->command_done); | |
1505 | #endif | |
a7535ba7 | 1506 | lcd_writel(fbi, LCSR, lcsr); |
198fc108 EM |
1507 | |
1508 | #ifdef CONFIG_FB_PXA_OVERLAY | |
ff14ed5d DL |
1509 | { |
1510 | unsigned int lcsr1 = lcd_readl(fbi, LCSR1); | |
1511 | if (lcsr1 & LCSR1_BS(1)) | |
1512 | complete(&fbi->overlay[0].branch_done); | |
198fc108 | 1513 | |
ff14ed5d DL |
1514 | if (lcsr1 & LCSR1_BS(2)) |
1515 | complete(&fbi->overlay[1].branch_done); | |
198fc108 | 1516 | |
ff14ed5d DL |
1517 | lcd_writel(fbi, LCSR1, lcsr1); |
1518 | } | |
198fc108 | 1519 | #endif |
1da177e4 LT |
1520 | return IRQ_HANDLED; |
1521 | } | |
1522 | ||
1523 | /* | |
1524 | * This function must be called from task context only, since it will | |
1525 | * sleep when disabling the LCD controller, or if we get two contending | |
1526 | * processes trying to alter state. | |
1527 | */ | |
1528 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) | |
1529 | { | |
1530 | u_int old_state; | |
1531 | ||
b91dbce5 | 1532 | mutex_lock(&fbi->ctrlr_lock); |
1da177e4 LT |
1533 | |
1534 | old_state = fbi->state; | |
1535 | ||
1536 | /* | |
1537 | * Hack around fbcon initialisation. | |
1538 | */ | |
1539 | if (old_state == C_STARTUP && state == C_REENABLE) | |
1540 | state = C_ENABLE; | |
1541 | ||
1542 | switch (state) { | |
1543 | case C_DISABLE_CLKCHANGE: | |
1544 | /* | |
1545 | * Disable controller for clock change. If the | |
1546 | * controller is already disabled, then do nothing. | |
1547 | */ | |
1548 | if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { | |
1549 | fbi->state = state; | |
b0086efb | 1550 | /* TODO __pxafb_lcd_power(fbi, 0); */ |
1da177e4 LT |
1551 | pxafb_disable_controller(fbi); |
1552 | } | |
1553 | break; | |
1554 | ||
1555 | case C_DISABLE_PM: | |
1556 | case C_DISABLE: | |
1557 | /* | |
1558 | * Disable controller | |
1559 | */ | |
1560 | if (old_state != C_DISABLE) { | |
1561 | fbi->state = state; | |
1562 | __pxafb_backlight_power(fbi, 0); | |
1563 | __pxafb_lcd_power(fbi, 0); | |
1564 | if (old_state != C_DISABLE_CLKCHANGE) | |
1565 | pxafb_disable_controller(fbi); | |
1566 | } | |
1567 | break; | |
1568 | ||
1569 | case C_ENABLE_CLKCHANGE: | |
1570 | /* | |
1571 | * Enable the controller after clock change. Only | |
1572 | * do this if we were disabled for the clock change. | |
1573 | */ | |
1574 | if (old_state == C_DISABLE_CLKCHANGE) { | |
1575 | fbi->state = C_ENABLE; | |
1576 | pxafb_enable_controller(fbi); | |
b0086efb | 1577 | /* TODO __pxafb_lcd_power(fbi, 1); */ |
1da177e4 LT |
1578 | } |
1579 | break; | |
1580 | ||
1581 | case C_REENABLE: | |
1582 | /* | |
1583 | * Re-enable the controller only if it was already | |
1584 | * enabled. This is so we reprogram the control | |
1585 | * registers. | |
1586 | */ | |
1587 | if (old_state == C_ENABLE) { | |
d14b272b | 1588 | __pxafb_lcd_power(fbi, 0); |
1da177e4 | 1589 | pxafb_disable_controller(fbi); |
1da177e4 | 1590 | pxafb_enable_controller(fbi); |
d14b272b | 1591 | __pxafb_lcd_power(fbi, 1); |
1da177e4 LT |
1592 | } |
1593 | break; | |
1594 | ||
1595 | case C_ENABLE_PM: | |
1596 | /* | |
1597 | * Re-enable the controller after PM. This is not | |
1598 | * perfect - think about the case where we were doing | |
1599 | * a clock change, and we suspended half-way through. | |
1600 | */ | |
1601 | if (old_state != C_DISABLE_PM) | |
1602 | break; | |
1603 | /* fall through */ | |
1604 | ||
1605 | case C_ENABLE: | |
1606 | /* | |
1607 | * Power up the LCD screen, enable controller, and | |
1608 | * turn on the backlight. | |
1609 | */ | |
1610 | if (old_state != C_ENABLE) { | |
1611 | fbi->state = C_ENABLE; | |
1da177e4 LT |
1612 | pxafb_enable_controller(fbi); |
1613 | __pxafb_lcd_power(fbi, 1); | |
1614 | __pxafb_backlight_power(fbi, 1); | |
1615 | } | |
1616 | break; | |
1617 | } | |
b91dbce5 | 1618 | mutex_unlock(&fbi->ctrlr_lock); |
1da177e4 LT |
1619 | } |
1620 | ||
1621 | /* | |
1622 | * Our LCD controller task (which is called when we blank or unblank) | |
1623 | * via keventd. | |
1624 | */ | |
6d5aefb8 | 1625 | static void pxafb_task(struct work_struct *work) |
1da177e4 | 1626 | { |
6d5aefb8 DH |
1627 | struct pxafb_info *fbi = |
1628 | container_of(work, struct pxafb_info, task); | |
1da177e4 LT |
1629 | u_int state = xchg(&fbi->task_state, -1); |
1630 | ||
1631 | set_ctrlr_state(fbi, state); | |
1632 | } | |
1633 | ||
1634 | #ifdef CONFIG_CPU_FREQ | |
1635 | /* | |
1636 | * CPU clock speed change handler. We need to adjust the LCD timing | |
1637 | * parameters when the CPU clock is adjusted by the power management | |
1638 | * subsystem. | |
1639 | * | |
1640 | * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() | |
1641 | */ | |
1642 | static int | |
1643 | pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) | |
1644 | { | |
1645 | struct pxafb_info *fbi = TO_INF(nb, freq_transition); | |
b0086efb | 1646 | /* TODO struct cpufreq_freqs *f = data; */ |
1da177e4 LT |
1647 | u_int pcd; |
1648 | ||
1649 | switch (val) { | |
1650 | case CPUFREQ_PRECHANGE: | |
a6d710fe MV |
1651 | #ifdef CONFIG_FB_PXA_OVERLAY |
1652 | if (!(fbi->overlay[0].usage || fbi->overlay[1].usage)) | |
1653 | #endif | |
27be9a9e | 1654 | set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); |
1da177e4 LT |
1655 | break; |
1656 | ||
1657 | case CPUFREQ_POSTCHANGE: | |
72e3524c | 1658 | pcd = get_pcd(fbi, fbi->fb.var.pixclock); |
ba44cd2d | 1659 | set_hsync_time(fbi, pcd); |
b0086efb | 1660 | fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | |
1661 | LCCR3_PixClkDiv(pcd); | |
1da177e4 LT |
1662 | set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); |
1663 | break; | |
1664 | } | |
1665 | return 0; | |
1666 | } | |
1667 | ||
1668 | static int | |
1669 | pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) | |
1670 | { | |
1671 | struct pxafb_info *fbi = TO_INF(nb, freq_policy); | |
1672 | struct fb_var_screeninfo *var = &fbi->fb.var; | |
1673 | struct cpufreq_policy *policy = data; | |
1674 | ||
1675 | switch (val) { | |
1676 | case CPUFREQ_ADJUST: | |
1677 | case CPUFREQ_INCOMPATIBLE: | |
ac2bf5bd | 1678 | pr_debug("min dma period: %d ps, " |
1da177e4 LT |
1679 | "new clock %d kHz\n", pxafb_display_dma_period(var), |
1680 | policy->max); | |
b0086efb | 1681 | /* TODO: fill in min/max values */ |
1da177e4 | 1682 | break; |
1da177e4 LT |
1683 | } |
1684 | return 0; | |
1685 | } | |
1686 | #endif | |
1687 | ||
1688 | #ifdef CONFIG_PM | |
1689 | /* | |
1690 | * Power management hooks. Note that we won't be called from IRQ context, | |
1691 | * unlike the blank functions above, so we may sleep. | |
1692 | */ | |
4f3edfe3 | 1693 | static int pxafb_suspend(struct device *dev) |
1da177e4 | 1694 | { |
4f3edfe3 | 1695 | struct pxafb_info *fbi = dev_get_drvdata(dev); |
1da177e4 | 1696 | |
9480e307 | 1697 | set_ctrlr_state(fbi, C_DISABLE_PM); |
1da177e4 LT |
1698 | return 0; |
1699 | } | |
1700 | ||
4f3edfe3 | 1701 | static int pxafb_resume(struct device *dev) |
1da177e4 | 1702 | { |
4f3edfe3 | 1703 | struct pxafb_info *fbi = dev_get_drvdata(dev); |
1da177e4 | 1704 | |
9480e307 | 1705 | set_ctrlr_state(fbi, C_ENABLE_PM); |
1da177e4 LT |
1706 | return 0; |
1707 | } | |
4f3edfe3 | 1708 | |
47145210 | 1709 | static const struct dev_pm_ops pxafb_pm_ops = { |
4f3edfe3 MR |
1710 | .suspend = pxafb_suspend, |
1711 | .resume = pxafb_resume, | |
1712 | }; | |
1da177e4 LT |
1713 | #endif |
1714 | ||
77e19675 | 1715 | static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi) |
1da177e4 | 1716 | { |
77e19675 | 1717 | int size = PAGE_ALIGN(fbi->video_mem_size); |
3c42a449 | 1718 | |
77e19675 EM |
1719 | fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); |
1720 | if (fbi->video_mem == NULL) | |
1721 | return -ENOMEM; | |
1da177e4 | 1722 | |
77e19675 EM |
1723 | fbi->video_mem_phys = virt_to_phys(fbi->video_mem); |
1724 | fbi->video_mem_size = size; | |
1da177e4 | 1725 | |
77e19675 EM |
1726 | fbi->fb.fix.smem_start = fbi->video_mem_phys; |
1727 | fbi->fb.fix.smem_len = fbi->video_mem_size; | |
1728 | fbi->fb.screen_base = fbi->video_mem; | |
84f43c30 | 1729 | |
77e19675 | 1730 | return fbi->video_mem ? 0 : -ENOMEM; |
84f43c30 | 1731 | } |
1732 | ||
ebdf982a GL |
1733 | static void pxafb_decode_mach_info(struct pxafb_info *fbi, |
1734 | struct pxafb_mach_info *inf) | |
84f43c30 | 1735 | { |
1736 | unsigned int lcd_conn = inf->lcd_conn; | |
77e19675 EM |
1737 | struct pxafb_mode_info *m; |
1738 | int i; | |
84f43c30 | 1739 | |
1740 | fbi->cmap_inverse = inf->cmap_inverse; | |
1741 | fbi->cmap_static = inf->cmap_static; | |
a0427509 | 1742 | fbi->lccr4 = inf->lccr4; |
84f43c30 | 1743 | |
1ec26db1 | 1744 | switch (lcd_conn & LCD_TYPE_MASK) { |
84f43c30 | 1745 | case LCD_TYPE_MONO_STN: |
1746 | fbi->lccr0 = LCCR0_CMS; | |
1747 | break; | |
1748 | case LCD_TYPE_MONO_DSTN: | |
1749 | fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; | |
1750 | break; | |
1751 | case LCD_TYPE_COLOR_STN: | |
1752 | fbi->lccr0 = 0; | |
1753 | break; | |
1754 | case LCD_TYPE_COLOR_DSTN: | |
1755 | fbi->lccr0 = LCCR0_SDS; | |
1756 | break; | |
1757 | case LCD_TYPE_COLOR_TFT: | |
1758 | fbi->lccr0 = LCCR0_PAS; | |
1759 | break; | |
1760 | case LCD_TYPE_SMART_PANEL: | |
1761 | fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; | |
1762 | break; | |
1763 | default: | |
1764 | /* fall back to backward compatibility way */ | |
1765 | fbi->lccr0 = inf->lccr0; | |
1766 | fbi->lccr3 = inf->lccr3; | |
ebdf982a | 1767 | goto decode_mode; |
84f43c30 | 1768 | } |
1769 | ||
1770 | if (lcd_conn == LCD_MONO_STN_8BPP) | |
1771 | fbi->lccr0 |= LCCR0_DPD; | |
1772 | ||
9a1ac7e4 EM |
1773 | fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0; |
1774 | ||
84f43c30 | 1775 | fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); |
1776 | fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; | |
1777 | fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; | |
1778 | ||
ebdf982a | 1779 | decode_mode: |
77e19675 EM |
1780 | pxafb_setmode(&fbi->fb.var, &inf->modes[0]); |
1781 | ||
1782 | /* decide video memory size as follows: | |
1783 | * 1. default to mode of maximum resolution | |
1784 | * 2. allow platform to override | |
1785 | * 3. allow module parameter to override | |
1786 | */ | |
1787 | for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++) | |
1788 | fbi->video_mem_size = max_t(size_t, fbi->video_mem_size, | |
1789 | m->xres * m->yres * m->bpp / 8); | |
1790 | ||
1791 | if (inf->video_mem_size > fbi->video_mem_size) | |
1792 | fbi->video_mem_size = inf->video_mem_size; | |
1793 | ||
1794 | if (video_mem_size > fbi->video_mem_size) | |
1795 | fbi->video_mem_size = video_mem_size; | |
84f43c30 | 1796 | } |
1797 | ||
9e6c2976 | 1798 | static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) |
1da177e4 LT |
1799 | { |
1800 | struct pxafb_info *fbi; | |
1801 | void *addr; | |
1802 | struct pxafb_mach_info *inf = dev->platform_data; | |
1803 | ||
1804 | /* Alloc the pxafb_info and pseudo_palette in one step */ | |
1805 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | |
1806 | if (!fbi) | |
1807 | return NULL; | |
1808 | ||
1809 | memset(fbi, 0, sizeof(struct pxafb_info)); | |
1810 | fbi->dev = dev; | |
1811 | ||
e0d8b13a | 1812 | fbi->clk = clk_get(dev, NULL); |
72e3524c RK |
1813 | if (IS_ERR(fbi->clk)) { |
1814 | kfree(fbi); | |
1815 | return NULL; | |
1816 | } | |
1817 | ||
1da177e4 LT |
1818 | strcpy(fbi->fb.fix.id, PXA_NAME); |
1819 | ||
1820 | fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1821 | fbi->fb.fix.type_aux = 0; | |
1822 | fbi->fb.fix.xpanstep = 0; | |
7e4b19c9 | 1823 | fbi->fb.fix.ypanstep = 1; |
1da177e4 LT |
1824 | fbi->fb.fix.ywrapstep = 0; |
1825 | fbi->fb.fix.accel = FB_ACCEL_NONE; | |
1826 | ||
1827 | fbi->fb.var.nonstd = 0; | |
1828 | fbi->fb.var.activate = FB_ACTIVATE_NOW; | |
1829 | fbi->fb.var.height = -1; | |
1830 | fbi->fb.var.width = -1; | |
7e4b19c9 | 1831 | fbi->fb.var.accel_flags = FB_ACCELF_TEXT; |
1da177e4 LT |
1832 | fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; |
1833 | ||
1834 | fbi->fb.fbops = &pxafb_ops; | |
1835 | fbi->fb.flags = FBINFO_DEFAULT; | |
1836 | fbi->fb.node = -1; | |
1837 | ||
1838 | addr = fbi; | |
1839 | addr = addr + sizeof(struct pxafb_info); | |
1840 | fbi->fb.pseudo_palette = addr; | |
1841 | ||
b0086efb | 1842 | fbi->state = C_STARTUP; |
1843 | fbi->task_state = (u_char)-1; | |
d14b272b | 1844 | |
84f43c30 | 1845 | pxafb_decode_mach_info(fbi, inf); |
1da177e4 | 1846 | |
7779cee3 VK |
1847 | #ifdef CONFIG_FB_PXA_OVERLAY |
1848 | /* place overlay(s) on top of base */ | |
1849 | if (pxafb_overlay_supported()) | |
1850 | fbi->lccr0 |= LCCR0_OUC; | |
1851 | #endif | |
1852 | ||
1da177e4 | 1853 | init_waitqueue_head(&fbi->ctrlr_wait); |
6d5aefb8 | 1854 | INIT_WORK(&fbi->task, pxafb_task); |
b91dbce5 | 1855 | mutex_init(&fbi->ctrlr_lock); |
2ba162b9 | 1856 | init_completion(&fbi->disable_done); |
1da177e4 LT |
1857 | |
1858 | return fbi; | |
1859 | } | |
1860 | ||
1861 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
9e6c2976 | 1862 | static int __devinit parse_opt_mode(struct device *dev, const char *this_opt) |
1da177e4 LT |
1863 | { |
1864 | struct pxafb_mach_info *inf = dev->platform_data; | |
817daf14 | 1865 | |
1866 | const char *name = this_opt+5; | |
1867 | unsigned int namelen = strlen(name); | |
1868 | int res_specified = 0, bpp_specified = 0; | |
1869 | unsigned int xres = 0, yres = 0, bpp = 0; | |
1870 | int yres_specified = 0; | |
1871 | int i; | |
1872 | for (i = namelen-1; i >= 0; i--) { | |
1873 | switch (name[i]) { | |
1874 | case '-': | |
1875 | namelen = i; | |
1876 | if (!bpp_specified && !yres_specified) { | |
1877 | bpp = simple_strtoul(&name[i+1], NULL, 0); | |
1878 | bpp_specified = 1; | |
1879 | } else | |
1880 | goto done; | |
1881 | break; | |
1882 | case 'x': | |
1883 | if (!yres_specified) { | |
1884 | yres = simple_strtoul(&name[i+1], NULL, 0); | |
1885 | yres_specified = 1; | |
1886 | } else | |
1887 | goto done; | |
1888 | break; | |
1889 | case '0' ... '9': | |
1890 | break; | |
1891 | default: | |
1892 | goto done; | |
1893 | } | |
1894 | } | |
1895 | if (i < 0 && yres_specified) { | |
1896 | xres = simple_strtoul(name, NULL, 0); | |
1897 | res_specified = 1; | |
1898 | } | |
1899 | done: | |
1900 | if (res_specified) { | |
1901 | dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); | |
1902 | inf->modes[0].xres = xres; inf->modes[0].yres = yres; | |
1903 | } | |
1904 | if (bpp_specified) | |
1905 | switch (bpp) { | |
1906 | case 1: | |
1907 | case 2: | |
1908 | case 4: | |
1909 | case 8: | |
1910 | case 16: | |
1911 | inf->modes[0].bpp = bpp; | |
1912 | dev_info(dev, "overriding bit depth: %d\n", bpp); | |
1913 | break; | |
1914 | default: | |
1915 | dev_err(dev, "Depth %d is not valid\n", bpp); | |
1916 | return -EINVAL; | |
1917 | } | |
1918 | return 0; | |
1919 | } | |
1920 | ||
9e6c2976 | 1921 | static int __devinit parse_opt(struct device *dev, char *this_opt) |
817daf14 | 1922 | { |
1923 | struct pxafb_mach_info *inf = dev->platform_data; | |
1924 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
1925 | char s[64]; | |
1926 | ||
1927 | s[0] = '\0'; | |
1928 | ||
77e19675 EM |
1929 | if (!strncmp(this_opt, "vmem:", 5)) { |
1930 | video_mem_size = memparse(this_opt + 5, NULL); | |
1931 | } else if (!strncmp(this_opt, "mode:", 5)) { | |
817daf14 | 1932 | return parse_opt_mode(dev, this_opt); |
1933 | } else if (!strncmp(this_opt, "pixclock:", 9)) { | |
1934 | mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); | |
1935 | sprintf(s, "pixclock: %ld\n", mode->pixclock); | |
1936 | } else if (!strncmp(this_opt, "left:", 5)) { | |
1937 | mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); | |
1938 | sprintf(s, "left: %u\n", mode->left_margin); | |
1939 | } else if (!strncmp(this_opt, "right:", 6)) { | |
1940 | mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1941 | sprintf(s, "right: %u\n", mode->right_margin); | |
1942 | } else if (!strncmp(this_opt, "upper:", 6)) { | |
1943 | mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1944 | sprintf(s, "upper: %u\n", mode->upper_margin); | |
1945 | } else if (!strncmp(this_opt, "lower:", 6)) { | |
1946 | mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1947 | sprintf(s, "lower: %u\n", mode->lower_margin); | |
1948 | } else if (!strncmp(this_opt, "hsynclen:", 9)) { | |
1949 | mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1950 | sprintf(s, "hsynclen: %u\n", mode->hsync_len); | |
1951 | } else if (!strncmp(this_opt, "vsynclen:", 9)) { | |
1952 | mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1953 | sprintf(s, "vsynclen: %u\n", mode->vsync_len); | |
1954 | } else if (!strncmp(this_opt, "hsync:", 6)) { | |
1955 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1956 | sprintf(s, "hsync: Active Low\n"); | |
1957 | mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; | |
1958 | } else { | |
1959 | sprintf(s, "hsync: Active High\n"); | |
1960 | mode->sync |= FB_SYNC_HOR_HIGH_ACT; | |
1961 | } | |
1962 | } else if (!strncmp(this_opt, "vsync:", 6)) { | |
1963 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1964 | sprintf(s, "vsync: Active Low\n"); | |
1965 | mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; | |
1966 | } else { | |
1967 | sprintf(s, "vsync: Active High\n"); | |
1968 | mode->sync |= FB_SYNC_VERT_HIGH_ACT; | |
1969 | } | |
1970 | } else if (!strncmp(this_opt, "dpc:", 4)) { | |
1971 | if (simple_strtoul(this_opt+4, NULL, 0) == 0) { | |
1972 | sprintf(s, "double pixel clock: false\n"); | |
1973 | inf->lccr3 &= ~LCCR3_DPC; | |
1974 | } else { | |
1975 | sprintf(s, "double pixel clock: true\n"); | |
1976 | inf->lccr3 |= LCCR3_DPC; | |
1977 | } | |
1978 | } else if (!strncmp(this_opt, "outputen:", 9)) { | |
1979 | if (simple_strtoul(this_opt+9, NULL, 0) == 0) { | |
1980 | sprintf(s, "output enable: active low\n"); | |
1981 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; | |
1982 | } else { | |
1983 | sprintf(s, "output enable: active high\n"); | |
1984 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; | |
1985 | } | |
1986 | } else if (!strncmp(this_opt, "pixclockpol:", 12)) { | |
1987 | if (simple_strtoul(this_opt+12, NULL, 0) == 0) { | |
1988 | sprintf(s, "pixel clock polarity: falling edge\n"); | |
1989 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; | |
1990 | } else { | |
1991 | sprintf(s, "pixel clock polarity: rising edge\n"); | |
1992 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; | |
1993 | } | |
1994 | } else if (!strncmp(this_opt, "color", 5)) { | |
1995 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; | |
1996 | } else if (!strncmp(this_opt, "mono", 4)) { | |
1997 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; | |
1998 | } else if (!strncmp(this_opt, "active", 6)) { | |
1999 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; | |
2000 | } else if (!strncmp(this_opt, "passive", 7)) { | |
2001 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; | |
2002 | } else if (!strncmp(this_opt, "single", 6)) { | |
2003 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; | |
2004 | } else if (!strncmp(this_opt, "dual", 4)) { | |
2005 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; | |
2006 | } else if (!strncmp(this_opt, "4pix", 4)) { | |
2007 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; | |
2008 | } else if (!strncmp(this_opt, "8pix", 4)) { | |
2009 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; | |
2010 | } else { | |
2011 | dev_err(dev, "unknown option: %s\n", this_opt); | |
2012 | return -EINVAL; | |
2013 | } | |
2014 | ||
2015 | if (s[0] != '\0') | |
2016 | dev_info(dev, "override %s", s); | |
2017 | ||
2018 | return 0; | |
2019 | } | |
2020 | ||
9e6c2976 | 2021 | static int __devinit pxafb_parse_options(struct device *dev, char *options) |
817daf14 | 2022 | { |
1da177e4 | 2023 | char *this_opt; |
817daf14 | 2024 | int ret; |
1da177e4 | 2025 | |
817daf14 | 2026 | if (!options || !*options) |
2027 | return 0; | |
1da177e4 LT |
2028 | |
2029 | dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); | |
2030 | ||
2031 | /* could be made table driven or similar?... */ | |
817daf14 | 2032 | while ((this_opt = strsep(&options, ",")) != NULL) { |
2033 | ret = parse_opt(dev, this_opt); | |
2034 | if (ret) | |
2035 | return ret; | |
2036 | } | |
2037 | return 0; | |
1da177e4 | 2038 | } |
92ac73c1 | 2039 | |
2040 | static char g_options[256] __devinitdata = ""; | |
2041 | ||
f1edfc42 | 2042 | #ifndef MODULE |
9e6c2976 | 2043 | static int __init pxafb_setup_options(void) |
92ac73c1 | 2044 | { |
2045 | char *options = NULL; | |
2046 | ||
2047 | if (fb_get_options("pxafb", &options)) | |
2048 | return -ENODEV; | |
2049 | ||
2050 | if (options) | |
2051 | strlcpy(g_options, options, sizeof(g_options)); | |
2052 | ||
2053 | return 0; | |
2054 | } | |
2055 | #else | |
2056 | #define pxafb_setup_options() (0) | |
2057 | ||
2058 | module_param_string(options, g_options, sizeof(g_options), 0); | |
2059 | MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |
2060 | #endif | |
2061 | ||
2062 | #else | |
2063 | #define pxafb_parse_options(...) (0) | |
2064 | #define pxafb_setup_options() (0) | |
1da177e4 LT |
2065 | #endif |
2066 | ||
1da177e4 | 2067 | #ifdef DEBUG_VAR |
4f3e2664 EM |
2068 | /* Check for various illegal bit-combinations. Currently only |
2069 | * a warning is given. */ | |
2070 | static void __devinit pxafb_check_options(struct device *dev, | |
2071 | struct pxafb_mach_info *inf) | |
2072 | { | |
2073 | if (inf->lcd_conn) | |
2074 | return; | |
1da177e4 | 2075 | |
b0086efb | 2076 | if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) |
4f3e2664 | 2077 | dev_warn(dev, "machine LCCR0 setting contains " |
b0086efb | 2078 | "illegal bits: %08x\n", |
2079 | inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); | |
2080 | if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) | |
4f3e2664 | 2081 | dev_warn(dev, "machine LCCR3 setting contains " |
b0086efb | 2082 | "illegal bits: %08x\n", |
2083 | inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); | |
2084 | if (inf->lccr0 & LCCR0_DPD && | |
1da177e4 LT |
2085 | ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || |
2086 | (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || | |
2087 | (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) | |
4f3e2664 | 2088 | dev_warn(dev, "Double Pixel Data (DPD) mode is " |
b0086efb | 2089 | "only valid in passive mono" |
2090 | " single panel mode\n"); | |
2091 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && | |
1da177e4 | 2092 | (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) |
4f3e2664 | 2093 | dev_warn(dev, "Dual panel only valid in passive mode\n"); |
b0086efb | 2094 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && |
2095 | (inf->modes->upper_margin || inf->modes->lower_margin)) | |
4f3e2664 | 2096 | dev_warn(dev, "Upper and lower margins must be 0 in " |
b0086efb | 2097 | "passive mode\n"); |
4f3e2664 EM |
2098 | } |
2099 | #else | |
2100 | #define pxafb_check_options(...) do {} while (0) | |
1da177e4 LT |
2101 | #endif |
2102 | ||
4f3e2664 EM |
2103 | static int __devinit pxafb_probe(struct platform_device *dev) |
2104 | { | |
2105 | struct pxafb_info *fbi; | |
2106 | struct pxafb_mach_info *inf; | |
2107 | struct resource *r; | |
2108 | int irq, ret; | |
2109 | ||
2110 | dev_dbg(&dev->dev, "pxafb_probe\n"); | |
2111 | ||
2112 | inf = dev->dev.platform_data; | |
2113 | ret = -ENOMEM; | |
2114 | fbi = NULL; | |
2115 | if (!inf) | |
2116 | goto failed; | |
2117 | ||
2118 | ret = pxafb_parse_options(&dev->dev, g_options); | |
2119 | if (ret < 0) | |
2120 | goto failed; | |
2121 | ||
2122 | pxafb_check_options(&dev->dev, inf); | |
2123 | ||
b0086efb | 2124 | dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", |
2125 | inf->modes->xres, | |
2126 | inf->modes->yres, | |
2127 | inf->modes->bpp); | |
2128 | if (inf->modes->xres == 0 || | |
2129 | inf->modes->yres == 0 || | |
2130 | inf->modes->bpp == 0) { | |
3ae5eaec | 2131 | dev_err(&dev->dev, "Invalid resolution or bit depth\n"); |
1da177e4 LT |
2132 | ret = -EINVAL; |
2133 | goto failed; | |
2134 | } | |
a5718a14 | 2135 | |
3ae5eaec | 2136 | fbi = pxafb_init_fbinfo(&dev->dev); |
1da177e4 | 2137 | if (!fbi) { |
b0086efb | 2138 | /* only reason for pxafb_init_fbinfo to fail is kmalloc */ |
3ae5eaec | 2139 | dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); |
b0086efb | 2140 | ret = -ENOMEM; |
1da177e4 LT |
2141 | goto failed; |
2142 | } | |
2143 | ||
52a7a1ce DM |
2144 | if (cpu_is_pxa3xx() && inf->acceleration_enabled) |
2145 | fbi->fb.fix.accel = FB_ACCEL_PXA3XX; | |
2146 | ||
a5718a14 EM |
2147 | fbi->backlight_power = inf->pxafb_backlight_power; |
2148 | fbi->lcd_power = inf->pxafb_lcd_power; | |
2149 | ||
ce4fb7b8 | 2150 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); |
2151 | if (r == NULL) { | |
2152 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | |
2153 | ret = -ENODEV; | |
ee98476b | 2154 | goto failed_fbi; |
ce4fb7b8 | 2155 | } |
2156 | ||
53eff417 | 2157 | r = request_mem_region(r->start, resource_size(r), dev->name); |
ce4fb7b8 | 2158 | if (r == NULL) { |
2159 | dev_err(&dev->dev, "failed to request I/O memory\n"); | |
2160 | ret = -EBUSY; | |
ee98476b | 2161 | goto failed_fbi; |
ce4fb7b8 | 2162 | } |
2163 | ||
53eff417 | 2164 | fbi->mmio_base = ioremap(r->start, resource_size(r)); |
ce4fb7b8 | 2165 | if (fbi->mmio_base == NULL) { |
2166 | dev_err(&dev->dev, "failed to map I/O memory\n"); | |
2167 | ret = -EBUSY; | |
2168 | goto failed_free_res; | |
2169 | } | |
2170 | ||
77e19675 EM |
2171 | fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); |
2172 | fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size, | |
2173 | &fbi->dma_buff_phys, GFP_KERNEL); | |
2174 | if (fbi->dma_buff == NULL) { | |
2175 | dev_err(&dev->dev, "failed to allocate memory for DMA\n"); | |
2176 | ret = -ENOMEM; | |
2177 | goto failed_free_io; | |
2178 | } | |
2179 | ||
2180 | ret = pxafb_init_video_memory(fbi); | |
1da177e4 | 2181 | if (ret) { |
3ae5eaec | 2182 | dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); |
1da177e4 | 2183 | ret = -ENOMEM; |
77e19675 | 2184 | goto failed_free_dma; |
1da177e4 | 2185 | } |
1da177e4 | 2186 | |
ce4fb7b8 | 2187 | irq = platform_get_irq(dev, 0); |
2188 | if (irq < 0) { | |
2189 | dev_err(&dev->dev, "no IRQ defined\n"); | |
2190 | ret = -ENODEV; | |
2191 | goto failed_free_mem; | |
2192 | } | |
2193 | ||
2194 | ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); | |
1da177e4 | 2195 | if (ret) { |
3ae5eaec | 2196 | dev_err(&dev->dev, "request_irq failed: %d\n", ret); |
1da177e4 | 2197 | ret = -EBUSY; |
ce4fb7b8 | 2198 | goto failed_free_mem; |
1da177e4 LT |
2199 | } |
2200 | ||
3c42a449 EM |
2201 | ret = pxafb_smart_init(fbi); |
2202 | if (ret) { | |
2203 | dev_err(&dev->dev, "failed to initialize smartpanel\n"); | |
2204 | goto failed_free_irq; | |
2205 | } | |
07df1c4f | 2206 | |
1da177e4 LT |
2207 | /* |
2208 | * This makes sure that our colour bitfield | |
2209 | * descriptors are correctly initialised. | |
2210 | */ | |
ee98476b JK |
2211 | ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); |
2212 | if (ret) { | |
2213 | dev_err(&dev->dev, "failed to get suitable mode\n"); | |
2214 | goto failed_free_irq; | |
2215 | } | |
2216 | ||
2217 | ret = pxafb_set_par(&fbi->fb); | |
2218 | if (ret) { | |
2219 | dev_err(&dev->dev, "Failed to set parameters\n"); | |
2220 | goto failed_free_irq; | |
2221 | } | |
1da177e4 | 2222 | |
3ae5eaec | 2223 | platform_set_drvdata(dev, fbi); |
1da177e4 LT |
2224 | |
2225 | ret = register_framebuffer(&fbi->fb); | |
2226 | if (ret < 0) { | |
b0086efb | 2227 | dev_err(&dev->dev, |
2228 | "Failed to register framebuffer device: %d\n", ret); | |
ee98476b | 2229 | goto failed_free_cmap; |
1da177e4 LT |
2230 | } |
2231 | ||
198fc108 EM |
2232 | pxafb_overlay_init(fbi); |
2233 | ||
1da177e4 LT |
2234 | #ifdef CONFIG_CPU_FREQ |
2235 | fbi->freq_transition.notifier_call = pxafb_freq_transition; | |
2236 | fbi->freq_policy.notifier_call = pxafb_freq_policy; | |
b0086efb | 2237 | cpufreq_register_notifier(&fbi->freq_transition, |
2238 | CPUFREQ_TRANSITION_NOTIFIER); | |
2239 | cpufreq_register_notifier(&fbi->freq_policy, | |
2240 | CPUFREQ_POLICY_NOTIFIER); | |
1da177e4 LT |
2241 | #endif |
2242 | ||
2243 | /* | |
2244 | * Ok, now enable the LCD controller | |
2245 | */ | |
2246 | set_ctrlr_state(fbi, C_ENABLE); | |
2247 | ||
2248 | return 0; | |
2249 | ||
ee98476b JK |
2250 | failed_free_cmap: |
2251 | if (fbi->fb.cmap.len) | |
2252 | fb_dealloc_cmap(&fbi->fb.cmap); | |
ce4fb7b8 | 2253 | failed_free_irq: |
2254 | free_irq(irq, fbi); | |
ce4fb7b8 | 2255 | failed_free_mem: |
77e19675 EM |
2256 | free_pages_exact(fbi->video_mem, fbi->video_mem_size); |
2257 | failed_free_dma: | |
2258 | dma_free_coherent(&dev->dev, fbi->dma_buff_size, | |
2259 | fbi->dma_buff, fbi->dma_buff_phys); | |
ee98476b JK |
2260 | failed_free_io: |
2261 | iounmap(fbi->mmio_base); | |
2262 | failed_free_res: | |
53eff417 | 2263 | release_mem_region(r->start, resource_size(r)); |
ee98476b JK |
2264 | failed_fbi: |
2265 | clk_put(fbi->clk); | |
3ae5eaec | 2266 | platform_set_drvdata(dev, NULL); |
1da177e4 | 2267 | kfree(fbi); |
ee98476b | 2268 | failed: |
1da177e4 LT |
2269 | return ret; |
2270 | } | |
2271 | ||
9f17f287 JK |
2272 | static int __devexit pxafb_remove(struct platform_device *dev) |
2273 | { | |
2274 | struct pxafb_info *fbi = platform_get_drvdata(dev); | |
2275 | struct resource *r; | |
2276 | int irq; | |
2277 | struct fb_info *info; | |
2278 | ||
2279 | if (!fbi) | |
2280 | return 0; | |
2281 | ||
2282 | info = &fbi->fb; | |
2283 | ||
198fc108 | 2284 | pxafb_overlay_exit(fbi); |
9f17f287 JK |
2285 | unregister_framebuffer(info); |
2286 | ||
2287 | pxafb_disable_controller(fbi); | |
2288 | ||
2289 | if (fbi->fb.cmap.len) | |
2290 | fb_dealloc_cmap(&fbi->fb.cmap); | |
2291 | ||
2292 | irq = platform_get_irq(dev, 0); | |
2293 | free_irq(irq, fbi); | |
2294 | ||
77e19675 EM |
2295 | free_pages_exact(fbi->video_mem, fbi->video_mem_size); |
2296 | ||
2297 | dma_free_writecombine(&dev->dev, fbi->dma_buff_size, | |
2298 | fbi->dma_buff, fbi->dma_buff_phys); | |
9f17f287 JK |
2299 | |
2300 | iounmap(fbi->mmio_base); | |
2301 | ||
2302 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
53eff417 | 2303 | release_mem_region(r->start, resource_size(r)); |
9f17f287 JK |
2304 | |
2305 | clk_put(fbi->clk); | |
2306 | kfree(fbi); | |
2307 | ||
2308 | return 0; | |
2309 | } | |
2310 | ||
3ae5eaec | 2311 | static struct platform_driver pxafb_driver = { |
1da177e4 | 2312 | .probe = pxafb_probe, |
bdf602bd | 2313 | .remove = __devexit_p(pxafb_remove), |
3ae5eaec | 2314 | .driver = { |
9f17f287 | 2315 | .owner = THIS_MODULE, |
3ae5eaec | 2316 | .name = "pxa2xx-fb", |
4f3edfe3 MR |
2317 | #ifdef CONFIG_PM |
2318 | .pm = &pxafb_pm_ops, | |
2319 | #endif | |
3ae5eaec | 2320 | }, |
1da177e4 LT |
2321 | }; |
2322 | ||
9e6c2976 | 2323 | static int __init pxafb_init(void) |
1da177e4 | 2324 | { |
92ac73c1 | 2325 | if (pxafb_setup_options()) |
2326 | return -EINVAL; | |
1da177e4 | 2327 | |
3ae5eaec | 2328 | return platform_driver_register(&pxafb_driver); |
1da177e4 LT |
2329 | } |
2330 | ||
9f17f287 JK |
2331 | static void __exit pxafb_exit(void) |
2332 | { | |
2333 | platform_driver_unregister(&pxafb_driver); | |
2334 | } | |
2335 | ||
1da177e4 | 2336 | module_init(pxafb_init); |
9f17f287 | 2337 | module_exit(pxafb_exit); |
1da177e4 LT |
2338 | |
2339 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | |
2340 | MODULE_LICENSE("GPL"); |