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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/pxafb.c | |
3 | * | |
4 | * Copyright (C) 1999 Eric A. Thomas. | |
5 | * Copyright (C) 2004 Jean-Frederic Clere. | |
6 | * Copyright (C) 2004 Ian Campbell. | |
7 | * Copyright (C) 2004 Jeff Lackey. | |
8 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas | |
9 | * which in turn is | |
10 | * Based on acornfb.c Copyright (C) Russell King. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | * | |
16 | * Intel PXA250/210 LCD Controller Frame Buffer Driver | |
17 | * | |
18 | * Please direct your questions and comments on this driver to the following | |
19 | * email address: | |
20 | * | |
21 | * linux-arm-kernel@lists.arm.linux.org.uk | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/config.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/fb.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/cpufreq.h> | |
39 | #include <linux/device.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | ||
42 | #include <asm/hardware.h> | |
43 | #include <asm/io.h> | |
44 | #include <asm/irq.h> | |
45 | #include <asm/uaccess.h> | |
bf1b8ab6 | 46 | #include <asm/div64.h> |
1da177e4 LT |
47 | #include <asm/arch/pxa-regs.h> |
48 | #include <asm/arch/bitfield.h> | |
49 | #include <asm/arch/pxafb.h> | |
50 | ||
51 | /* | |
52 | * Complain if VAR is out of range. | |
53 | */ | |
54 | #define DEBUG_VAR 1 | |
55 | ||
56 | #include "pxafb.h" | |
57 | ||
58 | /* Bits which should not be set in machine configuration structures */ | |
59 | #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB) | |
60 | #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP) | |
61 | ||
62 | static void (*pxafb_backlight_power)(int); | |
63 | static void (*pxafb_lcd_power)(int); | |
64 | ||
65 | static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *); | |
66 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); | |
67 | ||
68 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
69 | #define PXAFB_OPTIONS_SIZE 256 | |
70 | static char g_options[PXAFB_OPTIONS_SIZE] __initdata = ""; | |
71 | #endif | |
72 | ||
73 | static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) | |
74 | { | |
75 | unsigned long flags; | |
76 | ||
77 | local_irq_save(flags); | |
78 | /* | |
79 | * We need to handle two requests being made at the same time. | |
80 | * There are two important cases: | |
81 | * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE) | |
82 | * We must perform the unblanking, which will do our REENABLE for us. | |
83 | * 2. When we are blanking, but immediately unblank before we have | |
84 | * blanked. We do the "REENABLE" thing here as well, just to be sure. | |
85 | */ | |
86 | if (fbi->task_state == C_ENABLE && state == C_REENABLE) | |
87 | state = (u_int) -1; | |
88 | if (fbi->task_state == C_DISABLE && state == C_ENABLE) | |
89 | state = C_REENABLE; | |
90 | ||
91 | if (state != (u_int)-1) { | |
92 | fbi->task_state = state; | |
93 | schedule_work(&fbi->task); | |
94 | } | |
95 | local_irq_restore(flags); | |
96 | } | |
97 | ||
98 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
99 | { | |
100 | chan &= 0xffff; | |
101 | chan >>= 16 - bf->length; | |
102 | return chan << bf->offset; | |
103 | } | |
104 | ||
105 | static int | |
106 | pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, | |
107 | u_int trans, struct fb_info *info) | |
108 | { | |
109 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
110 | u_int val, ret = 1; | |
111 | ||
112 | if (regno < fbi->palette_size) { | |
113 | if (fbi->fb.var.grayscale) { | |
114 | val = ((blue >> 8) & 0x00ff); | |
115 | } else { | |
116 | val = ((red >> 0) & 0xf800); | |
117 | val |= ((green >> 5) & 0x07e0); | |
118 | val |= ((blue >> 11) & 0x001f); | |
119 | } | |
120 | fbi->palette_cpu[regno] = val; | |
121 | ret = 0; | |
122 | } | |
123 | return ret; | |
124 | } | |
125 | ||
126 | static int | |
127 | pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
128 | u_int trans, struct fb_info *info) | |
129 | { | |
130 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
131 | unsigned int val; | |
132 | int ret = 1; | |
133 | ||
134 | /* | |
135 | * If inverse mode was selected, invert all the colours | |
136 | * rather than the register number. The register number | |
137 | * is what you poke into the framebuffer to produce the | |
138 | * colour you requested. | |
139 | */ | |
140 | if (fbi->cmap_inverse) { | |
141 | red = 0xffff - red; | |
142 | green = 0xffff - green; | |
143 | blue = 0xffff - blue; | |
144 | } | |
145 | ||
146 | /* | |
147 | * If greyscale is true, then we convert the RGB value | |
148 | * to greyscale no matter what visual we are using. | |
149 | */ | |
150 | if (fbi->fb.var.grayscale) | |
151 | red = green = blue = (19595 * red + 38470 * green + | |
152 | 7471 * blue) >> 16; | |
153 | ||
154 | switch (fbi->fb.fix.visual) { | |
155 | case FB_VISUAL_TRUECOLOR: | |
156 | /* | |
157 | * 16-bit True Colour. We encode the RGB value | |
158 | * according to the RGB bitfield information. | |
159 | */ | |
160 | if (regno < 16) { | |
161 | u32 *pal = fbi->fb.pseudo_palette; | |
162 | ||
163 | val = chan_to_field(red, &fbi->fb.var.red); | |
164 | val |= chan_to_field(green, &fbi->fb.var.green); | |
165 | val |= chan_to_field(blue, &fbi->fb.var.blue); | |
166 | ||
167 | pal[regno] = val; | |
168 | ret = 0; | |
169 | } | |
170 | break; | |
171 | ||
172 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
173 | case FB_VISUAL_PSEUDOCOLOR: | |
174 | ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); | |
175 | break; | |
176 | } | |
177 | ||
178 | return ret; | |
179 | } | |
180 | ||
181 | /* | |
182 | * pxafb_bpp_to_lccr3(): | |
183 | * Convert a bits per pixel value to the correct bit pattern for LCCR3 | |
184 | */ | |
185 | static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) | |
186 | { | |
187 | int ret = 0; | |
188 | switch (var->bits_per_pixel) { | |
189 | case 1: ret = LCCR3_1BPP; break; | |
190 | case 2: ret = LCCR3_2BPP; break; | |
191 | case 4: ret = LCCR3_4BPP; break; | |
192 | case 8: ret = LCCR3_8BPP; break; | |
193 | case 16: ret = LCCR3_16BPP; break; | |
194 | } | |
195 | return ret; | |
196 | } | |
197 | ||
198 | #ifdef CONFIG_CPU_FREQ | |
199 | /* | |
200 | * pxafb_display_dma_period() | |
201 | * Calculate the minimum period (in picoseconds) between two DMA | |
202 | * requests for the LCD controller. If we hit this, it means we're | |
203 | * doing nothing but LCD DMA. | |
204 | */ | |
205 | static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) | |
206 | { | |
207 | /* | |
208 | * Period = pixclock * bits_per_byte * bytes_per_transfer | |
209 | * / memory_bits_per_pixel; | |
210 | */ | |
211 | return var->pixclock * 8 * 16 / var->bits_per_pixel; | |
212 | } | |
213 | ||
214 | extern unsigned int get_clk_frequency_khz(int info); | |
215 | #endif | |
216 | ||
217 | /* | |
218 | * pxafb_check_var(): | |
219 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
220 | * if it's too big, return -EINVAL. | |
221 | * | |
222 | * Round up in the following order: bits_per_pixel, xres, | |
223 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
224 | * bitfields, horizontal timing, vertical timing. | |
225 | */ | |
226 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
227 | { | |
228 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
229 | ||
230 | if (var->xres < MIN_XRES) | |
231 | var->xres = MIN_XRES; | |
232 | if (var->yres < MIN_YRES) | |
233 | var->yres = MIN_YRES; | |
234 | if (var->xres > fbi->max_xres) | |
235 | var->xres = fbi->max_xres; | |
236 | if (var->yres > fbi->max_yres) | |
237 | var->yres = fbi->max_yres; | |
238 | var->xres_virtual = | |
239 | max(var->xres_virtual, var->xres); | |
240 | var->yres_virtual = | |
241 | max(var->yres_virtual, var->yres); | |
242 | ||
243 | /* | |
244 | * Setup the RGB parameters for this display. | |
245 | * | |
246 | * The pixel packing format is described on page 7-11 of the | |
247 | * PXA2XX Developer's Manual. | |
248 | */ | |
249 | if (var->bits_per_pixel == 16) { | |
250 | var->red.offset = 11; var->red.length = 5; | |
251 | var->green.offset = 5; var->green.length = 6; | |
252 | var->blue.offset = 0; var->blue.length = 5; | |
253 | var->transp.offset = var->transp.length = 0; | |
254 | } else { | |
255 | var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0; | |
256 | var->red.length = 8; | |
257 | var->green.length = 8; | |
258 | var->blue.length = 8; | |
259 | var->transp.length = 0; | |
260 | } | |
261 | ||
262 | #ifdef CONFIG_CPU_FREQ | |
263 | DPRINTK("dma period = %d ps, clock = %d kHz\n", | |
264 | pxafb_display_dma_period(var), | |
265 | get_clk_frequency_khz(0)); | |
266 | #endif | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static inline void pxafb_set_truecolor(u_int is_true_color) | |
272 | { | |
273 | DPRINTK("true_color = %d\n", is_true_color); | |
274 | // do your machine-specific setup if needed | |
275 | } | |
276 | ||
277 | /* | |
278 | * pxafb_set_par(): | |
279 | * Set the user defined part of the display for the specified console | |
280 | */ | |
281 | static int pxafb_set_par(struct fb_info *info) | |
282 | { | |
283 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
284 | struct fb_var_screeninfo *var = &info->var; | |
285 | unsigned long palette_mem_size; | |
286 | ||
287 | DPRINTK("set_par\n"); | |
288 | ||
289 | if (var->bits_per_pixel == 16) | |
290 | fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
291 | else if (!fbi->cmap_static) | |
292 | fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
293 | else { | |
294 | /* | |
295 | * Some people have weird ideas about wanting static | |
296 | * pseudocolor maps. I suspect their user space | |
297 | * applications are broken. | |
298 | */ | |
299 | fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
300 | } | |
301 | ||
302 | fbi->fb.fix.line_length = var->xres_virtual * | |
303 | var->bits_per_pixel / 8; | |
304 | if (var->bits_per_pixel == 16) | |
305 | fbi->palette_size = 0; | |
306 | else | |
307 | fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel; | |
308 | ||
309 | palette_mem_size = fbi->palette_size * sizeof(u16); | |
310 | ||
311 | DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); | |
312 | ||
313 | fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); | |
314 | fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; | |
315 | ||
316 | /* | |
317 | * Set (any) board control register to handle new color depth | |
318 | */ | |
319 | pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); | |
320 | ||
321 | if (fbi->fb.var.bits_per_pixel == 16) | |
322 | fb_dealloc_cmap(&fbi->fb.cmap); | |
323 | else | |
324 | fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); | |
325 | ||
326 | pxafb_activate_var(var, fbi); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | /* | |
332 | * Formal definition of the VESA spec: | |
333 | * On | |
334 | * This refers to the state of the display when it is in full operation | |
335 | * Stand-By | |
336 | * This defines an optional operating state of minimal power reduction with | |
337 | * the shortest recovery time | |
338 | * Suspend | |
339 | * This refers to a level of power management in which substantial power | |
340 | * reduction is achieved by the display. The display can have a longer | |
341 | * recovery time from this state than from the Stand-by state | |
342 | * Off | |
343 | * This indicates that the display is consuming the lowest level of power | |
344 | * and is non-operational. Recovery from this state may optionally require | |
345 | * the user to manually power on the monitor | |
346 | * | |
347 | * Now, the fbdev driver adds an additional state, (blank), where they | |
348 | * turn off the video (maybe by colormap tricks), but don't mess with the | |
349 | * video itself: think of it semantically between on and Stand-By. | |
350 | * | |
351 | * So here's what we should do in our fbdev blank routine: | |
352 | * | |
353 | * VESA_NO_BLANKING (mode 0) Video on, front/back light on | |
354 | * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off | |
355 | * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off | |
356 | * VESA_POWERDOWN (mode 3) Video off, front/back light off | |
357 | * | |
358 | * This will match the matrox implementation. | |
359 | */ | |
360 | ||
361 | /* | |
362 | * pxafb_blank(): | |
363 | * Blank the display by setting all palette values to zero. Note, the | |
364 | * 16 bpp mode does not really use the palette, so this will not | |
365 | * blank the display in all modes. | |
366 | */ | |
367 | static int pxafb_blank(int blank, struct fb_info *info) | |
368 | { | |
369 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
370 | int i; | |
371 | ||
372 | DPRINTK("pxafb_blank: blank=%d\n", blank); | |
373 | ||
374 | switch (blank) { | |
375 | case FB_BLANK_POWERDOWN: | |
376 | case FB_BLANK_VSYNC_SUSPEND: | |
377 | case FB_BLANK_HSYNC_SUSPEND: | |
378 | case FB_BLANK_NORMAL: | |
379 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
380 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
381 | for (i = 0; i < fbi->palette_size; i++) | |
382 | pxafb_setpalettereg(i, 0, 0, 0, 0, info); | |
383 | ||
384 | pxafb_schedule_work(fbi, C_DISABLE); | |
385 | //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); | |
386 | break; | |
387 | ||
388 | case FB_BLANK_UNBLANK: | |
389 | //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); | |
390 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
391 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
392 | fb_set_cmap(&fbi->fb.cmap, info); | |
393 | pxafb_schedule_work(fbi, C_ENABLE); | |
394 | } | |
395 | return 0; | |
396 | } | |
397 | ||
398 | static int pxafb_mmap(struct fb_info *info, struct file *file, | |
399 | struct vm_area_struct *vma) | |
400 | { | |
401 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
402 | unsigned long off = vma->vm_pgoff << PAGE_SHIFT; | |
403 | ||
404 | if (off < info->fix.smem_len) { | |
405 | vma->vm_pgoff += 1; | |
406 | return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, | |
407 | fbi->map_dma, fbi->map_size); | |
408 | } | |
409 | return -EINVAL; | |
410 | } | |
411 | ||
412 | static struct fb_ops pxafb_ops = { | |
413 | .owner = THIS_MODULE, | |
414 | .fb_check_var = pxafb_check_var, | |
415 | .fb_set_par = pxafb_set_par, | |
416 | .fb_setcolreg = pxafb_setcolreg, | |
417 | .fb_fillrect = cfb_fillrect, | |
418 | .fb_copyarea = cfb_copyarea, | |
419 | .fb_imageblit = cfb_imageblit, | |
420 | .fb_blank = pxafb_blank, | |
421 | .fb_cursor = soft_cursor, | |
422 | .fb_mmap = pxafb_mmap, | |
423 | }; | |
424 | ||
425 | /* | |
426 | * Calculate the PCD value from the clock rate (in picoseconds). | |
427 | * We take account of the PPCR clock setting. | |
428 | * From PXA Developer's Manual: | |
429 | * | |
430 | * PixelClock = LCLK | |
431 | * ------------- | |
432 | * 2 ( PCD + 1 ) | |
433 | * | |
434 | * PCD = LCLK | |
435 | * ------------- - 1 | |
436 | * 2(PixelClock) | |
437 | * | |
438 | * Where: | |
439 | * LCLK = LCD/Memory Clock | |
440 | * PCD = LCCR3[7:0] | |
441 | * | |
442 | * PixelClock here is in Hz while the pixclock argument given is the | |
443 | * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) | |
444 | * | |
445 | * The function get_lclk_frequency_10khz returns LCLK in units of | |
446 | * 10khz. Calling the result of this function lclk gives us the | |
447 | * following | |
448 | * | |
449 | * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) | |
450 | * -------------------------------------- - 1 | |
451 | * 2 | |
452 | * | |
453 | * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. | |
454 | */ | |
455 | static inline unsigned int get_pcd(unsigned int pixclock) | |
456 | { | |
457 | unsigned long long pcd; | |
458 | ||
459 | /* FIXME: Need to take into account Double Pixel Clock mode | |
460 | * (DPC) bit? or perhaps set it based on the various clock | |
461 | * speeds */ | |
462 | ||
463 | pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock; | |
bf1b8ab6 | 464 | do_div(pcd, 100000000 * 2); |
1da177e4 LT |
465 | /* no need for this, since we should subtract 1 anyway. they cancel */ |
466 | /* pcd += 1; */ /* make up for integer math truncations */ | |
467 | return (unsigned int)pcd; | |
468 | } | |
469 | ||
470 | /* | |
471 | * pxafb_activate_var(): | |
472 | * Configures LCD Controller based on entries in var parameter. Settings are | |
473 | * only written to the controller if changes were made. | |
474 | */ | |
475 | static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi) | |
476 | { | |
477 | struct pxafb_lcd_reg new_regs; | |
478 | u_long flags; | |
479 | u_int lines_per_panel, pcd = get_pcd(var->pixclock); | |
480 | ||
481 | DPRINTK("Configuring PXA LCD\n"); | |
482 | ||
483 | DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n", | |
484 | var->xres, var->hsync_len, | |
485 | var->left_margin, var->right_margin); | |
486 | DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n", | |
487 | var->yres, var->vsync_len, | |
488 | var->upper_margin, var->lower_margin); | |
489 | DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd); | |
490 | ||
491 | #if DEBUG_VAR | |
492 | if (var->xres < 16 || var->xres > 1024) | |
493 | printk(KERN_ERR "%s: invalid xres %d\n", | |
494 | fbi->fb.fix.id, var->xres); | |
495 | switch(var->bits_per_pixel) { | |
496 | case 1: | |
497 | case 2: | |
498 | case 4: | |
499 | case 8: | |
500 | case 16: | |
501 | break; | |
502 | default: | |
503 | printk(KERN_ERR "%s: invalid bit depth %d\n", | |
504 | fbi->fb.fix.id, var->bits_per_pixel); | |
505 | break; | |
506 | } | |
507 | if (var->hsync_len < 1 || var->hsync_len > 64) | |
508 | printk(KERN_ERR "%s: invalid hsync_len %d\n", | |
509 | fbi->fb.fix.id, var->hsync_len); | |
510 | if (var->left_margin < 1 || var->left_margin > 255) | |
511 | printk(KERN_ERR "%s: invalid left_margin %d\n", | |
512 | fbi->fb.fix.id, var->left_margin); | |
513 | if (var->right_margin < 1 || var->right_margin > 255) | |
514 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
515 | fbi->fb.fix.id, var->right_margin); | |
516 | if (var->yres < 1 || var->yres > 1024) | |
517 | printk(KERN_ERR "%s: invalid yres %d\n", | |
518 | fbi->fb.fix.id, var->yres); | |
519 | if (var->vsync_len < 1 || var->vsync_len > 64) | |
520 | printk(KERN_ERR "%s: invalid vsync_len %d\n", | |
521 | fbi->fb.fix.id, var->vsync_len); | |
522 | if (var->upper_margin < 0 || var->upper_margin > 255) | |
523 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
524 | fbi->fb.fix.id, var->upper_margin); | |
525 | if (var->lower_margin < 0 || var->lower_margin > 255) | |
526 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
527 | fbi->fb.fix.id, var->lower_margin); | |
528 | #endif | |
529 | ||
530 | new_regs.lccr0 = fbi->lccr0 | | |
531 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | | |
532 | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); | |
533 | ||
534 | new_regs.lccr1 = | |
535 | LCCR1_DisWdth(var->xres) + | |
536 | LCCR1_HorSnchWdth(var->hsync_len) + | |
537 | LCCR1_BegLnDel(var->left_margin) + | |
538 | LCCR1_EndLnDel(var->right_margin); | |
539 | ||
540 | /* | |
541 | * If we have a dual scan LCD, we need to halve | |
542 | * the YRES parameter. | |
543 | */ | |
544 | lines_per_panel = var->yres; | |
545 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
546 | lines_per_panel /= 2; | |
547 | ||
548 | new_regs.lccr2 = | |
549 | LCCR2_DisHght(lines_per_panel) + | |
550 | LCCR2_VrtSnchWdth(var->vsync_len) + | |
551 | LCCR2_BegFrmDel(var->upper_margin) + | |
552 | LCCR2_EndFrmDel(var->lower_margin); | |
553 | ||
554 | new_regs.lccr3 = fbi->lccr3 | | |
555 | pxafb_bpp_to_lccr3(var) | | |
556 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) | | |
557 | (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL); | |
558 | ||
559 | if (pcd) | |
560 | new_regs.lccr3 |= LCCR3_PixClkDiv(pcd); | |
561 | ||
562 | DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0); | |
563 | DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1); | |
564 | DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2); | |
565 | DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3); | |
566 | ||
567 | /* Update shadow copy atomically */ | |
568 | local_irq_save(flags); | |
569 | ||
570 | /* setup dma descriptors */ | |
571 | fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16); | |
572 | fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16); | |
573 | fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16); | |
574 | ||
575 | fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16; | |
576 | fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16; | |
577 | fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16; | |
578 | ||
579 | #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length) | |
580 | ||
581 | /* populate descriptors */ | |
582 | fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma; | |
583 | fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL; | |
584 | fbi->dmadesc_fblow_cpu->fidr = 0; | |
585 | fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL; | |
586 | ||
587 | fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */ | |
588 | ||
589 | fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma; | |
590 | fbi->dmadesc_fbhigh_cpu->fidr = 0; | |
591 | fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL; | |
592 | ||
593 | fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma; | |
594 | fbi->dmadesc_palette_cpu->fidr = 0; | |
595 | fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; | |
596 | ||
597 | if (var->bits_per_pixel == 16) { | |
598 | /* palette shouldn't be loaded in true-color mode */ | |
599 | fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma; | |
600 | fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */ | |
601 | /* init it to something, even though we won't be using it */ | |
602 | fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma; | |
603 | } else { | |
604 | fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma; | |
605 | fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma; | |
606 | fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */ | |
607 | } | |
608 | ||
609 | #if 0 | |
610 | DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu); | |
611 | DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu); | |
612 | DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu); | |
613 | DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma); | |
614 | DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma); | |
615 | DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma); | |
616 | ||
617 | DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr); | |
618 | DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr); | |
619 | DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr); | |
620 | ||
621 | DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr); | |
622 | DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr); | |
623 | DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr); | |
624 | ||
625 | DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd); | |
626 | DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd); | |
627 | DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd); | |
628 | #endif | |
629 | ||
630 | fbi->reg_lccr0 = new_regs.lccr0; | |
631 | fbi->reg_lccr1 = new_regs.lccr1; | |
632 | fbi->reg_lccr2 = new_regs.lccr2; | |
633 | fbi->reg_lccr3 = new_regs.lccr3; | |
634 | local_irq_restore(flags); | |
635 | ||
636 | /* | |
637 | * Only update the registers if the controller is enabled | |
638 | * and something has changed. | |
639 | */ | |
640 | if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) || | |
641 | (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) || | |
642 | (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1)) | |
643 | pxafb_schedule_work(fbi, C_REENABLE); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | /* | |
649 | * NOTE! The following functions are purely helpers for set_ctrlr_state. | |
650 | * Do not call them directly; set_ctrlr_state does the correct serialisation | |
651 | * to ensure that things happen in the right way 100% of time time. | |
652 | * -- rmk | |
653 | */ | |
654 | static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) | |
655 | { | |
656 | DPRINTK("backlight o%s\n", on ? "n" : "ff"); | |
657 | ||
658 | if (pxafb_backlight_power) | |
659 | pxafb_backlight_power(on); | |
660 | } | |
661 | ||
662 | static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) | |
663 | { | |
664 | DPRINTK("LCD power o%s\n", on ? "n" : "ff"); | |
665 | ||
666 | if (pxafb_lcd_power) | |
667 | pxafb_lcd_power(on); | |
668 | } | |
669 | ||
670 | static void pxafb_setup_gpio(struct pxafb_info *fbi) | |
671 | { | |
672 | int gpio, ldd_bits; | |
673 | unsigned int lccr0 = fbi->lccr0; | |
674 | ||
675 | /* | |
676 | * setup is based on type of panel supported | |
677 | */ | |
678 | ||
679 | /* 4 bit interface */ | |
680 | if ((lccr0 & LCCR0_CMS) == LCCR0_Mono && | |
681 | (lccr0 & LCCR0_SDS) == LCCR0_Sngl && | |
682 | (lccr0 & LCCR0_DPD) == LCCR0_4PixMono) | |
683 | ldd_bits = 4; | |
684 | ||
685 | /* 8 bit interface */ | |
686 | else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono && | |
687 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) || | |
688 | ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
689 | (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl)) | |
690 | ldd_bits = 8; | |
691 | ||
692 | /* 16 bit interface */ | |
693 | else if ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
694 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act)) | |
695 | ldd_bits = 16; | |
696 | ||
697 | else { | |
698 | printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n"); | |
699 | return; | |
700 | } | |
701 | ||
702 | for (gpio = 58; ldd_bits; gpio++, ldd_bits--) | |
703 | pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); | |
704 | pxa_gpio_mode(GPIO74_LCD_FCLK_MD); | |
705 | pxa_gpio_mode(GPIO75_LCD_LCLK_MD); | |
706 | pxa_gpio_mode(GPIO76_LCD_PCLK_MD); | |
707 | pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); | |
708 | } | |
709 | ||
710 | static void pxafb_enable_controller(struct pxafb_info *fbi) | |
711 | { | |
712 | DPRINTK("Enabling LCD controller\n"); | |
713 | DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0); | |
714 | DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1); | |
715 | DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); | |
716 | DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); | |
717 | DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); | |
718 | DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); | |
719 | ||
8d372266 NP |
720 | /* enable LCD controller clock */ |
721 | pxa_set_cken(CKEN16_LCD, 1); | |
722 | ||
1da177e4 LT |
723 | /* Sequence from 11.7.10 */ |
724 | LCCR3 = fbi->reg_lccr3; | |
725 | LCCR2 = fbi->reg_lccr2; | |
726 | LCCR1 = fbi->reg_lccr1; | |
727 | LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB; | |
728 | ||
729 | FDADR0 = fbi->fdadr0; | |
730 | FDADR1 = fbi->fdadr1; | |
731 | LCCR0 |= LCCR0_ENB; | |
732 | ||
733 | DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0); | |
734 | DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1); | |
735 | DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0); | |
736 | DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1); | |
737 | DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2); | |
738 | DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3); | |
739 | } | |
740 | ||
741 | static void pxafb_disable_controller(struct pxafb_info *fbi) | |
742 | { | |
743 | DECLARE_WAITQUEUE(wait, current); | |
744 | ||
745 | DPRINTK("Disabling LCD controller\n"); | |
746 | ||
747 | set_current_state(TASK_UNINTERRUPTIBLE); | |
748 | add_wait_queue(&fbi->ctrlr_wait, &wait); | |
749 | ||
750 | LCSR = 0xffffffff; /* Clear LCD Status Register */ | |
751 | LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ | |
752 | LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ | |
753 | ||
754 | schedule_timeout(20 * HZ / 1000); | |
755 | remove_wait_queue(&fbi->ctrlr_wait, &wait); | |
8d372266 NP |
756 | |
757 | /* disable LCD controller clock */ | |
758 | pxa_set_cken(CKEN16_LCD, 0); | |
1da177e4 LT |
759 | } |
760 | ||
761 | /* | |
762 | * pxafb_handle_irq: Handle 'LCD DONE' interrupts. | |
763 | */ | |
764 | static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs) | |
765 | { | |
766 | struct pxafb_info *fbi = dev_id; | |
767 | unsigned int lcsr = LCSR; | |
768 | ||
769 | if (lcsr & LCSR_LDD) { | |
770 | LCCR0 |= LCCR0_LDM; | |
771 | wake_up(&fbi->ctrlr_wait); | |
772 | } | |
773 | ||
774 | LCSR = lcsr; | |
775 | return IRQ_HANDLED; | |
776 | } | |
777 | ||
778 | /* | |
779 | * This function must be called from task context only, since it will | |
780 | * sleep when disabling the LCD controller, or if we get two contending | |
781 | * processes trying to alter state. | |
782 | */ | |
783 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) | |
784 | { | |
785 | u_int old_state; | |
786 | ||
787 | down(&fbi->ctrlr_sem); | |
788 | ||
789 | old_state = fbi->state; | |
790 | ||
791 | /* | |
792 | * Hack around fbcon initialisation. | |
793 | */ | |
794 | if (old_state == C_STARTUP && state == C_REENABLE) | |
795 | state = C_ENABLE; | |
796 | ||
797 | switch (state) { | |
798 | case C_DISABLE_CLKCHANGE: | |
799 | /* | |
800 | * Disable controller for clock change. If the | |
801 | * controller is already disabled, then do nothing. | |
802 | */ | |
803 | if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { | |
804 | fbi->state = state; | |
805 | //TODO __pxafb_lcd_power(fbi, 0); | |
806 | pxafb_disable_controller(fbi); | |
807 | } | |
808 | break; | |
809 | ||
810 | case C_DISABLE_PM: | |
811 | case C_DISABLE: | |
812 | /* | |
813 | * Disable controller | |
814 | */ | |
815 | if (old_state != C_DISABLE) { | |
816 | fbi->state = state; | |
817 | __pxafb_backlight_power(fbi, 0); | |
818 | __pxafb_lcd_power(fbi, 0); | |
819 | if (old_state != C_DISABLE_CLKCHANGE) | |
820 | pxafb_disable_controller(fbi); | |
821 | } | |
822 | break; | |
823 | ||
824 | case C_ENABLE_CLKCHANGE: | |
825 | /* | |
826 | * Enable the controller after clock change. Only | |
827 | * do this if we were disabled for the clock change. | |
828 | */ | |
829 | if (old_state == C_DISABLE_CLKCHANGE) { | |
830 | fbi->state = C_ENABLE; | |
831 | pxafb_enable_controller(fbi); | |
832 | //TODO __pxafb_lcd_power(fbi, 1); | |
833 | } | |
834 | break; | |
835 | ||
836 | case C_REENABLE: | |
837 | /* | |
838 | * Re-enable the controller only if it was already | |
839 | * enabled. This is so we reprogram the control | |
840 | * registers. | |
841 | */ | |
842 | if (old_state == C_ENABLE) { | |
843 | pxafb_disable_controller(fbi); | |
844 | pxafb_setup_gpio(fbi); | |
845 | pxafb_enable_controller(fbi); | |
846 | } | |
847 | break; | |
848 | ||
849 | case C_ENABLE_PM: | |
850 | /* | |
851 | * Re-enable the controller after PM. This is not | |
852 | * perfect - think about the case where we were doing | |
853 | * a clock change, and we suspended half-way through. | |
854 | */ | |
855 | if (old_state != C_DISABLE_PM) | |
856 | break; | |
857 | /* fall through */ | |
858 | ||
859 | case C_ENABLE: | |
860 | /* | |
861 | * Power up the LCD screen, enable controller, and | |
862 | * turn on the backlight. | |
863 | */ | |
864 | if (old_state != C_ENABLE) { | |
865 | fbi->state = C_ENABLE; | |
866 | pxafb_setup_gpio(fbi); | |
867 | pxafb_enable_controller(fbi); | |
868 | __pxafb_lcd_power(fbi, 1); | |
869 | __pxafb_backlight_power(fbi, 1); | |
870 | } | |
871 | break; | |
872 | } | |
873 | up(&fbi->ctrlr_sem); | |
874 | } | |
875 | ||
876 | /* | |
877 | * Our LCD controller task (which is called when we blank or unblank) | |
878 | * via keventd. | |
879 | */ | |
880 | static void pxafb_task(void *dummy) | |
881 | { | |
882 | struct pxafb_info *fbi = dummy; | |
883 | u_int state = xchg(&fbi->task_state, -1); | |
884 | ||
885 | set_ctrlr_state(fbi, state); | |
886 | } | |
887 | ||
888 | #ifdef CONFIG_CPU_FREQ | |
889 | /* | |
890 | * CPU clock speed change handler. We need to adjust the LCD timing | |
891 | * parameters when the CPU clock is adjusted by the power management | |
892 | * subsystem. | |
893 | * | |
894 | * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() | |
895 | */ | |
896 | static int | |
897 | pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) | |
898 | { | |
899 | struct pxafb_info *fbi = TO_INF(nb, freq_transition); | |
900 | //TODO struct cpufreq_freqs *f = data; | |
901 | u_int pcd; | |
902 | ||
903 | switch (val) { | |
904 | case CPUFREQ_PRECHANGE: | |
905 | set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); | |
906 | break; | |
907 | ||
908 | case CPUFREQ_POSTCHANGE: | |
909 | pcd = get_pcd(fbi->fb.var.pixclock); | |
910 | fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); | |
911 | set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); | |
912 | break; | |
913 | } | |
914 | return 0; | |
915 | } | |
916 | ||
917 | static int | |
918 | pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) | |
919 | { | |
920 | struct pxafb_info *fbi = TO_INF(nb, freq_policy); | |
921 | struct fb_var_screeninfo *var = &fbi->fb.var; | |
922 | struct cpufreq_policy *policy = data; | |
923 | ||
924 | switch (val) { | |
925 | case CPUFREQ_ADJUST: | |
926 | case CPUFREQ_INCOMPATIBLE: | |
927 | printk(KERN_DEBUG "min dma period: %d ps, " | |
928 | "new clock %d kHz\n", pxafb_display_dma_period(var), | |
929 | policy->max); | |
930 | // TODO: fill in min/max values | |
931 | break; | |
932 | #if 0 | |
933 | case CPUFREQ_NOTIFY: | |
934 | printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__); | |
935 | do {} while(0); | |
936 | /* todo: panic if min/max values aren't fulfilled | |
937 | * [can't really happen unless there's a bug in the | |
938 | * CPU policy verification process * | |
939 | */ | |
940 | break; | |
941 | #endif | |
942 | } | |
943 | return 0; | |
944 | } | |
945 | #endif | |
946 | ||
947 | #ifdef CONFIG_PM | |
948 | /* | |
949 | * Power management hooks. Note that we won't be called from IRQ context, | |
950 | * unlike the blank functions above, so we may sleep. | |
951 | */ | |
9bfd354b | 952 | static int pxafb_suspend(struct device *dev, pm_message_t state, u32 level) |
1da177e4 LT |
953 | { |
954 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
955 | ||
956 | if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN) | |
957 | set_ctrlr_state(fbi, C_DISABLE_PM); | |
958 | return 0; | |
959 | } | |
960 | ||
961 | static int pxafb_resume(struct device *dev, u32 level) | |
962 | { | |
963 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
964 | ||
965 | if (level == RESUME_ENABLE) | |
966 | set_ctrlr_state(fbi, C_ENABLE_PM); | |
967 | return 0; | |
968 | } | |
969 | #else | |
970 | #define pxafb_suspend NULL | |
971 | #define pxafb_resume NULL | |
972 | #endif | |
973 | ||
974 | /* | |
975 | * pxafb_map_video_memory(): | |
976 | * Allocates the DRAM memory for the frame buffer. This buffer is | |
977 | * remapped into a non-cached, non-buffered, memory region to | |
978 | * allow palette and pixel writes to occur without flushing the | |
979 | * cache. Once this area is remapped, all virtual memory | |
980 | * access to the video memory should occur at the new region. | |
981 | */ | |
982 | static int __init pxafb_map_video_memory(struct pxafb_info *fbi) | |
983 | { | |
984 | u_long palette_mem_size; | |
985 | ||
986 | /* | |
987 | * We reserve one page for the palette, plus the size | |
988 | * of the framebuffer. | |
989 | */ | |
990 | fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); | |
991 | fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, | |
992 | &fbi->map_dma, GFP_KERNEL); | |
993 | ||
994 | if (fbi->map_cpu) { | |
995 | /* prevent initial garbage on screen */ | |
996 | memset(fbi->map_cpu, 0, fbi->map_size); | |
997 | fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; | |
998 | fbi->screen_dma = fbi->map_dma + PAGE_SIZE; | |
999 | /* | |
1000 | * FIXME: this is actually the wrong thing to place in | |
1001 | * smem_start. But fbdev suffers from the problem that | |
1002 | * it needs an API which doesn't exist (in this case, | |
1003 | * dma_writecombine_mmap) | |
1004 | */ | |
1005 | fbi->fb.fix.smem_start = fbi->screen_dma; | |
1006 | ||
1007 | fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; | |
1008 | ||
1009 | palette_mem_size = fbi->palette_size * sizeof(u16); | |
1010 | DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); | |
1011 | ||
1012 | fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); | |
1013 | fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; | |
1014 | } | |
1015 | ||
1016 | return fbi->map_cpu ? 0 : -ENOMEM; | |
1017 | } | |
1018 | ||
1019 | static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) | |
1020 | { | |
1021 | struct pxafb_info *fbi; | |
1022 | void *addr; | |
1023 | struct pxafb_mach_info *inf = dev->platform_data; | |
1024 | ||
1025 | /* Alloc the pxafb_info and pseudo_palette in one step */ | |
1026 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | |
1027 | if (!fbi) | |
1028 | return NULL; | |
1029 | ||
1030 | memset(fbi, 0, sizeof(struct pxafb_info)); | |
1031 | fbi->dev = dev; | |
1032 | ||
1033 | strcpy(fbi->fb.fix.id, PXA_NAME); | |
1034 | ||
1035 | fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1036 | fbi->fb.fix.type_aux = 0; | |
1037 | fbi->fb.fix.xpanstep = 0; | |
1038 | fbi->fb.fix.ypanstep = 0; | |
1039 | fbi->fb.fix.ywrapstep = 0; | |
1040 | fbi->fb.fix.accel = FB_ACCEL_NONE; | |
1041 | ||
1042 | fbi->fb.var.nonstd = 0; | |
1043 | fbi->fb.var.activate = FB_ACTIVATE_NOW; | |
1044 | fbi->fb.var.height = -1; | |
1045 | fbi->fb.var.width = -1; | |
1046 | fbi->fb.var.accel_flags = 0; | |
1047 | fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; | |
1048 | ||
1049 | fbi->fb.fbops = &pxafb_ops; | |
1050 | fbi->fb.flags = FBINFO_DEFAULT; | |
1051 | fbi->fb.node = -1; | |
1052 | ||
1053 | addr = fbi; | |
1054 | addr = addr + sizeof(struct pxafb_info); | |
1055 | fbi->fb.pseudo_palette = addr; | |
1056 | ||
1057 | fbi->max_xres = inf->xres; | |
1058 | fbi->fb.var.xres = inf->xres; | |
1059 | fbi->fb.var.xres_virtual = inf->xres; | |
1060 | fbi->max_yres = inf->yres; | |
1061 | fbi->fb.var.yres = inf->yres; | |
1062 | fbi->fb.var.yres_virtual = inf->yres; | |
1063 | fbi->max_bpp = inf->bpp; | |
1064 | fbi->fb.var.bits_per_pixel = inf->bpp; | |
1065 | fbi->fb.var.pixclock = inf->pixclock; | |
1066 | fbi->fb.var.hsync_len = inf->hsync_len; | |
1067 | fbi->fb.var.left_margin = inf->left_margin; | |
1068 | fbi->fb.var.right_margin = inf->right_margin; | |
1069 | fbi->fb.var.vsync_len = inf->vsync_len; | |
1070 | fbi->fb.var.upper_margin = inf->upper_margin; | |
1071 | fbi->fb.var.lower_margin = inf->lower_margin; | |
1072 | fbi->fb.var.sync = inf->sync; | |
1073 | fbi->fb.var.grayscale = inf->cmap_greyscale; | |
1074 | fbi->cmap_inverse = inf->cmap_inverse; | |
1075 | fbi->cmap_static = inf->cmap_static; | |
1076 | fbi->lccr0 = inf->lccr0; | |
1077 | fbi->lccr3 = inf->lccr3; | |
1078 | fbi->state = C_STARTUP; | |
1079 | fbi->task_state = (u_char)-1; | |
1080 | fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres * | |
1081 | fbi->max_bpp / 8; | |
1082 | ||
1083 | init_waitqueue_head(&fbi->ctrlr_wait); | |
1084 | INIT_WORK(&fbi->task, pxafb_task, fbi); | |
1085 | init_MUTEX(&fbi->ctrlr_sem); | |
1086 | ||
1087 | return fbi; | |
1088 | } | |
1089 | ||
1090 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
1091 | static int __init pxafb_parse_options(struct device *dev, char *options) | |
1092 | { | |
1093 | struct pxafb_mach_info *inf = dev->platform_data; | |
1094 | char *this_opt; | |
1095 | ||
1096 | if (!options || !*options) | |
1097 | return 0; | |
1098 | ||
1099 | dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); | |
1100 | ||
1101 | /* could be made table driven or similar?... */ | |
1102 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1103 | if (!strncmp(this_opt, "mode:", 5)) { | |
1104 | const char *name = this_opt+5; | |
1105 | unsigned int namelen = strlen(name); | |
1106 | int res_specified = 0, bpp_specified = 0; | |
1107 | unsigned int xres = 0, yres = 0, bpp = 0; | |
1108 | int yres_specified = 0; | |
1109 | int i; | |
1110 | for (i = namelen-1; i >= 0; i--) { | |
1111 | switch (name[i]) { | |
1112 | case '-': | |
1113 | namelen = i; | |
1114 | if (!bpp_specified && !yres_specified) { | |
1115 | bpp = simple_strtoul(&name[i+1], NULL, 0); | |
1116 | bpp_specified = 1; | |
1117 | } else | |
1118 | goto done; | |
1119 | break; | |
1120 | case 'x': | |
1121 | if (!yres_specified) { | |
1122 | yres = simple_strtoul(&name[i+1], NULL, 0); | |
1123 | yres_specified = 1; | |
1124 | } else | |
1125 | goto done; | |
1126 | break; | |
1127 | case '0'...'9': | |
1128 | break; | |
1129 | default: | |
1130 | goto done; | |
1131 | } | |
1132 | } | |
1133 | if (i < 0 && yres_specified) { | |
1134 | xres = simple_strtoul(name, NULL, 0); | |
1135 | res_specified = 1; | |
1136 | } | |
1137 | done: | |
1138 | if (res_specified) { | |
1139 | dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); | |
1140 | inf->xres = xres; inf->yres = yres; | |
1141 | } | |
1142 | if (bpp_specified) | |
1143 | switch (bpp) { | |
1144 | case 1: | |
1145 | case 2: | |
1146 | case 4: | |
1147 | case 8: | |
1148 | case 16: | |
1149 | inf->bpp = bpp; | |
1150 | dev_info(dev, "overriding bit depth: %d\n", bpp); | |
1151 | break; | |
1152 | default: | |
1153 | dev_err(dev, "Depth %d is not valid\n", bpp); | |
1154 | } | |
1155 | } else if (!strncmp(this_opt, "pixclock:", 9)) { | |
1156 | inf->pixclock = simple_strtoul(this_opt+9, NULL, 0); | |
1157 | dev_info(dev, "override pixclock: %ld\n", inf->pixclock); | |
1158 | } else if (!strncmp(this_opt, "left:", 5)) { | |
1159 | inf->left_margin = simple_strtoul(this_opt+5, NULL, 0); | |
1160 | dev_info(dev, "override left: %u\n", inf->left_margin); | |
1161 | } else if (!strncmp(this_opt, "right:", 6)) { | |
1162 | inf->right_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1163 | dev_info(dev, "override right: %u\n", inf->right_margin); | |
1164 | } else if (!strncmp(this_opt, "upper:", 6)) { | |
1165 | inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1166 | dev_info(dev, "override upper: %u\n", inf->upper_margin); | |
1167 | } else if (!strncmp(this_opt, "lower:", 6)) { | |
1168 | inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1169 | dev_info(dev, "override lower: %u\n", inf->lower_margin); | |
1170 | } else if (!strncmp(this_opt, "hsynclen:", 9)) { | |
1171 | inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1172 | dev_info(dev, "override hsynclen: %u\n", inf->hsync_len); | |
1173 | } else if (!strncmp(this_opt, "vsynclen:", 9)) { | |
1174 | inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1175 | dev_info(dev, "override vsynclen: %u\n", inf->vsync_len); | |
1176 | } else if (!strncmp(this_opt, "hsync:", 6)) { | |
1177 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1178 | dev_info(dev, "override hsync: Active Low\n"); | |
1179 | inf->sync &= ~FB_SYNC_HOR_HIGH_ACT; | |
1180 | } else { | |
1181 | dev_info(dev, "override hsync: Active High\n"); | |
1182 | inf->sync |= FB_SYNC_HOR_HIGH_ACT; | |
1183 | } | |
1184 | } else if (!strncmp(this_opt, "vsync:", 6)) { | |
1185 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1186 | dev_info(dev, "override vsync: Active Low\n"); | |
1187 | inf->sync &= ~FB_SYNC_VERT_HIGH_ACT; | |
1188 | } else { | |
1189 | dev_info(dev, "override vsync: Active High\n"); | |
1190 | inf->sync |= FB_SYNC_VERT_HIGH_ACT; | |
1191 | } | |
1192 | } else if (!strncmp(this_opt, "dpc:", 4)) { | |
1193 | if (simple_strtoul(this_opt+4, NULL, 0) == 0) { | |
1194 | dev_info(dev, "override double pixel clock: false\n"); | |
1195 | inf->lccr3 &= ~LCCR3_DPC; | |
1196 | } else { | |
1197 | dev_info(dev, "override double pixel clock: true\n"); | |
1198 | inf->lccr3 |= LCCR3_DPC; | |
1199 | } | |
1200 | } else if (!strncmp(this_opt, "outputen:", 9)) { | |
1201 | if (simple_strtoul(this_opt+9, NULL, 0) == 0) { | |
1202 | dev_info(dev, "override output enable: active low\n"); | |
1203 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; | |
1204 | } else { | |
1205 | dev_info(dev, "override output enable: active high\n"); | |
1206 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; | |
1207 | } | |
1208 | } else if (!strncmp(this_opt, "pixclockpol:", 12)) { | |
1209 | if (simple_strtoul(this_opt+12, NULL, 0) == 0) { | |
1210 | dev_info(dev, "override pixel clock polarity: falling edge\n"); | |
1211 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; | |
1212 | } else { | |
1213 | dev_info(dev, "override pixel clock polarity: rising edge\n"); | |
1214 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; | |
1215 | } | |
1216 | } else if (!strncmp(this_opt, "color", 5)) { | |
1217 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; | |
1218 | } else if (!strncmp(this_opt, "mono", 4)) { | |
1219 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; | |
1220 | } else if (!strncmp(this_opt, "active", 6)) { | |
1221 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; | |
1222 | } else if (!strncmp(this_opt, "passive", 7)) { | |
1223 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; | |
1224 | } else if (!strncmp(this_opt, "single", 6)) { | |
1225 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; | |
1226 | } else if (!strncmp(this_opt, "dual", 4)) { | |
1227 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; | |
1228 | } else if (!strncmp(this_opt, "4pix", 4)) { | |
1229 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; | |
1230 | } else if (!strncmp(this_opt, "8pix", 4)) { | |
1231 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; | |
1232 | } else { | |
1233 | dev_err(dev, "unknown option: %s\n", this_opt); | |
1234 | return -EINVAL; | |
1235 | } | |
1236 | } | |
1237 | return 0; | |
1238 | ||
1239 | } | |
1240 | #endif | |
1241 | ||
1242 | int __init pxafb_probe(struct device *dev) | |
1243 | { | |
1244 | struct pxafb_info *fbi; | |
1245 | struct pxafb_mach_info *inf; | |
1246 | int ret; | |
1247 | ||
1248 | dev_dbg(dev, "pxafb_probe\n"); | |
1249 | ||
1250 | inf = dev->platform_data; | |
1251 | ret = -ENOMEM; | |
1252 | fbi = NULL; | |
1253 | if (!inf) | |
1254 | goto failed; | |
1255 | ||
1256 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
1257 | ret = pxafb_parse_options(dev, g_options); | |
1258 | if (ret < 0) | |
1259 | goto failed; | |
1260 | #endif | |
1261 | ||
1262 | #ifdef DEBUG_VAR | |
1263 | /* Check for various illegal bit-combinations. Currently only | |
1264 | * a warning is given. */ | |
1265 | ||
1266 | if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) | |
1267 | dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n", | |
1268 | inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); | |
1269 | if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) | |
1270 | dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n", | |
1271 | inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); | |
1272 | if (inf->lccr0 & LCCR0_DPD && | |
1273 | ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || | |
1274 | (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || | |
1275 | (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) | |
1276 | dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono" | |
1277 | " single panel mode\n"); | |
1278 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && | |
1279 | (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
1280 | dev_warn(dev, "Dual panel only valid in passive mode\n"); | |
1281 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && | |
1282 | (inf->upper_margin || inf->lower_margin)) | |
1283 | dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n"); | |
1284 | #endif | |
1285 | ||
1286 | dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp); | |
1287 | if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) { | |
1288 | dev_err(dev, "Invalid resolution or bit depth\n"); | |
1289 | ret = -EINVAL; | |
1290 | goto failed; | |
1291 | } | |
1292 | pxafb_backlight_power = inf->pxafb_backlight_power; | |
1293 | pxafb_lcd_power = inf->pxafb_lcd_power; | |
1294 | fbi = pxafb_init_fbinfo(dev); | |
1295 | if (!fbi) { | |
1296 | dev_err(dev, "Failed to initialize framebuffer device\n"); | |
1297 | ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc | |
1298 | goto failed; | |
1299 | } | |
1300 | ||
1301 | /* Initialize video memory */ | |
1302 | ret = pxafb_map_video_memory(fbi); | |
1303 | if (ret) { | |
1304 | dev_err(dev, "Failed to allocate video RAM: %d\n", ret); | |
1305 | ret = -ENOMEM; | |
1306 | goto failed; | |
1307 | } | |
1da177e4 LT |
1308 | |
1309 | ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi); | |
1310 | if (ret) { | |
1311 | dev_err(dev, "request_irq failed: %d\n", ret); | |
1312 | ret = -EBUSY; | |
1313 | goto failed; | |
1314 | } | |
1315 | ||
1316 | /* | |
1317 | * This makes sure that our colour bitfield | |
1318 | * descriptors are correctly initialised. | |
1319 | */ | |
1320 | pxafb_check_var(&fbi->fb.var, &fbi->fb); | |
1321 | pxafb_set_par(&fbi->fb); | |
1322 | ||
1323 | dev_set_drvdata(dev, fbi); | |
1324 | ||
1325 | ret = register_framebuffer(&fbi->fb); | |
1326 | if (ret < 0) { | |
1327 | dev_err(dev, "Failed to register framebuffer device: %d\n", ret); | |
1328 | goto failed; | |
1329 | } | |
1330 | ||
1331 | #ifdef CONFIG_PM | |
1332 | // TODO | |
1333 | #endif | |
1334 | ||
1335 | #ifdef CONFIG_CPU_FREQ | |
1336 | fbi->freq_transition.notifier_call = pxafb_freq_transition; | |
1337 | fbi->freq_policy.notifier_call = pxafb_freq_policy; | |
1338 | cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); | |
1339 | cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER); | |
1340 | #endif | |
1341 | ||
1342 | /* | |
1343 | * Ok, now enable the LCD controller | |
1344 | */ | |
1345 | set_ctrlr_state(fbi, C_ENABLE); | |
1346 | ||
1347 | return 0; | |
1348 | ||
1349 | failed: | |
1350 | dev_set_drvdata(dev, NULL); | |
1351 | kfree(fbi); | |
1352 | return ret; | |
1353 | } | |
1354 | ||
1355 | static struct device_driver pxafb_driver = { | |
1356 | .name = "pxa2xx-fb", | |
1357 | .bus = &platform_bus_type, | |
1358 | .probe = pxafb_probe, | |
1359 | #ifdef CONFIG_PM | |
1360 | .suspend = pxafb_suspend, | |
1361 | .resume = pxafb_resume, | |
1362 | #endif | |
1363 | }; | |
1364 | ||
1365 | #ifndef MODULE | |
1366 | int __devinit pxafb_setup(char *options) | |
1367 | { | |
1368 | # ifdef CONFIG_FB_PXA_PARAMETERS | |
1369 | strlcpy(g_options, options, sizeof(g_options)); | |
1370 | # endif | |
1371 | return 0; | |
1372 | } | |
1373 | #else | |
1374 | # ifdef CONFIG_FB_PXA_PARAMETERS | |
1375 | module_param_string(options, g_options, sizeof(g_options), 0); | |
1376 | MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |
1377 | # endif | |
1378 | #endif | |
1379 | ||
1380 | int __devinit pxafb_init(void) | |
1381 | { | |
1382 | #ifndef MODULE | |
1383 | char *option = NULL; | |
1384 | ||
1385 | if (fb_get_options("pxafb", &option)) | |
1386 | return -ENODEV; | |
1387 | pxafb_setup(option); | |
1388 | #endif | |
1389 | return driver_register(&pxafb_driver); | |
1390 | } | |
1391 | ||
1392 | module_init(pxafb_init); | |
1393 | ||
1394 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | |
1395 | MODULE_LICENSE("GPL"); |