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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/pxafb.c | |
3 | * | |
4 | * Copyright (C) 1999 Eric A. Thomas. | |
5 | * Copyright (C) 2004 Jean-Frederic Clere. | |
6 | * Copyright (C) 2004 Ian Campbell. | |
7 | * Copyright (C) 2004 Jeff Lackey. | |
8 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas | |
9 | * which in turn is | |
10 | * Based on acornfb.c Copyright (C) Russell King. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | * | |
16 | * Intel PXA250/210 LCD Controller Frame Buffer Driver | |
17 | * | |
18 | * Please direct your questions and comments on this driver to the following | |
19 | * email address: | |
20 | * | |
21 | * linux-arm-kernel@lists.arm.linux.org.uk | |
22 | * | |
23 | */ | |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/fb.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/cpufreq.h> | |
d052d1be | 38 | #include <linux/platform_device.h> |
1da177e4 | 39 | #include <linux/dma-mapping.h> |
72e3524c RK |
40 | #include <linux/clk.h> |
41 | #include <linux/err.h> | |
1da177e4 LT |
42 | |
43 | #include <asm/hardware.h> | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
bf1b8ab6 | 46 | #include <asm/div64.h> |
1da177e4 | 47 | #include <asm/arch/pxa-regs.h> |
a683b14d | 48 | #include <asm/arch/pxa2xx-gpio.h> |
1da177e4 LT |
49 | #include <asm/arch/bitfield.h> |
50 | #include <asm/arch/pxafb.h> | |
51 | ||
52 | /* | |
53 | * Complain if VAR is out of range. | |
54 | */ | |
55 | #define DEBUG_VAR 1 | |
56 | ||
57 | #include "pxafb.h" | |
58 | ||
59 | /* Bits which should not be set in machine configuration structures */ | |
b0086efb | 60 | #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ |
61 | LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ | |
62 | LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) | |
63 | ||
64 | #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ | |
65 | LCCR3_PCD | LCCR3_BPP) | |
1da177e4 LT |
66 | |
67 | static void (*pxafb_backlight_power)(int); | |
d14b272b | 68 | static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); |
1da177e4 | 69 | |
b0086efb | 70 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
71 | struct pxafb_info *); | |
1da177e4 LT |
72 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); |
73 | ||
1da177e4 LT |
74 | static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) |
75 | { | |
76 | unsigned long flags; | |
77 | ||
78 | local_irq_save(flags); | |
79 | /* | |
80 | * We need to handle two requests being made at the same time. | |
81 | * There are two important cases: | |
b0086efb | 82 | * 1. When we are changing VT (C_REENABLE) while unblanking |
83 | * (C_ENABLE) We must perform the unblanking, which will | |
84 | * do our REENABLE for us. | |
85 | * 2. When we are blanking, but immediately unblank before | |
86 | * we have blanked. We do the "REENABLE" thing here as | |
87 | * well, just to be sure. | |
1da177e4 LT |
88 | */ |
89 | if (fbi->task_state == C_ENABLE && state == C_REENABLE) | |
90 | state = (u_int) -1; | |
91 | if (fbi->task_state == C_DISABLE && state == C_ENABLE) | |
92 | state = C_REENABLE; | |
93 | ||
94 | if (state != (u_int)-1) { | |
95 | fbi->task_state = state; | |
96 | schedule_work(&fbi->task); | |
97 | } | |
98 | local_irq_restore(flags); | |
99 | } | |
100 | ||
101 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
102 | { | |
103 | chan &= 0xffff; | |
104 | chan >>= 16 - bf->length; | |
105 | return chan << bf->offset; | |
106 | } | |
107 | ||
108 | static int | |
109 | pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, | |
110 | u_int trans, struct fb_info *info) | |
111 | { | |
112 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
9ffa7396 HK |
113 | u_int val; |
114 | ||
115 | if (regno >= fbi->palette_size) | |
116 | return 1; | |
117 | ||
118 | if (fbi->fb.var.grayscale) { | |
119 | fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); | |
120 | return 0; | |
121 | } | |
122 | ||
123 | switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { | |
124 | case LCCR4_PAL_FOR_0: | |
125 | val = ((red >> 0) & 0xf800); | |
126 | val |= ((green >> 5) & 0x07e0); | |
127 | val |= ((blue >> 11) & 0x001f); | |
1da177e4 | 128 | fbi->palette_cpu[regno] = val; |
9ffa7396 HK |
129 | break; |
130 | case LCCR4_PAL_FOR_1: | |
131 | val = ((red << 8) & 0x00f80000); | |
132 | val |= ((green >> 0) & 0x0000fc00); | |
133 | val |= ((blue >> 8) & 0x000000f8); | |
b0086efb | 134 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 HK |
135 | break; |
136 | case LCCR4_PAL_FOR_2: | |
137 | val = ((red << 8) & 0x00fc0000); | |
138 | val |= ((green >> 0) & 0x0000fc00); | |
139 | val |= ((blue >> 8) & 0x000000fc); | |
b0086efb | 140 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 | 141 | break; |
1da177e4 | 142 | } |
9ffa7396 HK |
143 | |
144 | return 0; | |
1da177e4 LT |
145 | } |
146 | ||
147 | static int | |
148 | pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
149 | u_int trans, struct fb_info *info) | |
150 | { | |
151 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
152 | unsigned int val; | |
153 | int ret = 1; | |
154 | ||
155 | /* | |
156 | * If inverse mode was selected, invert all the colours | |
157 | * rather than the register number. The register number | |
158 | * is what you poke into the framebuffer to produce the | |
159 | * colour you requested. | |
160 | */ | |
161 | if (fbi->cmap_inverse) { | |
162 | red = 0xffff - red; | |
163 | green = 0xffff - green; | |
164 | blue = 0xffff - blue; | |
165 | } | |
166 | ||
167 | /* | |
168 | * If greyscale is true, then we convert the RGB value | |
169 | * to greyscale no matter what visual we are using. | |
170 | */ | |
171 | if (fbi->fb.var.grayscale) | |
172 | red = green = blue = (19595 * red + 38470 * green + | |
173 | 7471 * blue) >> 16; | |
174 | ||
175 | switch (fbi->fb.fix.visual) { | |
176 | case FB_VISUAL_TRUECOLOR: | |
177 | /* | |
178 | * 16-bit True Colour. We encode the RGB value | |
179 | * according to the RGB bitfield information. | |
180 | */ | |
181 | if (regno < 16) { | |
182 | u32 *pal = fbi->fb.pseudo_palette; | |
183 | ||
184 | val = chan_to_field(red, &fbi->fb.var.red); | |
185 | val |= chan_to_field(green, &fbi->fb.var.green); | |
186 | val |= chan_to_field(blue, &fbi->fb.var.blue); | |
187 | ||
188 | pal[regno] = val; | |
189 | ret = 0; | |
190 | } | |
191 | break; | |
192 | ||
193 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
194 | case FB_VISUAL_PSEUDOCOLOR: | |
195 | ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); | |
196 | break; | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
202 | /* | |
203 | * pxafb_bpp_to_lccr3(): | |
204 | * Convert a bits per pixel value to the correct bit pattern for LCCR3 | |
205 | */ | |
206 | static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) | |
207 | { | |
b0086efb | 208 | int ret = 0; |
209 | switch (var->bits_per_pixel) { | |
210 | case 1: ret = LCCR3_1BPP; break; | |
211 | case 2: ret = LCCR3_2BPP; break; | |
212 | case 4: ret = LCCR3_4BPP; break; | |
213 | case 8: ret = LCCR3_8BPP; break; | |
214 | case 16: ret = LCCR3_16BPP; break; | |
215 | } | |
216 | return ret; | |
1da177e4 LT |
217 | } |
218 | ||
219 | #ifdef CONFIG_CPU_FREQ | |
220 | /* | |
221 | * pxafb_display_dma_period() | |
222 | * Calculate the minimum period (in picoseconds) between two DMA | |
223 | * requests for the LCD controller. If we hit this, it means we're | |
224 | * doing nothing but LCD DMA. | |
225 | */ | |
226 | static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) | |
227 | { | |
b0086efb | 228 | /* |
229 | * Period = pixclock * bits_per_byte * bytes_per_transfer | |
230 | * / memory_bits_per_pixel; | |
231 | */ | |
232 | return var->pixclock * 8 * 16 / var->bits_per_pixel; | |
1da177e4 | 233 | } |
1da177e4 LT |
234 | #endif |
235 | ||
d14b272b RP |
236 | /* |
237 | * Select the smallest mode that allows the desired resolution to be | |
238 | * displayed. If desired parameters can be rounded up. | |
239 | */ | |
b0086efb | 240 | static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, |
241 | struct fb_var_screeninfo *var) | |
d14b272b RP |
242 | { |
243 | struct pxafb_mode_info *mode = NULL; | |
244 | struct pxafb_mode_info *modelist = mach->modes; | |
245 | unsigned int best_x = 0xffffffff, best_y = 0xffffffff; | |
246 | unsigned int i; | |
247 | ||
b0086efb | 248 | for (i = 0; i < mach->num_modes; i++) { |
249 | if (modelist[i].xres >= var->xres && | |
250 | modelist[i].yres >= var->yres && | |
251 | modelist[i].xres < best_x && | |
252 | modelist[i].yres < best_y && | |
253 | modelist[i].bpp >= var->bits_per_pixel) { | |
d14b272b RP |
254 | best_x = modelist[i].xres; |
255 | best_y = modelist[i].yres; | |
256 | mode = &modelist[i]; | |
257 | } | |
258 | } | |
259 | ||
260 | return mode; | |
261 | } | |
262 | ||
b0086efb | 263 | static void pxafb_setmode(struct fb_var_screeninfo *var, |
264 | struct pxafb_mode_info *mode) | |
d14b272b RP |
265 | { |
266 | var->xres = mode->xres; | |
267 | var->yres = mode->yres; | |
268 | var->bits_per_pixel = mode->bpp; | |
269 | var->pixclock = mode->pixclock; | |
270 | var->hsync_len = mode->hsync_len; | |
271 | var->left_margin = mode->left_margin; | |
272 | var->right_margin = mode->right_margin; | |
273 | var->vsync_len = mode->vsync_len; | |
274 | var->upper_margin = mode->upper_margin; | |
275 | var->lower_margin = mode->lower_margin; | |
276 | var->sync = mode->sync; | |
277 | var->grayscale = mode->cmap_greyscale; | |
278 | var->xres_virtual = var->xres; | |
279 | var->yres_virtual = var->yres; | |
280 | } | |
281 | ||
1da177e4 LT |
282 | /* |
283 | * pxafb_check_var(): | |
284 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
285 | * if it's too big, return -EINVAL. | |
286 | * | |
287 | * Round up in the following order: bits_per_pixel, xres, | |
288 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
289 | * bitfields, horizontal timing, vertical timing. | |
290 | */ | |
291 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
292 | { | |
293 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
d14b272b | 294 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
1da177e4 LT |
295 | |
296 | if (var->xres < MIN_XRES) | |
297 | var->xres = MIN_XRES; | |
298 | if (var->yres < MIN_YRES) | |
299 | var->yres = MIN_YRES; | |
d14b272b RP |
300 | |
301 | if (inf->fixed_modes) { | |
302 | struct pxafb_mode_info *mode; | |
303 | ||
304 | mode = pxafb_getmode(inf, var); | |
305 | if (!mode) | |
306 | return -EINVAL; | |
307 | pxafb_setmode(var, mode); | |
308 | } else { | |
309 | if (var->xres > inf->modes->xres) | |
310 | return -EINVAL; | |
311 | if (var->yres > inf->modes->yres) | |
312 | return -EINVAL; | |
313 | if (var->bits_per_pixel > inf->modes->bpp) | |
314 | return -EINVAL; | |
315 | } | |
316 | ||
1da177e4 LT |
317 | var->xres_virtual = |
318 | max(var->xres_virtual, var->xres); | |
319 | var->yres_virtual = | |
320 | max(var->yres_virtual, var->yres); | |
321 | ||
b0086efb | 322 | /* |
1da177e4 LT |
323 | * Setup the RGB parameters for this display. |
324 | * | |
325 | * The pixel packing format is described on page 7-11 of the | |
326 | * PXA2XX Developer's Manual. | |
b0086efb | 327 | */ |
1da177e4 LT |
328 | if (var->bits_per_pixel == 16) { |
329 | var->red.offset = 11; var->red.length = 5; | |
330 | var->green.offset = 5; var->green.length = 6; | |
331 | var->blue.offset = 0; var->blue.length = 5; | |
332 | var->transp.offset = var->transp.length = 0; | |
333 | } else { | |
b0086efb | 334 | var->red.offset = var->green.offset = 0; |
335 | var->blue.offset = var->transp.offset = 0; | |
1da177e4 LT |
336 | var->red.length = 8; |
337 | var->green.length = 8; | |
338 | var->blue.length = 8; | |
339 | var->transp.length = 0; | |
340 | } | |
341 | ||
342 | #ifdef CONFIG_CPU_FREQ | |
ca5da710 RK |
343 | pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n", |
344 | pxafb_display_dma_period(var), | |
345 | get_clk_frequency_khz(0)); | |
1da177e4 LT |
346 | #endif |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static inline void pxafb_set_truecolor(u_int is_true_color) | |
352 | { | |
b0086efb | 353 | /* do your machine-specific setup if needed */ |
1da177e4 LT |
354 | } |
355 | ||
356 | /* | |
357 | * pxafb_set_par(): | |
358 | * Set the user defined part of the display for the specified console | |
359 | */ | |
360 | static int pxafb_set_par(struct fb_info *info) | |
361 | { | |
362 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
363 | struct fb_var_screeninfo *var = &info->var; | |
364 | unsigned long palette_mem_size; | |
365 | ||
1da177e4 LT |
366 | if (var->bits_per_pixel == 16) |
367 | fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
368 | else if (!fbi->cmap_static) | |
369 | fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
370 | else { | |
371 | /* | |
372 | * Some people have weird ideas about wanting static | |
373 | * pseudocolor maps. I suspect their user space | |
374 | * applications are broken. | |
375 | */ | |
376 | fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
377 | } | |
378 | ||
379 | fbi->fb.fix.line_length = var->xres_virtual * | |
380 | var->bits_per_pixel / 8; | |
381 | if (var->bits_per_pixel == 16) | |
382 | fbi->palette_size = 0; | |
383 | else | |
b0086efb | 384 | fbi->palette_size = var->bits_per_pixel == 1 ? |
385 | 4 : 1 << var->bits_per_pixel; | |
1da177e4 | 386 | |
9ffa7396 HK |
387 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) |
388 | palette_mem_size = fbi->palette_size * sizeof(u16); | |
389 | else | |
390 | palette_mem_size = fbi->palette_size * sizeof(u32); | |
1da177e4 | 391 | |
1da177e4 LT |
392 | fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); |
393 | fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; | |
394 | ||
395 | /* | |
396 | * Set (any) board control register to handle new color depth | |
397 | */ | |
398 | pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); | |
399 | ||
400 | if (fbi->fb.var.bits_per_pixel == 16) | |
401 | fb_dealloc_cmap(&fbi->fb.cmap); | |
402 | else | |
403 | fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); | |
404 | ||
405 | pxafb_activate_var(var, fbi); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
1da177e4 LT |
410 | /* |
411 | * pxafb_blank(): | |
412 | * Blank the display by setting all palette values to zero. Note, the | |
413 | * 16 bpp mode does not really use the palette, so this will not | |
414 | * blank the display in all modes. | |
415 | */ | |
416 | static int pxafb_blank(int blank, struct fb_info *info) | |
417 | { | |
418 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
419 | int i; | |
420 | ||
1da177e4 LT |
421 | switch (blank) { |
422 | case FB_BLANK_POWERDOWN: | |
423 | case FB_BLANK_VSYNC_SUSPEND: | |
424 | case FB_BLANK_HSYNC_SUSPEND: | |
425 | case FB_BLANK_NORMAL: | |
426 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
427 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
428 | for (i = 0; i < fbi->palette_size; i++) | |
429 | pxafb_setpalettereg(i, 0, 0, 0, 0, info); | |
430 | ||
431 | pxafb_schedule_work(fbi, C_DISABLE); | |
b0086efb | 432 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
433 | break; |
434 | ||
435 | case FB_BLANK_UNBLANK: | |
b0086efb | 436 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
437 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || |
438 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
439 | fb_set_cmap(&fbi->fb.cmap, info); | |
440 | pxafb_schedule_work(fbi, C_ENABLE); | |
441 | } | |
442 | return 0; | |
443 | } | |
444 | ||
216d526c | 445 | static int pxafb_mmap(struct fb_info *info, |
1da177e4 LT |
446 | struct vm_area_struct *vma) |
447 | { | |
448 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
449 | unsigned long off = vma->vm_pgoff << PAGE_SHIFT; | |
450 | ||
451 | if (off < info->fix.smem_len) { | |
452 | vma->vm_pgoff += 1; | |
453 | return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, | |
454 | fbi->map_dma, fbi->map_size); | |
455 | } | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
459 | static struct fb_ops pxafb_ops = { | |
460 | .owner = THIS_MODULE, | |
461 | .fb_check_var = pxafb_check_var, | |
462 | .fb_set_par = pxafb_set_par, | |
463 | .fb_setcolreg = pxafb_setcolreg, | |
464 | .fb_fillrect = cfb_fillrect, | |
465 | .fb_copyarea = cfb_copyarea, | |
466 | .fb_imageblit = cfb_imageblit, | |
467 | .fb_blank = pxafb_blank, | |
1da177e4 LT |
468 | .fb_mmap = pxafb_mmap, |
469 | }; | |
470 | ||
471 | /* | |
472 | * Calculate the PCD value from the clock rate (in picoseconds). | |
473 | * We take account of the PPCR clock setting. | |
474 | * From PXA Developer's Manual: | |
475 | * | |
476 | * PixelClock = LCLK | |
477 | * ------------- | |
478 | * 2 ( PCD + 1 ) | |
479 | * | |
480 | * PCD = LCLK | |
481 | * ------------- - 1 | |
482 | * 2(PixelClock) | |
483 | * | |
484 | * Where: | |
485 | * LCLK = LCD/Memory Clock | |
486 | * PCD = LCCR3[7:0] | |
487 | * | |
488 | * PixelClock here is in Hz while the pixclock argument given is the | |
489 | * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) | |
490 | * | |
491 | * The function get_lclk_frequency_10khz returns LCLK in units of | |
492 | * 10khz. Calling the result of this function lclk gives us the | |
493 | * following | |
494 | * | |
495 | * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) | |
496 | * -------------------------------------- - 1 | |
497 | * 2 | |
498 | * | |
499 | * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. | |
500 | */ | |
b0086efb | 501 | static inline unsigned int get_pcd(struct pxafb_info *fbi, |
502 | unsigned int pixclock) | |
1da177e4 LT |
503 | { |
504 | unsigned long long pcd; | |
505 | ||
506 | /* FIXME: Need to take into account Double Pixel Clock mode | |
72e3524c RK |
507 | * (DPC) bit? or perhaps set it based on the various clock |
508 | * speeds */ | |
509 | pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); | |
510 | pcd *= pixclock; | |
bf1b8ab6 | 511 | do_div(pcd, 100000000 * 2); |
1da177e4 LT |
512 | /* no need for this, since we should subtract 1 anyway. they cancel */ |
513 | /* pcd += 1; */ /* make up for integer math truncations */ | |
514 | return (unsigned int)pcd; | |
515 | } | |
516 | ||
ba44cd2d RP |
517 | /* |
518 | * Some touchscreens need hsync information from the video driver to | |
72e3524c RK |
519 | * function correctly. We export it here. Note that 'hsync_time' and |
520 | * the value returned from pxafb_get_hsync_time() is the *reciprocal* | |
521 | * of the hsync period in seconds. | |
ba44cd2d RP |
522 | */ |
523 | static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) | |
524 | { | |
72e3524c | 525 | unsigned long htime; |
ba44cd2d RP |
526 | |
527 | if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { | |
b0086efb | 528 | fbi->hsync_time = 0; |
ba44cd2d RP |
529 | return; |
530 | } | |
531 | ||
72e3524c RK |
532 | htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); |
533 | ||
ba44cd2d RP |
534 | fbi->hsync_time = htime; |
535 | } | |
536 | ||
537 | unsigned long pxafb_get_hsync_time(struct device *dev) | |
538 | { | |
539 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
540 | ||
541 | /* If display is blanked/suspended, hsync isn't active */ | |
542 | if (!fbi || (fbi->state != C_ENABLE)) | |
543 | return 0; | |
544 | ||
545 | return fbi->hsync_time; | |
546 | } | |
547 | EXPORT_SYMBOL(pxafb_get_hsync_time); | |
548 | ||
1da177e4 LT |
549 | /* |
550 | * pxafb_activate_var(): | |
b0086efb | 551 | * Configures LCD Controller based on entries in var parameter. |
552 | * Settings are only written to the controller if changes were made. | |
1da177e4 | 553 | */ |
b0086efb | 554 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
555 | struct pxafb_info *fbi) | |
1da177e4 LT |
556 | { |
557 | struct pxafb_lcd_reg new_regs; | |
558 | u_long flags; | |
72e3524c | 559 | u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); |
1da177e4 | 560 | |
1da177e4 | 561 | #if DEBUG_VAR |
b0086efb | 562 | if (var->xres < 16 || var->xres > 1024) |
1da177e4 LT |
563 | printk(KERN_ERR "%s: invalid xres %d\n", |
564 | fbi->fb.fix.id, var->xres); | |
b0086efb | 565 | switch (var->bits_per_pixel) { |
1da177e4 LT |
566 | case 1: |
567 | case 2: | |
568 | case 4: | |
569 | case 8: | |
570 | case 16: | |
571 | break; | |
572 | default: | |
573 | printk(KERN_ERR "%s: invalid bit depth %d\n", | |
574 | fbi->fb.fix.id, var->bits_per_pixel); | |
575 | break; | |
576 | } | |
b0086efb | 577 | if (var->hsync_len < 1 || var->hsync_len > 64) |
1da177e4 LT |
578 | printk(KERN_ERR "%s: invalid hsync_len %d\n", |
579 | fbi->fb.fix.id, var->hsync_len); | |
b0086efb | 580 | if (var->left_margin < 1 || var->left_margin > 255) |
1da177e4 LT |
581 | printk(KERN_ERR "%s: invalid left_margin %d\n", |
582 | fbi->fb.fix.id, var->left_margin); | |
583 | if (var->right_margin < 1 || var->right_margin > 255) | |
584 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
585 | fbi->fb.fix.id, var->right_margin); | |
b0086efb | 586 | if (var->yres < 1 || var->yres > 1024) |
1da177e4 LT |
587 | printk(KERN_ERR "%s: invalid yres %d\n", |
588 | fbi->fb.fix.id, var->yres); | |
b0086efb | 589 | if (var->vsync_len < 1 || var->vsync_len > 64) |
1da177e4 LT |
590 | printk(KERN_ERR "%s: invalid vsync_len %d\n", |
591 | fbi->fb.fix.id, var->vsync_len); | |
592 | if (var->upper_margin < 0 || var->upper_margin > 255) | |
593 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
594 | fbi->fb.fix.id, var->upper_margin); | |
595 | if (var->lower_margin < 0 || var->lower_margin > 255) | |
596 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
597 | fbi->fb.fix.id, var->lower_margin); | |
598 | #endif | |
599 | ||
600 | new_regs.lccr0 = fbi->lccr0 | | |
601 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | | |
b0086efb | 602 | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); |
1da177e4 LT |
603 | |
604 | new_regs.lccr1 = | |
605 | LCCR1_DisWdth(var->xres) + | |
606 | LCCR1_HorSnchWdth(var->hsync_len) + | |
607 | LCCR1_BegLnDel(var->left_margin) + | |
608 | LCCR1_EndLnDel(var->right_margin); | |
609 | ||
610 | /* | |
611 | * If we have a dual scan LCD, we need to halve | |
612 | * the YRES parameter. | |
613 | */ | |
614 | lines_per_panel = var->yres; | |
615 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
616 | lines_per_panel /= 2; | |
617 | ||
618 | new_regs.lccr2 = | |
619 | LCCR2_DisHght(lines_per_panel) + | |
620 | LCCR2_VrtSnchWdth(var->vsync_len) + | |
621 | LCCR2_BegFrmDel(var->upper_margin) + | |
622 | LCCR2_EndFrmDel(var->lower_margin); | |
623 | ||
624 | new_regs.lccr3 = fbi->lccr3 | | |
625 | pxafb_bpp_to_lccr3(var) | | |
b0086efb | 626 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? |
627 | LCCR3_HorSnchH : LCCR3_HorSnchL) | | |
628 | (var->sync & FB_SYNC_VERT_HIGH_ACT ? | |
629 | LCCR3_VrtSnchH : LCCR3_VrtSnchL); | |
1da177e4 LT |
630 | |
631 | if (pcd) | |
632 | new_regs.lccr3 |= LCCR3_PixClkDiv(pcd); | |
633 | ||
1da177e4 LT |
634 | /* Update shadow copy atomically */ |
635 | local_irq_save(flags); | |
636 | ||
637 | /* setup dma descriptors */ | |
b0086efb | 638 | fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *) |
639 | ((unsigned int)fbi->palette_cpu - 3*16); | |
640 | fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *) | |
641 | ((unsigned int)fbi->palette_cpu - 2*16); | |
642 | fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *) | |
643 | ((unsigned int)fbi->palette_cpu - 1*16); | |
1da177e4 LT |
644 | |
645 | fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16; | |
646 | fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16; | |
647 | fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16; | |
648 | ||
649 | #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length) | |
650 | ||
651 | /* populate descriptors */ | |
652 | fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma; | |
653 | fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL; | |
654 | fbi->dmadesc_fblow_cpu->fidr = 0; | |
655 | fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL; | |
656 | ||
657 | fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */ | |
658 | ||
659 | fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma; | |
660 | fbi->dmadesc_fbhigh_cpu->fidr = 0; | |
661 | fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL; | |
662 | ||
663 | fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma; | |
664 | fbi->dmadesc_palette_cpu->fidr = 0; | |
9ffa7396 HK |
665 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) |
666 | fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size * | |
667 | sizeof(u16); | |
668 | else | |
669 | fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size * | |
670 | sizeof(u32); | |
671 | fbi->dmadesc_palette_cpu->ldcmd |= LDCMD_PAL; | |
1da177e4 LT |
672 | |
673 | if (var->bits_per_pixel == 16) { | |
674 | /* palette shouldn't be loaded in true-color mode */ | |
675 | fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma; | |
676 | fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */ | |
677 | /* init it to something, even though we won't be using it */ | |
678 | fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma; | |
679 | } else { | |
b0086efb | 680 | /* flips back and forth between pal and fbhigh */ |
1da177e4 LT |
681 | fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma; |
682 | fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma; | |
b0086efb | 683 | fbi->fdadr0 = fbi->dmadesc_palette_dma; |
1da177e4 LT |
684 | } |
685 | ||
1da177e4 LT |
686 | fbi->reg_lccr0 = new_regs.lccr0; |
687 | fbi->reg_lccr1 = new_regs.lccr1; | |
688 | fbi->reg_lccr2 = new_regs.lccr2; | |
689 | fbi->reg_lccr3 = new_regs.lccr3; | |
9ffa7396 HK |
690 | fbi->reg_lccr4 = LCCR4 & (~LCCR4_PAL_FOR_MASK); |
691 | fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); | |
ba44cd2d | 692 | set_hsync_time(fbi, pcd); |
1da177e4 LT |
693 | local_irq_restore(flags); |
694 | ||
695 | /* | |
696 | * Only update the registers if the controller is enabled | |
697 | * and something has changed. | |
698 | */ | |
699 | if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) || | |
700 | (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) || | |
701 | (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1)) | |
702 | pxafb_schedule_work(fbi, C_REENABLE); | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
707 | /* | |
708 | * NOTE! The following functions are purely helpers for set_ctrlr_state. | |
709 | * Do not call them directly; set_ctrlr_state does the correct serialisation | |
710 | * to ensure that things happen in the right way 100% of time time. | |
711 | * -- rmk | |
712 | */ | |
713 | static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) | |
714 | { | |
ca5da710 | 715 | pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); |
1da177e4 | 716 | |
b0086efb | 717 | if (pxafb_backlight_power) |
718 | pxafb_backlight_power(on); | |
1da177e4 LT |
719 | } |
720 | ||
721 | static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) | |
722 | { | |
ca5da710 | 723 | pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); |
1da177e4 LT |
724 | |
725 | if (pxafb_lcd_power) | |
d14b272b | 726 | pxafb_lcd_power(on, &fbi->fb.var); |
1da177e4 LT |
727 | } |
728 | ||
729 | static void pxafb_setup_gpio(struct pxafb_info *fbi) | |
730 | { | |
731 | int gpio, ldd_bits; | |
b0086efb | 732 | unsigned int lccr0 = fbi->lccr0; |
1da177e4 LT |
733 | |
734 | /* | |
735 | * setup is based on type of panel supported | |
b0086efb | 736 | */ |
1da177e4 LT |
737 | |
738 | /* 4 bit interface */ | |
739 | if ((lccr0 & LCCR0_CMS) == LCCR0_Mono && | |
740 | (lccr0 & LCCR0_SDS) == LCCR0_Sngl && | |
741 | (lccr0 & LCCR0_DPD) == LCCR0_4PixMono) | |
742 | ldd_bits = 4; | |
743 | ||
744 | /* 8 bit interface */ | |
b0086efb | 745 | else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono && |
746 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || | |
747 | (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) || | |
748 | ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
749 | (lccr0 & LCCR0_PAS) == LCCR0_Pas && | |
750 | (lccr0 & LCCR0_SDS) == LCCR0_Sngl)) | |
1da177e4 LT |
751 | ldd_bits = 8; |
752 | ||
753 | /* 16 bit interface */ | |
754 | else if ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
b0086efb | 755 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || |
756 | (lccr0 & LCCR0_PAS) == LCCR0_Act)) | |
1da177e4 LT |
757 | ldd_bits = 16; |
758 | ||
759 | else { | |
b0086efb | 760 | printk(KERN_ERR "pxafb_setup_gpio: unable to determine " |
761 | "bits per pixel\n"); | |
1da177e4 | 762 | return; |
b0086efb | 763 | } |
1da177e4 LT |
764 | |
765 | for (gpio = 58; ldd_bits; gpio++, ldd_bits--) | |
766 | pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); | |
767 | pxa_gpio_mode(GPIO74_LCD_FCLK_MD); | |
768 | pxa_gpio_mode(GPIO75_LCD_LCLK_MD); | |
769 | pxa_gpio_mode(GPIO76_LCD_PCLK_MD); | |
770 | pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); | |
771 | } | |
772 | ||
773 | static void pxafb_enable_controller(struct pxafb_info *fbi) | |
774 | { | |
ca5da710 RK |
775 | pr_debug("pxafb: Enabling LCD controller\n"); |
776 | pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0); | |
777 | pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1); | |
778 | pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); | |
779 | pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); | |
780 | pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); | |
781 | pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); | |
1da177e4 | 782 | |
8d372266 | 783 | /* enable LCD controller clock */ |
72e3524c | 784 | clk_enable(fbi->clk); |
8d372266 | 785 | |
1da177e4 LT |
786 | /* Sequence from 11.7.10 */ |
787 | LCCR3 = fbi->reg_lccr3; | |
788 | LCCR2 = fbi->reg_lccr2; | |
789 | LCCR1 = fbi->reg_lccr1; | |
790 | LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB; | |
791 | ||
792 | FDADR0 = fbi->fdadr0; | |
793 | FDADR1 = fbi->fdadr1; | |
794 | LCCR0 |= LCCR0_ENB; | |
1da177e4 LT |
795 | } |
796 | ||
797 | static void pxafb_disable_controller(struct pxafb_info *fbi) | |
798 | { | |
799 | DECLARE_WAITQUEUE(wait, current); | |
800 | ||
1da177e4 LT |
801 | set_current_state(TASK_UNINTERRUPTIBLE); |
802 | add_wait_queue(&fbi->ctrlr_wait, &wait); | |
803 | ||
804 | LCSR = 0xffffffff; /* Clear LCD Status Register */ | |
805 | LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ | |
806 | LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ | |
807 | ||
2cbbb3b5 | 808 | schedule_timeout(200 * HZ / 1000); |
1da177e4 | 809 | remove_wait_queue(&fbi->ctrlr_wait, &wait); |
8d372266 NP |
810 | |
811 | /* disable LCD controller clock */ | |
72e3524c | 812 | clk_disable(fbi->clk); |
1da177e4 LT |
813 | } |
814 | ||
815 | /* | |
816 | * pxafb_handle_irq: Handle 'LCD DONE' interrupts. | |
817 | */ | |
7d12e780 | 818 | static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) |
1da177e4 LT |
819 | { |
820 | struct pxafb_info *fbi = dev_id; | |
821 | unsigned int lcsr = LCSR; | |
822 | ||
823 | if (lcsr & LCSR_LDD) { | |
824 | LCCR0 |= LCCR0_LDM; | |
825 | wake_up(&fbi->ctrlr_wait); | |
826 | } | |
827 | ||
828 | LCSR = lcsr; | |
829 | return IRQ_HANDLED; | |
830 | } | |
831 | ||
832 | /* | |
833 | * This function must be called from task context only, since it will | |
834 | * sleep when disabling the LCD controller, or if we get two contending | |
835 | * processes trying to alter state. | |
836 | */ | |
837 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) | |
838 | { | |
839 | u_int old_state; | |
840 | ||
841 | down(&fbi->ctrlr_sem); | |
842 | ||
843 | old_state = fbi->state; | |
844 | ||
845 | /* | |
846 | * Hack around fbcon initialisation. | |
847 | */ | |
848 | if (old_state == C_STARTUP && state == C_REENABLE) | |
849 | state = C_ENABLE; | |
850 | ||
851 | switch (state) { | |
852 | case C_DISABLE_CLKCHANGE: | |
853 | /* | |
854 | * Disable controller for clock change. If the | |
855 | * controller is already disabled, then do nothing. | |
856 | */ | |
857 | if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { | |
858 | fbi->state = state; | |
b0086efb | 859 | /* TODO __pxafb_lcd_power(fbi, 0); */ |
1da177e4 LT |
860 | pxafb_disable_controller(fbi); |
861 | } | |
862 | break; | |
863 | ||
864 | case C_DISABLE_PM: | |
865 | case C_DISABLE: | |
866 | /* | |
867 | * Disable controller | |
868 | */ | |
869 | if (old_state != C_DISABLE) { | |
870 | fbi->state = state; | |
871 | __pxafb_backlight_power(fbi, 0); | |
872 | __pxafb_lcd_power(fbi, 0); | |
873 | if (old_state != C_DISABLE_CLKCHANGE) | |
874 | pxafb_disable_controller(fbi); | |
875 | } | |
876 | break; | |
877 | ||
878 | case C_ENABLE_CLKCHANGE: | |
879 | /* | |
880 | * Enable the controller after clock change. Only | |
881 | * do this if we were disabled for the clock change. | |
882 | */ | |
883 | if (old_state == C_DISABLE_CLKCHANGE) { | |
884 | fbi->state = C_ENABLE; | |
885 | pxafb_enable_controller(fbi); | |
b0086efb | 886 | /* TODO __pxafb_lcd_power(fbi, 1); */ |
1da177e4 LT |
887 | } |
888 | break; | |
889 | ||
890 | case C_REENABLE: | |
891 | /* | |
892 | * Re-enable the controller only if it was already | |
893 | * enabled. This is so we reprogram the control | |
894 | * registers. | |
895 | */ | |
896 | if (old_state == C_ENABLE) { | |
d14b272b | 897 | __pxafb_lcd_power(fbi, 0); |
1da177e4 LT |
898 | pxafb_disable_controller(fbi); |
899 | pxafb_setup_gpio(fbi); | |
900 | pxafb_enable_controller(fbi); | |
d14b272b | 901 | __pxafb_lcd_power(fbi, 1); |
1da177e4 LT |
902 | } |
903 | break; | |
904 | ||
905 | case C_ENABLE_PM: | |
906 | /* | |
907 | * Re-enable the controller after PM. This is not | |
908 | * perfect - think about the case where we were doing | |
909 | * a clock change, and we suspended half-way through. | |
910 | */ | |
911 | if (old_state != C_DISABLE_PM) | |
912 | break; | |
913 | /* fall through */ | |
914 | ||
915 | case C_ENABLE: | |
916 | /* | |
917 | * Power up the LCD screen, enable controller, and | |
918 | * turn on the backlight. | |
919 | */ | |
920 | if (old_state != C_ENABLE) { | |
921 | fbi->state = C_ENABLE; | |
922 | pxafb_setup_gpio(fbi); | |
923 | pxafb_enable_controller(fbi); | |
924 | __pxafb_lcd_power(fbi, 1); | |
925 | __pxafb_backlight_power(fbi, 1); | |
926 | } | |
927 | break; | |
928 | } | |
929 | up(&fbi->ctrlr_sem); | |
930 | } | |
931 | ||
932 | /* | |
933 | * Our LCD controller task (which is called when we blank or unblank) | |
934 | * via keventd. | |
935 | */ | |
6d5aefb8 | 936 | static void pxafb_task(struct work_struct *work) |
1da177e4 | 937 | { |
6d5aefb8 DH |
938 | struct pxafb_info *fbi = |
939 | container_of(work, struct pxafb_info, task); | |
1da177e4 LT |
940 | u_int state = xchg(&fbi->task_state, -1); |
941 | ||
942 | set_ctrlr_state(fbi, state); | |
943 | } | |
944 | ||
945 | #ifdef CONFIG_CPU_FREQ | |
946 | /* | |
947 | * CPU clock speed change handler. We need to adjust the LCD timing | |
948 | * parameters when the CPU clock is adjusted by the power management | |
949 | * subsystem. | |
950 | * | |
951 | * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() | |
952 | */ | |
953 | static int | |
954 | pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) | |
955 | { | |
956 | struct pxafb_info *fbi = TO_INF(nb, freq_transition); | |
b0086efb | 957 | /* TODO struct cpufreq_freqs *f = data; */ |
1da177e4 LT |
958 | u_int pcd; |
959 | ||
960 | switch (val) { | |
961 | case CPUFREQ_PRECHANGE: | |
962 | set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); | |
963 | break; | |
964 | ||
965 | case CPUFREQ_POSTCHANGE: | |
72e3524c | 966 | pcd = get_pcd(fbi, fbi->fb.var.pixclock); |
ba44cd2d | 967 | set_hsync_time(fbi, pcd); |
b0086efb | 968 | fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | |
969 | LCCR3_PixClkDiv(pcd); | |
1da177e4 LT |
970 | set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); |
971 | break; | |
972 | } | |
973 | return 0; | |
974 | } | |
975 | ||
976 | static int | |
977 | pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) | |
978 | { | |
979 | struct pxafb_info *fbi = TO_INF(nb, freq_policy); | |
980 | struct fb_var_screeninfo *var = &fbi->fb.var; | |
981 | struct cpufreq_policy *policy = data; | |
982 | ||
983 | switch (val) { | |
984 | case CPUFREQ_ADJUST: | |
985 | case CPUFREQ_INCOMPATIBLE: | |
ac2bf5bd | 986 | pr_debug("min dma period: %d ps, " |
1da177e4 LT |
987 | "new clock %d kHz\n", pxafb_display_dma_period(var), |
988 | policy->max); | |
b0086efb | 989 | /* TODO: fill in min/max values */ |
1da177e4 | 990 | break; |
1da177e4 LT |
991 | } |
992 | return 0; | |
993 | } | |
994 | #endif | |
995 | ||
996 | #ifdef CONFIG_PM | |
997 | /* | |
998 | * Power management hooks. Note that we won't be called from IRQ context, | |
999 | * unlike the blank functions above, so we may sleep. | |
1000 | */ | |
3ae5eaec | 1001 | static int pxafb_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1002 | { |
3ae5eaec | 1003 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1004 | |
9480e307 | 1005 | set_ctrlr_state(fbi, C_DISABLE_PM); |
1da177e4 LT |
1006 | return 0; |
1007 | } | |
1008 | ||
3ae5eaec | 1009 | static int pxafb_resume(struct platform_device *dev) |
1da177e4 | 1010 | { |
3ae5eaec | 1011 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1012 | |
9480e307 | 1013 | set_ctrlr_state(fbi, C_ENABLE_PM); |
1da177e4 LT |
1014 | return 0; |
1015 | } | |
1016 | #else | |
1017 | #define pxafb_suspend NULL | |
1018 | #define pxafb_resume NULL | |
1019 | #endif | |
1020 | ||
1021 | /* | |
1022 | * pxafb_map_video_memory(): | |
1023 | * Allocates the DRAM memory for the frame buffer. This buffer is | |
1024 | * remapped into a non-cached, non-buffered, memory region to | |
1025 | * allow palette and pixel writes to occur without flushing the | |
1026 | * cache. Once this area is remapped, all virtual memory | |
1027 | * access to the video memory should occur at the new region. | |
1028 | */ | |
1029 | static int __init pxafb_map_video_memory(struct pxafb_info *fbi) | |
1030 | { | |
1031 | u_long palette_mem_size; | |
1032 | ||
1033 | /* | |
1034 | * We reserve one page for the palette, plus the size | |
1035 | * of the framebuffer. | |
1036 | */ | |
1037 | fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); | |
1038 | fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, | |
1039 | &fbi->map_dma, GFP_KERNEL); | |
1040 | ||
1041 | if (fbi->map_cpu) { | |
1042 | /* prevent initial garbage on screen */ | |
1043 | memset(fbi->map_cpu, 0, fbi->map_size); | |
1044 | fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; | |
1045 | fbi->screen_dma = fbi->map_dma + PAGE_SIZE; | |
1046 | /* | |
1047 | * FIXME: this is actually the wrong thing to place in | |
1048 | * smem_start. But fbdev suffers from the problem that | |
1049 | * it needs an API which doesn't exist (in this case, | |
1050 | * dma_writecombine_mmap) | |
1051 | */ | |
1052 | fbi->fb.fix.smem_start = fbi->screen_dma; | |
1da177e4 LT |
1053 | fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; |
1054 | ||
9ffa7396 HK |
1055 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) |
1056 | palette_mem_size = fbi->palette_size * sizeof(u16); | |
1057 | else | |
1058 | palette_mem_size = fbi->palette_size * sizeof(u32); | |
1059 | ||
b0086efb | 1060 | fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE |
1061 | - palette_mem_size); | |
1da177e4 LT |
1062 | fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; |
1063 | } | |
1064 | ||
1065 | return fbi->map_cpu ? 0 : -ENOMEM; | |
1066 | } | |
1067 | ||
1068 | static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) | |
1069 | { | |
1070 | struct pxafb_info *fbi; | |
1071 | void *addr; | |
1072 | struct pxafb_mach_info *inf = dev->platform_data; | |
d14b272b RP |
1073 | struct pxafb_mode_info *mode = inf->modes; |
1074 | int i, smemlen; | |
1da177e4 LT |
1075 | |
1076 | /* Alloc the pxafb_info and pseudo_palette in one step */ | |
1077 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | |
1078 | if (!fbi) | |
1079 | return NULL; | |
1080 | ||
1081 | memset(fbi, 0, sizeof(struct pxafb_info)); | |
1082 | fbi->dev = dev; | |
1083 | ||
72e3524c RK |
1084 | fbi->clk = clk_get(dev, "LCDCLK"); |
1085 | if (IS_ERR(fbi->clk)) { | |
1086 | kfree(fbi); | |
1087 | return NULL; | |
1088 | } | |
1089 | ||
1da177e4 LT |
1090 | strcpy(fbi->fb.fix.id, PXA_NAME); |
1091 | ||
1092 | fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1093 | fbi->fb.fix.type_aux = 0; | |
1094 | fbi->fb.fix.xpanstep = 0; | |
1095 | fbi->fb.fix.ypanstep = 0; | |
1096 | fbi->fb.fix.ywrapstep = 0; | |
1097 | fbi->fb.fix.accel = FB_ACCEL_NONE; | |
1098 | ||
1099 | fbi->fb.var.nonstd = 0; | |
1100 | fbi->fb.var.activate = FB_ACTIVATE_NOW; | |
1101 | fbi->fb.var.height = -1; | |
1102 | fbi->fb.var.width = -1; | |
1103 | fbi->fb.var.accel_flags = 0; | |
1104 | fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; | |
1105 | ||
1106 | fbi->fb.fbops = &pxafb_ops; | |
1107 | fbi->fb.flags = FBINFO_DEFAULT; | |
1108 | fbi->fb.node = -1; | |
1109 | ||
1110 | addr = fbi; | |
1111 | addr = addr + sizeof(struct pxafb_info); | |
1112 | fbi->fb.pseudo_palette = addr; | |
1113 | ||
d14b272b RP |
1114 | pxafb_setmode(&fbi->fb.var, mode); |
1115 | ||
b0086efb | 1116 | fbi->cmap_inverse = inf->cmap_inverse; |
1117 | fbi->cmap_static = inf->cmap_static; | |
d14b272b | 1118 | |
b0086efb | 1119 | fbi->lccr0 = inf->lccr0; |
1120 | fbi->lccr3 = inf->lccr3; | |
1121 | fbi->lccr4 = inf->lccr4; | |
1122 | fbi->state = C_STARTUP; | |
1123 | fbi->task_state = (u_char)-1; | |
d14b272b RP |
1124 | |
1125 | for (i = 0; i < inf->num_modes; i++) { | |
1126 | smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8; | |
1127 | if (smemlen > fbi->fb.fix.smem_len) | |
1128 | fbi->fb.fix.smem_len = smemlen; | |
1129 | } | |
1da177e4 LT |
1130 | |
1131 | init_waitqueue_head(&fbi->ctrlr_wait); | |
6d5aefb8 | 1132 | INIT_WORK(&fbi->task, pxafb_task); |
1da177e4 LT |
1133 | init_MUTEX(&fbi->ctrlr_sem); |
1134 | ||
1135 | return fbi; | |
1136 | } | |
1137 | ||
1138 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
b0086efb | 1139 | static int __init parse_opt_mode(struct device *dev, const char *this_opt) |
1da177e4 LT |
1140 | { |
1141 | struct pxafb_mach_info *inf = dev->platform_data; | |
817daf14 | 1142 | |
1143 | const char *name = this_opt+5; | |
1144 | unsigned int namelen = strlen(name); | |
1145 | int res_specified = 0, bpp_specified = 0; | |
1146 | unsigned int xres = 0, yres = 0, bpp = 0; | |
1147 | int yres_specified = 0; | |
1148 | int i; | |
1149 | for (i = namelen-1; i >= 0; i--) { | |
1150 | switch (name[i]) { | |
1151 | case '-': | |
1152 | namelen = i; | |
1153 | if (!bpp_specified && !yres_specified) { | |
1154 | bpp = simple_strtoul(&name[i+1], NULL, 0); | |
1155 | bpp_specified = 1; | |
1156 | } else | |
1157 | goto done; | |
1158 | break; | |
1159 | case 'x': | |
1160 | if (!yres_specified) { | |
1161 | yres = simple_strtoul(&name[i+1], NULL, 0); | |
1162 | yres_specified = 1; | |
1163 | } else | |
1164 | goto done; | |
1165 | break; | |
1166 | case '0' ... '9': | |
1167 | break; | |
1168 | default: | |
1169 | goto done; | |
1170 | } | |
1171 | } | |
1172 | if (i < 0 && yres_specified) { | |
1173 | xres = simple_strtoul(name, NULL, 0); | |
1174 | res_specified = 1; | |
1175 | } | |
1176 | done: | |
1177 | if (res_specified) { | |
1178 | dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); | |
1179 | inf->modes[0].xres = xres; inf->modes[0].yres = yres; | |
1180 | } | |
1181 | if (bpp_specified) | |
1182 | switch (bpp) { | |
1183 | case 1: | |
1184 | case 2: | |
1185 | case 4: | |
1186 | case 8: | |
1187 | case 16: | |
1188 | inf->modes[0].bpp = bpp; | |
1189 | dev_info(dev, "overriding bit depth: %d\n", bpp); | |
1190 | break; | |
1191 | default: | |
1192 | dev_err(dev, "Depth %d is not valid\n", bpp); | |
1193 | return -EINVAL; | |
1194 | } | |
1195 | return 0; | |
1196 | } | |
1197 | ||
b0086efb | 1198 | static int __init parse_opt(struct device *dev, char *this_opt) |
817daf14 | 1199 | { |
1200 | struct pxafb_mach_info *inf = dev->platform_data; | |
1201 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
1202 | char s[64]; | |
1203 | ||
1204 | s[0] = '\0'; | |
1205 | ||
1206 | if (!strncmp(this_opt, "mode:", 5)) { | |
1207 | return parse_opt_mode(dev, this_opt); | |
1208 | } else if (!strncmp(this_opt, "pixclock:", 9)) { | |
1209 | mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); | |
1210 | sprintf(s, "pixclock: %ld\n", mode->pixclock); | |
1211 | } else if (!strncmp(this_opt, "left:", 5)) { | |
1212 | mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); | |
1213 | sprintf(s, "left: %u\n", mode->left_margin); | |
1214 | } else if (!strncmp(this_opt, "right:", 6)) { | |
1215 | mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1216 | sprintf(s, "right: %u\n", mode->right_margin); | |
1217 | } else if (!strncmp(this_opt, "upper:", 6)) { | |
1218 | mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1219 | sprintf(s, "upper: %u\n", mode->upper_margin); | |
1220 | } else if (!strncmp(this_opt, "lower:", 6)) { | |
1221 | mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1222 | sprintf(s, "lower: %u\n", mode->lower_margin); | |
1223 | } else if (!strncmp(this_opt, "hsynclen:", 9)) { | |
1224 | mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1225 | sprintf(s, "hsynclen: %u\n", mode->hsync_len); | |
1226 | } else if (!strncmp(this_opt, "vsynclen:", 9)) { | |
1227 | mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1228 | sprintf(s, "vsynclen: %u\n", mode->vsync_len); | |
1229 | } else if (!strncmp(this_opt, "hsync:", 6)) { | |
1230 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1231 | sprintf(s, "hsync: Active Low\n"); | |
1232 | mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; | |
1233 | } else { | |
1234 | sprintf(s, "hsync: Active High\n"); | |
1235 | mode->sync |= FB_SYNC_HOR_HIGH_ACT; | |
1236 | } | |
1237 | } else if (!strncmp(this_opt, "vsync:", 6)) { | |
1238 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1239 | sprintf(s, "vsync: Active Low\n"); | |
1240 | mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; | |
1241 | } else { | |
1242 | sprintf(s, "vsync: Active High\n"); | |
1243 | mode->sync |= FB_SYNC_VERT_HIGH_ACT; | |
1244 | } | |
1245 | } else if (!strncmp(this_opt, "dpc:", 4)) { | |
1246 | if (simple_strtoul(this_opt+4, NULL, 0) == 0) { | |
1247 | sprintf(s, "double pixel clock: false\n"); | |
1248 | inf->lccr3 &= ~LCCR3_DPC; | |
1249 | } else { | |
1250 | sprintf(s, "double pixel clock: true\n"); | |
1251 | inf->lccr3 |= LCCR3_DPC; | |
1252 | } | |
1253 | } else if (!strncmp(this_opt, "outputen:", 9)) { | |
1254 | if (simple_strtoul(this_opt+9, NULL, 0) == 0) { | |
1255 | sprintf(s, "output enable: active low\n"); | |
1256 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; | |
1257 | } else { | |
1258 | sprintf(s, "output enable: active high\n"); | |
1259 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; | |
1260 | } | |
1261 | } else if (!strncmp(this_opt, "pixclockpol:", 12)) { | |
1262 | if (simple_strtoul(this_opt+12, NULL, 0) == 0) { | |
1263 | sprintf(s, "pixel clock polarity: falling edge\n"); | |
1264 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; | |
1265 | } else { | |
1266 | sprintf(s, "pixel clock polarity: rising edge\n"); | |
1267 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; | |
1268 | } | |
1269 | } else if (!strncmp(this_opt, "color", 5)) { | |
1270 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; | |
1271 | } else if (!strncmp(this_opt, "mono", 4)) { | |
1272 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; | |
1273 | } else if (!strncmp(this_opt, "active", 6)) { | |
1274 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; | |
1275 | } else if (!strncmp(this_opt, "passive", 7)) { | |
1276 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; | |
1277 | } else if (!strncmp(this_opt, "single", 6)) { | |
1278 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; | |
1279 | } else if (!strncmp(this_opt, "dual", 4)) { | |
1280 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; | |
1281 | } else if (!strncmp(this_opt, "4pix", 4)) { | |
1282 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; | |
1283 | } else if (!strncmp(this_opt, "8pix", 4)) { | |
1284 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; | |
1285 | } else { | |
1286 | dev_err(dev, "unknown option: %s\n", this_opt); | |
1287 | return -EINVAL; | |
1288 | } | |
1289 | ||
1290 | if (s[0] != '\0') | |
1291 | dev_info(dev, "override %s", s); | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int __init pxafb_parse_options(struct device *dev, char *options) | |
1297 | { | |
1da177e4 | 1298 | char *this_opt; |
817daf14 | 1299 | int ret; |
1da177e4 | 1300 | |
817daf14 | 1301 | if (!options || !*options) |
1302 | return 0; | |
1da177e4 LT |
1303 | |
1304 | dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); | |
1305 | ||
1306 | /* could be made table driven or similar?... */ | |
817daf14 | 1307 | while ((this_opt = strsep(&options, ",")) != NULL) { |
1308 | ret = parse_opt(dev, this_opt); | |
1309 | if (ret) | |
1310 | return ret; | |
1311 | } | |
1312 | return 0; | |
1da177e4 | 1313 | } |
92ac73c1 | 1314 | |
1315 | static char g_options[256] __devinitdata = ""; | |
1316 | ||
1317 | #ifndef CONFIG_MODULES | |
1318 | static int __devinit pxafb_setup_options(void) | |
1319 | { | |
1320 | char *options = NULL; | |
1321 | ||
1322 | if (fb_get_options("pxafb", &options)) | |
1323 | return -ENODEV; | |
1324 | ||
1325 | if (options) | |
1326 | strlcpy(g_options, options, sizeof(g_options)); | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | #else | |
1331 | #define pxafb_setup_options() (0) | |
1332 | ||
1333 | module_param_string(options, g_options, sizeof(g_options), 0); | |
1334 | MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |
1335 | #endif | |
1336 | ||
1337 | #else | |
1338 | #define pxafb_parse_options(...) (0) | |
1339 | #define pxafb_setup_options() (0) | |
1da177e4 LT |
1340 | #endif |
1341 | ||
ac2bf5bd | 1342 | static int __init pxafb_probe(struct platform_device *dev) |
1da177e4 LT |
1343 | { |
1344 | struct pxafb_info *fbi; | |
1345 | struct pxafb_mach_info *inf; | |
1346 | int ret; | |
1347 | ||
2cbbb3b5 | 1348 | dev_dbg(&dev->dev, "pxafb_probe\n"); |
1da177e4 | 1349 | |
3ae5eaec | 1350 | inf = dev->dev.platform_data; |
1da177e4 LT |
1351 | ret = -ENOMEM; |
1352 | fbi = NULL; | |
1353 | if (!inf) | |
1354 | goto failed; | |
1355 | ||
3ae5eaec | 1356 | ret = pxafb_parse_options(&dev->dev, g_options); |
1da177e4 LT |
1357 | if (ret < 0) |
1358 | goto failed; | |
1da177e4 LT |
1359 | |
1360 | #ifdef DEBUG_VAR | |
b0086efb | 1361 | /* Check for various illegal bit-combinations. Currently only |
1da177e4 LT |
1362 | * a warning is given. */ |
1363 | ||
b0086efb | 1364 | if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) |
1365 | dev_warn(&dev->dev, "machine LCCR0 setting contains " | |
1366 | "illegal bits: %08x\n", | |
1367 | inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); | |
1368 | if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) | |
1369 | dev_warn(&dev->dev, "machine LCCR3 setting contains " | |
1370 | "illegal bits: %08x\n", | |
1371 | inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); | |
1372 | if (inf->lccr0 & LCCR0_DPD && | |
1da177e4 LT |
1373 | ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || |
1374 | (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || | |
1375 | (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) | |
b0086efb | 1376 | dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is " |
1377 | "only valid in passive mono" | |
1378 | " single panel mode\n"); | |
1379 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && | |
1da177e4 | 1380 | (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) |
b0086efb | 1381 | dev_warn(&dev->dev, "Dual panel only valid in passive mode\n"); |
1382 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && | |
1383 | (inf->modes->upper_margin || inf->modes->lower_margin)) | |
1384 | dev_warn(&dev->dev, "Upper and lower margins must be 0 in " | |
1385 | "passive mode\n"); | |
1da177e4 LT |
1386 | #endif |
1387 | ||
b0086efb | 1388 | dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", |
1389 | inf->modes->xres, | |
1390 | inf->modes->yres, | |
1391 | inf->modes->bpp); | |
1392 | if (inf->modes->xres == 0 || | |
1393 | inf->modes->yres == 0 || | |
1394 | inf->modes->bpp == 0) { | |
3ae5eaec | 1395 | dev_err(&dev->dev, "Invalid resolution or bit depth\n"); |
1da177e4 LT |
1396 | ret = -EINVAL; |
1397 | goto failed; | |
1398 | } | |
1399 | pxafb_backlight_power = inf->pxafb_backlight_power; | |
1400 | pxafb_lcd_power = inf->pxafb_lcd_power; | |
3ae5eaec | 1401 | fbi = pxafb_init_fbinfo(&dev->dev); |
1da177e4 | 1402 | if (!fbi) { |
b0086efb | 1403 | /* only reason for pxafb_init_fbinfo to fail is kmalloc */ |
3ae5eaec | 1404 | dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); |
b0086efb | 1405 | ret = -ENOMEM; |
1da177e4 LT |
1406 | goto failed; |
1407 | } | |
1408 | ||
1409 | /* Initialize video memory */ | |
1410 | ret = pxafb_map_video_memory(fbi); | |
1411 | if (ret) { | |
3ae5eaec | 1412 | dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); |
1da177e4 LT |
1413 | ret = -ENOMEM; |
1414 | goto failed; | |
1415 | } | |
1da177e4 | 1416 | |
63a43399 | 1417 | ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); |
1da177e4 | 1418 | if (ret) { |
3ae5eaec | 1419 | dev_err(&dev->dev, "request_irq failed: %d\n", ret); |
1da177e4 LT |
1420 | ret = -EBUSY; |
1421 | goto failed; | |
1422 | } | |
1423 | ||
1424 | /* | |
1425 | * This makes sure that our colour bitfield | |
1426 | * descriptors are correctly initialised. | |
1427 | */ | |
1428 | pxafb_check_var(&fbi->fb.var, &fbi->fb); | |
1429 | pxafb_set_par(&fbi->fb); | |
1430 | ||
3ae5eaec | 1431 | platform_set_drvdata(dev, fbi); |
1da177e4 LT |
1432 | |
1433 | ret = register_framebuffer(&fbi->fb); | |
1434 | if (ret < 0) { | |
b0086efb | 1435 | dev_err(&dev->dev, |
1436 | "Failed to register framebuffer device: %d\n", ret); | |
1da177e4 LT |
1437 | goto failed; |
1438 | } | |
1439 | ||
1da177e4 LT |
1440 | #ifdef CONFIG_CPU_FREQ |
1441 | fbi->freq_transition.notifier_call = pxafb_freq_transition; | |
1442 | fbi->freq_policy.notifier_call = pxafb_freq_policy; | |
b0086efb | 1443 | cpufreq_register_notifier(&fbi->freq_transition, |
1444 | CPUFREQ_TRANSITION_NOTIFIER); | |
1445 | cpufreq_register_notifier(&fbi->freq_policy, | |
1446 | CPUFREQ_POLICY_NOTIFIER); | |
1da177e4 LT |
1447 | #endif |
1448 | ||
1449 | /* | |
1450 | * Ok, now enable the LCD controller | |
1451 | */ | |
1452 | set_ctrlr_state(fbi, C_ENABLE); | |
1453 | ||
1454 | return 0; | |
1455 | ||
1456 | failed: | |
3ae5eaec | 1457 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
1458 | kfree(fbi); |
1459 | return ret; | |
1460 | } | |
1461 | ||
3ae5eaec | 1462 | static struct platform_driver pxafb_driver = { |
1da177e4 | 1463 | .probe = pxafb_probe, |
1da177e4 LT |
1464 | .suspend = pxafb_suspend, |
1465 | .resume = pxafb_resume, | |
3ae5eaec RK |
1466 | .driver = { |
1467 | .name = "pxa2xx-fb", | |
1468 | }, | |
1da177e4 LT |
1469 | }; |
1470 | ||
ac2bf5bd | 1471 | static int __devinit pxafb_init(void) |
1da177e4 | 1472 | { |
92ac73c1 | 1473 | if (pxafb_setup_options()) |
1474 | return -EINVAL; | |
1da177e4 | 1475 | |
3ae5eaec | 1476 | return platform_driver_register(&pxafb_driver); |
1da177e4 LT |
1477 | } |
1478 | ||
1479 | module_init(pxafb_init); | |
1480 | ||
1481 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | |
1482 | MODULE_LICENSE("GPL"); |