]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/pxafb.c | |
3 | * | |
4 | * Copyright (C) 1999 Eric A. Thomas. | |
5 | * Copyright (C) 2004 Jean-Frederic Clere. | |
6 | * Copyright (C) 2004 Ian Campbell. | |
7 | * Copyright (C) 2004 Jeff Lackey. | |
8 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas | |
9 | * which in turn is | |
10 | * Based on acornfb.c Copyright (C) Russell King. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | * | |
16 | * Intel PXA250/210 LCD Controller Frame Buffer Driver | |
17 | * | |
18 | * Please direct your questions and comments on this driver to the following | |
19 | * email address: | |
20 | * | |
21 | * linux-arm-kernel@lists.arm.linux.org.uk | |
22 | * | |
23 | */ | |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/slab.h> | |
27ac792c | 33 | #include <linux/mm.h> |
1da177e4 LT |
34 | #include <linux/fb.h> |
35 | #include <linux/delay.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/cpufreq.h> | |
d052d1be | 39 | #include <linux/platform_device.h> |
1da177e4 | 40 | #include <linux/dma-mapping.h> |
72e3524c RK |
41 | #include <linux/clk.h> |
42 | #include <linux/err.h> | |
2ba162b9 | 43 | #include <linux/completion.h> |
b91dbce5 | 44 | #include <linux/mutex.h> |
3c42a449 EM |
45 | #include <linux/kthread.h> |
46 | #include <linux/freezer.h> | |
1da177e4 | 47 | |
a09e64fb | 48 | #include <mach/hardware.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | #include <asm/irq.h> | |
bf1b8ab6 | 51 | #include <asm/div64.h> |
a09e64fb | 52 | #include <mach/pxa-regs.h> |
a09e64fb RK |
53 | #include <mach/bitfield.h> |
54 | #include <mach/pxafb.h> | |
1da177e4 LT |
55 | |
56 | /* | |
57 | * Complain if VAR is out of range. | |
58 | */ | |
59 | #define DEBUG_VAR 1 | |
60 | ||
61 | #include "pxafb.h" | |
62 | ||
63 | /* Bits which should not be set in machine configuration structures */ | |
b0086efb | 64 | #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ |
65 | LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ | |
66 | LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) | |
67 | ||
68 | #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ | |
69 | LCCR3_PCD | LCCR3_BPP) | |
1da177e4 | 70 | |
b0086efb | 71 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
72 | struct pxafb_info *); | |
1da177e4 LT |
73 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); |
74 | ||
a7535ba7 EM |
75 | static inline unsigned long |
76 | lcd_readl(struct pxafb_info *fbi, unsigned int off) | |
77 | { | |
78 | return __raw_readl(fbi->mmio_base + off); | |
79 | } | |
80 | ||
81 | static inline void | |
82 | lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) | |
83 | { | |
84 | __raw_writel(val, fbi->mmio_base + off); | |
85 | } | |
86 | ||
1da177e4 LT |
87 | static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) |
88 | { | |
89 | unsigned long flags; | |
90 | ||
91 | local_irq_save(flags); | |
92 | /* | |
93 | * We need to handle two requests being made at the same time. | |
94 | * There are two important cases: | |
b0086efb | 95 | * 1. When we are changing VT (C_REENABLE) while unblanking |
96 | * (C_ENABLE) We must perform the unblanking, which will | |
97 | * do our REENABLE for us. | |
98 | * 2. When we are blanking, but immediately unblank before | |
99 | * we have blanked. We do the "REENABLE" thing here as | |
100 | * well, just to be sure. | |
1da177e4 LT |
101 | */ |
102 | if (fbi->task_state == C_ENABLE && state == C_REENABLE) | |
103 | state = (u_int) -1; | |
104 | if (fbi->task_state == C_DISABLE && state == C_ENABLE) | |
105 | state = C_REENABLE; | |
106 | ||
107 | if (state != (u_int)-1) { | |
108 | fbi->task_state = state; | |
109 | schedule_work(&fbi->task); | |
110 | } | |
111 | local_irq_restore(flags); | |
112 | } | |
113 | ||
114 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
115 | { | |
116 | chan &= 0xffff; | |
117 | chan >>= 16 - bf->length; | |
118 | return chan << bf->offset; | |
119 | } | |
120 | ||
121 | static int | |
122 | pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, | |
123 | u_int trans, struct fb_info *info) | |
124 | { | |
125 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
9ffa7396 HK |
126 | u_int val; |
127 | ||
128 | if (regno >= fbi->palette_size) | |
129 | return 1; | |
130 | ||
131 | if (fbi->fb.var.grayscale) { | |
132 | fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); | |
133 | return 0; | |
134 | } | |
135 | ||
136 | switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { | |
137 | case LCCR4_PAL_FOR_0: | |
138 | val = ((red >> 0) & 0xf800); | |
139 | val |= ((green >> 5) & 0x07e0); | |
140 | val |= ((blue >> 11) & 0x001f); | |
1da177e4 | 141 | fbi->palette_cpu[regno] = val; |
9ffa7396 HK |
142 | break; |
143 | case LCCR4_PAL_FOR_1: | |
144 | val = ((red << 8) & 0x00f80000); | |
145 | val |= ((green >> 0) & 0x0000fc00); | |
146 | val |= ((blue >> 8) & 0x000000f8); | |
b0086efb | 147 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 HK |
148 | break; |
149 | case LCCR4_PAL_FOR_2: | |
150 | val = ((red << 8) & 0x00fc0000); | |
151 | val |= ((green >> 0) & 0x0000fc00); | |
152 | val |= ((blue >> 8) & 0x000000fc); | |
b0086efb | 153 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 | 154 | break; |
1da177e4 | 155 | } |
9ffa7396 HK |
156 | |
157 | return 0; | |
1da177e4 LT |
158 | } |
159 | ||
160 | static int | |
161 | pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
162 | u_int trans, struct fb_info *info) | |
163 | { | |
164 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
165 | unsigned int val; | |
166 | int ret = 1; | |
167 | ||
168 | /* | |
169 | * If inverse mode was selected, invert all the colours | |
170 | * rather than the register number. The register number | |
171 | * is what you poke into the framebuffer to produce the | |
172 | * colour you requested. | |
173 | */ | |
174 | if (fbi->cmap_inverse) { | |
175 | red = 0xffff - red; | |
176 | green = 0xffff - green; | |
177 | blue = 0xffff - blue; | |
178 | } | |
179 | ||
180 | /* | |
181 | * If greyscale is true, then we convert the RGB value | |
182 | * to greyscale no matter what visual we are using. | |
183 | */ | |
184 | if (fbi->fb.var.grayscale) | |
185 | red = green = blue = (19595 * red + 38470 * green + | |
186 | 7471 * blue) >> 16; | |
187 | ||
188 | switch (fbi->fb.fix.visual) { | |
189 | case FB_VISUAL_TRUECOLOR: | |
190 | /* | |
191 | * 16-bit True Colour. We encode the RGB value | |
192 | * according to the RGB bitfield information. | |
193 | */ | |
194 | if (regno < 16) { | |
195 | u32 *pal = fbi->fb.pseudo_palette; | |
196 | ||
197 | val = chan_to_field(red, &fbi->fb.var.red); | |
198 | val |= chan_to_field(green, &fbi->fb.var.green); | |
199 | val |= chan_to_field(blue, &fbi->fb.var.blue); | |
200 | ||
201 | pal[regno] = val; | |
202 | ret = 0; | |
203 | } | |
204 | break; | |
205 | ||
206 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
207 | case FB_VISUAL_PSEUDOCOLOR: | |
208 | ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); | |
209 | break; | |
210 | } | |
211 | ||
212 | return ret; | |
213 | } | |
214 | ||
215 | /* | |
216 | * pxafb_bpp_to_lccr3(): | |
217 | * Convert a bits per pixel value to the correct bit pattern for LCCR3 | |
218 | */ | |
219 | static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) | |
220 | { | |
b0086efb | 221 | int ret = 0; |
222 | switch (var->bits_per_pixel) { | |
223 | case 1: ret = LCCR3_1BPP; break; | |
224 | case 2: ret = LCCR3_2BPP; break; | |
225 | case 4: ret = LCCR3_4BPP; break; | |
226 | case 8: ret = LCCR3_8BPP; break; | |
227 | case 16: ret = LCCR3_16BPP; break; | |
c1450f15 SS |
228 | case 24: |
229 | switch (var->red.length + var->green.length + | |
230 | var->blue.length + var->transp.length) { | |
231 | case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break; | |
232 | case 19: ret = LCCR3_19BPP_P; break; | |
233 | } | |
234 | break; | |
235 | case 32: | |
236 | switch (var->red.length + var->green.length + | |
237 | var->blue.length + var->transp.length) { | |
238 | case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break; | |
239 | case 19: ret = LCCR3_19BPP; break; | |
240 | case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break; | |
241 | case 25: ret = LCCR3_25BPP; break; | |
242 | } | |
243 | break; | |
b0086efb | 244 | } |
245 | return ret; | |
1da177e4 LT |
246 | } |
247 | ||
248 | #ifdef CONFIG_CPU_FREQ | |
249 | /* | |
250 | * pxafb_display_dma_period() | |
251 | * Calculate the minimum period (in picoseconds) between two DMA | |
252 | * requests for the LCD controller. If we hit this, it means we're | |
253 | * doing nothing but LCD DMA. | |
254 | */ | |
255 | static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) | |
256 | { | |
b0086efb | 257 | /* |
258 | * Period = pixclock * bits_per_byte * bytes_per_transfer | |
259 | * / memory_bits_per_pixel; | |
260 | */ | |
261 | return var->pixclock * 8 * 16 / var->bits_per_pixel; | |
1da177e4 | 262 | } |
1da177e4 LT |
263 | #endif |
264 | ||
d14b272b RP |
265 | /* |
266 | * Select the smallest mode that allows the desired resolution to be | |
267 | * displayed. If desired parameters can be rounded up. | |
268 | */ | |
b0086efb | 269 | static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, |
270 | struct fb_var_screeninfo *var) | |
d14b272b RP |
271 | { |
272 | struct pxafb_mode_info *mode = NULL; | |
273 | struct pxafb_mode_info *modelist = mach->modes; | |
274 | unsigned int best_x = 0xffffffff, best_y = 0xffffffff; | |
275 | unsigned int i; | |
276 | ||
b0086efb | 277 | for (i = 0; i < mach->num_modes; i++) { |
278 | if (modelist[i].xres >= var->xres && | |
279 | modelist[i].yres >= var->yres && | |
280 | modelist[i].xres < best_x && | |
281 | modelist[i].yres < best_y && | |
282 | modelist[i].bpp >= var->bits_per_pixel) { | |
d14b272b RP |
283 | best_x = modelist[i].xres; |
284 | best_y = modelist[i].yres; | |
285 | mode = &modelist[i]; | |
286 | } | |
287 | } | |
288 | ||
289 | return mode; | |
290 | } | |
291 | ||
b0086efb | 292 | static void pxafb_setmode(struct fb_var_screeninfo *var, |
293 | struct pxafb_mode_info *mode) | |
d14b272b RP |
294 | { |
295 | var->xres = mode->xres; | |
296 | var->yres = mode->yres; | |
297 | var->bits_per_pixel = mode->bpp; | |
298 | var->pixclock = mode->pixclock; | |
299 | var->hsync_len = mode->hsync_len; | |
300 | var->left_margin = mode->left_margin; | |
301 | var->right_margin = mode->right_margin; | |
302 | var->vsync_len = mode->vsync_len; | |
303 | var->upper_margin = mode->upper_margin; | |
304 | var->lower_margin = mode->lower_margin; | |
305 | var->sync = mode->sync; | |
306 | var->grayscale = mode->cmap_greyscale; | |
307 | var->xres_virtual = var->xres; | |
308 | var->yres_virtual = var->yres; | |
309 | } | |
310 | ||
1da177e4 LT |
311 | /* |
312 | * pxafb_check_var(): | |
313 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
314 | * if it's too big, return -EINVAL. | |
315 | * | |
316 | * Round up in the following order: bits_per_pixel, xres, | |
317 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
318 | * bitfields, horizontal timing, vertical timing. | |
319 | */ | |
320 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
321 | { | |
322 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
d14b272b | 323 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
1da177e4 LT |
324 | |
325 | if (var->xres < MIN_XRES) | |
326 | var->xres = MIN_XRES; | |
327 | if (var->yres < MIN_YRES) | |
328 | var->yres = MIN_YRES; | |
d14b272b RP |
329 | |
330 | if (inf->fixed_modes) { | |
331 | struct pxafb_mode_info *mode; | |
332 | ||
333 | mode = pxafb_getmode(inf, var); | |
334 | if (!mode) | |
335 | return -EINVAL; | |
336 | pxafb_setmode(var, mode); | |
337 | } else { | |
338 | if (var->xres > inf->modes->xres) | |
339 | return -EINVAL; | |
340 | if (var->yres > inf->modes->yres) | |
341 | return -EINVAL; | |
342 | if (var->bits_per_pixel > inf->modes->bpp) | |
343 | return -EINVAL; | |
344 | } | |
345 | ||
1da177e4 LT |
346 | var->xres_virtual = |
347 | max(var->xres_virtual, var->xres); | |
348 | var->yres_virtual = | |
349 | max(var->yres_virtual, var->yres); | |
350 | ||
b0086efb | 351 | /* |
1da177e4 LT |
352 | * Setup the RGB parameters for this display. |
353 | * | |
354 | * The pixel packing format is described on page 7-11 of the | |
355 | * PXA2XX Developer's Manual. | |
b0086efb | 356 | */ |
1da177e4 LT |
357 | if (var->bits_per_pixel == 16) { |
358 | var->red.offset = 11; var->red.length = 5; | |
359 | var->green.offset = 5; var->green.length = 6; | |
360 | var->blue.offset = 0; var->blue.length = 5; | |
361 | var->transp.offset = var->transp.length = 0; | |
c1450f15 SS |
362 | } else if (var->bits_per_pixel > 16) { |
363 | struct pxafb_mode_info *mode; | |
364 | ||
365 | mode = pxafb_getmode(inf, var); | |
366 | if (!mode) | |
367 | return -EINVAL; | |
368 | ||
369 | switch (mode->depth) { | |
370 | case 18: /* RGB666 */ | |
371 | var->transp.offset = var->transp.length = 0; | |
372 | var->red.offset = 12; var->red.length = 6; | |
373 | var->green.offset = 6; var->green.length = 6; | |
374 | var->blue.offset = 0; var->blue.length = 6; | |
375 | break; | |
376 | case 19: /* RGBT666 */ | |
377 | var->transp.offset = 18; var->transp.length = 1; | |
378 | var->red.offset = 12; var->red.length = 6; | |
379 | var->green.offset = 6; var->green.length = 6; | |
380 | var->blue.offset = 0; var->blue.length = 6; | |
381 | break; | |
382 | case 24: /* RGB888 */ | |
383 | var->transp.offset = var->transp.length = 0; | |
384 | var->red.offset = 16; var->red.length = 8; | |
385 | var->green.offset = 8; var->green.length = 8; | |
386 | var->blue.offset = 0; var->blue.length = 8; | |
387 | break; | |
388 | case 25: /* RGBT888 */ | |
389 | var->transp.offset = 24; var->transp.length = 1; | |
390 | var->red.offset = 16; var->red.length = 8; | |
391 | var->green.offset = 8; var->green.length = 8; | |
392 | var->blue.offset = 0; var->blue.length = 8; | |
393 | break; | |
394 | default: | |
395 | return -EINVAL; | |
396 | } | |
1da177e4 | 397 | } else { |
b0086efb | 398 | var->red.offset = var->green.offset = 0; |
399 | var->blue.offset = var->transp.offset = 0; | |
1da177e4 LT |
400 | var->red.length = 8; |
401 | var->green.length = 8; | |
402 | var->blue.length = 8; | |
403 | var->transp.length = 0; | |
404 | } | |
405 | ||
406 | #ifdef CONFIG_CPU_FREQ | |
78d3cfd3 RK |
407 | pr_debug("pxafb: dma period = %d ps\n", |
408 | pxafb_display_dma_period(var)); | |
1da177e4 LT |
409 | #endif |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static inline void pxafb_set_truecolor(u_int is_true_color) | |
415 | { | |
b0086efb | 416 | /* do your machine-specific setup if needed */ |
1da177e4 LT |
417 | } |
418 | ||
419 | /* | |
420 | * pxafb_set_par(): | |
421 | * Set the user defined part of the display for the specified console | |
422 | */ | |
423 | static int pxafb_set_par(struct fb_info *info) | |
424 | { | |
425 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
426 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 | 427 | |
c1450f15 | 428 | if (var->bits_per_pixel >= 16) |
1da177e4 LT |
429 | fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; |
430 | else if (!fbi->cmap_static) | |
431 | fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
432 | else { | |
433 | /* | |
434 | * Some people have weird ideas about wanting static | |
435 | * pseudocolor maps. I suspect their user space | |
436 | * applications are broken. | |
437 | */ | |
438 | fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
439 | } | |
440 | ||
441 | fbi->fb.fix.line_length = var->xres_virtual * | |
442 | var->bits_per_pixel / 8; | |
c1450f15 | 443 | if (var->bits_per_pixel >= 16) |
1da177e4 LT |
444 | fbi->palette_size = 0; |
445 | else | |
b0086efb | 446 | fbi->palette_size = var->bits_per_pixel == 1 ? |
447 | 4 : 1 << var->bits_per_pixel; | |
1da177e4 | 448 | |
2c42dd8e | 449 | fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; |
1da177e4 LT |
450 | |
451 | /* | |
452 | * Set (any) board control register to handle new color depth | |
453 | */ | |
454 | pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); | |
455 | ||
c1450f15 | 456 | if (fbi->fb.var.bits_per_pixel >= 16) |
1da177e4 LT |
457 | fb_dealloc_cmap(&fbi->fb.cmap); |
458 | else | |
459 | fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); | |
460 | ||
461 | pxafb_activate_var(var, fbi); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
1da177e4 LT |
466 | /* |
467 | * pxafb_blank(): | |
468 | * Blank the display by setting all palette values to zero. Note, the | |
469 | * 16 bpp mode does not really use the palette, so this will not | |
470 | * blank the display in all modes. | |
471 | */ | |
472 | static int pxafb_blank(int blank, struct fb_info *info) | |
473 | { | |
474 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
475 | int i; | |
476 | ||
1da177e4 LT |
477 | switch (blank) { |
478 | case FB_BLANK_POWERDOWN: | |
479 | case FB_BLANK_VSYNC_SUSPEND: | |
480 | case FB_BLANK_HSYNC_SUSPEND: | |
481 | case FB_BLANK_NORMAL: | |
482 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
483 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
484 | for (i = 0; i < fbi->palette_size; i++) | |
485 | pxafb_setpalettereg(i, 0, 0, 0, 0, info); | |
486 | ||
487 | pxafb_schedule_work(fbi, C_DISABLE); | |
b0086efb | 488 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
489 | break; |
490 | ||
491 | case FB_BLANK_UNBLANK: | |
b0086efb | 492 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
493 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || |
494 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
495 | fb_set_cmap(&fbi->fb.cmap, info); | |
496 | pxafb_schedule_work(fbi, C_ENABLE); | |
497 | } | |
498 | return 0; | |
499 | } | |
500 | ||
216d526c | 501 | static int pxafb_mmap(struct fb_info *info, |
1da177e4 LT |
502 | struct vm_area_struct *vma) |
503 | { | |
504 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
505 | unsigned long off = vma->vm_pgoff << PAGE_SHIFT; | |
506 | ||
507 | if (off < info->fix.smem_len) { | |
3c42a449 | 508 | vma->vm_pgoff += fbi->video_offset / PAGE_SIZE; |
1da177e4 LT |
509 | return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, |
510 | fbi->map_dma, fbi->map_size); | |
511 | } | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | static struct fb_ops pxafb_ops = { | |
516 | .owner = THIS_MODULE, | |
517 | .fb_check_var = pxafb_check_var, | |
518 | .fb_set_par = pxafb_set_par, | |
519 | .fb_setcolreg = pxafb_setcolreg, | |
520 | .fb_fillrect = cfb_fillrect, | |
521 | .fb_copyarea = cfb_copyarea, | |
522 | .fb_imageblit = cfb_imageblit, | |
523 | .fb_blank = pxafb_blank, | |
1da177e4 LT |
524 | .fb_mmap = pxafb_mmap, |
525 | }; | |
526 | ||
527 | /* | |
528 | * Calculate the PCD value from the clock rate (in picoseconds). | |
529 | * We take account of the PPCR clock setting. | |
530 | * From PXA Developer's Manual: | |
531 | * | |
532 | * PixelClock = LCLK | |
533 | * ------------- | |
534 | * 2 ( PCD + 1 ) | |
535 | * | |
536 | * PCD = LCLK | |
537 | * ------------- - 1 | |
538 | * 2(PixelClock) | |
539 | * | |
540 | * Where: | |
541 | * LCLK = LCD/Memory Clock | |
542 | * PCD = LCCR3[7:0] | |
543 | * | |
544 | * PixelClock here is in Hz while the pixclock argument given is the | |
545 | * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) | |
546 | * | |
547 | * The function get_lclk_frequency_10khz returns LCLK in units of | |
548 | * 10khz. Calling the result of this function lclk gives us the | |
549 | * following | |
550 | * | |
551 | * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) | |
552 | * -------------------------------------- - 1 | |
553 | * 2 | |
554 | * | |
555 | * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. | |
556 | */ | |
b0086efb | 557 | static inline unsigned int get_pcd(struct pxafb_info *fbi, |
558 | unsigned int pixclock) | |
1da177e4 LT |
559 | { |
560 | unsigned long long pcd; | |
561 | ||
562 | /* FIXME: Need to take into account Double Pixel Clock mode | |
72e3524c RK |
563 | * (DPC) bit? or perhaps set it based on the various clock |
564 | * speeds */ | |
565 | pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); | |
566 | pcd *= pixclock; | |
bf1b8ab6 | 567 | do_div(pcd, 100000000 * 2); |
1da177e4 LT |
568 | /* no need for this, since we should subtract 1 anyway. they cancel */ |
569 | /* pcd += 1; */ /* make up for integer math truncations */ | |
570 | return (unsigned int)pcd; | |
571 | } | |
572 | ||
ba44cd2d RP |
573 | /* |
574 | * Some touchscreens need hsync information from the video driver to | |
72e3524c RK |
575 | * function correctly. We export it here. Note that 'hsync_time' and |
576 | * the value returned from pxafb_get_hsync_time() is the *reciprocal* | |
577 | * of the hsync period in seconds. | |
ba44cd2d RP |
578 | */ |
579 | static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) | |
580 | { | |
72e3524c | 581 | unsigned long htime; |
ba44cd2d RP |
582 | |
583 | if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { | |
b0086efb | 584 | fbi->hsync_time = 0; |
ba44cd2d RP |
585 | return; |
586 | } | |
587 | ||
72e3524c RK |
588 | htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); |
589 | ||
ba44cd2d RP |
590 | fbi->hsync_time = htime; |
591 | } | |
592 | ||
593 | unsigned long pxafb_get_hsync_time(struct device *dev) | |
594 | { | |
595 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
596 | ||
597 | /* If display is blanked/suspended, hsync isn't active */ | |
598 | if (!fbi || (fbi->state != C_ENABLE)) | |
599 | return 0; | |
600 | ||
601 | return fbi->hsync_time; | |
602 | } | |
603 | EXPORT_SYMBOL(pxafb_get_hsync_time); | |
604 | ||
2c42dd8e | 605 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, |
606 | unsigned int offset, size_t size) | |
607 | { | |
608 | struct pxafb_dma_descriptor *dma_desc, *pal_desc; | |
609 | unsigned int dma_desc_off, pal_desc_off; | |
610 | ||
611 | if (dma < 0 || dma >= DMA_MAX) | |
612 | return -EINVAL; | |
613 | ||
614 | dma_desc = &fbi->dma_buff->dma_desc[dma]; | |
615 | dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); | |
616 | ||
617 | dma_desc->fsadr = fbi->screen_dma + offset; | |
618 | dma_desc->fidr = 0; | |
619 | dma_desc->ldcmd = size; | |
620 | ||
621 | if (pal < 0 || pal >= PAL_MAX) { | |
622 | dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
623 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
624 | } else { | |
62cfcf4f JS |
625 | pal_desc = &fbi->dma_buff->pal_desc[pal]; |
626 | pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); | |
2c42dd8e | 627 | |
628 | pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; | |
629 | pal_desc->fidr = 0; | |
630 | ||
631 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) | |
632 | pal_desc->ldcmd = fbi->palette_size * sizeof(u16); | |
633 | else | |
634 | pal_desc->ldcmd = fbi->palette_size * sizeof(u32); | |
635 | ||
636 | pal_desc->ldcmd |= LDCMD_PAL; | |
637 | ||
638 | /* flip back and forth between palette and frame buffer */ | |
639 | pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
640 | dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; | |
641 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
642 | } | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
3c42a449 EM |
647 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
648 | static int setup_smart_dma(struct pxafb_info *fbi) | |
649 | { | |
650 | struct pxafb_dma_descriptor *dma_desc; | |
651 | unsigned long dma_desc_off, cmd_buff_off; | |
652 | ||
653 | dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD]; | |
654 | dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]); | |
655 | cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff); | |
656 | ||
657 | dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
658 | dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off; | |
659 | dma_desc->fidr = 0; | |
660 | dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t); | |
661 | ||
662 | fbi->fdadr[DMA_CMD] = dma_desc->fdadr; | |
663 | return 0; | |
664 | } | |
665 | ||
666 | int pxafb_smart_flush(struct fb_info *info) | |
667 | { | |
668 | struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); | |
669 | uint32_t prsr; | |
670 | int ret = 0; | |
671 | ||
672 | /* disable controller until all registers are set up */ | |
673 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
674 | ||
675 | /* 1. make it an even number of commands to align on 32-bit boundary | |
676 | * 2. add the interrupt command to the end of the chain so we can | |
677 | * keep track of the end of the transfer | |
678 | */ | |
679 | ||
680 | while (fbi->n_smart_cmds & 1) | |
681 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP; | |
682 | ||
683 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT; | |
684 | fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC; | |
685 | setup_smart_dma(fbi); | |
686 | ||
687 | /* continue to execute next command */ | |
688 | prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT; | |
689 | lcd_writel(fbi, PRSR, prsr); | |
690 | ||
691 | /* stop the processor in case it executed "wait for sync" cmd */ | |
692 | lcd_writel(fbi, CMDCR, 0x0001); | |
693 | ||
694 | /* don't send interrupts for fifo underruns on channel 6 */ | |
695 | lcd_writel(fbi, LCCR5, LCCR5_IUM(6)); | |
696 | ||
697 | lcd_writel(fbi, LCCR1, fbi->reg_lccr1); | |
698 | lcd_writel(fbi, LCCR2, fbi->reg_lccr2); | |
699 | lcd_writel(fbi, LCCR3, fbi->reg_lccr3); | |
700 | lcd_writel(fbi, FDADR0, fbi->fdadr[0]); | |
701 | lcd_writel(fbi, FDADR6, fbi->fdadr[6]); | |
702 | ||
703 | /* begin sending */ | |
704 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); | |
705 | ||
706 | if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) { | |
707 | pr_warning("%s: timeout waiting for command done\n", | |
708 | __func__); | |
709 | ret = -ETIMEDOUT; | |
710 | } | |
711 | ||
712 | /* quick disable */ | |
713 | prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT); | |
714 | lcd_writel(fbi, PRSR, prsr); | |
715 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
716 | lcd_writel(fbi, FDADR6, 0); | |
717 | fbi->n_smart_cmds = 0; | |
718 | return ret; | |
719 | } | |
720 | ||
721 | int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) | |
722 | { | |
723 | int i; | |
724 | struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); | |
725 | ||
726 | /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ | |
727 | for (i = 0; i < n_cmds; i++) { | |
728 | if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) | |
729 | pxafb_smart_flush(info); | |
730 | ||
731 | fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++; | |
732 | } | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
737 | static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) | |
738 | { | |
739 | unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000); | |
740 | return (t == 0) ? 1 : t; | |
741 | } | |
742 | ||
743 | static void setup_smart_timing(struct pxafb_info *fbi, | |
744 | struct fb_var_screeninfo *var) | |
745 | { | |
746 | struct pxafb_mach_info *inf = fbi->dev->platform_data; | |
747 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
748 | unsigned long lclk = clk_get_rate(fbi->clk); | |
749 | unsigned t1, t2, t3, t4; | |
750 | ||
751 | t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld); | |
752 | t2 = max(mode->rd_pulse_width, mode->wr_pulse_width); | |
753 | t3 = mode->op_hold_time; | |
754 | t4 = mode->cmd_inh_time; | |
755 | ||
756 | fbi->reg_lccr1 = | |
757 | LCCR1_DisWdth(var->xres) | | |
758 | LCCR1_BegLnDel(__smart_timing(t1, lclk)) | | |
759 | LCCR1_EndLnDel(__smart_timing(t2, lclk)) | | |
760 | LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); | |
761 | ||
762 | fbi->reg_lccr2 = LCCR2_DisHght(var->yres); | |
c1f99c21 EM |
763 | fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); |
764 | fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; | |
765 | fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; | |
3c42a449 EM |
766 | |
767 | /* FIXME: make this configurable */ | |
768 | fbi->reg_cmdcr = 1; | |
769 | } | |
770 | ||
771 | static int pxafb_smart_thread(void *arg) | |
772 | { | |
7f1133cb | 773 | struct pxafb_info *fbi = arg; |
3c42a449 EM |
774 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
775 | ||
776 | if (!fbi || !inf->smart_update) { | |
777 | pr_err("%s: not properly initialized, thread terminated\n", | |
778 | __func__); | |
779 | return -EINVAL; | |
780 | } | |
781 | ||
782 | pr_debug("%s(): task starting\n", __func__); | |
783 | ||
784 | set_freezable(); | |
785 | while (!kthread_should_stop()) { | |
786 | ||
787 | if (try_to_freeze()) | |
788 | continue; | |
789 | ||
790 | if (fbi->state == C_ENABLE) { | |
791 | inf->smart_update(&fbi->fb); | |
792 | complete(&fbi->refresh_done); | |
793 | } | |
794 | ||
795 | set_current_state(TASK_INTERRUPTIBLE); | |
796 | schedule_timeout(30 * HZ / 1000); | |
797 | } | |
798 | ||
799 | pr_debug("%s(): task ending\n", __func__); | |
800 | return 0; | |
801 | } | |
802 | ||
803 | static int pxafb_smart_init(struct pxafb_info *fbi) | |
804 | { | |
07df1c4f | 805 | if (!(fbi->lccr0 & LCCR0_LCDT)) |
6cc4abe4 EM |
806 | return 0; |
807 | ||
07df1c4f EM |
808 | fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; |
809 | fbi->n_smart_cmds = 0; | |
810 | ||
811 | init_completion(&fbi->command_done); | |
812 | init_completion(&fbi->refresh_done); | |
813 | ||
3c42a449 EM |
814 | fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, |
815 | "lcd_refresh"); | |
816 | if (IS_ERR(fbi->smart_thread)) { | |
07df1c4f | 817 | pr_err("%s: unable to create kernel thread\n", __func__); |
3c42a449 EM |
818 | return PTR_ERR(fbi->smart_thread); |
819 | } | |
a5718a14 | 820 | |
3c42a449 EM |
821 | return 0; |
822 | } | |
823 | #else | |
824 | int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) | |
825 | { | |
826 | return 0; | |
827 | } | |
828 | ||
829 | int pxafb_smart_flush(struct fb_info *info) | |
830 | { | |
831 | return 0; | |
832 | } | |
07df1c4f EM |
833 | |
834 | static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } | |
835 | #endif /* CONFIG_FB_PXA_SMARTPANEL */ | |
3c42a449 | 836 | |
90eabbf0 EM |
837 | static void setup_parallel_timing(struct pxafb_info *fbi, |
838 | struct fb_var_screeninfo *var) | |
839 | { | |
840 | unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); | |
841 | ||
842 | fbi->reg_lccr1 = | |
843 | LCCR1_DisWdth(var->xres) + | |
844 | LCCR1_HorSnchWdth(var->hsync_len) + | |
845 | LCCR1_BegLnDel(var->left_margin) + | |
846 | LCCR1_EndLnDel(var->right_margin); | |
847 | ||
848 | /* | |
849 | * If we have a dual scan LCD, we need to halve | |
850 | * the YRES parameter. | |
851 | */ | |
852 | lines_per_panel = var->yres; | |
853 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
854 | lines_per_panel /= 2; | |
855 | ||
856 | fbi->reg_lccr2 = | |
857 | LCCR2_DisHght(lines_per_panel) + | |
858 | LCCR2_VrtSnchWdth(var->vsync_len) + | |
859 | LCCR2_BegFrmDel(var->upper_margin) + | |
860 | LCCR2_EndFrmDel(var->lower_margin); | |
861 | ||
862 | fbi->reg_lccr3 = fbi->lccr3 | | |
863 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? | |
864 | LCCR3_HorSnchH : LCCR3_HorSnchL) | | |
865 | (var->sync & FB_SYNC_VERT_HIGH_ACT ? | |
866 | LCCR3_VrtSnchH : LCCR3_VrtSnchL); | |
867 | ||
868 | if (pcd) { | |
869 | fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd); | |
870 | set_hsync_time(fbi, pcd); | |
871 | } | |
872 | } | |
873 | ||
1da177e4 LT |
874 | /* |
875 | * pxafb_activate_var(): | |
b0086efb | 876 | * Configures LCD Controller based on entries in var parameter. |
877 | * Settings are only written to the controller if changes were made. | |
1da177e4 | 878 | */ |
b0086efb | 879 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
880 | struct pxafb_info *fbi) | |
1da177e4 | 881 | { |
1da177e4 | 882 | u_long flags; |
2c42dd8e | 883 | size_t nbytes; |
1da177e4 | 884 | |
1da177e4 | 885 | #if DEBUG_VAR |
3c42a449 EM |
886 | if (!(fbi->lccr0 & LCCR0_LCDT)) { |
887 | if (var->xres < 16 || var->xres > 1024) | |
888 | printk(KERN_ERR "%s: invalid xres %d\n", | |
889 | fbi->fb.fix.id, var->xres); | |
890 | switch (var->bits_per_pixel) { | |
891 | case 1: | |
892 | case 2: | |
893 | case 4: | |
894 | case 8: | |
895 | case 16: | |
c1450f15 SS |
896 | case 24: |
897 | case 32: | |
3c42a449 EM |
898 | break; |
899 | default: | |
900 | printk(KERN_ERR "%s: invalid bit depth %d\n", | |
901 | fbi->fb.fix.id, var->bits_per_pixel); | |
902 | break; | |
903 | } | |
904 | ||
905 | if (var->hsync_len < 1 || var->hsync_len > 64) | |
906 | printk(KERN_ERR "%s: invalid hsync_len %d\n", | |
907 | fbi->fb.fix.id, var->hsync_len); | |
908 | if (var->left_margin < 1 || var->left_margin > 255) | |
909 | printk(KERN_ERR "%s: invalid left_margin %d\n", | |
910 | fbi->fb.fix.id, var->left_margin); | |
911 | if (var->right_margin < 1 || var->right_margin > 255) | |
912 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
913 | fbi->fb.fix.id, var->right_margin); | |
914 | if (var->yres < 1 || var->yres > 1024) | |
915 | printk(KERN_ERR "%s: invalid yres %d\n", | |
916 | fbi->fb.fix.id, var->yres); | |
917 | if (var->vsync_len < 1 || var->vsync_len > 64) | |
918 | printk(KERN_ERR "%s: invalid vsync_len %d\n", | |
919 | fbi->fb.fix.id, var->vsync_len); | |
920 | if (var->upper_margin < 0 || var->upper_margin > 255) | |
921 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
922 | fbi->fb.fix.id, var->upper_margin); | |
923 | if (var->lower_margin < 0 || var->lower_margin > 255) | |
924 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
925 | fbi->fb.fix.id, var->lower_margin); | |
1da177e4 | 926 | } |
1da177e4 | 927 | #endif |
90eabbf0 EM |
928 | /* Update shadow copy atomically */ |
929 | local_irq_save(flags); | |
1da177e4 | 930 | |
3c42a449 EM |
931 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
932 | if (fbi->lccr0 & LCCR0_LCDT) | |
933 | setup_smart_timing(fbi, var); | |
934 | else | |
935 | #endif | |
936 | setup_parallel_timing(fbi, var); | |
90eabbf0 EM |
937 | |
938 | fbi->reg_lccr0 = fbi->lccr0 | | |
1da177e4 | 939 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | |
b0086efb | 940 | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); |
1da177e4 | 941 | |
90eabbf0 | 942 | fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var); |
1da177e4 | 943 | |
90eabbf0 | 944 | nbytes = var->yres * fbi->fb.fix.line_length; |
1da177e4 | 945 | |
90eabbf0 EM |
946 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) { |
947 | nbytes = nbytes / 2; | |
2c42dd8e | 948 | setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes); |
90eabbf0 | 949 | } |
2c42dd8e | 950 | |
3c42a449 | 951 | if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT)) |
2c42dd8e | 952 | setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes); |
953 | else | |
954 | setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes); | |
1da177e4 | 955 | |
a7535ba7 | 956 | fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; |
9ffa7396 | 957 | fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); |
1da177e4 LT |
958 | local_irq_restore(flags); |
959 | ||
960 | /* | |
961 | * Only update the registers if the controller is enabled | |
962 | * and something has changed. | |
963 | */ | |
a7535ba7 EM |
964 | if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || |
965 | (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || | |
966 | (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || | |
967 | (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || | |
968 | (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || | |
969 | (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) | |
1da177e4 LT |
970 | pxafb_schedule_work(fbi, C_REENABLE); |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
975 | /* | |
976 | * NOTE! The following functions are purely helpers for set_ctrlr_state. | |
977 | * Do not call them directly; set_ctrlr_state does the correct serialisation | |
978 | * to ensure that things happen in the right way 100% of time time. | |
979 | * -- rmk | |
980 | */ | |
981 | static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) | |
982 | { | |
ca5da710 | 983 | pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); |
1da177e4 | 984 | |
a5718a14 EM |
985 | if (fbi->backlight_power) |
986 | fbi->backlight_power(on); | |
1da177e4 LT |
987 | } |
988 | ||
989 | static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) | |
990 | { | |
ca5da710 | 991 | pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); |
1da177e4 | 992 | |
a5718a14 EM |
993 | if (fbi->lcd_power) |
994 | fbi->lcd_power(on, &fbi->fb.var); | |
1da177e4 LT |
995 | } |
996 | ||
1da177e4 LT |
997 | static void pxafb_enable_controller(struct pxafb_info *fbi) |
998 | { | |
ca5da710 | 999 | pr_debug("pxafb: Enabling LCD controller\n"); |
2c42dd8e | 1000 | pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); |
1001 | pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); | |
ca5da710 RK |
1002 | pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); |
1003 | pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); | |
1004 | pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); | |
1005 | pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); | |
1da177e4 | 1006 | |
8d372266 | 1007 | /* enable LCD controller clock */ |
72e3524c | 1008 | clk_enable(fbi->clk); |
8d372266 | 1009 | |
3c42a449 EM |
1010 | if (fbi->lccr0 & LCCR0_LCDT) |
1011 | return; | |
1012 | ||
1da177e4 | 1013 | /* Sequence from 11.7.10 */ |
a7535ba7 EM |
1014 | lcd_writel(fbi, LCCR3, fbi->reg_lccr3); |
1015 | lcd_writel(fbi, LCCR2, fbi->reg_lccr2); | |
1016 | lcd_writel(fbi, LCCR1, fbi->reg_lccr1); | |
1017 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
1018 | ||
1019 | lcd_writel(fbi, FDADR0, fbi->fdadr[0]); | |
1020 | lcd_writel(fbi, FDADR1, fbi->fdadr[1]); | |
1021 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); | |
1da177e4 LT |
1022 | } |
1023 | ||
1024 | static void pxafb_disable_controller(struct pxafb_info *fbi) | |
1025 | { | |
ce4fb7b8 | 1026 | uint32_t lccr0; |
1027 | ||
3c42a449 EM |
1028 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1029 | if (fbi->lccr0 & LCCR0_LCDT) { | |
1030 | wait_for_completion_timeout(&fbi->refresh_done, | |
1031 | 200 * HZ / 1000); | |
1032 | return; | |
1033 | } | |
1034 | #endif | |
1035 | ||
ce4fb7b8 | 1036 | /* Clear LCD Status Register */ |
a7535ba7 | 1037 | lcd_writel(fbi, LCSR, 0xffffffff); |
ce4fb7b8 | 1038 | |
a7535ba7 EM |
1039 | lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; |
1040 | lcd_writel(fbi, LCCR0, lccr0); | |
1041 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); | |
1da177e4 | 1042 | |
2ba162b9 | 1043 | wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000); |
8d372266 NP |
1044 | |
1045 | /* disable LCD controller clock */ | |
72e3524c | 1046 | clk_disable(fbi->clk); |
1da177e4 LT |
1047 | } |
1048 | ||
1049 | /* | |
1050 | * pxafb_handle_irq: Handle 'LCD DONE' interrupts. | |
1051 | */ | |
7d12e780 | 1052 | static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) |
1da177e4 LT |
1053 | { |
1054 | struct pxafb_info *fbi = dev_id; | |
a7535ba7 | 1055 | unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR); |
1da177e4 LT |
1056 | |
1057 | if (lcsr & LCSR_LDD) { | |
a7535ba7 EM |
1058 | lccr0 = lcd_readl(fbi, LCCR0); |
1059 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); | |
2ba162b9 | 1060 | complete(&fbi->disable_done); |
1da177e4 LT |
1061 | } |
1062 | ||
3c42a449 EM |
1063 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
1064 | if (lcsr & LCSR_CMD_INT) | |
1065 | complete(&fbi->command_done); | |
1066 | #endif | |
1067 | ||
a7535ba7 | 1068 | lcd_writel(fbi, LCSR, lcsr); |
1da177e4 LT |
1069 | return IRQ_HANDLED; |
1070 | } | |
1071 | ||
1072 | /* | |
1073 | * This function must be called from task context only, since it will | |
1074 | * sleep when disabling the LCD controller, or if we get two contending | |
1075 | * processes trying to alter state. | |
1076 | */ | |
1077 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) | |
1078 | { | |
1079 | u_int old_state; | |
1080 | ||
b91dbce5 | 1081 | mutex_lock(&fbi->ctrlr_lock); |
1da177e4 LT |
1082 | |
1083 | old_state = fbi->state; | |
1084 | ||
1085 | /* | |
1086 | * Hack around fbcon initialisation. | |
1087 | */ | |
1088 | if (old_state == C_STARTUP && state == C_REENABLE) | |
1089 | state = C_ENABLE; | |
1090 | ||
1091 | switch (state) { | |
1092 | case C_DISABLE_CLKCHANGE: | |
1093 | /* | |
1094 | * Disable controller for clock change. If the | |
1095 | * controller is already disabled, then do nothing. | |
1096 | */ | |
1097 | if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { | |
1098 | fbi->state = state; | |
b0086efb | 1099 | /* TODO __pxafb_lcd_power(fbi, 0); */ |
1da177e4 LT |
1100 | pxafb_disable_controller(fbi); |
1101 | } | |
1102 | break; | |
1103 | ||
1104 | case C_DISABLE_PM: | |
1105 | case C_DISABLE: | |
1106 | /* | |
1107 | * Disable controller | |
1108 | */ | |
1109 | if (old_state != C_DISABLE) { | |
1110 | fbi->state = state; | |
1111 | __pxafb_backlight_power(fbi, 0); | |
1112 | __pxafb_lcd_power(fbi, 0); | |
1113 | if (old_state != C_DISABLE_CLKCHANGE) | |
1114 | pxafb_disable_controller(fbi); | |
1115 | } | |
1116 | break; | |
1117 | ||
1118 | case C_ENABLE_CLKCHANGE: | |
1119 | /* | |
1120 | * Enable the controller after clock change. Only | |
1121 | * do this if we were disabled for the clock change. | |
1122 | */ | |
1123 | if (old_state == C_DISABLE_CLKCHANGE) { | |
1124 | fbi->state = C_ENABLE; | |
1125 | pxafb_enable_controller(fbi); | |
b0086efb | 1126 | /* TODO __pxafb_lcd_power(fbi, 1); */ |
1da177e4 LT |
1127 | } |
1128 | break; | |
1129 | ||
1130 | case C_REENABLE: | |
1131 | /* | |
1132 | * Re-enable the controller only if it was already | |
1133 | * enabled. This is so we reprogram the control | |
1134 | * registers. | |
1135 | */ | |
1136 | if (old_state == C_ENABLE) { | |
d14b272b | 1137 | __pxafb_lcd_power(fbi, 0); |
1da177e4 | 1138 | pxafb_disable_controller(fbi); |
1da177e4 | 1139 | pxafb_enable_controller(fbi); |
d14b272b | 1140 | __pxafb_lcd_power(fbi, 1); |
1da177e4 LT |
1141 | } |
1142 | break; | |
1143 | ||
1144 | case C_ENABLE_PM: | |
1145 | /* | |
1146 | * Re-enable the controller after PM. This is not | |
1147 | * perfect - think about the case where we were doing | |
1148 | * a clock change, and we suspended half-way through. | |
1149 | */ | |
1150 | if (old_state != C_DISABLE_PM) | |
1151 | break; | |
1152 | /* fall through */ | |
1153 | ||
1154 | case C_ENABLE: | |
1155 | /* | |
1156 | * Power up the LCD screen, enable controller, and | |
1157 | * turn on the backlight. | |
1158 | */ | |
1159 | if (old_state != C_ENABLE) { | |
1160 | fbi->state = C_ENABLE; | |
1da177e4 LT |
1161 | pxafb_enable_controller(fbi); |
1162 | __pxafb_lcd_power(fbi, 1); | |
1163 | __pxafb_backlight_power(fbi, 1); | |
1164 | } | |
1165 | break; | |
1166 | } | |
b91dbce5 | 1167 | mutex_unlock(&fbi->ctrlr_lock); |
1da177e4 LT |
1168 | } |
1169 | ||
1170 | /* | |
1171 | * Our LCD controller task (which is called when we blank or unblank) | |
1172 | * via keventd. | |
1173 | */ | |
6d5aefb8 | 1174 | static void pxafb_task(struct work_struct *work) |
1da177e4 | 1175 | { |
6d5aefb8 DH |
1176 | struct pxafb_info *fbi = |
1177 | container_of(work, struct pxafb_info, task); | |
1da177e4 LT |
1178 | u_int state = xchg(&fbi->task_state, -1); |
1179 | ||
1180 | set_ctrlr_state(fbi, state); | |
1181 | } | |
1182 | ||
1183 | #ifdef CONFIG_CPU_FREQ | |
1184 | /* | |
1185 | * CPU clock speed change handler. We need to adjust the LCD timing | |
1186 | * parameters when the CPU clock is adjusted by the power management | |
1187 | * subsystem. | |
1188 | * | |
1189 | * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() | |
1190 | */ | |
1191 | static int | |
1192 | pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) | |
1193 | { | |
1194 | struct pxafb_info *fbi = TO_INF(nb, freq_transition); | |
b0086efb | 1195 | /* TODO struct cpufreq_freqs *f = data; */ |
1da177e4 LT |
1196 | u_int pcd; |
1197 | ||
1198 | switch (val) { | |
1199 | case CPUFREQ_PRECHANGE: | |
1200 | set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); | |
1201 | break; | |
1202 | ||
1203 | case CPUFREQ_POSTCHANGE: | |
72e3524c | 1204 | pcd = get_pcd(fbi, fbi->fb.var.pixclock); |
ba44cd2d | 1205 | set_hsync_time(fbi, pcd); |
b0086efb | 1206 | fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | |
1207 | LCCR3_PixClkDiv(pcd); | |
1da177e4 LT |
1208 | set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); |
1209 | break; | |
1210 | } | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int | |
1215 | pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) | |
1216 | { | |
1217 | struct pxafb_info *fbi = TO_INF(nb, freq_policy); | |
1218 | struct fb_var_screeninfo *var = &fbi->fb.var; | |
1219 | struct cpufreq_policy *policy = data; | |
1220 | ||
1221 | switch (val) { | |
1222 | case CPUFREQ_ADJUST: | |
1223 | case CPUFREQ_INCOMPATIBLE: | |
ac2bf5bd | 1224 | pr_debug("min dma period: %d ps, " |
1da177e4 LT |
1225 | "new clock %d kHz\n", pxafb_display_dma_period(var), |
1226 | policy->max); | |
b0086efb | 1227 | /* TODO: fill in min/max values */ |
1da177e4 | 1228 | break; |
1da177e4 LT |
1229 | } |
1230 | return 0; | |
1231 | } | |
1232 | #endif | |
1233 | ||
1234 | #ifdef CONFIG_PM | |
1235 | /* | |
1236 | * Power management hooks. Note that we won't be called from IRQ context, | |
1237 | * unlike the blank functions above, so we may sleep. | |
1238 | */ | |
3ae5eaec | 1239 | static int pxafb_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1240 | { |
3ae5eaec | 1241 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1242 | |
9480e307 | 1243 | set_ctrlr_state(fbi, C_DISABLE_PM); |
1da177e4 LT |
1244 | return 0; |
1245 | } | |
1246 | ||
3ae5eaec | 1247 | static int pxafb_resume(struct platform_device *dev) |
1da177e4 | 1248 | { |
3ae5eaec | 1249 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1250 | |
9480e307 | 1251 | set_ctrlr_state(fbi, C_ENABLE_PM); |
1da177e4 LT |
1252 | return 0; |
1253 | } | |
1254 | #else | |
1255 | #define pxafb_suspend NULL | |
1256 | #define pxafb_resume NULL | |
1257 | #endif | |
1258 | ||
1259 | /* | |
1260 | * pxafb_map_video_memory(): | |
1261 | * Allocates the DRAM memory for the frame buffer. This buffer is | |
1262 | * remapped into a non-cached, non-buffered, memory region to | |
1263 | * allow palette and pixel writes to occur without flushing the | |
1264 | * cache. Once this area is remapped, all virtual memory | |
1265 | * access to the video memory should occur at the new region. | |
1266 | */ | |
9e6c2976 | 1267 | static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi) |
1da177e4 | 1268 | { |
1da177e4 LT |
1269 | /* |
1270 | * We reserve one page for the palette, plus the size | |
1271 | * of the framebuffer. | |
1272 | */ | |
3c42a449 EM |
1273 | fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); |
1274 | fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset); | |
1da177e4 LT |
1275 | fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, |
1276 | &fbi->map_dma, GFP_KERNEL); | |
1277 | ||
1278 | if (fbi->map_cpu) { | |
1279 | /* prevent initial garbage on screen */ | |
1280 | memset(fbi->map_cpu, 0, fbi->map_size); | |
3c42a449 EM |
1281 | fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset; |
1282 | fbi->screen_dma = fbi->map_dma + fbi->video_offset; | |
1283 | ||
1da177e4 LT |
1284 | /* |
1285 | * FIXME: this is actually the wrong thing to place in | |
1286 | * smem_start. But fbdev suffers from the problem that | |
1287 | * it needs an API which doesn't exist (in this case, | |
1288 | * dma_writecombine_mmap) | |
1289 | */ | |
1290 | fbi->fb.fix.smem_start = fbi->screen_dma; | |
1da177e4 LT |
1291 | fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; |
1292 | ||
3c42a449 | 1293 | fbi->dma_buff = (void *) fbi->map_cpu; |
2c42dd8e | 1294 | fbi->dma_buff_phys = fbi->map_dma; |
3c42a449 EM |
1295 | fbi->palette_cpu = (u16 *) fbi->dma_buff->palette; |
1296 | ||
e84e954a | 1297 | pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16)); |
1da177e4 LT |
1298 | } |
1299 | ||
1300 | return fbi->map_cpu ? 0 : -ENOMEM; | |
1301 | } | |
1302 | ||
84f43c30 | 1303 | static void pxafb_decode_mode_info(struct pxafb_info *fbi, |
1304 | struct pxafb_mode_info *modes, | |
1305 | unsigned int num_modes) | |
1306 | { | |
1307 | unsigned int i, smemlen; | |
1308 | ||
1309 | pxafb_setmode(&fbi->fb.var, &modes[0]); | |
1310 | ||
1311 | for (i = 0; i < num_modes; i++) { | |
1312 | smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8; | |
1313 | if (smemlen > fbi->fb.fix.smem_len) | |
1314 | fbi->fb.fix.smem_len = smemlen; | |
1315 | } | |
1316 | } | |
1317 | ||
ebdf982a GL |
1318 | static void pxafb_decode_mach_info(struct pxafb_info *fbi, |
1319 | struct pxafb_mach_info *inf) | |
84f43c30 | 1320 | { |
1321 | unsigned int lcd_conn = inf->lcd_conn; | |
1322 | ||
1323 | fbi->cmap_inverse = inf->cmap_inverse; | |
1324 | fbi->cmap_static = inf->cmap_static; | |
1325 | ||
1ec26db1 | 1326 | switch (lcd_conn & LCD_TYPE_MASK) { |
84f43c30 | 1327 | case LCD_TYPE_MONO_STN: |
1328 | fbi->lccr0 = LCCR0_CMS; | |
1329 | break; | |
1330 | case LCD_TYPE_MONO_DSTN: | |
1331 | fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; | |
1332 | break; | |
1333 | case LCD_TYPE_COLOR_STN: | |
1334 | fbi->lccr0 = 0; | |
1335 | break; | |
1336 | case LCD_TYPE_COLOR_DSTN: | |
1337 | fbi->lccr0 = LCCR0_SDS; | |
1338 | break; | |
1339 | case LCD_TYPE_COLOR_TFT: | |
1340 | fbi->lccr0 = LCCR0_PAS; | |
1341 | break; | |
1342 | case LCD_TYPE_SMART_PANEL: | |
1343 | fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; | |
1344 | break; | |
1345 | default: | |
1346 | /* fall back to backward compatibility way */ | |
1347 | fbi->lccr0 = inf->lccr0; | |
1348 | fbi->lccr3 = inf->lccr3; | |
1349 | fbi->lccr4 = inf->lccr4; | |
ebdf982a | 1350 | goto decode_mode; |
84f43c30 | 1351 | } |
1352 | ||
1353 | if (lcd_conn == LCD_MONO_STN_8BPP) | |
1354 | fbi->lccr0 |= LCCR0_DPD; | |
1355 | ||
9a1ac7e4 EM |
1356 | fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0; |
1357 | ||
84f43c30 | 1358 | fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); |
1359 | fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; | |
1360 | fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; | |
1361 | ||
ebdf982a | 1362 | decode_mode: |
84f43c30 | 1363 | pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); |
84f43c30 | 1364 | } |
1365 | ||
9e6c2976 | 1366 | static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) |
1da177e4 LT |
1367 | { |
1368 | struct pxafb_info *fbi; | |
1369 | void *addr; | |
1370 | struct pxafb_mach_info *inf = dev->platform_data; | |
1371 | ||
1372 | /* Alloc the pxafb_info and pseudo_palette in one step */ | |
1373 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | |
1374 | if (!fbi) | |
1375 | return NULL; | |
1376 | ||
1377 | memset(fbi, 0, sizeof(struct pxafb_info)); | |
1378 | fbi->dev = dev; | |
1379 | ||
72e3524c RK |
1380 | fbi->clk = clk_get(dev, "LCDCLK"); |
1381 | if (IS_ERR(fbi->clk)) { | |
1382 | kfree(fbi); | |
1383 | return NULL; | |
1384 | } | |
1385 | ||
1da177e4 LT |
1386 | strcpy(fbi->fb.fix.id, PXA_NAME); |
1387 | ||
1388 | fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1389 | fbi->fb.fix.type_aux = 0; | |
1390 | fbi->fb.fix.xpanstep = 0; | |
1391 | fbi->fb.fix.ypanstep = 0; | |
1392 | fbi->fb.fix.ywrapstep = 0; | |
1393 | fbi->fb.fix.accel = FB_ACCEL_NONE; | |
1394 | ||
1395 | fbi->fb.var.nonstd = 0; | |
1396 | fbi->fb.var.activate = FB_ACTIVATE_NOW; | |
1397 | fbi->fb.var.height = -1; | |
1398 | fbi->fb.var.width = -1; | |
1399 | fbi->fb.var.accel_flags = 0; | |
1400 | fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; | |
1401 | ||
1402 | fbi->fb.fbops = &pxafb_ops; | |
1403 | fbi->fb.flags = FBINFO_DEFAULT; | |
1404 | fbi->fb.node = -1; | |
1405 | ||
1406 | addr = fbi; | |
1407 | addr = addr + sizeof(struct pxafb_info); | |
1408 | fbi->fb.pseudo_palette = addr; | |
1409 | ||
b0086efb | 1410 | fbi->state = C_STARTUP; |
1411 | fbi->task_state = (u_char)-1; | |
d14b272b | 1412 | |
84f43c30 | 1413 | pxafb_decode_mach_info(fbi, inf); |
1da177e4 LT |
1414 | |
1415 | init_waitqueue_head(&fbi->ctrlr_wait); | |
6d5aefb8 | 1416 | INIT_WORK(&fbi->task, pxafb_task); |
b91dbce5 | 1417 | mutex_init(&fbi->ctrlr_lock); |
2ba162b9 | 1418 | init_completion(&fbi->disable_done); |
1da177e4 LT |
1419 | |
1420 | return fbi; | |
1421 | } | |
1422 | ||
1423 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
9e6c2976 | 1424 | static int __devinit parse_opt_mode(struct device *dev, const char *this_opt) |
1da177e4 LT |
1425 | { |
1426 | struct pxafb_mach_info *inf = dev->platform_data; | |
817daf14 | 1427 | |
1428 | const char *name = this_opt+5; | |
1429 | unsigned int namelen = strlen(name); | |
1430 | int res_specified = 0, bpp_specified = 0; | |
1431 | unsigned int xres = 0, yres = 0, bpp = 0; | |
1432 | int yres_specified = 0; | |
1433 | int i; | |
1434 | for (i = namelen-1; i >= 0; i--) { | |
1435 | switch (name[i]) { | |
1436 | case '-': | |
1437 | namelen = i; | |
1438 | if (!bpp_specified && !yres_specified) { | |
1439 | bpp = simple_strtoul(&name[i+1], NULL, 0); | |
1440 | bpp_specified = 1; | |
1441 | } else | |
1442 | goto done; | |
1443 | break; | |
1444 | case 'x': | |
1445 | if (!yres_specified) { | |
1446 | yres = simple_strtoul(&name[i+1], NULL, 0); | |
1447 | yres_specified = 1; | |
1448 | } else | |
1449 | goto done; | |
1450 | break; | |
1451 | case '0' ... '9': | |
1452 | break; | |
1453 | default: | |
1454 | goto done; | |
1455 | } | |
1456 | } | |
1457 | if (i < 0 && yres_specified) { | |
1458 | xres = simple_strtoul(name, NULL, 0); | |
1459 | res_specified = 1; | |
1460 | } | |
1461 | done: | |
1462 | if (res_specified) { | |
1463 | dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); | |
1464 | inf->modes[0].xres = xres; inf->modes[0].yres = yres; | |
1465 | } | |
1466 | if (bpp_specified) | |
1467 | switch (bpp) { | |
1468 | case 1: | |
1469 | case 2: | |
1470 | case 4: | |
1471 | case 8: | |
1472 | case 16: | |
1473 | inf->modes[0].bpp = bpp; | |
1474 | dev_info(dev, "overriding bit depth: %d\n", bpp); | |
1475 | break; | |
1476 | default: | |
1477 | dev_err(dev, "Depth %d is not valid\n", bpp); | |
1478 | return -EINVAL; | |
1479 | } | |
1480 | return 0; | |
1481 | } | |
1482 | ||
9e6c2976 | 1483 | static int __devinit parse_opt(struct device *dev, char *this_opt) |
817daf14 | 1484 | { |
1485 | struct pxafb_mach_info *inf = dev->platform_data; | |
1486 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
1487 | char s[64]; | |
1488 | ||
1489 | s[0] = '\0'; | |
1490 | ||
1491 | if (!strncmp(this_opt, "mode:", 5)) { | |
1492 | return parse_opt_mode(dev, this_opt); | |
1493 | } else if (!strncmp(this_opt, "pixclock:", 9)) { | |
1494 | mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); | |
1495 | sprintf(s, "pixclock: %ld\n", mode->pixclock); | |
1496 | } else if (!strncmp(this_opt, "left:", 5)) { | |
1497 | mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); | |
1498 | sprintf(s, "left: %u\n", mode->left_margin); | |
1499 | } else if (!strncmp(this_opt, "right:", 6)) { | |
1500 | mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1501 | sprintf(s, "right: %u\n", mode->right_margin); | |
1502 | } else if (!strncmp(this_opt, "upper:", 6)) { | |
1503 | mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1504 | sprintf(s, "upper: %u\n", mode->upper_margin); | |
1505 | } else if (!strncmp(this_opt, "lower:", 6)) { | |
1506 | mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1507 | sprintf(s, "lower: %u\n", mode->lower_margin); | |
1508 | } else if (!strncmp(this_opt, "hsynclen:", 9)) { | |
1509 | mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1510 | sprintf(s, "hsynclen: %u\n", mode->hsync_len); | |
1511 | } else if (!strncmp(this_opt, "vsynclen:", 9)) { | |
1512 | mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1513 | sprintf(s, "vsynclen: %u\n", mode->vsync_len); | |
1514 | } else if (!strncmp(this_opt, "hsync:", 6)) { | |
1515 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1516 | sprintf(s, "hsync: Active Low\n"); | |
1517 | mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; | |
1518 | } else { | |
1519 | sprintf(s, "hsync: Active High\n"); | |
1520 | mode->sync |= FB_SYNC_HOR_HIGH_ACT; | |
1521 | } | |
1522 | } else if (!strncmp(this_opt, "vsync:", 6)) { | |
1523 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1524 | sprintf(s, "vsync: Active Low\n"); | |
1525 | mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; | |
1526 | } else { | |
1527 | sprintf(s, "vsync: Active High\n"); | |
1528 | mode->sync |= FB_SYNC_VERT_HIGH_ACT; | |
1529 | } | |
1530 | } else if (!strncmp(this_opt, "dpc:", 4)) { | |
1531 | if (simple_strtoul(this_opt+4, NULL, 0) == 0) { | |
1532 | sprintf(s, "double pixel clock: false\n"); | |
1533 | inf->lccr3 &= ~LCCR3_DPC; | |
1534 | } else { | |
1535 | sprintf(s, "double pixel clock: true\n"); | |
1536 | inf->lccr3 |= LCCR3_DPC; | |
1537 | } | |
1538 | } else if (!strncmp(this_opt, "outputen:", 9)) { | |
1539 | if (simple_strtoul(this_opt+9, NULL, 0) == 0) { | |
1540 | sprintf(s, "output enable: active low\n"); | |
1541 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; | |
1542 | } else { | |
1543 | sprintf(s, "output enable: active high\n"); | |
1544 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; | |
1545 | } | |
1546 | } else if (!strncmp(this_opt, "pixclockpol:", 12)) { | |
1547 | if (simple_strtoul(this_opt+12, NULL, 0) == 0) { | |
1548 | sprintf(s, "pixel clock polarity: falling edge\n"); | |
1549 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; | |
1550 | } else { | |
1551 | sprintf(s, "pixel clock polarity: rising edge\n"); | |
1552 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; | |
1553 | } | |
1554 | } else if (!strncmp(this_opt, "color", 5)) { | |
1555 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; | |
1556 | } else if (!strncmp(this_opt, "mono", 4)) { | |
1557 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; | |
1558 | } else if (!strncmp(this_opt, "active", 6)) { | |
1559 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; | |
1560 | } else if (!strncmp(this_opt, "passive", 7)) { | |
1561 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; | |
1562 | } else if (!strncmp(this_opt, "single", 6)) { | |
1563 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; | |
1564 | } else if (!strncmp(this_opt, "dual", 4)) { | |
1565 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; | |
1566 | } else if (!strncmp(this_opt, "4pix", 4)) { | |
1567 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; | |
1568 | } else if (!strncmp(this_opt, "8pix", 4)) { | |
1569 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; | |
1570 | } else { | |
1571 | dev_err(dev, "unknown option: %s\n", this_opt); | |
1572 | return -EINVAL; | |
1573 | } | |
1574 | ||
1575 | if (s[0] != '\0') | |
1576 | dev_info(dev, "override %s", s); | |
1577 | ||
1578 | return 0; | |
1579 | } | |
1580 | ||
9e6c2976 | 1581 | static int __devinit pxafb_parse_options(struct device *dev, char *options) |
817daf14 | 1582 | { |
1da177e4 | 1583 | char *this_opt; |
817daf14 | 1584 | int ret; |
1da177e4 | 1585 | |
817daf14 | 1586 | if (!options || !*options) |
1587 | return 0; | |
1da177e4 LT |
1588 | |
1589 | dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); | |
1590 | ||
1591 | /* could be made table driven or similar?... */ | |
817daf14 | 1592 | while ((this_opt = strsep(&options, ",")) != NULL) { |
1593 | ret = parse_opt(dev, this_opt); | |
1594 | if (ret) | |
1595 | return ret; | |
1596 | } | |
1597 | return 0; | |
1da177e4 | 1598 | } |
92ac73c1 | 1599 | |
1600 | static char g_options[256] __devinitdata = ""; | |
1601 | ||
f1edfc42 | 1602 | #ifndef MODULE |
9e6c2976 | 1603 | static int __init pxafb_setup_options(void) |
92ac73c1 | 1604 | { |
1605 | char *options = NULL; | |
1606 | ||
1607 | if (fb_get_options("pxafb", &options)) | |
1608 | return -ENODEV; | |
1609 | ||
1610 | if (options) | |
1611 | strlcpy(g_options, options, sizeof(g_options)); | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | #else | |
1616 | #define pxafb_setup_options() (0) | |
1617 | ||
1618 | module_param_string(options, g_options, sizeof(g_options), 0); | |
1619 | MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |
1620 | #endif | |
1621 | ||
1622 | #else | |
1623 | #define pxafb_parse_options(...) (0) | |
1624 | #define pxafb_setup_options() (0) | |
1da177e4 LT |
1625 | #endif |
1626 | ||
1da177e4 | 1627 | #ifdef DEBUG_VAR |
4f3e2664 EM |
1628 | /* Check for various illegal bit-combinations. Currently only |
1629 | * a warning is given. */ | |
1630 | static void __devinit pxafb_check_options(struct device *dev, | |
1631 | struct pxafb_mach_info *inf) | |
1632 | { | |
1633 | if (inf->lcd_conn) | |
1634 | return; | |
1da177e4 | 1635 | |
b0086efb | 1636 | if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) |
4f3e2664 | 1637 | dev_warn(dev, "machine LCCR0 setting contains " |
b0086efb | 1638 | "illegal bits: %08x\n", |
1639 | inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); | |
1640 | if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) | |
4f3e2664 | 1641 | dev_warn(dev, "machine LCCR3 setting contains " |
b0086efb | 1642 | "illegal bits: %08x\n", |
1643 | inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); | |
1644 | if (inf->lccr0 & LCCR0_DPD && | |
1da177e4 LT |
1645 | ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || |
1646 | (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || | |
1647 | (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) | |
4f3e2664 | 1648 | dev_warn(dev, "Double Pixel Data (DPD) mode is " |
b0086efb | 1649 | "only valid in passive mono" |
1650 | " single panel mode\n"); | |
1651 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && | |
1da177e4 | 1652 | (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) |
4f3e2664 | 1653 | dev_warn(dev, "Dual panel only valid in passive mode\n"); |
b0086efb | 1654 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && |
1655 | (inf->modes->upper_margin || inf->modes->lower_margin)) | |
4f3e2664 | 1656 | dev_warn(dev, "Upper and lower margins must be 0 in " |
b0086efb | 1657 | "passive mode\n"); |
4f3e2664 EM |
1658 | } |
1659 | #else | |
1660 | #define pxafb_check_options(...) do {} while (0) | |
1da177e4 LT |
1661 | #endif |
1662 | ||
4f3e2664 EM |
1663 | static int __devinit pxafb_probe(struct platform_device *dev) |
1664 | { | |
1665 | struct pxafb_info *fbi; | |
1666 | struct pxafb_mach_info *inf; | |
1667 | struct resource *r; | |
1668 | int irq, ret; | |
1669 | ||
1670 | dev_dbg(&dev->dev, "pxafb_probe\n"); | |
1671 | ||
1672 | inf = dev->dev.platform_data; | |
1673 | ret = -ENOMEM; | |
1674 | fbi = NULL; | |
1675 | if (!inf) | |
1676 | goto failed; | |
1677 | ||
1678 | ret = pxafb_parse_options(&dev->dev, g_options); | |
1679 | if (ret < 0) | |
1680 | goto failed; | |
1681 | ||
1682 | pxafb_check_options(&dev->dev, inf); | |
1683 | ||
b0086efb | 1684 | dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", |
1685 | inf->modes->xres, | |
1686 | inf->modes->yres, | |
1687 | inf->modes->bpp); | |
1688 | if (inf->modes->xres == 0 || | |
1689 | inf->modes->yres == 0 || | |
1690 | inf->modes->bpp == 0) { | |
3ae5eaec | 1691 | dev_err(&dev->dev, "Invalid resolution or bit depth\n"); |
1da177e4 LT |
1692 | ret = -EINVAL; |
1693 | goto failed; | |
1694 | } | |
a5718a14 | 1695 | |
3ae5eaec | 1696 | fbi = pxafb_init_fbinfo(&dev->dev); |
1da177e4 | 1697 | if (!fbi) { |
b0086efb | 1698 | /* only reason for pxafb_init_fbinfo to fail is kmalloc */ |
3ae5eaec | 1699 | dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); |
b0086efb | 1700 | ret = -ENOMEM; |
1da177e4 LT |
1701 | goto failed; |
1702 | } | |
1703 | ||
a5718a14 EM |
1704 | fbi->backlight_power = inf->pxafb_backlight_power; |
1705 | fbi->lcd_power = inf->pxafb_lcd_power; | |
1706 | ||
ce4fb7b8 | 1707 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1708 | if (r == NULL) { | |
1709 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | |
1710 | ret = -ENODEV; | |
ee98476b | 1711 | goto failed_fbi; |
ce4fb7b8 | 1712 | } |
1713 | ||
1714 | r = request_mem_region(r->start, r->end - r->start + 1, dev->name); | |
1715 | if (r == NULL) { | |
1716 | dev_err(&dev->dev, "failed to request I/O memory\n"); | |
1717 | ret = -EBUSY; | |
ee98476b | 1718 | goto failed_fbi; |
ce4fb7b8 | 1719 | } |
1720 | ||
1721 | fbi->mmio_base = ioremap(r->start, r->end - r->start + 1); | |
1722 | if (fbi->mmio_base == NULL) { | |
1723 | dev_err(&dev->dev, "failed to map I/O memory\n"); | |
1724 | ret = -EBUSY; | |
1725 | goto failed_free_res; | |
1726 | } | |
1727 | ||
1da177e4 LT |
1728 | /* Initialize video memory */ |
1729 | ret = pxafb_map_video_memory(fbi); | |
1730 | if (ret) { | |
3ae5eaec | 1731 | dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); |
1da177e4 | 1732 | ret = -ENOMEM; |
ce4fb7b8 | 1733 | goto failed_free_io; |
1da177e4 | 1734 | } |
1da177e4 | 1735 | |
ce4fb7b8 | 1736 | irq = platform_get_irq(dev, 0); |
1737 | if (irq < 0) { | |
1738 | dev_err(&dev->dev, "no IRQ defined\n"); | |
1739 | ret = -ENODEV; | |
1740 | goto failed_free_mem; | |
1741 | } | |
1742 | ||
1743 | ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); | |
1da177e4 | 1744 | if (ret) { |
3ae5eaec | 1745 | dev_err(&dev->dev, "request_irq failed: %d\n", ret); |
1da177e4 | 1746 | ret = -EBUSY; |
ce4fb7b8 | 1747 | goto failed_free_mem; |
1da177e4 LT |
1748 | } |
1749 | ||
3c42a449 EM |
1750 | ret = pxafb_smart_init(fbi); |
1751 | if (ret) { | |
1752 | dev_err(&dev->dev, "failed to initialize smartpanel\n"); | |
1753 | goto failed_free_irq; | |
1754 | } | |
07df1c4f | 1755 | |
1da177e4 LT |
1756 | /* |
1757 | * This makes sure that our colour bitfield | |
1758 | * descriptors are correctly initialised. | |
1759 | */ | |
ee98476b JK |
1760 | ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); |
1761 | if (ret) { | |
1762 | dev_err(&dev->dev, "failed to get suitable mode\n"); | |
1763 | goto failed_free_irq; | |
1764 | } | |
1765 | ||
1766 | ret = pxafb_set_par(&fbi->fb); | |
1767 | if (ret) { | |
1768 | dev_err(&dev->dev, "Failed to set parameters\n"); | |
1769 | goto failed_free_irq; | |
1770 | } | |
1da177e4 | 1771 | |
3ae5eaec | 1772 | platform_set_drvdata(dev, fbi); |
1da177e4 LT |
1773 | |
1774 | ret = register_framebuffer(&fbi->fb); | |
1775 | if (ret < 0) { | |
b0086efb | 1776 | dev_err(&dev->dev, |
1777 | "Failed to register framebuffer device: %d\n", ret); | |
ee98476b | 1778 | goto failed_free_cmap; |
1da177e4 LT |
1779 | } |
1780 | ||
1da177e4 LT |
1781 | #ifdef CONFIG_CPU_FREQ |
1782 | fbi->freq_transition.notifier_call = pxafb_freq_transition; | |
1783 | fbi->freq_policy.notifier_call = pxafb_freq_policy; | |
b0086efb | 1784 | cpufreq_register_notifier(&fbi->freq_transition, |
1785 | CPUFREQ_TRANSITION_NOTIFIER); | |
1786 | cpufreq_register_notifier(&fbi->freq_policy, | |
1787 | CPUFREQ_POLICY_NOTIFIER); | |
1da177e4 LT |
1788 | #endif |
1789 | ||
1790 | /* | |
1791 | * Ok, now enable the LCD controller | |
1792 | */ | |
1793 | set_ctrlr_state(fbi, C_ENABLE); | |
1794 | ||
1795 | return 0; | |
1796 | ||
ee98476b JK |
1797 | failed_free_cmap: |
1798 | if (fbi->fb.cmap.len) | |
1799 | fb_dealloc_cmap(&fbi->fb.cmap); | |
ce4fb7b8 | 1800 | failed_free_irq: |
1801 | free_irq(irq, fbi); | |
ce4fb7b8 | 1802 | failed_free_mem: |
1803 | dma_free_writecombine(&dev->dev, fbi->map_size, | |
1804 | fbi->map_cpu, fbi->map_dma); | |
ee98476b JK |
1805 | failed_free_io: |
1806 | iounmap(fbi->mmio_base); | |
1807 | failed_free_res: | |
1808 | release_mem_region(r->start, r->end - r->start + 1); | |
1809 | failed_fbi: | |
1810 | clk_put(fbi->clk); | |
3ae5eaec | 1811 | platform_set_drvdata(dev, NULL); |
1da177e4 | 1812 | kfree(fbi); |
ee98476b | 1813 | failed: |
1da177e4 LT |
1814 | return ret; |
1815 | } | |
1816 | ||
9f17f287 JK |
1817 | static int __devexit pxafb_remove(struct platform_device *dev) |
1818 | { | |
1819 | struct pxafb_info *fbi = platform_get_drvdata(dev); | |
1820 | struct resource *r; | |
1821 | int irq; | |
1822 | struct fb_info *info; | |
1823 | ||
1824 | if (!fbi) | |
1825 | return 0; | |
1826 | ||
1827 | info = &fbi->fb; | |
1828 | ||
1829 | unregister_framebuffer(info); | |
1830 | ||
1831 | pxafb_disable_controller(fbi); | |
1832 | ||
1833 | if (fbi->fb.cmap.len) | |
1834 | fb_dealloc_cmap(&fbi->fb.cmap); | |
1835 | ||
1836 | irq = platform_get_irq(dev, 0); | |
1837 | free_irq(irq, fbi); | |
1838 | ||
1839 | dma_free_writecombine(&dev->dev, fbi->map_size, | |
1840 | fbi->map_cpu, fbi->map_dma); | |
1841 | ||
1842 | iounmap(fbi->mmio_base); | |
1843 | ||
1844 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1845 | release_mem_region(r->start, r->end - r->start + 1); | |
1846 | ||
1847 | clk_put(fbi->clk); | |
1848 | kfree(fbi); | |
1849 | ||
1850 | return 0; | |
1851 | } | |
1852 | ||
3ae5eaec | 1853 | static struct platform_driver pxafb_driver = { |
1da177e4 | 1854 | .probe = pxafb_probe, |
9f17f287 | 1855 | .remove = pxafb_remove, |
1da177e4 LT |
1856 | .suspend = pxafb_suspend, |
1857 | .resume = pxafb_resume, | |
3ae5eaec | 1858 | .driver = { |
9f17f287 | 1859 | .owner = THIS_MODULE, |
3ae5eaec RK |
1860 | .name = "pxa2xx-fb", |
1861 | }, | |
1da177e4 LT |
1862 | }; |
1863 | ||
9e6c2976 | 1864 | static int __init pxafb_init(void) |
1da177e4 | 1865 | { |
92ac73c1 | 1866 | if (pxafb_setup_options()) |
1867 | return -EINVAL; | |
1da177e4 | 1868 | |
3ae5eaec | 1869 | return platform_driver_register(&pxafb_driver); |
1da177e4 LT |
1870 | } |
1871 | ||
9f17f287 JK |
1872 | static void __exit pxafb_exit(void) |
1873 | { | |
1874 | platform_driver_unregister(&pxafb_driver); | |
1875 | } | |
1876 | ||
1da177e4 | 1877 | module_init(pxafb_init); |
9f17f287 | 1878 | module_exit(pxafb_exit); |
1da177e4 LT |
1879 | |
1880 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | |
1881 | MODULE_LICENSE("GPL"); |