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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[mirror_ubuntu-zesty-kernel.git] / drivers / video / riva / fbdev.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
1da177e4
LT		 32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
1da177e4
LT		 37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
5474c120 42#include <linux/backlight.h>
1da177e4
LT		 43#ifdef CONFIG_MTRR
44#include <asm/mtrr.h>
45#endif
46#ifdef CONFIG_PPC_OF
47#include <asm/prom.h>
48#include <asm/pci-bridge.h>
49#endif
50#ifdef CONFIG_PMAC_BACKLIGHT
e8222502 51#include <asm/machdep.h>
1da177e4
LT		 52#include <asm/backlight.h>
53#endif
54
55#include "rivafb.h"
56#include "nvreg.h"
57
58#ifndef CONFIG_PCI /* sanity check */
59#error This driver requires PCI support.
60#endif
61
62/* version number of this driver */
63#define RIVAFB_VERSION "0.9.5b"
64
65/* ------------------------------------------------------------------------- *
66 *
67 * various helpful macros and constants
68 *
69 * ------------------------------------------------------------------------- */
70#ifdef CONFIG_FB_RIVA_DEBUG
71#define NVTRACE printk
72#else
73#define NVTRACE if(0) printk
74#endif
75
76#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
78
79#ifdef CONFIG_FB_RIVA_DEBUG
80#define assert(expr) \
81 if(!(expr)) { \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
84 BUG(); \
85 }
86#else
87#define assert(expr)
88#endif
89
90#define PFX "rivafb: "
91
92/* macro that allows you to set overflow bits */
93#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94#define SetBit(n) (1<<(n))
95#define Set8Bits(value) ((value)&0xff)
96
97/* HW cursor parameters */
98#define MAX_CURS 32
99
100/* ------------------------------------------------------------------------- *
101 *
102 * prototypes
103 *
104 * ------------------------------------------------------------------------- */
105
106static int rivafb_blank(int blank, struct fb_info *info);
107
108/* ------------------------------------------------------------------------- *
109 *
110 * card identification
111 *
112 * ------------------------------------------------------------------------- */
113
114static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
201};
202MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
203
204/* ------------------------------------------------------------------------- *
205 *
206 * global variables
207 *
208 * ------------------------------------------------------------------------- */
209
210/* command line data, set in rivafb_setup() */
211static int flatpanel __devinitdata = -1; /* Autodetect later */
212static int forceCRTC __devinitdata = -1;
213static int noaccel __devinitdata = 0;
214#ifdef CONFIG_MTRR
215static int nomtrr __devinitdata = 0;
216#endif
217
218static char *mode_option __devinitdata = NULL;
219static int strictmode = 0;
220
221static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
223 .xpanstep = 1,
224 .ypanstep = 1,
225};
226
227static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
228 .xres = 640,
229 .yres = 480,
230 .xres_virtual = 640,
231 .yres_virtual = 480,
232 .bits_per_pixel = 8,
233 .red = {0, 8, 0},
234 .green = {0, 8, 0},
235 .blue = {0, 8, 0},
236 .transp = {0, 0, 0},
237 .activate = FB_ACTIVATE_NOW,
238 .height = -1,
239 .width = -1,
240 .pixclock = 39721,
241 .left_margin = 40,
242 .right_margin = 24,
243 .upper_margin = 32,
244 .lower_margin = 11,
245 .hsync_len = 96,
246 .vsync_len = 2,
247 .vmode = FB_VMODE_NONINTERLACED
248};
249
250/* from GGI */
251static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, /* 0x40 */
264 },
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
266 0xFF},
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
268 0xEB /* MISC */
269};
270
271/*
272 * Backlight control
273 */
5474c120
MH		 274#ifdef CONFIG_FB_RIVA_BACKLIGHT
275/* We do not have any information about which values are allowed, thus
276 * we used safe values.
277 */
278#define MIN_LEVEL 0x158
279#define MAX_LEVEL 0x534
e01af038 280#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
1da177e4 281
5474c120
MH		 282static struct backlight_properties riva_bl_data;
283
e01af038 284/* Call with fb_info->bl_mutex held */
5474c120
MH		 285static int riva_bl_get_level_brightness(struct riva_par *par,
286 int level)
287{
288 struct fb_info *info = pci_get_drvdata(par->pdev);
289 int nlevel;
290
291 /* Get and convert the value */
e01af038 292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
5474c120
MH		 293
294 if (nlevel < 0)
295 nlevel = 0;
296 else if (nlevel < MIN_LEVEL)
297 nlevel = MIN_LEVEL;
298 else if (nlevel > MAX_LEVEL)
299 nlevel = MAX_LEVEL;
300
301 return nlevel;
302}
303
e01af038
MH		 304/* Call with fb_info->bl_mutex held */
305static int __riva_bl_update_status(struct backlight_device *bd)
5474c120
MH		 306{
307 struct riva_par *par = class_get_devdata(&bd->class_dev);
308 U032 tmp_pcrt, tmp_pmc;
309 int level;
310
311 if (bd->props->power != FB_BLANK_UNBLANK ||
312 bd->props->fb_blank != FB_BLANK_UNBLANK)
313 level = 0;
314 else
315 level = bd->props->brightness;
316
317 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
318 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
319 if(level > 0) {
320 tmp_pcrt |= 0x1;
321 tmp_pmc |= (1 << 31); /* backlight bit */
322 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
323 }
324 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
325 par->riva.PMC[0x10F0/4] = tmp_pmc;
326
327 return 0;
328}
329
e01af038
MH		 330static int riva_bl_update_status(struct backlight_device *bd)
331{
332 struct riva_par *par = class_get_devdata(&bd->class_dev);
333 struct fb_info *info = pci_get_drvdata(par->pdev);
334 int ret;
335
336 mutex_lock(&info->bl_mutex);
337 ret = __riva_bl_update_status(bd);
338 mutex_unlock(&info->bl_mutex);
339
340 return ret;
341}
342
5474c120
MH		 343static int riva_bl_get_brightness(struct backlight_device *bd)
344{
345 return bd->props->brightness;
346}
1da177e4 347
5474c120
MH		 348static struct backlight_properties riva_bl_data = {
349 .owner = THIS_MODULE,
350 .get_brightness = riva_bl_get_brightness,
351 .update_status = riva_bl_update_status,
352 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
1da177e4 353};
5474c120 354
e01af038
MH		 355static void riva_bl_set_power(struct fb_info *info, int power)
356{
357 mutex_lock(&info->bl_mutex);
358 up(&info->bl_dev->sem);
359 info->bl_dev->props->power = power;
360 __riva_bl_update_status(info->bl_dev);
361 down(&info->bl_dev->sem);
362 mutex_unlock(&info->bl_mutex);
363}
364
5474c120
MH		 365static void riva_bl_init(struct riva_par *par)
366{
367 struct fb_info *info = pci_get_drvdata(par->pdev);
368 struct backlight_device *bd;
369 char name[12];
370
371 if (!par->FlatPanel)
372 return;
373
374#ifdef CONFIG_PMAC_BACKLIGHT
375 if (!machine_is(powermac) ||
376 !pmac_has_backlight_type("mnca"))
377 return;
378#endif
379
380 snprintf(name, sizeof(name), "rivabl%d", info->node);
381
382 bd = backlight_device_register(name, par, &riva_bl_data);
383 if (IS_ERR(bd)) {
384 info->bl_dev = NULL;
385 printk("riva: Backlight registration failed\n");
386 goto error;
387 }
388
389 mutex_lock(&info->bl_mutex);
390 info->bl_dev = bd;
391 fb_bl_default_curve(info, 0,
392 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
393 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
394 mutex_unlock(&info->bl_mutex);
395
396 up(&bd->sem);
397 bd->props->brightness = riva_bl_data.max_brightness;
398 bd->props->power = FB_BLANK_UNBLANK;
399 bd->props->update_status(bd);
400 down(&bd->sem);
401
402#ifdef CONFIG_PMAC_BACKLIGHT
403 mutex_lock(&pmac_backlight_mutex);
404 if (!pmac_backlight)
405 pmac_backlight = bd;
406 mutex_unlock(&pmac_backlight_mutex);
407#endif
408
409 printk("riva: Backlight initialized (%s)\n", name);
410
411 return;
412
413error:
414 return;
415}
416
417static void riva_bl_exit(struct riva_par *par)
418{
419 struct fb_info *info = pci_get_drvdata(par->pdev);
420
421#ifdef CONFIG_PMAC_BACKLIGHT
422 mutex_lock(&pmac_backlight_mutex);
423#endif
424
425 mutex_lock(&info->bl_mutex);
426 if (info->bl_dev) {
427#ifdef CONFIG_PMAC_BACKLIGHT
428 if (pmac_backlight == info->bl_dev)
429 pmac_backlight = NULL;
430#endif
431
432 backlight_device_unregister(info->bl_dev);
433
434 printk("riva: Backlight unloaded\n");
435 }
436 mutex_unlock(&info->bl_mutex);
437
438#ifdef CONFIG_PMAC_BACKLIGHT
439 mutex_unlock(&pmac_backlight_mutex);
440#endif
441}
442#else
443static inline void riva_bl_init(struct riva_par *par) {}
444static inline void riva_bl_exit(struct riva_par *par) {}
e01af038 445static inline void riva_bl_set_power(struct fb_info *info, int power) {}
5474c120 446#endif /* CONFIG_FB_RIVA_BACKLIGHT */
1da177e4
LT		 447
448/* ------------------------------------------------------------------------- *
449 *
450 * MMIO access macros
451 *
452 * ------------------------------------------------------------------------- */
453
454static inline void CRTCout(struct riva_par *par, unsigned char index,
455 unsigned char val)
456{
457 VGA_WR08(par->riva.PCIO, 0x3d4, index);
458 VGA_WR08(par->riva.PCIO, 0x3d5, val);
459}
460
461static inline unsigned char CRTCin(struct riva_par *par,
462 unsigned char index)
463{
464 VGA_WR08(par->riva.PCIO, 0x3d4, index);
465 return (VGA_RD08(par->riva.PCIO, 0x3d5));
466}
467
468static inline void GRAout(struct riva_par *par, unsigned char index,
469 unsigned char val)
470{
471 VGA_WR08(par->riva.PVIO, 0x3ce, index);
472 VGA_WR08(par->riva.PVIO, 0x3cf, val);
473}
474
475static inline unsigned char GRAin(struct riva_par *par,
476 unsigned char index)
477{
478 VGA_WR08(par->riva.PVIO, 0x3ce, index);
479 return (VGA_RD08(par->riva.PVIO, 0x3cf));
480}
481
482static inline void SEQout(struct riva_par *par, unsigned char index,
483 unsigned char val)
484{
485 VGA_WR08(par->riva.PVIO, 0x3c4, index);
486 VGA_WR08(par->riva.PVIO, 0x3c5, val);
487}
488
489static inline unsigned char SEQin(struct riva_par *par,
490 unsigned char index)
491{
492 VGA_WR08(par->riva.PVIO, 0x3c4, index);
493 return (VGA_RD08(par->riva.PVIO, 0x3c5));
494}
495
496static inline void ATTRout(struct riva_par *par, unsigned char index,
497 unsigned char val)
498{
499 VGA_WR08(par->riva.PCIO, 0x3c0, index);
500 VGA_WR08(par->riva.PCIO, 0x3c0, val);
501}
502
503static inline unsigned char ATTRin(struct riva_par *par,
504 unsigned char index)
505{
506 VGA_WR08(par->riva.PCIO, 0x3c0, index);
507 return (VGA_RD08(par->riva.PCIO, 0x3c1));
508}
509
510static inline void MISCout(struct riva_par *par, unsigned char val)
511{
512 VGA_WR08(par->riva.PVIO, 0x3c2, val);
513}
514
515static inline unsigned char MISCin(struct riva_par *par)
516{
517 return (VGA_RD08(par->riva.PVIO, 0x3cc));
518}
519
520static u8 byte_rev[256] = {
521 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
522 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
523 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
524 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
525 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
526 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
527 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
528 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
529 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
530 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
531 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
532 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
533 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
534 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
535 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
536 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
537 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
538 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
539 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
540 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
541 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
542 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
543 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
544 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
545 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
546 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
547 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
548 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
549 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
550 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
551 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
552 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
553};
554
555static inline void reverse_order(u32 *l)
556{
557 u8 *a = (u8 *)l;
558 *a = byte_rev[*a], a++;
559 *a = byte_rev[*a], a++;
560 *a = byte_rev[*a], a++;
561 *a = byte_rev[*a];
562}
563
564/* ------------------------------------------------------------------------- *
565 *
566 * cursor stuff
567 *
568 * ------------------------------------------------------------------------- */
569
570/**
571 * rivafb_load_cursor_image - load cursor image to hardware
572 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
573 * @par: pointer to private data
574 * @w: width of cursor image in pixels
575 * @h: height of cursor image in scanlines
576 * @bg: background color (ARGB1555) - alpha bit determines opacity
577 * @fg: foreground color (ARGB1555)
578 *
579 * DESCRIPTiON:
580 * Loads cursor image based on a monochrome source and mask bitmap. The
581 * image bits determines the color of the pixel, 0 for background, 1 for
582 * foreground. Only the affected region (as determined by @w and @h
583 * parameters) will be updated.
584 *
585 * CALLED FROM:
586 * rivafb_cursor()
587 */
588static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
589 u16 bg, u16 fg, u32 w, u32 h)
590{
591 int i, j, k = 0;
592 u32 b, tmp;
593 u32 *data = (u32 *)data8;
594 bg = le16_to_cpu(bg);
595 fg = le16_to_cpu(fg);
596
597 w = (w + 1) & ~1;
598
599 for (i = 0; i < h; i++) {
600 b = *data++;
601 reverse_order(&b);
602
603 for (j = 0; j < w/2; j++) {
604 tmp = 0;
605#if defined (__BIG_ENDIAN)
606 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
607 b <<= 1;
608 tmp |= (b & (1 << 31)) ? fg : bg;
609 b <<= 1;
610#else
611 tmp = (b & 1) ? fg : bg;
612 b >>= 1;
613 tmp |= (b & 1) ? fg << 16 : bg << 16;
614 b >>= 1;
615#endif
616 writel(tmp, &par->riva.CURSOR[k++]);
617 }
618 k += (MAX_CURS - w)/2;
619 }
620}
621
622/* ------------------------------------------------------------------------- *
623 *
624 * general utility functions
625 *
626 * ------------------------------------------------------------------------- */
627
628/**
629 * riva_wclut - set CLUT entry
630 * @chip: pointer to RIVA_HW_INST object
631 * @regnum: register number
632 * @red: red component
633 * @green: green component
634 * @blue: blue component
635 *
636 * DESCRIPTION:
637 * Sets color register @regnum.
638 *
639 * CALLED FROM:
640 * rivafb_setcolreg()
641 */
642static void riva_wclut(RIVA_HW_INST *chip,
643 unsigned char regnum, unsigned char red,
644 unsigned char green, unsigned char blue)
645{
646 VGA_WR08(chip->PDIO, 0x3c8, regnum);
647 VGA_WR08(chip->PDIO, 0x3c9, red);
648 VGA_WR08(chip->PDIO, 0x3c9, green);
649 VGA_WR08(chip->PDIO, 0x3c9, blue);
650}
651
652/**
653 * riva_rclut - read fromCLUT register
654 * @chip: pointer to RIVA_HW_INST object
655 * @regnum: register number
656 * @red: red component
657 * @green: green component
658 * @blue: blue component
659 *
660 * DESCRIPTION:
661 * Reads red, green, and blue from color register @regnum.
662 *
663 * CALLED FROM:
664 * rivafb_setcolreg()
665 */
666static void riva_rclut(RIVA_HW_INST *chip,
667 unsigned char regnum, unsigned char *red,
668 unsigned char *green, unsigned char *blue)
669{
670
671 VGA_WR08(chip->PDIO, 0x3c7, regnum);
672 *red = VGA_RD08(chip->PDIO, 0x3c9);
673 *green = VGA_RD08(chip->PDIO, 0x3c9);
674 *blue = VGA_RD08(chip->PDIO, 0x3c9);
675}
676
677/**
678 * riva_save_state - saves current chip state
679 * @par: pointer to riva_par object containing info for current riva board
680 * @regs: pointer to riva_regs object
681 *
682 * DESCRIPTION:
683 * Saves current chip state to @regs.
684 *
685 * CALLED FROM:
686 * rivafb_probe()
687 */
688/* from GGI */
689static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
690{
691 int i;
692
693 NVTRACE_ENTER();
694 par->riva.LockUnlock(&par->riva, 0);
695
696 par->riva.UnloadStateExt(&par->riva, &regs->ext);
697
698 regs->misc_output = MISCin(par);
699
700 for (i = 0; i < NUM_CRT_REGS; i++)
701 regs->crtc[i] = CRTCin(par, i);
702
703 for (i = 0; i < NUM_ATC_REGS; i++)
704 regs->attr[i] = ATTRin(par, i);
705
706 for (i = 0; i < NUM_GRC_REGS; i++)
707 regs->gra[i] = GRAin(par, i);
708
709 for (i = 0; i < NUM_SEQ_REGS; i++)
710 regs->seq[i] = SEQin(par, i);
711 NVTRACE_LEAVE();
712}
713
714/**
715 * riva_load_state - loads current chip state
716 * @par: pointer to riva_par object containing info for current riva board
717 * @regs: pointer to riva_regs object
718 *
719 * DESCRIPTION:
720 * Loads chip state from @regs.
721 *
722 * CALLED FROM:
723 * riva_load_video_mode()
724 * rivafb_probe()
725 * rivafb_remove()
726 */
727/* from GGI */
728static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
729{
730 RIVA_HW_STATE *state = &regs->ext;
731 int i;
732
733 NVTRACE_ENTER();
734 CRTCout(par, 0x11, 0x00);
735
736 par->riva.LockUnlock(&par->riva, 0);
737
738 par->riva.LoadStateExt(&par->riva, state);
739
740 MISCout(par, regs->misc_output);
741
742 for (i = 0; i < NUM_CRT_REGS; i++) {
743 switch (i) {
744 case 0x19:
745 case 0x20 ... 0x40:
746 break;
747 default:
748 CRTCout(par, i, regs->crtc[i]);
749 }
750 }
751
752 for (i = 0; i < NUM_ATC_REGS; i++)
753 ATTRout(par, i, regs->attr[i]);
754
755 for (i = 0; i < NUM_GRC_REGS; i++)
756 GRAout(par, i, regs->gra[i]);
757
758 for (i = 0; i < NUM_SEQ_REGS; i++)
759 SEQout(par, i, regs->seq[i]);
760 NVTRACE_LEAVE();
761}
762
763/**
764 * riva_load_video_mode - calculate timings
765 * @info: pointer to fb_info object containing info for current riva board
766 *
767 * DESCRIPTION:
768 * Calculate some timings and then send em off to riva_load_state().
769 *
770 * CALLED FROM:
771 * rivafb_set_par()
772 */
773static void riva_load_video_mode(struct fb_info *info)
774{
775 int bpp, width, hDisplaySize, hDisplay, hStart,
776 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
777 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
f4a41836 778 struct riva_par *par = info->par;
1da177e4
LT		 779 struct riva_regs newmode;
780
781 NVTRACE_ENTER();
782 /* time to calculate */
783 rivafb_blank(1, info);
784
785 bpp = info->var.bits_per_pixel;
786 if (bpp == 16 && info->var.green.length == 5)
787 bpp = 15;
788 width = info->var.xres_virtual;
789 hDisplaySize = info->var.xres;
790 hDisplay = (hDisplaySize / 8) - 1;
791 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
792 hEnd = (hDisplaySize + info->var.right_margin +
793 info->var.hsync_len) / 8 - 1;
794 hTotal = (hDisplaySize + info->var.right_margin +
795 info->var.hsync_len + info->var.left_margin) / 8 - 5;
796 hBlankStart = hDisplay;
797 hBlankEnd = hTotal + 4;
798
799 height = info->var.yres_virtual;
800 vDisplay = info->var.yres - 1;
801 vStart = info->var.yres + info->var.lower_margin - 1;
802 vEnd = info->var.yres + info->var.lower_margin +
803 info->var.vsync_len - 1;
804 vTotal = info->var.yres + info->var.lower_margin +
805 info->var.vsync_len + info->var.upper_margin + 2;
806 vBlankStart = vDisplay;
807 vBlankEnd = vTotal + 1;
808 dotClock = 1000000000 / info->var.pixclock;
809
810 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
811
812 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
813 vTotal |= 1;
814
815 if (par->FlatPanel) {
816 vStart = vTotal - 3;
817 vEnd = vTotal - 2;
818 vBlankStart = vStart;
819 hStart = hTotal - 3;
820 hEnd = hTotal - 2;
821 hBlankEnd = hTotal + 4;
822 }
823
824 newmode.crtc[0x0] = Set8Bits (hTotal);
825 newmode.crtc[0x1] = Set8Bits (hDisplay);
826 newmode.crtc[0x2] = Set8Bits (hBlankStart);
827 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
828 newmode.crtc[0x4] = Set8Bits (hStart);
829 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
830 | SetBitField (hEnd, 4: 0, 4:0);
831 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
832 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
833 | SetBitField (vDisplay, 8: 8, 1:1)
834 | SetBitField (vStart, 8: 8, 2:2)
835 | SetBitField (vBlankStart, 8: 8, 3:3)
836 | SetBit (4)
837 | SetBitField (vTotal, 9: 9, 5:5)
838 | SetBitField (vDisplay, 9: 9, 6:6)
839 | SetBitField (vStart, 9: 9, 7:7);
840 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
841 | SetBit (6);
842 newmode.crtc[0x10] = Set8Bits (vStart);
843 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
844 | SetBit (5);
845 newmode.crtc[0x12] = Set8Bits (vDisplay);
846 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
847 newmode.crtc[0x15] = Set8Bits (vBlankStart);
848 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
849
850 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
851 | SetBitField(vBlankStart,10:10,3:3)
852 | SetBitField(vStart,10:10,2:2)
853 | SetBitField(vDisplay,10:10,1:1)
854 | SetBitField(vTotal,10:10,0:0);
855 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
856 | SetBitField(hDisplay,8:8,1:1)
857 | SetBitField(hBlankStart,8:8,2:2)
858 | SetBitField(hStart,8:8,3:3);
859 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
860 | SetBitField(vDisplay,11:11,2:2)
861 | SetBitField(vStart,11:11,4:4)
862 | SetBitField(vBlankStart,11:11,6:6);
863
864 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
865 int tmp = (hTotal >> 1) & ~1;
866 newmode.ext.interlace = Set8Bits(tmp);
867 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
868 } else
869 newmode.ext.interlace = 0xff; /* interlace off */
870
871 if (par->riva.Architecture >= NV_ARCH_10)
872 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
873
874 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
875 newmode.misc_output &= ~0x40;
876 else
877 newmode.misc_output |= 0x40;
878 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
879 newmode.misc_output &= ~0x80;
880 else
881 newmode.misc_output |= 0x80;
882
883 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
884 hDisplaySize, height, dotClock);
885
886 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
887 0xfff000ff;
888 if (par->FlatPanel == 1) {
889 newmode.ext.pixel |= (1 << 7);
890 newmode.ext.scale |= (1 << 8);
891 }
892 if (par->SecondCRTC) {
893 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
894 ~0x00001000;
895 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
896 0x00001000;
897 newmode.ext.crtcOwner = 3;
898 newmode.ext.pllsel |= 0x20000800;
899 newmode.ext.vpll2 = newmode.ext.vpll;
900 } else if (par->riva.twoHeads) {
901 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
902 0x00001000;
903 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
904 ~0x00001000;
905 newmode.ext.crtcOwner = 0;
906 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
907 }
908 if (par->FlatPanel == 1) {
909 newmode.ext.pixel |= (1 << 7);
910 newmode.ext.scale |= (1 << 8);
911 }
912 newmode.ext.cursorConfig = 0x02000100;
913 par->current_state = newmode;
914 riva_load_state(par, &par->current_state);
915 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
916 rivafb_blank(0, info);
917 NVTRACE_LEAVE();
918}
919
920static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
921{
922 NVTRACE_ENTER();
923 var->xres = var->xres_virtual = modedb->xres;
924 var->yres = modedb->yres;
925 if (var->yres_virtual < var->yres)
926 var->yres_virtual = var->yres;
927 var->xoffset = var->yoffset = 0;
928 var->pixclock = modedb->pixclock;
929 var->left_margin = modedb->left_margin;
930 var->right_margin = modedb->right_margin;
931 var->upper_margin = modedb->upper_margin;
932 var->lower_margin = modedb->lower_margin;
933 var->hsync_len = modedb->hsync_len;
934 var->vsync_len = modedb->vsync_len;
935 var->sync = modedb->sync;
936 var->vmode = modedb->vmode;
937 NVTRACE_LEAVE();
938}
939
940/**
941 * rivafb_do_maximize -
942 * @info: pointer to fb_info object containing info for current riva board
943 * @var:
944 * @nom:
945 * @den:
946 *
947 * DESCRIPTION:
948 * .
949 *
950 * RETURNS:
951 * -EINVAL on failure, 0 on success
952 *
953 *
954 * CALLED FROM:
955 * rivafb_check_var()
956 */
957static int rivafb_do_maximize(struct fb_info *info,
958 struct fb_var_screeninfo *var,
959 int nom, int den)
960{
961 static struct {
962 int xres, yres;
963 } modes[] = {
964 {1600, 1280},
965 {1280, 1024},
966 {1024, 768},
967 {800, 600},
968 {640, 480},
969 {-1, -1}
970 };
971 int i;
972
973 NVTRACE_ENTER();
974 /* use highest possible virtual resolution */
975 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
976 printk(KERN_WARNING PFX
977 "using maximum available virtual resolution\n");
978 for (i = 0; modes[i].xres != -1; i++) {
979 if (modes[i].xres * nom / den * modes[i].yres <
980 info->fix.smem_len)
981 break;
982 }
983 if (modes[i].xres == -1) {
984 printk(KERN_ERR PFX
985 "could not find a virtual resolution that fits into video memory!!\n");
986 NVTRACE("EXIT - EINVAL error\n");
987 return -EINVAL;
988 }
989 var->xres_virtual = modes[i].xres;
990 var->yres_virtual = modes[i].yres;
991
992 printk(KERN_INFO PFX
993 "virtual resolution set to maximum of %dx%d\n",
994 var->xres_virtual, var->yres_virtual);
995 } else if (var->xres_virtual == -1) {
996 var->xres_virtual = (info->fix.smem_len * den /
997 (nom * var->yres_virtual)) & ~15;
998 printk(KERN_WARNING PFX
999 "setting virtual X resolution to %d\n", var->xres_virtual);
1000 } else if (var->yres_virtual == -1) {
1001 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1002 var->yres_virtual = info->fix.smem_len * den /
1003 (nom * var->xres_virtual);
1004 printk(KERN_WARNING PFX
1005 "setting virtual Y resolution to %d\n", var->yres_virtual);
1006 } else {
1007 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1008 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
1009 printk(KERN_ERR PFX
1010 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
1011 var->xres, var->yres, var->bits_per_pixel);
1012 NVTRACE("EXIT - EINVAL error\n");
1013 return -EINVAL;
1014 }
1015 }
1016
1017 if (var->xres_virtual * nom / den >= 8192) {
1018 printk(KERN_WARNING PFX
1019 "virtual X resolution (%d) is too high, lowering to %d\n",
1020 var->xres_virtual, 8192 * den / nom - 16);
1021 var->xres_virtual = 8192 * den / nom - 16;
1022 }
1023
1024 if (var->xres_virtual < var->xres) {
1025 printk(KERN_ERR PFX
1026 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1027 return -EINVAL;
1028 }
1029
1030 if (var->yres_virtual < var->yres) {
1031 printk(KERN_ERR PFX
1032 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1033 return -EINVAL;
1034 }
1035 if (var->yres_virtual > 0x7fff/nom)
1036 var->yres_virtual = 0x7fff/nom;
1037 if (var->xres_virtual > 0x7fff/nom)
1038 var->xres_virtual = 0x7fff/nom;
1039 NVTRACE_LEAVE();
1040 return 0;
1041}
1042
1043static void
1044riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1045{
1046 RIVA_FIFO_FREE(par->riva, Patt, 4);
1047 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1048 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1049 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1050 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1051}
1052
1053/* acceleration routines */
1054static inline void wait_for_idle(struct riva_par *par)
1055{
1056 while (par->riva.Busy(&par->riva));
1057}
1058
1059/*
1060 * Set ROP. Translate X rop into ROP3. Internal routine.
1061 */
1062static void
1063riva_set_rop_solid(struct riva_par *par, int rop)
1064{
1065 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1066 RIVA_FIFO_FREE(par->riva, Rop, 1);
1067 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1068
1069}
1070
1071static void riva_setup_accel(struct fb_info *info)
1072{
f4a41836 1073 struct riva_par *par = info->par;
1da177e4
LT		 1074
1075 RIVA_FIFO_FREE(par->riva, Clip, 2);
1076 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1077 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1078 (info->var.xres_virtual & 0xffff) |
1079 (info->var.yres_virtual << 16));
1080 riva_set_rop_solid(par, 0xcc);
1081 wait_for_idle(par);
1082}
1083
1084/**
1085 * riva_get_cmap_len - query current color map length
1086 * @var: standard kernel fb changeable data
1087 *
1088 * DESCRIPTION:
1089 * Get current color map length.
1090 *
1091 * RETURNS:
1092 * Length of color map
1093 *
1094 * CALLED FROM:
1095 * rivafb_setcolreg()
1096 */
1097static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1098{
1099 int rc = 256; /* reasonable default */
1100
1101 switch (var->green.length) {
1102 case 8:
1103 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1104 break;
1105 case 5:
1106 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1107 break;
1108 case 6:
1109 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1110 break;
1111 default:
1112 /* should not occur */
1113 break;
1114 }
1115 return rc;
1116}
1117
1da177e4
LT		 1118/* ------------------------------------------------------------------------- *
1119 *
1120 * framebuffer operations
1121 *
1122 * ------------------------------------------------------------------------- */
1123
1124static int rivafb_open(struct fb_info *info, int user)
1125{
f4a41836 1126 struct riva_par *par = info->par;
1da177e4
LT		 1127 int cnt = atomic_read(&par->ref_count);
1128
1129 NVTRACE_ENTER();
1130 if (!cnt) {
1131#ifdef CONFIG_X86
1132 memset(&par->state, 0, sizeof(struct vgastate));
1133 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1134 /* save the DAC for Riva128 */
1135 if (par->riva.Architecture == NV_ARCH_03)
1136 par->state.flags |= VGA_SAVE_CMAP;
1137 save_vga(&par->state);
1138#endif
1139 /* vgaHWunlock() + riva unlock (0x7F) */
1140 CRTCout(par, 0x11, 0xFF);
1141 par->riva.LockUnlock(&par->riva, 0);
1142
1143 riva_save_state(par, &par->initial_state);
1144 }
1145 atomic_inc(&par->ref_count);
1146 NVTRACE_LEAVE();
1147 return 0;
1148}
1149
1150static int rivafb_release(struct fb_info *info, int user)
1151{
f4a41836 1152 struct riva_par *par = info->par;
1da177e4
LT		 1153 int cnt = atomic_read(&par->ref_count);
1154
1155 NVTRACE_ENTER();
1156 if (!cnt)
1157 return -EINVAL;
1158 if (cnt == 1) {
1159 par->riva.LockUnlock(&par->riva, 0);
1160 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1161 riva_load_state(par, &par->initial_state);
1162#ifdef CONFIG_X86
1163 restore_vga(&par->state);
1164#endif
1165 par->riva.LockUnlock(&par->riva, 1);
1166 }
1167 atomic_dec(&par->ref_count);
1168 NVTRACE_LEAVE();
1169 return 0;
1170}
1171
1172static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1173{
1174 struct fb_videomode *mode;
f4a41836 1175 struct riva_par *par = info->par;
1da177e4
LT		 1176 int nom, den; /* translating from pixels->bytes */
1177 int mode_valid = 0;
1178
1179 NVTRACE_ENTER();
1180 switch (var->bits_per_pixel) {
1181 case 1 ... 8:
1182 var->red.offset = var->green.offset = var->blue.offset = 0;
1183 var->red.length = var->green.length = var->blue.length = 8;
1184 var->bits_per_pixel = 8;
1185 nom = den = 1;
1186 break;
1187 case 9 ... 15:
1188 var->green.length = 5;
1189 /* fall through */
1190 case 16:
1191 var->bits_per_pixel = 16;
1192 /* The Riva128 supports RGB555 only */
1193 if (par->riva.Architecture == NV_ARCH_03)
1194 var->green.length = 5;
1195 if (var->green.length == 5) {
1196 /* 0rrrrrgg gggbbbbb */
1197 var->red.offset = 10;
1198 var->green.offset = 5;
1199 var->blue.offset = 0;
1200 var->red.length = 5;
1201 var->green.length = 5;
1202 var->blue.length = 5;
1203 } else {
1204 /* rrrrrggg gggbbbbb */
1205 var->red.offset = 11;
1206 var->green.offset = 5;
1207 var->blue.offset = 0;
1208 var->red.length = 5;
1209 var->green.length = 6;
1210 var->blue.length = 5;
1211 }
1212 nom = 2;
1213 den = 1;
1214 break;
1215 case 17 ... 32:
1216 var->red.length = var->green.length = var->blue.length = 8;
1217 var->bits_per_pixel = 32;
1218 var->red.offset = 16;
1219 var->green.offset = 8;
1220 var->blue.offset = 0;
1221 nom = 4;
1222 den = 1;
1223 break;
1224 default:
1225 printk(KERN_ERR PFX
1226 "mode %dx%dx%d rejected...color depth not supported.\n",
1227 var->xres, var->yres, var->bits_per_pixel);
1228 NVTRACE("EXIT, returning -EINVAL\n");
1229 return -EINVAL;
1230 }
1231
1232 if (!strictmode) {
1233 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1234 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1235 mode_valid = 1;
1236 }
1237
1238 /* calculate modeline if supported by monitor */
1239 if (!mode_valid && info->monspecs.gtf) {
1240 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1241 mode_valid = 1;
1242 }
1243
1244 if (!mode_valid) {
1245 mode = fb_find_best_mode(var, &info->modelist);
1246 if (mode) {
1247 riva_update_var(var, mode);
1248 mode_valid = 1;
1249 }
1250 }
1251
1252 if (!mode_valid && info->monspecs.modedb_len)
1253 return -EINVAL;
1254
1255 if (var->xres_virtual < var->xres)
1256 var->xres_virtual = var->xres;
1257 if (var->yres_virtual <= var->yres)
1258 var->yres_virtual = -1;
1259 if (rivafb_do_maximize(info, var, nom, den) < 0)
1260 return -EINVAL;
1261
1262 if (var->xoffset < 0)
1263 var->xoffset = 0;
1264 if (var->yoffset < 0)
1265 var->yoffset = 0;
1266
1267 /* truncate xoffset and yoffset to maximum if too high */
1268 if (var->xoffset > var->xres_virtual - var->xres)
1269 var->xoffset = var->xres_virtual - var->xres - 1;
1270
1271 if (var->yoffset > var->yres_virtual - var->yres)
1272 var->yoffset = var->yres_virtual - var->yres - 1;
1273
1274 var->red.msb_right =
1275 var->green.msb_right =
1276 var->blue.msb_right =
1277 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1278 NVTRACE_LEAVE();
1279 return 0;
1280}
1281
1282static int rivafb_set_par(struct fb_info *info)
1283{
f4a41836 1284 struct riva_par *par = info->par;
1da177e4
LT		 1285
1286 NVTRACE_ENTER();
1287 /* vgaHWunlock() + riva unlock (0x7F) */
1288 CRTCout(par, 0x11, 0xFF);
1289 par->riva.LockUnlock(&par->riva, 0);
1290 riva_load_video_mode(info);
1291 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1292 riva_setup_accel(info);
1293
1294 par->cursor_reset = 1;
1295 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1296 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1297 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1298
1299 if (info->flags & FBINFO_HWACCEL_DISABLED)
1300 info->pixmap.scan_align = 1;
1301 else
1302 info->pixmap.scan_align = 4;
1303 NVTRACE_LEAVE();
1304 return 0;
1305}
1306
1307/**
1308 * rivafb_pan_display
1309 * @var: standard kernel fb changeable data
1310 * @con: TODO
1311 * @info: pointer to fb_info object containing info for current riva board
1312 *
1313 * DESCRIPTION:
1314 * Pan (or wrap, depending on the `vmode' field) the display using the
1315 * `xoffset' and `yoffset' fields of the `var' structure.
1316 * If the values don't fit, return -EINVAL.
1317 *
1318 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1319 */
1320static int rivafb_pan_display(struct fb_var_screeninfo *var,
1321 struct fb_info *info)
1322{
f4a41836 1323 struct riva_par *par = info->par;
1da177e4
LT		 1324 unsigned int base;
1325
1326 NVTRACE_ENTER();
1da177e4 1327 base = var->yoffset * info->fix.line_length + var->xoffset;
1da177e4 1328 par->riva.SetStartAddress(&par->riva, base);
1da177e4
LT		 1329 NVTRACE_LEAVE();
1330 return 0;
1331}
1332
1333static int rivafb_blank(int blank, struct fb_info *info)
1334{
f4a41836 1335 struct riva_par *par= info->par;
1da177e4
LT		 1336 unsigned char tmp, vesa;
1337
1338 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1339 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1340
1341 NVTRACE_ENTER();
1342
1343 if (blank)
1344 tmp |= 0x20;
1345
1346 switch (blank) {
1347 case FB_BLANK_UNBLANK:
1348 case FB_BLANK_NORMAL:
1349 break;
1350 case FB_BLANK_VSYNC_SUSPEND:
1351 vesa |= 0x80;
1352 break;
1353 case FB_BLANK_HSYNC_SUSPEND:
1354 vesa |= 0x40;
1355 break;
1356 case FB_BLANK_POWERDOWN:
1357 vesa |= 0xc0;
1358 break;
1359 }
1360
1361 SEQout(par, 0x01, tmp);
1362 CRTCout(par, 0x1a, vesa);
1363
e01af038 1364 riva_bl_set_power(info, blank);
1da177e4
LT		 1365
1366 NVTRACE_LEAVE();
1367
1368 return 0;
1369}
1370
1371/**
1372 * rivafb_setcolreg
1373 * @regno: register index
1374 * @red: red component
1375 * @green: green component
1376 * @blue: blue component
1377 * @transp: transparency
1378 * @info: pointer to fb_info object containing info for current riva board
1379 *
1380 * DESCRIPTION:
1381 * Set a single color register. The values supplied have a 16 bit
1382 * magnitude.
1383 *
1384 * RETURNS:
1385 * Return != 0 for invalid regno.
1386 *
1387 * CALLED FROM:
1388 * fbcmap.c:fb_set_cmap()
1389 */
1390static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1391 unsigned blue, unsigned transp,
1392 struct fb_info *info)
1393{
f4a41836 1394 struct riva_par *par = info->par;
1da177e4
LT		 1395 RIVA_HW_INST *chip = &par->riva;
1396 int i;
1397
1398 if (regno >= riva_get_cmap_len(&info->var))
1399 return -EINVAL;
1400
1401 if (info->var.grayscale) {
1402 /* gray = 0.30*R + 0.59*G + 0.11*B */
1403 red = green = blue =
1404 (red * 77 + green * 151 + blue * 28) >> 8;
1405 }
1406
1407 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1408 ((u32 *) info->pseudo_palette)[regno] =
1409 (regno << info->var.red.offset) |
1410 (regno << info->var.green.offset) |
1411 (regno << info->var.blue.offset);
1412 /*
1413 * The Riva128 2D engine requires color information in
1414 * TrueColor format even if framebuffer is in DirectColor
1415 */
1416 if (par->riva.Architecture == NV_ARCH_03) {
1417 switch (info->var.bits_per_pixel) {
1418 case 16:
1419 par->palette[regno] = ((red & 0xf800) >> 1) |
1420 ((green & 0xf800) >> 6) |
1421 ((blue & 0xf800) >> 11);
1422 break;
1423 case 32:
1424 par->palette[regno] = ((red & 0xff00) << 8) |
1425 ((green & 0xff00)) |
1426 ((blue & 0xff00) >> 8);
1427 break;
1428 }
1429 }
1430 }
1431
1432 switch (info->var.bits_per_pixel) {
1433 case 8:
1434 /* "transparent" stuff is completely ignored. */
1435 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1436 break;
1437 case 16:
1438 if (info->var.green.length == 5) {
1439 for (i = 0; i < 8; i++) {
1440 riva_wclut(chip, regno*8+i, red >> 8,
1441 green >> 8, blue >> 8);
1442 }
1443 } else {
1444 u8 r, g, b;
1445
1446 if (regno < 32) {
1447 for (i = 0; i < 8; i++) {
1448 riva_wclut(chip, regno*8+i,
1449 red >> 8, green >> 8,
1450 blue >> 8);
1451 }
1452 }
1453 riva_rclut(chip, regno*4, &r, &g, &b);
1454 for (i = 0; i < 4; i++)
1455 riva_wclut(chip, regno*4+i, r,
1456 green >> 8, b);
1457 }
1458 break;
1459 case 32:
1460 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1461 break;
1462 default:
1463 /* do nothing */
1464 break;
1465 }
1466 return 0;
1467}
1468
1469/**
1470 * rivafb_fillrect - hardware accelerated color fill function
1471 * @info: pointer to fb_info structure
1472 * @rect: pointer to fb_fillrect structure
1473 *
1474 * DESCRIPTION:
1475 * This function fills up a region of framebuffer memory with a solid
1476 * color with a choice of two different ROP's, copy or invert.
1477 *
1478 * CALLED FROM:
1479 * framebuffer hook
1480 */
1481static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1482{
f4a41836 1483 struct riva_par *par = info->par;
1da177e4
LT		 1484 u_int color, rop = 0;
1485
1486 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1487 cfb_fillrect(info, rect);
1488 return;
1489 }
1490
1491 if (info->var.bits_per_pixel == 8)
1492 color = rect->color;
1493 else {
1494 if (par->riva.Architecture != NV_ARCH_03)
1495 color = ((u32 *)info->pseudo_palette)[rect->color];
1496 else
1497 color = par->palette[rect->color];
1498 }
1499
1500 switch (rect->rop) {
1501 case ROP_XOR:
1502 rop = 0x66;
1503 break;
1504 case ROP_COPY:
1505 default:
1506 rop = 0xCC;
1507 break;
1508 }
1509
1510 riva_set_rop_solid(par, rop);
1511
1512 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1513 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1514
1515 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1516 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1517 (rect->dx << 16) | rect->dy);
1518 mb();
1519 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1520 (rect->width << 16) | rect->height);
1521 mb();
1522 riva_set_rop_solid(par, 0xcc);
1523
1524}
1525
1526/**
1527 * rivafb_copyarea - hardware accelerated blit function
1528 * @info: pointer to fb_info structure
1529 * @region: pointer to fb_copyarea structure
1530 *
1531 * DESCRIPTION:
1532 * This copies an area of pixels from one location to another
1533 *
1534 * CALLED FROM:
1535 * framebuffer hook
1536 */
1537static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1538{
f4a41836 1539 struct riva_par *par = info->par;
1da177e4
LT		 1540
1541 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1542 cfb_copyarea(info, region);
1543 return;
1544 }
1545
1546 RIVA_FIFO_FREE(par->riva, Blt, 3);
1547 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1548 (region->sy << 16) | region->sx);
1549 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1550 (region->dy << 16) | region->dx);
1551 mb();
1552 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1553 (region->height << 16) | region->width);
1554 mb();
1555}
1556
1557static inline void convert_bgcolor_16(u32 *col)
1558{
1559 *col = ((*col & 0x0000F800) << 8)
1560 | ((*col & 0x00007E0) << 5)
1561 | ((*col & 0x0000001F) << 3)
1562 | 0xFF000000;
1563 mb();
1564}
1565
1566/**
1567 * rivafb_imageblit: hardware accelerated color expand function
1568 * @info: pointer to fb_info structure
1569 * @image: pointer to fb_image structure
1570 *
1571 * DESCRIPTION:
1572 * If the source is a monochrome bitmap, the function fills up a a region
1573 * of framebuffer memory with pixels whose color is determined by the bit
1574 * setting of the bitmap, 1 - foreground, 0 - background.
1575 *
1576 * If the source is not a monochrome bitmap, color expansion is not done.
1577 * In this case, it is channeled to a software function.
1578 *
1579 * CALLED FROM:
1580 * framebuffer hook
1581 */
1582static void rivafb_imageblit(struct fb_info *info,
1583 const struct fb_image *image)
1584{
f4a41836 1585 struct riva_par *par = info->par;
1da177e4
LT		 1586 u32 fgx = 0, bgx = 0, width, tmp;
1587 u8 *cdat = (u8 *) image->data;
1588 volatile u32 __iomem *d;
1589 int i, size;
1590
1591 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1592 cfb_imageblit(info, image);
1593 return;
1594 }
1595
1596 switch (info->var.bits_per_pixel) {
1597 case 8:
1598 fgx = image->fg_color;
1599 bgx = image->bg_color;
1600 break;
1601 case 16:
1602 case 32:
1603 if (par->riva.Architecture != NV_ARCH_03) {
1604 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1605 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1606 } else {
1607 fgx = par->palette[image->fg_color];
1608 bgx = par->palette[image->bg_color];
1609 }
1610 if (info->var.green.length == 6)
1611 convert_bgcolor_16(&bgx);
1612 break;
1613 }
1614
1615 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1616 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1617 (image->dy << 16) | (image->dx & 0xFFFF));
1618 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1619 (((image->dy + image->height) << 16) |
1620 ((image->dx + image->width) & 0xffff)));
1621 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1622 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1623 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1624 (image->height << 16) | ((image->width + 31) & ~31));
1625 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1626 (image->height << 16) | ((image->width + 31) & ~31));
1627 NV_WR32(&par->riva.Bitmap->PointE, 0,
1628 (image->dy << 16) | (image->dx & 0xFFFF));
1629
1630 d = &par->riva.Bitmap->MonochromeData01E;
1631
1632 width = (image->width + 31)/32;
1633 size = width * image->height;
1634 while (size >= 16) {
1635 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1636 for (i = 0; i < 16; i++) {
1637 tmp = *((u32 *)cdat);
1638 cdat = (u8 *)((u32 *)cdat + 1);
1639 reverse_order(&tmp);
1640 NV_WR32(d, i*4, tmp);
1641 }
1642 size -= 16;
1643 }
1644 if (size) {
1645 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1646 for (i = 0; i < size; i++) {
1647 tmp = *((u32 *) cdat);
1648 cdat = (u8 *)((u32 *)cdat + 1);
1649 reverse_order(&tmp);
1650 NV_WR32(d, i*4, tmp);
1651 }
1652 }
1653}
1654
1655/**
1656 * rivafb_cursor - hardware cursor function
1657 * @info: pointer to info structure
1658 * @cursor: pointer to fbcursor structure
1659 *
1660 * DESCRIPTION:
1661 * A cursor function that supports displaying a cursor image via hardware.
1662 * Within the kernel, copy and invert rops are supported. If exported
1663 * to user space, only the copy rop will be supported.
1664 *
1665 * CALLED FROM
1666 * framebuffer hook
1667 */
1668static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1669{
f4a41836 1670 struct riva_par *par = info->par;
1da177e4 1671 u8 data[MAX_CURS * MAX_CURS/8];
1da177e4 1672 int i, set = cursor->set;
f1ab5dac 1673 u16 fg, bg;
1da177e4 1674
f1ab5dac
JS		 1675 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1676 return -ENXIO;
1da177e4
LT		 1677
1678 par->riva.ShowHideCursor(&par->riva, 0);
1679
1680 if (par->cursor_reset) {
1681 set = FB_CUR_SETALL;
1682 par->cursor_reset = 0;
1683 }
1684
1685 if (set & FB_CUR_SETSIZE)
1686 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1687
1688 if (set & FB_CUR_SETPOS) {
1689 u32 xx, yy, temp;
1690
1691 yy = cursor->image.dy - info->var.yoffset;
1692 xx = cursor->image.dx - info->var.xoffset;
1693 temp = xx & 0xFFFF;
1694 temp |= yy << 16;
1695
1696 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1697 }
1698
1699
1700 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1701 u32 bg_idx = cursor->image.bg_color;
1702 u32 fg_idx = cursor->image.fg_color;
1703 u32 s_pitch = (cursor->image.width+7) >> 3;
1704 u32 d_pitch = MAX_CURS/8;
1705 u8 *dat = (u8 *) cursor->image.data;
1706 u8 *msk = (u8 *) cursor->mask;
1707 u8 *src;
1708
1709 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1710
1711 if (src) {
1712 switch (cursor->rop) {
1713 case ROP_XOR:
f1ab5dac 1714 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1715 src[i] = dat[i] ^ msk[i];
1716 break;
1717 case ROP_COPY:
1718 default:
f1ab5dac 1719 for (i = 0; i < s_pitch * cursor->image.height; i++)
1da177e4
LT		 1720 src[i] = dat[i] & msk[i];
1721 break;
1722 }
1723
f1ab5dac
JS		 1724 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1725 cursor->image.height);
1da177e4
LT		 1726
1727 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1728 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1729 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1730 1 << 15;
1731
1732 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1733 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1734 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1735 1 << 15;
1736
1737 par->riva.LockUnlock(&par->riva, 0);
1738
1739 rivafb_load_cursor_image(par, data, bg, fg,
1740 cursor->image.width,
1741 cursor->image.height);
1742 kfree(src);
1743 }
1744 }
1745
1746 if (cursor->enable)
1747 par->riva.ShowHideCursor(&par->riva, 1);
1748
1749 return 0;
1750}
1751
1752static int rivafb_sync(struct fb_info *info)
1753{
f4a41836 1754 struct riva_par *par = info->par;
1da177e4
LT		 1755
1756 wait_for_idle(par);
1757 return 0;
1758}
1759
1760/* ------------------------------------------------------------------------- *
1761 *
1762 * initialization helper functions
1763 *
1764 * ------------------------------------------------------------------------- */
1765
1766/* kernel interface */
1767static struct fb_ops riva_fb_ops = {
1768 .owner = THIS_MODULE,
1769 .fb_open = rivafb_open,
1770 .fb_release = rivafb_release,
1771 .fb_check_var = rivafb_check_var,
1772 .fb_set_par = rivafb_set_par,
1773 .fb_setcolreg = rivafb_setcolreg,
1774 .fb_pan_display = rivafb_pan_display,
1775 .fb_blank = rivafb_blank,
1776 .fb_fillrect = rivafb_fillrect,
1777 .fb_copyarea = rivafb_copyarea,
1778 .fb_imageblit = rivafb_imageblit,
1779 .fb_cursor = rivafb_cursor,
1780 .fb_sync = rivafb_sync,
1781};
1782
1783static int __devinit riva_set_fbinfo(struct fb_info *info)
1784{
1785 unsigned int cmap_len;
f4a41836 1786 struct riva_par *par = info->par;
1da177e4
LT		 1787
1788 NVTRACE_ENTER();
1789 info->flags = FBINFO_DEFAULT
1790 | FBINFO_HWACCEL_XPAN
1791 | FBINFO_HWACCEL_YPAN
1792 | FBINFO_HWACCEL_COPYAREA
1793 | FBINFO_HWACCEL_FILLRECT
1794 | FBINFO_HWACCEL_IMAGEBLIT;
1795
1796 /* Accel seems to not work properly on NV30 yet...*/
1797 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1798 printk(KERN_DEBUG PFX "disabling acceleration\n");
1799 info->flags |= FBINFO_HWACCEL_DISABLED;
1800 }
1801
1802 info->var = rivafb_default_var;
1803 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1804 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1805
1806 info->pseudo_palette = par->pseudo_palette;
1807
1808 cmap_len = riva_get_cmap_len(&info->var);
1809 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1810
1811 info->pixmap.size = 8 * 1024;
1812 info->pixmap.buf_align = 4;
58a60643 1813 info->pixmap.access_align = 32;
1da177e4
LT		 1814 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1815 info->var.yres_virtual = -1;
1816 NVTRACE_LEAVE();
1817 return (rivafb_check_var(&info->var, info));
1818}
1819
1820#ifdef CONFIG_PPC_OF
1821static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1822{
f4a41836 1823 struct riva_par *par = info->par;
1da177e4
LT		 1824 struct device_node *dp;
1825 unsigned char *pedid = NULL;
1826 unsigned char *disptype = NULL;
1827 static char *propnames[] = {
1828 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1829 int i;
1830
1831 NVTRACE_ENTER();
1832 dp = pci_device_to_OF_node(pd);
1833 for (; dp != NULL; dp = dp->child) {
1834 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1835 if (disptype == NULL)
1836 continue;
1837 if (strncmp(disptype, "LCD", 3) != 0)
1838 continue;
1839 for (i = 0; propnames[i] != NULL; ++i) {
1840 pedid = (unsigned char *)
1841 get_property(dp, propnames[i], NULL);
1842 if (pedid != NULL) {
1843 par->EDID = pedid;
1844 NVTRACE("LCD found.\n");
1845 return 1;
1846 }
1847 }
1848 }
1849 NVTRACE_LEAVE();
1850 return 0;
1851}
1852#endif /* CONFIG_PPC_OF */
1853
1854#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1855static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1856{
f4a41836 1857 struct riva_par *par = info->par;
1da177e4
LT		 1858 struct fb_var_screeninfo var;
1859 int i;
1860
1861 NVTRACE_ENTER();
1862 riva_create_i2c_busses(par);
1863 for (i = 0; i < par->bus; i++) {
1864 riva_probe_i2c_connector(par, i+1, &par->EDID);
1865 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1866 printk(PFX "Found EDID Block from BUS %i\n", i);
1867 break;
1868 }
1869 }
1870
1871 NVTRACE_LEAVE();
1872 return (par->EDID) ? 1 : 0;
1873}
1874#endif /* CONFIG_FB_RIVA_I2C */
1875
1876static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1877 struct fb_info *info)
1878{
1879 struct fb_monspecs *specs = &info->monspecs;
1880 struct fb_videomode modedb;
1881
1882 NVTRACE_ENTER();
1883 /* respect mode options */
1884 if (mode_option) {
1885 fb_find_mode(var, info, mode_option,
1886 specs->modedb, specs->modedb_len,
1887 NULL, 8);
1888 } else if (specs->modedb != NULL) {
1889 /* get preferred timing */
1890 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1891 int i;
1892
1893 for (i = 0; i < specs->modedb_len; i++) {
1894 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1895 modedb = specs->modedb[i];
1896 break;
1897 }
1898 }
1899 } else {
1900 /* otherwise, get first mode in database */
1901 modedb = specs->modedb[0];
1902 }
1903 var->bits_per_pixel = 8;
1904 riva_update_var(var, &modedb);
1905 }
1906 NVTRACE_LEAVE();
1907}
1908
1909
1910static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1911{
1912 NVTRACE_ENTER();
1913#ifdef CONFIG_PPC_OF
1914 if (!riva_get_EDID_OF(info, pdev))
1915 printk(PFX "could not retrieve EDID from OF\n");
44456d37 1916#elif defined(CONFIG_FB_RIVA_I2C)
1da177e4
LT		 1917 if (!riva_get_EDID_i2c(info))
1918 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1919#endif
1920 NVTRACE_LEAVE();
1921}
1922
1923
1924static void __devinit riva_get_edidinfo(struct fb_info *info)
1925{
1926 struct fb_var_screeninfo *var = &rivafb_default_var;
f4a41836 1927 struct riva_par *par = info->par;
1da177e4
LT		 1928
1929 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1930 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1931 &info->modelist);
1932 riva_update_default_var(var, info);
1933
1934 /* if user specified flatpanel, we respect that */
1935 if (info->monspecs.input & FB_DISP_DDI)
1936 par->FlatPanel = 1;
1937}
1938
1939/* ------------------------------------------------------------------------- *
1940 *
1941 * PCI bus
1942 *
1943 * ------------------------------------------------------------------------- */
1944
1945static u32 __devinit riva_get_arch(struct pci_dev *pd)
1946{
1947 u32 arch = 0;
1948
1949 switch (pd->device & 0x0ff0) {
1950 case 0x0100: /* GeForce 256 */
1951 case 0x0110: /* GeForce2 MX */
1952 case 0x0150: /* GeForce2 */
1953 case 0x0170: /* GeForce4 MX */
1954 case 0x0180: /* GeForce4 MX (8x AGP) */
1955 case 0x01A0: /* nForce */
1956 case 0x01F0: /* nForce2 */
1957 arch = NV_ARCH_10;
1958 break;
1959 case 0x0200: /* GeForce3 */
1960 case 0x0250: /* GeForce4 Ti */
1961 case 0x0280: /* GeForce4 Ti (8x AGP) */
1962 arch = NV_ARCH_20;
1963 break;
1964 case 0x0300: /* GeForceFX 5800 */
1965 case 0x0310: /* GeForceFX 5600 */
1966 case 0x0320: /* GeForceFX 5200 */
1967 case 0x0330: /* GeForceFX 5900 */
1968 case 0x0340: /* GeForceFX 5700 */
1969 arch = NV_ARCH_30;
1970 break;
1971 case 0x0020: /* TNT, TNT2 */
1972 arch = NV_ARCH_04;
1973 break;
1974 case 0x0010: /* Riva128 */
1975 arch = NV_ARCH_03;
1976 break;
1977 default: /* unknown architecture */
1978 break;
1979 }
1980 return arch;
1981}
1982
1983static int __devinit rivafb_probe(struct pci_dev *pd,
1984 const struct pci_device_id *ent)
1985{
1986 struct riva_par *default_par;
1987 struct fb_info *info;
1988 int ret;
1989
1990 NVTRACE_ENTER();
1991 assert(pd != NULL);
1992
1993 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1994 if (!info) {
1995 printk (KERN_ERR PFX "could not allocate memory\n");
1996 ret = -ENOMEM;
1997 goto err_ret;
1998 }
f4a41836 1999 default_par = info->par;
1da177e4
LT		 2000 default_par->pdev = pd;
2001
2002 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
2003 if (info->pixmap.addr == NULL) {
2004 ret = -ENOMEM;
2005 goto err_framebuffer_release;
2006 }
2007 memset(info->pixmap.addr, 0, 8 * 1024);
2008
2009 ret = pci_enable_device(pd);
2010 if (ret < 0) {
2011 printk(KERN_ERR PFX "cannot enable PCI device\n");
2012 goto err_free_pixmap;
2013 }
2014
2015 ret = pci_request_regions(pd, "rivafb");
2016 if (ret < 0) {
2017 printk(KERN_ERR PFX "cannot request PCI regions\n");
2018 goto err_disable_device;
2019 }
2020
2021 default_par->riva.Architecture = riva_get_arch(pd);
2022
2023 default_par->Chipset = (pd->vendor << 16) | pd->device;
2024 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
2025
1da177e4
LT		 2026 if(default_par->riva.Architecture == 0) {
2027 printk(KERN_ERR PFX "unknown NV_ARCH\n");
2028 ret=-ENODEV;
2029 goto err_release_region;
2030 }
2031 if(default_par->riva.Architecture == NV_ARCH_10 ||
2032 default_par->riva.Architecture == NV_ARCH_20 ||
2033 default_par->riva.Architecture == NV_ARCH_30) {
2034 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2035 } else {
2036 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2037 }
2038
2039 default_par->FlatPanel = flatpanel;
2040 if (flatpanel == 1)
2041 printk(KERN_INFO PFX "flatpanel support enabled\n");
2042 default_par->forceCRTC = forceCRTC;
2043
2044 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2045 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2046
2047 {
2048 /* enable IO and mem if not already done */
2049 unsigned short cmd;
2050
2051 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2052 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2053 pci_write_config_word(pd, PCI_COMMAND, cmd);
2054 }
2055
2056 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2057 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2058
2059 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2060 rivafb_fix.mmio_len);
2061 if (!default_par->ctrl_base) {
2062 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2063 ret = -EIO;
2064 goto err_release_region;
2065 }
2066
2067 switch (default_par->riva.Architecture) {
2068 case NV_ARCH_03:
2069 /* Riva128's PRAMIN is in the "framebuffer" space
2070 * Since these cards were never made with more than 8 megabytes
2071 * we can safely allocate this separately.
2072 */
2073 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2074 if (!default_par->riva.PRAMIN) {
2075 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2076 ret = -EIO;
2077 goto err_iounmap_ctrl_base;
2078 }
2079 break;
2080 case NV_ARCH_04:
2081 case NV_ARCH_10:
2082 case NV_ARCH_20:
2083 case NV_ARCH_30:
2084 default_par->riva.PCRTC0 =
2085 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2086 default_par->riva.PRAMIN =
2087 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2088 break;
2089 }
2090 riva_common_setup(default_par);
2091
2092 if (default_par->riva.Architecture == NV_ARCH_03) {
2093 default_par->riva.PCRTC = default_par->riva.PCRTC0
2094 = default_par->riva.PGRAPH;
2095 }
2096
2097 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2098 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2099 info->screen_base = ioremap(rivafb_fix.smem_start,
2100 rivafb_fix.smem_len);
2101 if (!info->screen_base) {
2102 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2103 ret = -EIO;
2104 goto err_iounmap_pramin;
2105 }
2106
2107#ifdef CONFIG_MTRR
2108 if (!nomtrr) {
2109 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2110 rivafb_fix.smem_len,
2111 MTRR_TYPE_WRCOMB, 1);
2112 if (default_par->mtrr.vram < 0) {
2113 printk(KERN_ERR PFX "unable to setup MTRR\n");
2114 } else {
2115 default_par->mtrr.vram_valid = 1;
2116 /* let there be speed */
2117 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2118 }
2119 }
2120#endif /* CONFIG_MTRR */
2121
2122 info->fbops = &riva_fb_ops;
2123 info->fix = rivafb_fix;
2124 riva_get_EDID(info, pd);
2125 riva_get_edidinfo(info);
2126
2127 ret=riva_set_fbinfo(info);
2128 if (ret < 0) {
2129 printk(KERN_ERR PFX "error setting initial video mode\n");
2130 goto err_iounmap_screen_base;
2131 }
2132
2133 fb_destroy_modedb(info->monspecs.modedb);
2134 info->monspecs.modedb = NULL;
ce38cac4
GG		 2135
2136 pci_set_drvdata(pd, info);
2137 riva_bl_init(info->par);
1da177e4
LT		 2138 ret = register_framebuffer(info);
2139 if (ret < 0) {
2140 printk(KERN_ERR PFX
2141 "error registering riva framebuffer\n");
2142 goto err_iounmap_screen_base;
2143 }
2144
1da177e4
LT		 2145 printk(KERN_INFO PFX
2146 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2147 info->fix.id,
2148 RIVAFB_VERSION,
2149 info->fix.smem_len / (1024 * 1024),
2150 info->fix.smem_start);
5474c120 2151
1da177e4
LT		 2152 NVTRACE_LEAVE();
2153 return 0;
2154
2155err_iounmap_screen_base:
2156#ifdef CONFIG_FB_RIVA_I2C
f4a41836 2157 riva_delete_i2c_busses(info->par);
1da177e4
LT		 2158#endif
2159 iounmap(info->screen_base);
2160err_iounmap_pramin:
2161 if (default_par->riva.Architecture == NV_ARCH_03)
2162 iounmap(default_par->riva.PRAMIN);
2163err_iounmap_ctrl_base:
2164 iounmap(default_par->ctrl_base);
2165err_release_region:
2166 pci_release_regions(pd);
2167err_disable_device:
1da177e4
LT		 2168err_free_pixmap:
2169 kfree(info->pixmap.addr);
2170err_framebuffer_release:
2171 framebuffer_release(info);
2172err_ret:
2173 return ret;
2174}
2175
2176static void __exit rivafb_remove(struct pci_dev *pd)
2177{
2178 struct fb_info *info = pci_get_drvdata(pd);
f4a41836 2179 struct riva_par *par = info->par;
1da177e4
LT		 2180
2181 NVTRACE_ENTER();
1da177e4 2182
5474c120
MH		 2183 riva_bl_exit(par);
2184
1da177e4
LT		 2185#ifdef CONFIG_FB_RIVA_I2C
2186 riva_delete_i2c_busses(par);
2187 kfree(par->EDID);
2188#endif
2189
2190 unregister_framebuffer(info);
2191#ifdef CONFIG_MTRR
2192 if (par->mtrr.vram_valid)
2193 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2194 info->fix.smem_len);
2195#endif /* CONFIG_MTRR */
2196
2197 iounmap(par->ctrl_base);
2198 iounmap(info->screen_base);
2199 if (par->riva.Architecture == NV_ARCH_03)
2200 iounmap(par->riva.PRAMIN);
2201 pci_release_regions(pd);
1da177e4
LT		 2202 kfree(info->pixmap.addr);
2203 framebuffer_release(info);
2204 pci_set_drvdata(pd, NULL);
2205 NVTRACE_LEAVE();
2206}
2207
2208/* ------------------------------------------------------------------------- *
2209 *
2210 * initialization
2211 *
2212 * ------------------------------------------------------------------------- */
2213
2214#ifndef MODULE
2215static int __init rivafb_setup(char *options)
2216{
2217 char *this_opt;
2218
2219 NVTRACE_ENTER();
2220 if (!options || !*options)
2221 return 0;
2222
2223 while ((this_opt = strsep(&options, ",")) != NULL) {
2224 if (!strncmp(this_opt, "forceCRTC", 9)) {
2225 char *p;
2226
2227 p = this_opt + 9;
2228 if (!*p || !*(++p)) continue;
2229 forceCRTC = *p - '0';
2230 if (forceCRTC < 0 || forceCRTC > 1)
2231 forceCRTC = -1;
2232 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2233 flatpanel = 1;
2234#ifdef CONFIG_MTRR
2235 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2236 nomtrr = 1;
2237#endif
2238 } else if (!strncmp(this_opt, "strictmode", 10)) {
2239 strictmode = 1;
2240 } else if (!strncmp(this_opt, "noaccel", 7)) {
2241 noaccel = 1;
2242 } else
2243 mode_option = this_opt;
2244 }
2245 NVTRACE_LEAVE();
2246 return 0;
2247}
2248#endif /* !MODULE */
2249
2250static struct pci_driver rivafb_driver = {
2251 .name = "rivafb",
2252 .id_table = rivafb_pci_tbl,
2253 .probe = rivafb_probe,
2254 .remove = __exit_p(rivafb_remove),
2255};
2256
2257
2258
2259/* ------------------------------------------------------------------------- *
2260 *
2261 * modularization
2262 *
2263 * ------------------------------------------------------------------------- */
2264
2265static int __devinit rivafb_init(void)
2266{
2267#ifndef MODULE
2268 char *option = NULL;
2269
2270 if (fb_get_options("rivafb", &option))
2271 return -ENODEV;
2272 rivafb_setup(option);
2273#endif
2274 return pci_register_driver(&rivafb_driver);
2275}
2276
2277
2278module_init(rivafb_init);
2279
2280#ifdef MODULE
2281static void __exit rivafb_exit(void)
2282{
2283 pci_unregister_driver(&rivafb_driver);
2284}
2285
2286module_exit(rivafb_exit);
2287#endif /* MODULE */
2288
2289module_param(noaccel, bool, 0);
2290MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2291module_param(flatpanel, int, 0);
2292MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2293module_param(forceCRTC, int, 0);
2294MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2295#ifdef CONFIG_MTRR
2296module_param(nomtrr, bool, 0);
2297MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2298#endif
2299module_param(strictmode, bool, 0);
2300MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2301
2302MODULE_AUTHOR("Ani Joshi, maintainer");
2303MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2304MODULE_LICENSE("GPL");
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