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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver | |
3 | * | |
4 | * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> | |
5 | * | |
6 | * Copyright 1999-2000 Jeff Garzik | |
7 | * | |
8 | * Contributors: | |
9 | * | |
10 | * Ani Joshi: Lots of debugging and cleanup work, really helped | |
11 | * get the driver going | |
12 | * | |
13 | * Ferenc Bakonyi: Bug fixes, cleanup, modularization | |
14 | * | |
15 | * Jindrich Makovicka: Accel code help, hw cursor, mtrr | |
16 | * | |
17 | * Paul Richards: Bug fixes, updates | |
18 | * | |
19 | * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven | |
20 | * Includes riva_hw.c from nVidia, see copyright below. | |
21 | * KGI code provided the basis for state storage, init, and mode switching. | |
22 | * | |
23 | * This file is subject to the terms and conditions of the GNU General Public | |
24 | * License. See the file COPYING in the main directory of this archive | |
25 | * for more details. | |
26 | * | |
27 | * Known bugs and issues: | |
28 | * restoring text mode fails | |
29 | * doublescan modes are broken | |
30 | */ | |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/kernel.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/mm.h> | |
1da177e4 LT |
37 | #include <linux/slab.h> |
38 | #include <linux/delay.h> | |
39 | #include <linux/fb.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/pci.h> | |
5474c120 | 42 | #include <linux/backlight.h> |
1c667682 | 43 | #include <linux/bitrev.h> |
1da177e4 LT |
44 | #ifdef CONFIG_MTRR |
45 | #include <asm/mtrr.h> | |
46 | #endif | |
47 | #ifdef CONFIG_PPC_OF | |
48 | #include <asm/prom.h> | |
49 | #include <asm/pci-bridge.h> | |
50 | #endif | |
51 | #ifdef CONFIG_PMAC_BACKLIGHT | |
e8222502 | 52 | #include <asm/machdep.h> |
1da177e4 LT |
53 | #include <asm/backlight.h> |
54 | #endif | |
55 | ||
56 | #include "rivafb.h" | |
57 | #include "nvreg.h" | |
58 | ||
59 | #ifndef CONFIG_PCI /* sanity check */ | |
60 | #error This driver requires PCI support. | |
61 | #endif | |
62 | ||
63 | /* version number of this driver */ | |
64 | #define RIVAFB_VERSION "0.9.5b" | |
65 | ||
66 | /* ------------------------------------------------------------------------- * | |
67 | * | |
68 | * various helpful macros and constants | |
69 | * | |
70 | * ------------------------------------------------------------------------- */ | |
71 | #ifdef CONFIG_FB_RIVA_DEBUG | |
72 | #define NVTRACE printk | |
73 | #else | |
74 | #define NVTRACE if(0) printk | |
75 | #endif | |
76 | ||
77 | #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__) | |
78 | #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__) | |
79 | ||
80 | #ifdef CONFIG_FB_RIVA_DEBUG | |
81 | #define assert(expr) \ | |
82 | if(!(expr)) { \ | |
83 | printk( "Assertion failed! %s,%s,%s,line=%d\n",\ | |
84 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
85 | BUG(); \ | |
86 | } | |
87 | #else | |
88 | #define assert(expr) | |
89 | #endif | |
90 | ||
91 | #define PFX "rivafb: " | |
92 | ||
93 | /* macro that allows you to set overflow bits */ | |
94 | #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) | |
95 | #define SetBit(n) (1<<(n)) | |
96 | #define Set8Bits(value) ((value)&0xff) | |
97 | ||
98 | /* HW cursor parameters */ | |
99 | #define MAX_CURS 32 | |
100 | ||
101 | /* ------------------------------------------------------------------------- * | |
102 | * | |
103 | * prototypes | |
104 | * | |
105 | * ------------------------------------------------------------------------- */ | |
106 | ||
107 | static int rivafb_blank(int blank, struct fb_info *info); | |
108 | ||
109 | /* ------------------------------------------------------------------------- * | |
110 | * | |
111 | * card identification | |
112 | * | |
113 | * ------------------------------------------------------------------------- */ | |
114 | ||
115 | static struct pci_device_id rivafb_pci_tbl[] = { | |
116 | { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, | |
117 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
118 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, | |
119 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
120 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, | |
121 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
122 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, | |
123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
124 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, | |
125 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
126 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, | |
127 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
128 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, | |
129 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
130 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, | |
131 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
132 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, | |
133 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
134 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, | |
135 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
136 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, | |
137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
138 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, | |
139 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
140 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, | |
141 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
142 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, | |
143 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
144 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, | |
145 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
146 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, | |
147 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
148 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, | |
149 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
150 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, | |
151 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
152 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, | |
153 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
154 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, | |
155 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
156 | // NF2/IGP version, GeForce 4 MX, NV18 | |
157 | { PCI_VENDOR_ID_NVIDIA, 0x01f0, | |
158 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
159 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, | |
160 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
161 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, | |
162 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
163 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, | |
164 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
165 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, | |
166 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
167 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, | |
168 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
169 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, | |
170 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
171 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, | |
172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
173 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, | |
174 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
175 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, | |
176 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
177 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, | |
178 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
179 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, | |
180 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
181 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, | |
182 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
183 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, | |
184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
185 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, | |
186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
187 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, | |
188 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
189 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, | |
190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
191 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, | |
192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
193 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, | |
194 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
195 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, | |
196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
197 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, | |
198 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
199 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, | |
200 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
201 | { 0, } /* terminate list */ | |
202 | }; | |
203 | MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); | |
204 | ||
205 | /* ------------------------------------------------------------------------- * | |
206 | * | |
207 | * global variables | |
208 | * | |
209 | * ------------------------------------------------------------------------- */ | |
210 | ||
211 | /* command line data, set in rivafb_setup() */ | |
212 | static int flatpanel __devinitdata = -1; /* Autodetect later */ | |
213 | static int forceCRTC __devinitdata = -1; | |
214 | static int noaccel __devinitdata = 0; | |
215 | #ifdef CONFIG_MTRR | |
216 | static int nomtrr __devinitdata = 0; | |
217 | #endif | |
218 | ||
219 | static char *mode_option __devinitdata = NULL; | |
220 | static int strictmode = 0; | |
221 | ||
222 | static struct fb_fix_screeninfo __devinitdata rivafb_fix = { | |
223 | .type = FB_TYPE_PACKED_PIXELS, | |
224 | .xpanstep = 1, | |
225 | .ypanstep = 1, | |
226 | }; | |
227 | ||
228 | static struct fb_var_screeninfo __devinitdata rivafb_default_var = { | |
229 | .xres = 640, | |
230 | .yres = 480, | |
231 | .xres_virtual = 640, | |
232 | .yres_virtual = 480, | |
233 | .bits_per_pixel = 8, | |
234 | .red = {0, 8, 0}, | |
235 | .green = {0, 8, 0}, | |
236 | .blue = {0, 8, 0}, | |
237 | .transp = {0, 0, 0}, | |
238 | .activate = FB_ACTIVATE_NOW, | |
239 | .height = -1, | |
240 | .width = -1, | |
241 | .pixclock = 39721, | |
242 | .left_margin = 40, | |
243 | .right_margin = 24, | |
244 | .upper_margin = 32, | |
245 | .lower_margin = 11, | |
246 | .hsync_len = 96, | |
247 | .vsync_len = 2, | |
248 | .vmode = FB_VMODE_NONINTERLACED | |
249 | }; | |
250 | ||
251 | /* from GGI */ | |
252 | static const struct riva_regs reg_template = { | |
253 | {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ | |
254 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
255 | 0x41, 0x01, 0x0F, 0x00, 0x00}, | |
256 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ | |
257 | 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, | |
258 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ | |
259 | 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
260 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ | |
261 | 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
262 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ | |
263 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
264 | 0x00, /* 0x40 */ | |
265 | }, | |
266 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ | |
267 | 0xFF}, | |
268 | {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ | |
269 | 0xEB /* MISC */ | |
270 | }; | |
271 | ||
272 | /* | |
273 | * Backlight control | |
274 | */ | |
5474c120 MH |
275 | #ifdef CONFIG_FB_RIVA_BACKLIGHT |
276 | /* We do not have any information about which values are allowed, thus | |
277 | * we used safe values. | |
278 | */ | |
279 | #define MIN_LEVEL 0x158 | |
280 | #define MAX_LEVEL 0x534 | |
e01af038 | 281 | #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) |
1da177e4 | 282 | |
5474c120 MH |
283 | static struct backlight_properties riva_bl_data; |
284 | ||
e01af038 | 285 | /* Call with fb_info->bl_mutex held */ |
5474c120 MH |
286 | static int riva_bl_get_level_brightness(struct riva_par *par, |
287 | int level) | |
288 | { | |
289 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
290 | int nlevel; | |
291 | ||
292 | /* Get and convert the value */ | |
e01af038 | 293 | nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; |
5474c120 MH |
294 | |
295 | if (nlevel < 0) | |
296 | nlevel = 0; | |
297 | else if (nlevel < MIN_LEVEL) | |
298 | nlevel = MIN_LEVEL; | |
299 | else if (nlevel > MAX_LEVEL) | |
300 | nlevel = MAX_LEVEL; | |
301 | ||
302 | return nlevel; | |
303 | } | |
304 | ||
e01af038 MH |
305 | /* Call with fb_info->bl_mutex held */ |
306 | static int __riva_bl_update_status(struct backlight_device *bd) | |
5474c120 MH |
307 | { |
308 | struct riva_par *par = class_get_devdata(&bd->class_dev); | |
309 | U032 tmp_pcrt, tmp_pmc; | |
310 | int level; | |
311 | ||
312 | if (bd->props->power != FB_BLANK_UNBLANK || | |
313 | bd->props->fb_blank != FB_BLANK_UNBLANK) | |
314 | level = 0; | |
315 | else | |
316 | level = bd->props->brightness; | |
317 | ||
318 | tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF; | |
319 | tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC; | |
320 | if(level > 0) { | |
321 | tmp_pcrt |= 0x1; | |
322 | tmp_pmc |= (1 << 31); /* backlight bit */ | |
323 | tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ | |
324 | } | |
325 | par->riva.PCRTC0[0x081C/4] = tmp_pcrt; | |
326 | par->riva.PMC[0x10F0/4] = tmp_pmc; | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
e01af038 MH |
331 | static int riva_bl_update_status(struct backlight_device *bd) |
332 | { | |
333 | struct riva_par *par = class_get_devdata(&bd->class_dev); | |
334 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
335 | int ret; | |
336 | ||
337 | mutex_lock(&info->bl_mutex); | |
338 | ret = __riva_bl_update_status(bd); | |
339 | mutex_unlock(&info->bl_mutex); | |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
5474c120 MH |
344 | static int riva_bl_get_brightness(struct backlight_device *bd) |
345 | { | |
346 | return bd->props->brightness; | |
347 | } | |
1da177e4 | 348 | |
5474c120 MH |
349 | static struct backlight_properties riva_bl_data = { |
350 | .owner = THIS_MODULE, | |
351 | .get_brightness = riva_bl_get_brightness, | |
352 | .update_status = riva_bl_update_status, | |
353 | .max_brightness = (FB_BACKLIGHT_LEVELS - 1), | |
1da177e4 | 354 | }; |
5474c120 | 355 | |
e01af038 MH |
356 | static void riva_bl_set_power(struct fb_info *info, int power) |
357 | { | |
358 | mutex_lock(&info->bl_mutex); | |
a9303638 BH |
359 | |
360 | if (info->bl_dev) { | |
361 | down(&info->bl_dev->sem); | |
362 | info->bl_dev->props->power = power; | |
363 | __riva_bl_update_status(info->bl_dev); | |
364 | up(&info->bl_dev->sem); | |
365 | } | |
366 | ||
e01af038 MH |
367 | mutex_unlock(&info->bl_mutex); |
368 | } | |
369 | ||
5474c120 MH |
370 | static void riva_bl_init(struct riva_par *par) |
371 | { | |
372 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
373 | struct backlight_device *bd; | |
374 | char name[12]; | |
375 | ||
376 | if (!par->FlatPanel) | |
377 | return; | |
378 | ||
379 | #ifdef CONFIG_PMAC_BACKLIGHT | |
380 | if (!machine_is(powermac) || | |
381 | !pmac_has_backlight_type("mnca")) | |
382 | return; | |
383 | #endif | |
384 | ||
385 | snprintf(name, sizeof(name), "rivabl%d", info->node); | |
386 | ||
387 | bd = backlight_device_register(name, par, &riva_bl_data); | |
388 | if (IS_ERR(bd)) { | |
389 | info->bl_dev = NULL; | |
98a3c781 | 390 | printk(KERN_WARNING "riva: Backlight registration failed\n"); |
5474c120 MH |
391 | goto error; |
392 | } | |
393 | ||
394 | mutex_lock(&info->bl_mutex); | |
395 | info->bl_dev = bd; | |
396 | fb_bl_default_curve(info, 0, | |
535a09ad GG |
397 | MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, |
398 | FB_BACKLIGHT_MAX); | |
5474c120 MH |
399 | mutex_unlock(&info->bl_mutex); |
400 | ||
a9303638 | 401 | down(&bd->sem); |
5474c120 MH |
402 | bd->props->brightness = riva_bl_data.max_brightness; |
403 | bd->props->power = FB_BLANK_UNBLANK; | |
404 | bd->props->update_status(bd); | |
a9303638 | 405 | up(&bd->sem); |
5474c120 MH |
406 | |
407 | #ifdef CONFIG_PMAC_BACKLIGHT | |
408 | mutex_lock(&pmac_backlight_mutex); | |
409 | if (!pmac_backlight) | |
410 | pmac_backlight = bd; | |
411 | mutex_unlock(&pmac_backlight_mutex); | |
412 | #endif | |
413 | ||
414 | printk("riva: Backlight initialized (%s)\n", name); | |
415 | ||
416 | return; | |
417 | ||
418 | error: | |
419 | return; | |
420 | } | |
421 | ||
422 | static void riva_bl_exit(struct riva_par *par) | |
423 | { | |
424 | struct fb_info *info = pci_get_drvdata(par->pdev); | |
425 | ||
426 | #ifdef CONFIG_PMAC_BACKLIGHT | |
427 | mutex_lock(&pmac_backlight_mutex); | |
428 | #endif | |
429 | ||
430 | mutex_lock(&info->bl_mutex); | |
431 | if (info->bl_dev) { | |
432 | #ifdef CONFIG_PMAC_BACKLIGHT | |
433 | if (pmac_backlight == info->bl_dev) | |
434 | pmac_backlight = NULL; | |
435 | #endif | |
436 | ||
437 | backlight_device_unregister(info->bl_dev); | |
438 | ||
439 | printk("riva: Backlight unloaded\n"); | |
440 | } | |
441 | mutex_unlock(&info->bl_mutex); | |
442 | ||
443 | #ifdef CONFIG_PMAC_BACKLIGHT | |
444 | mutex_unlock(&pmac_backlight_mutex); | |
445 | #endif | |
446 | } | |
447 | #else | |
448 | static inline void riva_bl_init(struct riva_par *par) {} | |
449 | static inline void riva_bl_exit(struct riva_par *par) {} | |
e01af038 | 450 | static inline void riva_bl_set_power(struct fb_info *info, int power) {} |
5474c120 | 451 | #endif /* CONFIG_FB_RIVA_BACKLIGHT */ |
1da177e4 LT |
452 | |
453 | /* ------------------------------------------------------------------------- * | |
454 | * | |
455 | * MMIO access macros | |
456 | * | |
457 | * ------------------------------------------------------------------------- */ | |
458 | ||
459 | static inline void CRTCout(struct riva_par *par, unsigned char index, | |
460 | unsigned char val) | |
461 | { | |
462 | VGA_WR08(par->riva.PCIO, 0x3d4, index); | |
463 | VGA_WR08(par->riva.PCIO, 0x3d5, val); | |
464 | } | |
465 | ||
466 | static inline unsigned char CRTCin(struct riva_par *par, | |
467 | unsigned char index) | |
468 | { | |
469 | VGA_WR08(par->riva.PCIO, 0x3d4, index); | |
470 | return (VGA_RD08(par->riva.PCIO, 0x3d5)); | |
471 | } | |
472 | ||
473 | static inline void GRAout(struct riva_par *par, unsigned char index, | |
474 | unsigned char val) | |
475 | { | |
476 | VGA_WR08(par->riva.PVIO, 0x3ce, index); | |
477 | VGA_WR08(par->riva.PVIO, 0x3cf, val); | |
478 | } | |
479 | ||
480 | static inline unsigned char GRAin(struct riva_par *par, | |
481 | unsigned char index) | |
482 | { | |
483 | VGA_WR08(par->riva.PVIO, 0x3ce, index); | |
484 | return (VGA_RD08(par->riva.PVIO, 0x3cf)); | |
485 | } | |
486 | ||
487 | static inline void SEQout(struct riva_par *par, unsigned char index, | |
488 | unsigned char val) | |
489 | { | |
490 | VGA_WR08(par->riva.PVIO, 0x3c4, index); | |
491 | VGA_WR08(par->riva.PVIO, 0x3c5, val); | |
492 | } | |
493 | ||
494 | static inline unsigned char SEQin(struct riva_par *par, | |
495 | unsigned char index) | |
496 | { | |
497 | VGA_WR08(par->riva.PVIO, 0x3c4, index); | |
498 | return (VGA_RD08(par->riva.PVIO, 0x3c5)); | |
499 | } | |
500 | ||
501 | static inline void ATTRout(struct riva_par *par, unsigned char index, | |
502 | unsigned char val) | |
503 | { | |
504 | VGA_WR08(par->riva.PCIO, 0x3c0, index); | |
505 | VGA_WR08(par->riva.PCIO, 0x3c0, val); | |
506 | } | |
507 | ||
508 | static inline unsigned char ATTRin(struct riva_par *par, | |
509 | unsigned char index) | |
510 | { | |
511 | VGA_WR08(par->riva.PCIO, 0x3c0, index); | |
512 | return (VGA_RD08(par->riva.PCIO, 0x3c1)); | |
513 | } | |
514 | ||
515 | static inline void MISCout(struct riva_par *par, unsigned char val) | |
516 | { | |
517 | VGA_WR08(par->riva.PVIO, 0x3c2, val); | |
518 | } | |
519 | ||
520 | static inline unsigned char MISCin(struct riva_par *par) | |
521 | { | |
522 | return (VGA_RD08(par->riva.PVIO, 0x3cc)); | |
523 | } | |
524 | ||
1da177e4 LT |
525 | static inline void reverse_order(u32 *l) |
526 | { | |
527 | u8 *a = (u8 *)l; | |
1c667682 AM |
528 | a[0] = bitrev8(a[0]); |
529 | a[1] = bitrev8(a[1]); | |
530 | a[2] = bitrev8(a[2]); | |
531 | a[3] = bitrev8(a[3]); | |
1da177e4 LT |
532 | } |
533 | ||
534 | /* ------------------------------------------------------------------------- * | |
535 | * | |
536 | * cursor stuff | |
537 | * | |
538 | * ------------------------------------------------------------------------- */ | |
539 | ||
540 | /** | |
541 | * rivafb_load_cursor_image - load cursor image to hardware | |
542 | * @data: address to monochrome bitmap (1 = foreground color, 0 = background) | |
543 | * @par: pointer to private data | |
544 | * @w: width of cursor image in pixels | |
545 | * @h: height of cursor image in scanlines | |
546 | * @bg: background color (ARGB1555) - alpha bit determines opacity | |
547 | * @fg: foreground color (ARGB1555) | |
548 | * | |
549 | * DESCRIPTiON: | |
550 | * Loads cursor image based on a monochrome source and mask bitmap. The | |
551 | * image bits determines the color of the pixel, 0 for background, 1 for | |
552 | * foreground. Only the affected region (as determined by @w and @h | |
553 | * parameters) will be updated. | |
554 | * | |
555 | * CALLED FROM: | |
556 | * rivafb_cursor() | |
557 | */ | |
558 | static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, | |
559 | u16 bg, u16 fg, u32 w, u32 h) | |
560 | { | |
561 | int i, j, k = 0; | |
562 | u32 b, tmp; | |
563 | u32 *data = (u32 *)data8; | |
564 | bg = le16_to_cpu(bg); | |
565 | fg = le16_to_cpu(fg); | |
566 | ||
567 | w = (w + 1) & ~1; | |
568 | ||
569 | for (i = 0; i < h; i++) { | |
570 | b = *data++; | |
571 | reverse_order(&b); | |
572 | ||
573 | for (j = 0; j < w/2; j++) { | |
574 | tmp = 0; | |
575 | #if defined (__BIG_ENDIAN) | |
576 | tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; | |
577 | b <<= 1; | |
578 | tmp |= (b & (1 << 31)) ? fg : bg; | |
579 | b <<= 1; | |
580 | #else | |
581 | tmp = (b & 1) ? fg : bg; | |
582 | b >>= 1; | |
583 | tmp |= (b & 1) ? fg << 16 : bg << 16; | |
584 | b >>= 1; | |
585 | #endif | |
586 | writel(tmp, &par->riva.CURSOR[k++]); | |
587 | } | |
588 | k += (MAX_CURS - w)/2; | |
589 | } | |
590 | } | |
591 | ||
592 | /* ------------------------------------------------------------------------- * | |
593 | * | |
594 | * general utility functions | |
595 | * | |
596 | * ------------------------------------------------------------------------- */ | |
597 | ||
598 | /** | |
599 | * riva_wclut - set CLUT entry | |
600 | * @chip: pointer to RIVA_HW_INST object | |
601 | * @regnum: register number | |
602 | * @red: red component | |
603 | * @green: green component | |
604 | * @blue: blue component | |
605 | * | |
606 | * DESCRIPTION: | |
607 | * Sets color register @regnum. | |
608 | * | |
609 | * CALLED FROM: | |
610 | * rivafb_setcolreg() | |
611 | */ | |
612 | static void riva_wclut(RIVA_HW_INST *chip, | |
613 | unsigned char regnum, unsigned char red, | |
614 | unsigned char green, unsigned char blue) | |
615 | { | |
616 | VGA_WR08(chip->PDIO, 0x3c8, regnum); | |
617 | VGA_WR08(chip->PDIO, 0x3c9, red); | |
618 | VGA_WR08(chip->PDIO, 0x3c9, green); | |
619 | VGA_WR08(chip->PDIO, 0x3c9, blue); | |
620 | } | |
621 | ||
622 | /** | |
623 | * riva_rclut - read fromCLUT register | |
624 | * @chip: pointer to RIVA_HW_INST object | |
625 | * @regnum: register number | |
626 | * @red: red component | |
627 | * @green: green component | |
628 | * @blue: blue component | |
629 | * | |
630 | * DESCRIPTION: | |
631 | * Reads red, green, and blue from color register @regnum. | |
632 | * | |
633 | * CALLED FROM: | |
634 | * rivafb_setcolreg() | |
635 | */ | |
636 | static void riva_rclut(RIVA_HW_INST *chip, | |
637 | unsigned char regnum, unsigned char *red, | |
638 | unsigned char *green, unsigned char *blue) | |
639 | { | |
640 | ||
641 | VGA_WR08(chip->PDIO, 0x3c7, regnum); | |
642 | *red = VGA_RD08(chip->PDIO, 0x3c9); | |
643 | *green = VGA_RD08(chip->PDIO, 0x3c9); | |
644 | *blue = VGA_RD08(chip->PDIO, 0x3c9); | |
645 | } | |
646 | ||
647 | /** | |
648 | * riva_save_state - saves current chip state | |
649 | * @par: pointer to riva_par object containing info for current riva board | |
650 | * @regs: pointer to riva_regs object | |
651 | * | |
652 | * DESCRIPTION: | |
653 | * Saves current chip state to @regs. | |
654 | * | |
655 | * CALLED FROM: | |
656 | * rivafb_probe() | |
657 | */ | |
658 | /* from GGI */ | |
659 | static void riva_save_state(struct riva_par *par, struct riva_regs *regs) | |
660 | { | |
661 | int i; | |
662 | ||
663 | NVTRACE_ENTER(); | |
664 | par->riva.LockUnlock(&par->riva, 0); | |
665 | ||
666 | par->riva.UnloadStateExt(&par->riva, ®s->ext); | |
667 | ||
668 | regs->misc_output = MISCin(par); | |
669 | ||
670 | for (i = 0; i < NUM_CRT_REGS; i++) | |
671 | regs->crtc[i] = CRTCin(par, i); | |
672 | ||
673 | for (i = 0; i < NUM_ATC_REGS; i++) | |
674 | regs->attr[i] = ATTRin(par, i); | |
675 | ||
676 | for (i = 0; i < NUM_GRC_REGS; i++) | |
677 | regs->gra[i] = GRAin(par, i); | |
678 | ||
679 | for (i = 0; i < NUM_SEQ_REGS; i++) | |
680 | regs->seq[i] = SEQin(par, i); | |
681 | NVTRACE_LEAVE(); | |
682 | } | |
683 | ||
684 | /** | |
685 | * riva_load_state - loads current chip state | |
686 | * @par: pointer to riva_par object containing info for current riva board | |
687 | * @regs: pointer to riva_regs object | |
688 | * | |
689 | * DESCRIPTION: | |
690 | * Loads chip state from @regs. | |
691 | * | |
692 | * CALLED FROM: | |
693 | * riva_load_video_mode() | |
694 | * rivafb_probe() | |
695 | * rivafb_remove() | |
696 | */ | |
697 | /* from GGI */ | |
698 | static void riva_load_state(struct riva_par *par, struct riva_regs *regs) | |
699 | { | |
700 | RIVA_HW_STATE *state = ®s->ext; | |
701 | int i; | |
702 | ||
703 | NVTRACE_ENTER(); | |
704 | CRTCout(par, 0x11, 0x00); | |
705 | ||
706 | par->riva.LockUnlock(&par->riva, 0); | |
707 | ||
708 | par->riva.LoadStateExt(&par->riva, state); | |
709 | ||
710 | MISCout(par, regs->misc_output); | |
711 | ||
712 | for (i = 0; i < NUM_CRT_REGS; i++) { | |
713 | switch (i) { | |
714 | case 0x19: | |
715 | case 0x20 ... 0x40: | |
716 | break; | |
717 | default: | |
718 | CRTCout(par, i, regs->crtc[i]); | |
719 | } | |
720 | } | |
721 | ||
722 | for (i = 0; i < NUM_ATC_REGS; i++) | |
723 | ATTRout(par, i, regs->attr[i]); | |
724 | ||
725 | for (i = 0; i < NUM_GRC_REGS; i++) | |
726 | GRAout(par, i, regs->gra[i]); | |
727 | ||
728 | for (i = 0; i < NUM_SEQ_REGS; i++) | |
729 | SEQout(par, i, regs->seq[i]); | |
730 | NVTRACE_LEAVE(); | |
731 | } | |
732 | ||
733 | /** | |
734 | * riva_load_video_mode - calculate timings | |
735 | * @info: pointer to fb_info object containing info for current riva board | |
736 | * | |
737 | * DESCRIPTION: | |
738 | * Calculate some timings and then send em off to riva_load_state(). | |
739 | * | |
740 | * CALLED FROM: | |
741 | * rivafb_set_par() | |
742 | */ | |
743 | static void riva_load_video_mode(struct fb_info *info) | |
744 | { | |
745 | int bpp, width, hDisplaySize, hDisplay, hStart, | |
746 | hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; | |
747 | int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; | |
f4a41836 | 748 | struct riva_par *par = info->par; |
1da177e4 LT |
749 | struct riva_regs newmode; |
750 | ||
751 | NVTRACE_ENTER(); | |
752 | /* time to calculate */ | |
535a09ad | 753 | rivafb_blank(FB_BLANK_NORMAL, info); |
1da177e4 LT |
754 | |
755 | bpp = info->var.bits_per_pixel; | |
756 | if (bpp == 16 && info->var.green.length == 5) | |
757 | bpp = 15; | |
758 | width = info->var.xres_virtual; | |
759 | hDisplaySize = info->var.xres; | |
760 | hDisplay = (hDisplaySize / 8) - 1; | |
761 | hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; | |
762 | hEnd = (hDisplaySize + info->var.right_margin + | |
763 | info->var.hsync_len) / 8 - 1; | |
764 | hTotal = (hDisplaySize + info->var.right_margin + | |
765 | info->var.hsync_len + info->var.left_margin) / 8 - 5; | |
766 | hBlankStart = hDisplay; | |
767 | hBlankEnd = hTotal + 4; | |
768 | ||
769 | height = info->var.yres_virtual; | |
770 | vDisplay = info->var.yres - 1; | |
771 | vStart = info->var.yres + info->var.lower_margin - 1; | |
772 | vEnd = info->var.yres + info->var.lower_margin + | |
773 | info->var.vsync_len - 1; | |
774 | vTotal = info->var.yres + info->var.lower_margin + | |
775 | info->var.vsync_len + info->var.upper_margin + 2; | |
776 | vBlankStart = vDisplay; | |
777 | vBlankEnd = vTotal + 1; | |
778 | dotClock = 1000000000 / info->var.pixclock; | |
779 | ||
780 | memcpy(&newmode, ®_template, sizeof(struct riva_regs)); | |
781 | ||
782 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) | |
783 | vTotal |= 1; | |
784 | ||
785 | if (par->FlatPanel) { | |
786 | vStart = vTotal - 3; | |
787 | vEnd = vTotal - 2; | |
788 | vBlankStart = vStart; | |
789 | hStart = hTotal - 3; | |
790 | hEnd = hTotal - 2; | |
791 | hBlankEnd = hTotal + 4; | |
792 | } | |
793 | ||
794 | newmode.crtc[0x0] = Set8Bits (hTotal); | |
795 | newmode.crtc[0x1] = Set8Bits (hDisplay); | |
796 | newmode.crtc[0x2] = Set8Bits (hBlankStart); | |
797 | newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); | |
798 | newmode.crtc[0x4] = Set8Bits (hStart); | |
799 | newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) | |
800 | | SetBitField (hEnd, 4: 0, 4:0); | |
801 | newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); | |
802 | newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) | |
803 | | SetBitField (vDisplay, 8: 8, 1:1) | |
804 | | SetBitField (vStart, 8: 8, 2:2) | |
805 | | SetBitField (vBlankStart, 8: 8, 3:3) | |
806 | | SetBit (4) | |
807 | | SetBitField (vTotal, 9: 9, 5:5) | |
808 | | SetBitField (vDisplay, 9: 9, 6:6) | |
809 | | SetBitField (vStart, 9: 9, 7:7); | |
810 | newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) | |
811 | | SetBit (6); | |
812 | newmode.crtc[0x10] = Set8Bits (vStart); | |
813 | newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) | |
814 | | SetBit (5); | |
815 | newmode.crtc[0x12] = Set8Bits (vDisplay); | |
816 | newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); | |
817 | newmode.crtc[0x15] = Set8Bits (vBlankStart); | |
818 | newmode.crtc[0x16] = Set8Bits (vBlankEnd); | |
819 | ||
820 | newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) | |
821 | | SetBitField(vBlankStart,10:10,3:3) | |
822 | | SetBitField(vStart,10:10,2:2) | |
823 | | SetBitField(vDisplay,10:10,1:1) | |
824 | | SetBitField(vTotal,10:10,0:0); | |
825 | newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) | |
826 | | SetBitField(hDisplay,8:8,1:1) | |
827 | | SetBitField(hBlankStart,8:8,2:2) | |
828 | | SetBitField(hStart,8:8,3:3); | |
829 | newmode.ext.extra = SetBitField(vTotal,11:11,0:0) | |
830 | | SetBitField(vDisplay,11:11,2:2) | |
831 | | SetBitField(vStart,11:11,4:4) | |
832 | | SetBitField(vBlankStart,11:11,6:6); | |
833 | ||
834 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { | |
835 | int tmp = (hTotal >> 1) & ~1; | |
836 | newmode.ext.interlace = Set8Bits(tmp); | |
837 | newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); | |
838 | } else | |
839 | newmode.ext.interlace = 0xff; /* interlace off */ | |
840 | ||
841 | if (par->riva.Architecture >= NV_ARCH_10) | |
842 | par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); | |
843 | ||
844 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) | |
845 | newmode.misc_output &= ~0x40; | |
846 | else | |
847 | newmode.misc_output |= 0x40; | |
848 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) | |
849 | newmode.misc_output &= ~0x80; | |
850 | else | |
851 | newmode.misc_output |= 0x80; | |
852 | ||
853 | par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width, | |
854 | hDisplaySize, height, dotClock); | |
855 | ||
856 | newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & | |
857 | 0xfff000ff; | |
858 | if (par->FlatPanel == 1) { | |
859 | newmode.ext.pixel |= (1 << 7); | |
860 | newmode.ext.scale |= (1 << 8); | |
861 | } | |
862 | if (par->SecondCRTC) { | |
863 | newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & | |
864 | ~0x00001000; | |
865 | newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | | |
866 | 0x00001000; | |
867 | newmode.ext.crtcOwner = 3; | |
868 | newmode.ext.pllsel |= 0x20000800; | |
869 | newmode.ext.vpll2 = newmode.ext.vpll; | |
870 | } else if (par->riva.twoHeads) { | |
871 | newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | | |
872 | 0x00001000; | |
873 | newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & | |
874 | ~0x00001000; | |
875 | newmode.ext.crtcOwner = 0; | |
876 | newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); | |
877 | } | |
878 | if (par->FlatPanel == 1) { | |
879 | newmode.ext.pixel |= (1 << 7); | |
880 | newmode.ext.scale |= (1 << 8); | |
881 | } | |
882 | newmode.ext.cursorConfig = 0x02000100; | |
883 | par->current_state = newmode; | |
884 | riva_load_state(par, &par->current_state); | |
885 | par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ | |
535a09ad | 886 | rivafb_blank(FB_BLANK_UNBLANK, info); |
1da177e4 LT |
887 | NVTRACE_LEAVE(); |
888 | } | |
889 | ||
890 | static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb) | |
891 | { | |
892 | NVTRACE_ENTER(); | |
893 | var->xres = var->xres_virtual = modedb->xres; | |
894 | var->yres = modedb->yres; | |
895 | if (var->yres_virtual < var->yres) | |
896 | var->yres_virtual = var->yres; | |
897 | var->xoffset = var->yoffset = 0; | |
898 | var->pixclock = modedb->pixclock; | |
899 | var->left_margin = modedb->left_margin; | |
900 | var->right_margin = modedb->right_margin; | |
901 | var->upper_margin = modedb->upper_margin; | |
902 | var->lower_margin = modedb->lower_margin; | |
903 | var->hsync_len = modedb->hsync_len; | |
904 | var->vsync_len = modedb->vsync_len; | |
905 | var->sync = modedb->sync; | |
906 | var->vmode = modedb->vmode; | |
907 | NVTRACE_LEAVE(); | |
908 | } | |
909 | ||
910 | /** | |
911 | * rivafb_do_maximize - | |
912 | * @info: pointer to fb_info object containing info for current riva board | |
913 | * @var: | |
914 | * @nom: | |
915 | * @den: | |
916 | * | |
917 | * DESCRIPTION: | |
918 | * . | |
919 | * | |
920 | * RETURNS: | |
921 | * -EINVAL on failure, 0 on success | |
922 | * | |
923 | * | |
924 | * CALLED FROM: | |
925 | * rivafb_check_var() | |
926 | */ | |
927 | static int rivafb_do_maximize(struct fb_info *info, | |
928 | struct fb_var_screeninfo *var, | |
929 | int nom, int den) | |
930 | { | |
931 | static struct { | |
932 | int xres, yres; | |
933 | } modes[] = { | |
934 | {1600, 1280}, | |
935 | {1280, 1024}, | |
936 | {1024, 768}, | |
937 | {800, 600}, | |
938 | {640, 480}, | |
939 | {-1, -1} | |
940 | }; | |
941 | int i; | |
942 | ||
943 | NVTRACE_ENTER(); | |
944 | /* use highest possible virtual resolution */ | |
945 | if (var->xres_virtual == -1 && var->yres_virtual == -1) { | |
946 | printk(KERN_WARNING PFX | |
947 | "using maximum available virtual resolution\n"); | |
948 | for (i = 0; modes[i].xres != -1; i++) { | |
949 | if (modes[i].xres * nom / den * modes[i].yres < | |
950 | info->fix.smem_len) | |
951 | break; | |
952 | } | |
953 | if (modes[i].xres == -1) { | |
954 | printk(KERN_ERR PFX | |
955 | "could not find a virtual resolution that fits into video memory!!\n"); | |
956 | NVTRACE("EXIT - EINVAL error\n"); | |
957 | return -EINVAL; | |
958 | } | |
959 | var->xres_virtual = modes[i].xres; | |
960 | var->yres_virtual = modes[i].yres; | |
961 | ||
962 | printk(KERN_INFO PFX | |
963 | "virtual resolution set to maximum of %dx%d\n", | |
964 | var->xres_virtual, var->yres_virtual); | |
965 | } else if (var->xres_virtual == -1) { | |
966 | var->xres_virtual = (info->fix.smem_len * den / | |
967 | (nom * var->yres_virtual)) & ~15; | |
968 | printk(KERN_WARNING PFX | |
969 | "setting virtual X resolution to %d\n", var->xres_virtual); | |
970 | } else if (var->yres_virtual == -1) { | |
971 | var->xres_virtual = (var->xres_virtual + 15) & ~15; | |
972 | var->yres_virtual = info->fix.smem_len * den / | |
973 | (nom * var->xres_virtual); | |
974 | printk(KERN_WARNING PFX | |
975 | "setting virtual Y resolution to %d\n", var->yres_virtual); | |
976 | } else { | |
977 | var->xres_virtual = (var->xres_virtual + 15) & ~15; | |
978 | if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { | |
979 | printk(KERN_ERR PFX | |
980 | "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", | |
981 | var->xres, var->yres, var->bits_per_pixel); | |
982 | NVTRACE("EXIT - EINVAL error\n"); | |
983 | return -EINVAL; | |
984 | } | |
985 | } | |
986 | ||
987 | if (var->xres_virtual * nom / den >= 8192) { | |
988 | printk(KERN_WARNING PFX | |
989 | "virtual X resolution (%d) is too high, lowering to %d\n", | |
990 | var->xres_virtual, 8192 * den / nom - 16); | |
991 | var->xres_virtual = 8192 * den / nom - 16; | |
992 | } | |
993 | ||
994 | if (var->xres_virtual < var->xres) { | |
995 | printk(KERN_ERR PFX | |
996 | "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | if (var->yres_virtual < var->yres) { | |
1001 | printk(KERN_ERR PFX | |
1002 | "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | if (var->yres_virtual > 0x7fff/nom) | |
1006 | var->yres_virtual = 0x7fff/nom; | |
1007 | if (var->xres_virtual > 0x7fff/nom) | |
1008 | var->xres_virtual = 0x7fff/nom; | |
1009 | NVTRACE_LEAVE(); | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | static void | |
1014 | riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) | |
1015 | { | |
1016 | RIVA_FIFO_FREE(par->riva, Patt, 4); | |
1017 | NV_WR32(&par->riva.Patt->Color0, 0, clr0); | |
1018 | NV_WR32(&par->riva.Patt->Color1, 0, clr1); | |
1019 | NV_WR32(par->riva.Patt->Monochrome, 0, pat0); | |
1020 | NV_WR32(par->riva.Patt->Monochrome, 4, pat1); | |
1021 | } | |
1022 | ||
1023 | /* acceleration routines */ | |
1024 | static inline void wait_for_idle(struct riva_par *par) | |
1025 | { | |
1026 | while (par->riva.Busy(&par->riva)); | |
1027 | } | |
1028 | ||
1029 | /* | |
1030 | * Set ROP. Translate X rop into ROP3. Internal routine. | |
1031 | */ | |
1032 | static void | |
1033 | riva_set_rop_solid(struct riva_par *par, int rop) | |
1034 | { | |
1035 | riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
1036 | RIVA_FIFO_FREE(par->riva, Rop, 1); | |
1037 | NV_WR32(&par->riva.Rop->Rop3, 0, rop); | |
1038 | ||
1039 | } | |
1040 | ||
1041 | static void riva_setup_accel(struct fb_info *info) | |
1042 | { | |
f4a41836 | 1043 | struct riva_par *par = info->par; |
1da177e4 LT |
1044 | |
1045 | RIVA_FIFO_FREE(par->riva, Clip, 2); | |
1046 | NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); | |
1047 | NV_WR32(&par->riva.Clip->WidthHeight, 0, | |
1048 | (info->var.xres_virtual & 0xffff) | | |
1049 | (info->var.yres_virtual << 16)); | |
1050 | riva_set_rop_solid(par, 0xcc); | |
1051 | wait_for_idle(par); | |
1052 | } | |
1053 | ||
1054 | /** | |
1055 | * riva_get_cmap_len - query current color map length | |
1056 | * @var: standard kernel fb changeable data | |
1057 | * | |
1058 | * DESCRIPTION: | |
1059 | * Get current color map length. | |
1060 | * | |
1061 | * RETURNS: | |
1062 | * Length of color map | |
1063 | * | |
1064 | * CALLED FROM: | |
1065 | * rivafb_setcolreg() | |
1066 | */ | |
1067 | static int riva_get_cmap_len(const struct fb_var_screeninfo *var) | |
1068 | { | |
1069 | int rc = 256; /* reasonable default */ | |
1070 | ||
1071 | switch (var->green.length) { | |
1072 | case 8: | |
1073 | rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ | |
1074 | break; | |
1075 | case 5: | |
1076 | rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ | |
1077 | break; | |
1078 | case 6: | |
1079 | rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ | |
1080 | break; | |
1081 | default: | |
1082 | /* should not occur */ | |
1083 | break; | |
1084 | } | |
1085 | return rc; | |
1086 | } | |
1087 | ||
1da177e4 LT |
1088 | /* ------------------------------------------------------------------------- * |
1089 | * | |
1090 | * framebuffer operations | |
1091 | * | |
1092 | * ------------------------------------------------------------------------- */ | |
1093 | ||
1094 | static int rivafb_open(struct fb_info *info, int user) | |
1095 | { | |
f4a41836 | 1096 | struct riva_par *par = info->par; |
1da177e4 LT |
1097 | int cnt = atomic_read(&par->ref_count); |
1098 | ||
1099 | NVTRACE_ENTER(); | |
1100 | if (!cnt) { | |
1101 | #ifdef CONFIG_X86 | |
1102 | memset(&par->state, 0, sizeof(struct vgastate)); | |
1103 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; | |
1104 | /* save the DAC for Riva128 */ | |
1105 | if (par->riva.Architecture == NV_ARCH_03) | |
1106 | par->state.flags |= VGA_SAVE_CMAP; | |
1107 | save_vga(&par->state); | |
1108 | #endif | |
1109 | /* vgaHWunlock() + riva unlock (0x7F) */ | |
1110 | CRTCout(par, 0x11, 0xFF); | |
1111 | par->riva.LockUnlock(&par->riva, 0); | |
1112 | ||
1113 | riva_save_state(par, &par->initial_state); | |
1114 | } | |
1115 | atomic_inc(&par->ref_count); | |
1116 | NVTRACE_LEAVE(); | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static int rivafb_release(struct fb_info *info, int user) | |
1121 | { | |
f4a41836 | 1122 | struct riva_par *par = info->par; |
1da177e4 LT |
1123 | int cnt = atomic_read(&par->ref_count); |
1124 | ||
1125 | NVTRACE_ENTER(); | |
1126 | if (!cnt) | |
1127 | return -EINVAL; | |
1128 | if (cnt == 1) { | |
1129 | par->riva.LockUnlock(&par->riva, 0); | |
1130 | par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); | |
1131 | riva_load_state(par, &par->initial_state); | |
1132 | #ifdef CONFIG_X86 | |
1133 | restore_vga(&par->state); | |
1134 | #endif | |
1135 | par->riva.LockUnlock(&par->riva, 1); | |
1136 | } | |
1137 | atomic_dec(&par->ref_count); | |
1138 | NVTRACE_LEAVE(); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
1143 | { | |
1144 | struct fb_videomode *mode; | |
f4a41836 | 1145 | struct riva_par *par = info->par; |
1da177e4 LT |
1146 | int nom, den; /* translating from pixels->bytes */ |
1147 | int mode_valid = 0; | |
1148 | ||
1149 | NVTRACE_ENTER(); | |
1150 | switch (var->bits_per_pixel) { | |
1151 | case 1 ... 8: | |
1152 | var->red.offset = var->green.offset = var->blue.offset = 0; | |
1153 | var->red.length = var->green.length = var->blue.length = 8; | |
1154 | var->bits_per_pixel = 8; | |
1155 | nom = den = 1; | |
1156 | break; | |
1157 | case 9 ... 15: | |
1158 | var->green.length = 5; | |
1159 | /* fall through */ | |
1160 | case 16: | |
1161 | var->bits_per_pixel = 16; | |
1162 | /* The Riva128 supports RGB555 only */ | |
1163 | if (par->riva.Architecture == NV_ARCH_03) | |
1164 | var->green.length = 5; | |
1165 | if (var->green.length == 5) { | |
1166 | /* 0rrrrrgg gggbbbbb */ | |
1167 | var->red.offset = 10; | |
1168 | var->green.offset = 5; | |
1169 | var->blue.offset = 0; | |
1170 | var->red.length = 5; | |
1171 | var->green.length = 5; | |
1172 | var->blue.length = 5; | |
1173 | } else { | |
1174 | /* rrrrrggg gggbbbbb */ | |
1175 | var->red.offset = 11; | |
1176 | var->green.offset = 5; | |
1177 | var->blue.offset = 0; | |
1178 | var->red.length = 5; | |
1179 | var->green.length = 6; | |
1180 | var->blue.length = 5; | |
1181 | } | |
1182 | nom = 2; | |
1183 | den = 1; | |
1184 | break; | |
1185 | case 17 ... 32: | |
1186 | var->red.length = var->green.length = var->blue.length = 8; | |
1187 | var->bits_per_pixel = 32; | |
1188 | var->red.offset = 16; | |
1189 | var->green.offset = 8; | |
1190 | var->blue.offset = 0; | |
1191 | nom = 4; | |
1192 | den = 1; | |
1193 | break; | |
1194 | default: | |
1195 | printk(KERN_ERR PFX | |
1196 | "mode %dx%dx%d rejected...color depth not supported.\n", | |
1197 | var->xres, var->yres, var->bits_per_pixel); | |
1198 | NVTRACE("EXIT, returning -EINVAL\n"); | |
1199 | return -EINVAL; | |
1200 | } | |
1201 | ||
1202 | if (!strictmode) { | |
1203 | if (!info->monspecs.vfmax || !info->monspecs.hfmax || | |
1204 | !info->monspecs.dclkmax || !fb_validate_mode(var, info)) | |
1205 | mode_valid = 1; | |
1206 | } | |
1207 | ||
1208 | /* calculate modeline if supported by monitor */ | |
1209 | if (!mode_valid && info->monspecs.gtf) { | |
1210 | if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) | |
1211 | mode_valid = 1; | |
1212 | } | |
1213 | ||
1214 | if (!mode_valid) { | |
1215 | mode = fb_find_best_mode(var, &info->modelist); | |
1216 | if (mode) { | |
1217 | riva_update_var(var, mode); | |
1218 | mode_valid = 1; | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | if (!mode_valid && info->monspecs.modedb_len) | |
1223 | return -EINVAL; | |
1224 | ||
1225 | if (var->xres_virtual < var->xres) | |
1226 | var->xres_virtual = var->xres; | |
1227 | if (var->yres_virtual <= var->yres) | |
1228 | var->yres_virtual = -1; | |
1229 | if (rivafb_do_maximize(info, var, nom, den) < 0) | |
1230 | return -EINVAL; | |
1231 | ||
1232 | if (var->xoffset < 0) | |
1233 | var->xoffset = 0; | |
1234 | if (var->yoffset < 0) | |
1235 | var->yoffset = 0; | |
1236 | ||
1237 | /* truncate xoffset and yoffset to maximum if too high */ | |
1238 | if (var->xoffset > var->xres_virtual - var->xres) | |
1239 | var->xoffset = var->xres_virtual - var->xres - 1; | |
1240 | ||
1241 | if (var->yoffset > var->yres_virtual - var->yres) | |
1242 | var->yoffset = var->yres_virtual - var->yres - 1; | |
1243 | ||
1244 | var->red.msb_right = | |
1245 | var->green.msb_right = | |
1246 | var->blue.msb_right = | |
1247 | var->transp.offset = var->transp.length = var->transp.msb_right = 0; | |
1248 | NVTRACE_LEAVE(); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int rivafb_set_par(struct fb_info *info) | |
1253 | { | |
f4a41836 | 1254 | struct riva_par *par = info->par; |
1da177e4 LT |
1255 | |
1256 | NVTRACE_ENTER(); | |
1257 | /* vgaHWunlock() + riva unlock (0x7F) */ | |
1258 | CRTCout(par, 0x11, 0xFF); | |
1259 | par->riva.LockUnlock(&par->riva, 0); | |
1260 | riva_load_video_mode(info); | |
1261 | if(!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1262 | riva_setup_accel(info); | |
1263 | ||
1264 | par->cursor_reset = 1; | |
1265 | info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); | |
1266 | info->fix.visual = (info->var.bits_per_pixel == 8) ? | |
1267 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; | |
1268 | ||
1269 | if (info->flags & FBINFO_HWACCEL_DISABLED) | |
1270 | info->pixmap.scan_align = 1; | |
1271 | else | |
1272 | info->pixmap.scan_align = 4; | |
1273 | NVTRACE_LEAVE(); | |
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * rivafb_pan_display | |
1279 | * @var: standard kernel fb changeable data | |
1280 | * @con: TODO | |
1281 | * @info: pointer to fb_info object containing info for current riva board | |
1282 | * | |
1283 | * DESCRIPTION: | |
1284 | * Pan (or wrap, depending on the `vmode' field) the display using the | |
1285 | * `xoffset' and `yoffset' fields of the `var' structure. | |
1286 | * If the values don't fit, return -EINVAL. | |
1287 | * | |
1288 | * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag | |
1289 | */ | |
1290 | static int rivafb_pan_display(struct fb_var_screeninfo *var, | |
1291 | struct fb_info *info) | |
1292 | { | |
f4a41836 | 1293 | struct riva_par *par = info->par; |
1da177e4 LT |
1294 | unsigned int base; |
1295 | ||
1296 | NVTRACE_ENTER(); | |
1da177e4 | 1297 | base = var->yoffset * info->fix.line_length + var->xoffset; |
1da177e4 | 1298 | par->riva.SetStartAddress(&par->riva, base); |
1da177e4 LT |
1299 | NVTRACE_LEAVE(); |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int rivafb_blank(int blank, struct fb_info *info) | |
1304 | { | |
f4a41836 | 1305 | struct riva_par *par= info->par; |
1da177e4 LT |
1306 | unsigned char tmp, vesa; |
1307 | ||
1308 | tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ | |
1309 | vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ | |
1310 | ||
1311 | NVTRACE_ENTER(); | |
1312 | ||
1313 | if (blank) | |
1314 | tmp |= 0x20; | |
1315 | ||
1316 | switch (blank) { | |
1317 | case FB_BLANK_UNBLANK: | |
1318 | case FB_BLANK_NORMAL: | |
1319 | break; | |
1320 | case FB_BLANK_VSYNC_SUSPEND: | |
1321 | vesa |= 0x80; | |
1322 | break; | |
1323 | case FB_BLANK_HSYNC_SUSPEND: | |
1324 | vesa |= 0x40; | |
1325 | break; | |
1326 | case FB_BLANK_POWERDOWN: | |
1327 | vesa |= 0xc0; | |
1328 | break; | |
1329 | } | |
1330 | ||
1331 | SEQout(par, 0x01, tmp); | |
1332 | CRTCout(par, 0x1a, vesa); | |
1333 | ||
e01af038 | 1334 | riva_bl_set_power(info, blank); |
1da177e4 LT |
1335 | |
1336 | NVTRACE_LEAVE(); | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | /** | |
1342 | * rivafb_setcolreg | |
1343 | * @regno: register index | |
1344 | * @red: red component | |
1345 | * @green: green component | |
1346 | * @blue: blue component | |
1347 | * @transp: transparency | |
1348 | * @info: pointer to fb_info object containing info for current riva board | |
1349 | * | |
1350 | * DESCRIPTION: | |
1351 | * Set a single color register. The values supplied have a 16 bit | |
1352 | * magnitude. | |
1353 | * | |
1354 | * RETURNS: | |
1355 | * Return != 0 for invalid regno. | |
1356 | * | |
1357 | * CALLED FROM: | |
1358 | * fbcmap.c:fb_set_cmap() | |
1359 | */ | |
1360 | static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
1361 | unsigned blue, unsigned transp, | |
1362 | struct fb_info *info) | |
1363 | { | |
f4a41836 | 1364 | struct riva_par *par = info->par; |
1da177e4 LT |
1365 | RIVA_HW_INST *chip = &par->riva; |
1366 | int i; | |
1367 | ||
1368 | if (regno >= riva_get_cmap_len(&info->var)) | |
1369 | return -EINVAL; | |
1370 | ||
1371 | if (info->var.grayscale) { | |
1372 | /* gray = 0.30*R + 0.59*G + 0.11*B */ | |
1373 | red = green = blue = | |
1374 | (red * 77 + green * 151 + blue * 28) >> 8; | |
1375 | } | |
1376 | ||
1377 | if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
1378 | ((u32 *) info->pseudo_palette)[regno] = | |
1379 | (regno << info->var.red.offset) | | |
1380 | (regno << info->var.green.offset) | | |
1381 | (regno << info->var.blue.offset); | |
1382 | /* | |
1383 | * The Riva128 2D engine requires color information in | |
1384 | * TrueColor format even if framebuffer is in DirectColor | |
1385 | */ | |
1386 | if (par->riva.Architecture == NV_ARCH_03) { | |
1387 | switch (info->var.bits_per_pixel) { | |
1388 | case 16: | |
1389 | par->palette[regno] = ((red & 0xf800) >> 1) | | |
1390 | ((green & 0xf800) >> 6) | | |
1391 | ((blue & 0xf800) >> 11); | |
1392 | break; | |
1393 | case 32: | |
1394 | par->palette[regno] = ((red & 0xff00) << 8) | | |
1395 | ((green & 0xff00)) | | |
1396 | ((blue & 0xff00) >> 8); | |
1397 | break; | |
1398 | } | |
1399 | } | |
1400 | } | |
1401 | ||
1402 | switch (info->var.bits_per_pixel) { | |
1403 | case 8: | |
1404 | /* "transparent" stuff is completely ignored. */ | |
1405 | riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); | |
1406 | break; | |
1407 | case 16: | |
1408 | if (info->var.green.length == 5) { | |
1409 | for (i = 0; i < 8; i++) { | |
1410 | riva_wclut(chip, regno*8+i, red >> 8, | |
1411 | green >> 8, blue >> 8); | |
1412 | } | |
1413 | } else { | |
1414 | u8 r, g, b; | |
1415 | ||
1416 | if (regno < 32) { | |
1417 | for (i = 0; i < 8; i++) { | |
1418 | riva_wclut(chip, regno*8+i, | |
1419 | red >> 8, green >> 8, | |
1420 | blue >> 8); | |
1421 | } | |
1422 | } | |
1423 | riva_rclut(chip, regno*4, &r, &g, &b); | |
1424 | for (i = 0; i < 4; i++) | |
1425 | riva_wclut(chip, regno*4+i, r, | |
1426 | green >> 8, b); | |
1427 | } | |
1428 | break; | |
1429 | case 32: | |
1430 | riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); | |
1431 | break; | |
1432 | default: | |
1433 | /* do nothing */ | |
1434 | break; | |
1435 | } | |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * rivafb_fillrect - hardware accelerated color fill function | |
1441 | * @info: pointer to fb_info structure | |
1442 | * @rect: pointer to fb_fillrect structure | |
1443 | * | |
1444 | * DESCRIPTION: | |
1445 | * This function fills up a region of framebuffer memory with a solid | |
1446 | * color with a choice of two different ROP's, copy or invert. | |
1447 | * | |
1448 | * CALLED FROM: | |
1449 | * framebuffer hook | |
1450 | */ | |
1451 | static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
1452 | { | |
f4a41836 | 1453 | struct riva_par *par = info->par; |
1da177e4 LT |
1454 | u_int color, rop = 0; |
1455 | ||
1456 | if ((info->flags & FBINFO_HWACCEL_DISABLED)) { | |
1457 | cfb_fillrect(info, rect); | |
1458 | return; | |
1459 | } | |
1460 | ||
1461 | if (info->var.bits_per_pixel == 8) | |
1462 | color = rect->color; | |
1463 | else { | |
1464 | if (par->riva.Architecture != NV_ARCH_03) | |
1465 | color = ((u32 *)info->pseudo_palette)[rect->color]; | |
1466 | else | |
1467 | color = par->palette[rect->color]; | |
1468 | } | |
1469 | ||
1470 | switch (rect->rop) { | |
1471 | case ROP_XOR: | |
1472 | rop = 0x66; | |
1473 | break; | |
1474 | case ROP_COPY: | |
1475 | default: | |
1476 | rop = 0xCC; | |
1477 | break; | |
1478 | } | |
1479 | ||
1480 | riva_set_rop_solid(par, rop); | |
1481 | ||
1482 | RIVA_FIFO_FREE(par->riva, Bitmap, 1); | |
1483 | NV_WR32(&par->riva.Bitmap->Color1A, 0, color); | |
1484 | ||
1485 | RIVA_FIFO_FREE(par->riva, Bitmap, 2); | |
1486 | NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, | |
1487 | (rect->dx << 16) | rect->dy); | |
1488 | mb(); | |
1489 | NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, | |
1490 | (rect->width << 16) | rect->height); | |
1491 | mb(); | |
1492 | riva_set_rop_solid(par, 0xcc); | |
1493 | ||
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * rivafb_copyarea - hardware accelerated blit function | |
1498 | * @info: pointer to fb_info structure | |
1499 | * @region: pointer to fb_copyarea structure | |
1500 | * | |
1501 | * DESCRIPTION: | |
1502 | * This copies an area of pixels from one location to another | |
1503 | * | |
1504 | * CALLED FROM: | |
1505 | * framebuffer hook | |
1506 | */ | |
1507 | static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) | |
1508 | { | |
f4a41836 | 1509 | struct riva_par *par = info->par; |
1da177e4 LT |
1510 | |
1511 | if ((info->flags & FBINFO_HWACCEL_DISABLED)) { | |
1512 | cfb_copyarea(info, region); | |
1513 | return; | |
1514 | } | |
1515 | ||
1516 | RIVA_FIFO_FREE(par->riva, Blt, 3); | |
1517 | NV_WR32(&par->riva.Blt->TopLeftSrc, 0, | |
1518 | (region->sy << 16) | region->sx); | |
1519 | NV_WR32(&par->riva.Blt->TopLeftDst, 0, | |
1520 | (region->dy << 16) | region->dx); | |
1521 | mb(); | |
1522 | NV_WR32(&par->riva.Blt->WidthHeight, 0, | |
1523 | (region->height << 16) | region->width); | |
1524 | mb(); | |
1525 | } | |
1526 | ||
1527 | static inline void convert_bgcolor_16(u32 *col) | |
1528 | { | |
1529 | *col = ((*col & 0x0000F800) << 8) | |
1530 | | ((*col & 0x00007E0) << 5) | |
1531 | | ((*col & 0x0000001F) << 3) | |
1532 | | 0xFF000000; | |
1533 | mb(); | |
1534 | } | |
1535 | ||
1536 | /** | |
1537 | * rivafb_imageblit: hardware accelerated color expand function | |
1538 | * @info: pointer to fb_info structure | |
1539 | * @image: pointer to fb_image structure | |
1540 | * | |
1541 | * DESCRIPTION: | |
1542 | * If the source is a monochrome bitmap, the function fills up a a region | |
1543 | * of framebuffer memory with pixels whose color is determined by the bit | |
1544 | * setting of the bitmap, 1 - foreground, 0 - background. | |
1545 | * | |
1546 | * If the source is not a monochrome bitmap, color expansion is not done. | |
1547 | * In this case, it is channeled to a software function. | |
1548 | * | |
1549 | * CALLED FROM: | |
1550 | * framebuffer hook | |
1551 | */ | |
1552 | static void rivafb_imageblit(struct fb_info *info, | |
1553 | const struct fb_image *image) | |
1554 | { | |
f4a41836 | 1555 | struct riva_par *par = info->par; |
1da177e4 LT |
1556 | u32 fgx = 0, bgx = 0, width, tmp; |
1557 | u8 *cdat = (u8 *) image->data; | |
1558 | volatile u32 __iomem *d; | |
1559 | int i, size; | |
1560 | ||
1561 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { | |
1562 | cfb_imageblit(info, image); | |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | switch (info->var.bits_per_pixel) { | |
1567 | case 8: | |
1568 | fgx = image->fg_color; | |
1569 | bgx = image->bg_color; | |
1570 | break; | |
1571 | case 16: | |
1572 | case 32: | |
1573 | if (par->riva.Architecture != NV_ARCH_03) { | |
1574 | fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; | |
1575 | bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; | |
1576 | } else { | |
1577 | fgx = par->palette[image->fg_color]; | |
1578 | bgx = par->palette[image->bg_color]; | |
1579 | } | |
1580 | if (info->var.green.length == 6) | |
1581 | convert_bgcolor_16(&bgx); | |
1582 | break; | |
1583 | } | |
1584 | ||
1585 | RIVA_FIFO_FREE(par->riva, Bitmap, 7); | |
1586 | NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, | |
1587 | (image->dy << 16) | (image->dx & 0xFFFF)); | |
1588 | NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, | |
1589 | (((image->dy + image->height) << 16) | | |
1590 | ((image->dx + image->width) & 0xffff))); | |
1591 | NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); | |
1592 | NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); | |
1593 | NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, | |
1594 | (image->height << 16) | ((image->width + 31) & ~31)); | |
1595 | NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, | |
1596 | (image->height << 16) | ((image->width + 31) & ~31)); | |
1597 | NV_WR32(&par->riva.Bitmap->PointE, 0, | |
1598 | (image->dy << 16) | (image->dx & 0xFFFF)); | |
1599 | ||
1600 | d = &par->riva.Bitmap->MonochromeData01E; | |
1601 | ||
1602 | width = (image->width + 31)/32; | |
1603 | size = width * image->height; | |
1604 | while (size >= 16) { | |
1605 | RIVA_FIFO_FREE(par->riva, Bitmap, 16); | |
1606 | for (i = 0; i < 16; i++) { | |
1607 | tmp = *((u32 *)cdat); | |
1608 | cdat = (u8 *)((u32 *)cdat + 1); | |
1609 | reverse_order(&tmp); | |
1610 | NV_WR32(d, i*4, tmp); | |
1611 | } | |
1612 | size -= 16; | |
1613 | } | |
1614 | if (size) { | |
1615 | RIVA_FIFO_FREE(par->riva, Bitmap, size); | |
1616 | for (i = 0; i < size; i++) { | |
1617 | tmp = *((u32 *) cdat); | |
1618 | cdat = (u8 *)((u32 *)cdat + 1); | |
1619 | reverse_order(&tmp); | |
1620 | NV_WR32(d, i*4, tmp); | |
1621 | } | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | /** | |
1626 | * rivafb_cursor - hardware cursor function | |
1627 | * @info: pointer to info structure | |
1628 | * @cursor: pointer to fbcursor structure | |
1629 | * | |
1630 | * DESCRIPTION: | |
1631 | * A cursor function that supports displaying a cursor image via hardware. | |
1632 | * Within the kernel, copy and invert rops are supported. If exported | |
1633 | * to user space, only the copy rop will be supported. | |
1634 | * | |
1635 | * CALLED FROM | |
1636 | * framebuffer hook | |
1637 | */ | |
1638 | static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
1639 | { | |
f4a41836 | 1640 | struct riva_par *par = info->par; |
1da177e4 | 1641 | u8 data[MAX_CURS * MAX_CURS/8]; |
1da177e4 | 1642 | int i, set = cursor->set; |
f1ab5dac | 1643 | u16 fg, bg; |
1da177e4 | 1644 | |
f1ab5dac JS |
1645 | if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) |
1646 | return -ENXIO; | |
1da177e4 LT |
1647 | |
1648 | par->riva.ShowHideCursor(&par->riva, 0); | |
1649 | ||
1650 | if (par->cursor_reset) { | |
1651 | set = FB_CUR_SETALL; | |
1652 | par->cursor_reset = 0; | |
1653 | } | |
1654 | ||
1655 | if (set & FB_CUR_SETSIZE) | |
1656 | memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); | |
1657 | ||
1658 | if (set & FB_CUR_SETPOS) { | |
1659 | u32 xx, yy, temp; | |
1660 | ||
1661 | yy = cursor->image.dy - info->var.yoffset; | |
1662 | xx = cursor->image.dx - info->var.xoffset; | |
1663 | temp = xx & 0xFFFF; | |
1664 | temp |= yy << 16; | |
1665 | ||
1666 | NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); | |
1667 | } | |
1668 | ||
1669 | ||
1670 | if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { | |
1671 | u32 bg_idx = cursor->image.bg_color; | |
1672 | u32 fg_idx = cursor->image.fg_color; | |
1673 | u32 s_pitch = (cursor->image.width+7) >> 3; | |
1674 | u32 d_pitch = MAX_CURS/8; | |
1675 | u8 *dat = (u8 *) cursor->image.data; | |
1676 | u8 *msk = (u8 *) cursor->mask; | |
1677 | u8 *src; | |
1678 | ||
1679 | src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); | |
1680 | ||
1681 | if (src) { | |
1682 | switch (cursor->rop) { | |
1683 | case ROP_XOR: | |
f1ab5dac | 1684 | for (i = 0; i < s_pitch * cursor->image.height; i++) |
1da177e4 LT |
1685 | src[i] = dat[i] ^ msk[i]; |
1686 | break; | |
1687 | case ROP_COPY: | |
1688 | default: | |
f1ab5dac | 1689 | for (i = 0; i < s_pitch * cursor->image.height; i++) |
1da177e4 LT |
1690 | src[i] = dat[i] & msk[i]; |
1691 | break; | |
1692 | } | |
1693 | ||
f1ab5dac JS |
1694 | fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, |
1695 | cursor->image.height); | |
1da177e4 LT |
1696 | |
1697 | bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | | |
1698 | ((info->cmap.green[bg_idx] & 0xf8) << 2) | | |
1699 | ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | | |
1700 | 1 << 15; | |
1701 | ||
1702 | fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | | |
1703 | ((info->cmap.green[fg_idx] & 0xf8) << 2) | | |
1704 | ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | | |
1705 | 1 << 15; | |
1706 | ||
1707 | par->riva.LockUnlock(&par->riva, 0); | |
1708 | ||
1709 | rivafb_load_cursor_image(par, data, bg, fg, | |
1710 | cursor->image.width, | |
1711 | cursor->image.height); | |
1712 | kfree(src); | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | if (cursor->enable) | |
1717 | par->riva.ShowHideCursor(&par->riva, 1); | |
1718 | ||
1719 | return 0; | |
1720 | } | |
1721 | ||
1722 | static int rivafb_sync(struct fb_info *info) | |
1723 | { | |
f4a41836 | 1724 | struct riva_par *par = info->par; |
1da177e4 LT |
1725 | |
1726 | wait_for_idle(par); | |
1727 | return 0; | |
1728 | } | |
1729 | ||
1730 | /* ------------------------------------------------------------------------- * | |
1731 | * | |
1732 | * initialization helper functions | |
1733 | * | |
1734 | * ------------------------------------------------------------------------- */ | |
1735 | ||
1736 | /* kernel interface */ | |
1737 | static struct fb_ops riva_fb_ops = { | |
1738 | .owner = THIS_MODULE, | |
1739 | .fb_open = rivafb_open, | |
1740 | .fb_release = rivafb_release, | |
1741 | .fb_check_var = rivafb_check_var, | |
1742 | .fb_set_par = rivafb_set_par, | |
1743 | .fb_setcolreg = rivafb_setcolreg, | |
1744 | .fb_pan_display = rivafb_pan_display, | |
1745 | .fb_blank = rivafb_blank, | |
1746 | .fb_fillrect = rivafb_fillrect, | |
1747 | .fb_copyarea = rivafb_copyarea, | |
1748 | .fb_imageblit = rivafb_imageblit, | |
1749 | .fb_cursor = rivafb_cursor, | |
1750 | .fb_sync = rivafb_sync, | |
1751 | }; | |
1752 | ||
1753 | static int __devinit riva_set_fbinfo(struct fb_info *info) | |
1754 | { | |
1755 | unsigned int cmap_len; | |
f4a41836 | 1756 | struct riva_par *par = info->par; |
1da177e4 LT |
1757 | |
1758 | NVTRACE_ENTER(); | |
1759 | info->flags = FBINFO_DEFAULT | |
1760 | | FBINFO_HWACCEL_XPAN | |
1761 | | FBINFO_HWACCEL_YPAN | |
1762 | | FBINFO_HWACCEL_COPYAREA | |
1763 | | FBINFO_HWACCEL_FILLRECT | |
1764 | | FBINFO_HWACCEL_IMAGEBLIT; | |
1765 | ||
1766 | /* Accel seems to not work properly on NV30 yet...*/ | |
1767 | if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { | |
1768 | printk(KERN_DEBUG PFX "disabling acceleration\n"); | |
1769 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1770 | } | |
1771 | ||
1772 | info->var = rivafb_default_var; | |
1773 | info->fix.visual = (info->var.bits_per_pixel == 8) ? | |
1774 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; | |
1775 | ||
1776 | info->pseudo_palette = par->pseudo_palette; | |
1777 | ||
1778 | cmap_len = riva_get_cmap_len(&info->var); | |
1779 | fb_alloc_cmap(&info->cmap, cmap_len, 0); | |
1780 | ||
1781 | info->pixmap.size = 8 * 1024; | |
1782 | info->pixmap.buf_align = 4; | |
58a60643 | 1783 | info->pixmap.access_align = 32; |
1da177e4 LT |
1784 | info->pixmap.flags = FB_PIXMAP_SYSTEM; |
1785 | info->var.yres_virtual = -1; | |
1786 | NVTRACE_LEAVE(); | |
1787 | return (rivafb_check_var(&info->var, info)); | |
1788 | } | |
1789 | ||
1790 | #ifdef CONFIG_PPC_OF | |
1791 | static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) | |
1792 | { | |
f4a41836 | 1793 | struct riva_par *par = info->par; |
1da177e4 | 1794 | struct device_node *dp; |
79da342c | 1795 | const unsigned char *pedid = NULL; |
13b5aecc | 1796 | const unsigned char *disptype = NULL; |
1da177e4 LT |
1797 | static char *propnames[] = { |
1798 | "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; | |
1799 | int i; | |
1800 | ||
1801 | NVTRACE_ENTER(); | |
1802 | dp = pci_device_to_OF_node(pd); | |
1803 | for (; dp != NULL; dp = dp->child) { | |
b04e3dd4 | 1804 | disptype = get_property(dp, "display-type", NULL); |
1da177e4 LT |
1805 | if (disptype == NULL) |
1806 | continue; | |
1807 | if (strncmp(disptype, "LCD", 3) != 0) | |
1808 | continue; | |
1809 | for (i = 0; propnames[i] != NULL; ++i) { | |
b04e3dd4 | 1810 | pedid = get_property(dp, propnames[i], NULL); |
1da177e4 | 1811 | if (pedid != NULL) { |
0271eb94 | 1812 | par->EDID = (unsigned char *)pedid; |
1da177e4 LT |
1813 | NVTRACE("LCD found.\n"); |
1814 | return 1; | |
1815 | } | |
1816 | } | |
1817 | } | |
1818 | NVTRACE_LEAVE(); | |
1819 | return 0; | |
1820 | } | |
1821 | #endif /* CONFIG_PPC_OF */ | |
1822 | ||
1823 | #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) | |
1824 | static int __devinit riva_get_EDID_i2c(struct fb_info *info) | |
1825 | { | |
f4a41836 | 1826 | struct riva_par *par = info->par; |
1da177e4 LT |
1827 | struct fb_var_screeninfo var; |
1828 | int i; | |
1829 | ||
1830 | NVTRACE_ENTER(); | |
1831 | riva_create_i2c_busses(par); | |
1832 | for (i = 0; i < par->bus; i++) { | |
1833 | riva_probe_i2c_connector(par, i+1, &par->EDID); | |
1834 | if (par->EDID && !fb_parse_edid(par->EDID, &var)) { | |
1835 | printk(PFX "Found EDID Block from BUS %i\n", i); | |
1836 | break; | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | NVTRACE_LEAVE(); | |
1841 | return (par->EDID) ? 1 : 0; | |
1842 | } | |
1843 | #endif /* CONFIG_FB_RIVA_I2C */ | |
1844 | ||
1845 | static void __devinit riva_update_default_var(struct fb_var_screeninfo *var, | |
1846 | struct fb_info *info) | |
1847 | { | |
1848 | struct fb_monspecs *specs = &info->monspecs; | |
1849 | struct fb_videomode modedb; | |
1850 | ||
1851 | NVTRACE_ENTER(); | |
1852 | /* respect mode options */ | |
1853 | if (mode_option) { | |
1854 | fb_find_mode(var, info, mode_option, | |
1855 | specs->modedb, specs->modedb_len, | |
1856 | NULL, 8); | |
1857 | } else if (specs->modedb != NULL) { | |
1858 | /* get preferred timing */ | |
1859 | if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { | |
1860 | int i; | |
1861 | ||
1862 | for (i = 0; i < specs->modedb_len; i++) { | |
1863 | if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { | |
1864 | modedb = specs->modedb[i]; | |
1865 | break; | |
1866 | } | |
1867 | } | |
1868 | } else { | |
1869 | /* otherwise, get first mode in database */ | |
1870 | modedb = specs->modedb[0]; | |
1871 | } | |
1872 | var->bits_per_pixel = 8; | |
1873 | riva_update_var(var, &modedb); | |
1874 | } | |
1875 | NVTRACE_LEAVE(); | |
1876 | } | |
1877 | ||
1878 | ||
1879 | static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) | |
1880 | { | |
1881 | NVTRACE_ENTER(); | |
1882 | #ifdef CONFIG_PPC_OF | |
1883 | if (!riva_get_EDID_OF(info, pdev)) | |
1884 | printk(PFX "could not retrieve EDID from OF\n"); | |
44456d37 | 1885 | #elif defined(CONFIG_FB_RIVA_I2C) |
1da177e4 LT |
1886 | if (!riva_get_EDID_i2c(info)) |
1887 | printk(PFX "could not retrieve EDID from DDC/I2C\n"); | |
1888 | #endif | |
1889 | NVTRACE_LEAVE(); | |
1890 | } | |
1891 | ||
1892 | ||
1893 | static void __devinit riva_get_edidinfo(struct fb_info *info) | |
1894 | { | |
1895 | struct fb_var_screeninfo *var = &rivafb_default_var; | |
f4a41836 | 1896 | struct riva_par *par = info->par; |
1da177e4 LT |
1897 | |
1898 | fb_edid_to_monspecs(par->EDID, &info->monspecs); | |
1899 | fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, | |
1900 | &info->modelist); | |
1901 | riva_update_default_var(var, info); | |
1902 | ||
1903 | /* if user specified flatpanel, we respect that */ | |
1904 | if (info->monspecs.input & FB_DISP_DDI) | |
1905 | par->FlatPanel = 1; | |
1906 | } | |
1907 | ||
1908 | /* ------------------------------------------------------------------------- * | |
1909 | * | |
1910 | * PCI bus | |
1911 | * | |
1912 | * ------------------------------------------------------------------------- */ | |
1913 | ||
1914 | static u32 __devinit riva_get_arch(struct pci_dev *pd) | |
1915 | { | |
1916 | u32 arch = 0; | |
1917 | ||
1918 | switch (pd->device & 0x0ff0) { | |
1919 | case 0x0100: /* GeForce 256 */ | |
1920 | case 0x0110: /* GeForce2 MX */ | |
1921 | case 0x0150: /* GeForce2 */ | |
1922 | case 0x0170: /* GeForce4 MX */ | |
1923 | case 0x0180: /* GeForce4 MX (8x AGP) */ | |
1924 | case 0x01A0: /* nForce */ | |
1925 | case 0x01F0: /* nForce2 */ | |
1926 | arch = NV_ARCH_10; | |
1927 | break; | |
1928 | case 0x0200: /* GeForce3 */ | |
1929 | case 0x0250: /* GeForce4 Ti */ | |
1930 | case 0x0280: /* GeForce4 Ti (8x AGP) */ | |
1931 | arch = NV_ARCH_20; | |
1932 | break; | |
1933 | case 0x0300: /* GeForceFX 5800 */ | |
1934 | case 0x0310: /* GeForceFX 5600 */ | |
1935 | case 0x0320: /* GeForceFX 5200 */ | |
1936 | case 0x0330: /* GeForceFX 5900 */ | |
1937 | case 0x0340: /* GeForceFX 5700 */ | |
1938 | arch = NV_ARCH_30; | |
1939 | break; | |
1940 | case 0x0020: /* TNT, TNT2 */ | |
1941 | arch = NV_ARCH_04; | |
1942 | break; | |
1943 | case 0x0010: /* Riva128 */ | |
1944 | arch = NV_ARCH_03; | |
1945 | break; | |
1946 | default: /* unknown architecture */ | |
1947 | break; | |
1948 | } | |
1949 | return arch; | |
1950 | } | |
1951 | ||
1952 | static int __devinit rivafb_probe(struct pci_dev *pd, | |
1953 | const struct pci_device_id *ent) | |
1954 | { | |
1955 | struct riva_par *default_par; | |
1956 | struct fb_info *info; | |
1957 | int ret; | |
1958 | ||
1959 | NVTRACE_ENTER(); | |
1960 | assert(pd != NULL); | |
1961 | ||
1962 | info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); | |
1963 | if (!info) { | |
1964 | printk (KERN_ERR PFX "could not allocate memory\n"); | |
1965 | ret = -ENOMEM; | |
1966 | goto err_ret; | |
1967 | } | |
f4a41836 | 1968 | default_par = info->par; |
1da177e4 LT |
1969 | default_par->pdev = pd; |
1970 | ||
1971 | info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL); | |
1972 | if (info->pixmap.addr == NULL) { | |
1973 | ret = -ENOMEM; | |
1974 | goto err_framebuffer_release; | |
1975 | } | |
1976 | memset(info->pixmap.addr, 0, 8 * 1024); | |
1977 | ||
1978 | ret = pci_enable_device(pd); | |
1979 | if (ret < 0) { | |
1980 | printk(KERN_ERR PFX "cannot enable PCI device\n"); | |
1981 | goto err_free_pixmap; | |
1982 | } | |
1983 | ||
1984 | ret = pci_request_regions(pd, "rivafb"); | |
1985 | if (ret < 0) { | |
1986 | printk(KERN_ERR PFX "cannot request PCI regions\n"); | |
1987 | goto err_disable_device; | |
1988 | } | |
1989 | ||
1990 | default_par->riva.Architecture = riva_get_arch(pd); | |
1991 | ||
1992 | default_par->Chipset = (pd->vendor << 16) | pd->device; | |
1993 | printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); | |
1994 | ||
1da177e4 LT |
1995 | if(default_par->riva.Architecture == 0) { |
1996 | printk(KERN_ERR PFX "unknown NV_ARCH\n"); | |
1997 | ret=-ENODEV; | |
1998 | goto err_release_region; | |
1999 | } | |
2000 | if(default_par->riva.Architecture == NV_ARCH_10 || | |
2001 | default_par->riva.Architecture == NV_ARCH_20 || | |
2002 | default_par->riva.Architecture == NV_ARCH_30) { | |
2003 | sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); | |
2004 | } else { | |
2005 | sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); | |
2006 | } | |
2007 | ||
2008 | default_par->FlatPanel = flatpanel; | |
2009 | if (flatpanel == 1) | |
2010 | printk(KERN_INFO PFX "flatpanel support enabled\n"); | |
2011 | default_par->forceCRTC = forceCRTC; | |
2012 | ||
2013 | rivafb_fix.mmio_len = pci_resource_len(pd, 0); | |
2014 | rivafb_fix.smem_len = pci_resource_len(pd, 1); | |
2015 | ||
2016 | { | |
2017 | /* enable IO and mem if not already done */ | |
2018 | unsigned short cmd; | |
2019 | ||
2020 | pci_read_config_word(pd, PCI_COMMAND, &cmd); | |
2021 | cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
2022 | pci_write_config_word(pd, PCI_COMMAND, cmd); | |
2023 | } | |
2024 | ||
2025 | rivafb_fix.mmio_start = pci_resource_start(pd, 0); | |
2026 | rivafb_fix.smem_start = pci_resource_start(pd, 1); | |
2027 | ||
2028 | default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, | |
2029 | rivafb_fix.mmio_len); | |
2030 | if (!default_par->ctrl_base) { | |
2031 | printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); | |
2032 | ret = -EIO; | |
2033 | goto err_release_region; | |
2034 | } | |
2035 | ||
2036 | switch (default_par->riva.Architecture) { | |
2037 | case NV_ARCH_03: | |
2038 | /* Riva128's PRAMIN is in the "framebuffer" space | |
2039 | * Since these cards were never made with more than 8 megabytes | |
2040 | * we can safely allocate this separately. | |
2041 | */ | |
2042 | default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); | |
2043 | if (!default_par->riva.PRAMIN) { | |
2044 | printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); | |
2045 | ret = -EIO; | |
2046 | goto err_iounmap_ctrl_base; | |
2047 | } | |
2048 | break; | |
2049 | case NV_ARCH_04: | |
2050 | case NV_ARCH_10: | |
2051 | case NV_ARCH_20: | |
2052 | case NV_ARCH_30: | |
2053 | default_par->riva.PCRTC0 = | |
2054 | (u32 __iomem *)(default_par->ctrl_base + 0x00600000); | |
2055 | default_par->riva.PRAMIN = | |
2056 | (u32 __iomem *)(default_par->ctrl_base + 0x00710000); | |
2057 | break; | |
2058 | } | |
2059 | riva_common_setup(default_par); | |
2060 | ||
2061 | if (default_par->riva.Architecture == NV_ARCH_03) { | |
2062 | default_par->riva.PCRTC = default_par->riva.PCRTC0 | |
2063 | = default_par->riva.PGRAPH; | |
2064 | } | |
2065 | ||
2066 | rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; | |
2067 | default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; | |
2068 | info->screen_base = ioremap(rivafb_fix.smem_start, | |
2069 | rivafb_fix.smem_len); | |
2070 | if (!info->screen_base) { | |
2071 | printk(KERN_ERR PFX "cannot ioremap FB base\n"); | |
2072 | ret = -EIO; | |
2073 | goto err_iounmap_pramin; | |
2074 | } | |
2075 | ||
2076 | #ifdef CONFIG_MTRR | |
2077 | if (!nomtrr) { | |
2078 | default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, | |
2079 | rivafb_fix.smem_len, | |
2080 | MTRR_TYPE_WRCOMB, 1); | |
2081 | if (default_par->mtrr.vram < 0) { | |
2082 | printk(KERN_ERR PFX "unable to setup MTRR\n"); | |
2083 | } else { | |
2084 | default_par->mtrr.vram_valid = 1; | |
2085 | /* let there be speed */ | |
2086 | printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); | |
2087 | } | |
2088 | } | |
2089 | #endif /* CONFIG_MTRR */ | |
2090 | ||
2091 | info->fbops = &riva_fb_ops; | |
2092 | info->fix = rivafb_fix; | |
2093 | riva_get_EDID(info, pd); | |
2094 | riva_get_edidinfo(info); | |
2095 | ||
2096 | ret=riva_set_fbinfo(info); | |
2097 | if (ret < 0) { | |
2098 | printk(KERN_ERR PFX "error setting initial video mode\n"); | |
2099 | goto err_iounmap_screen_base; | |
2100 | } | |
2101 | ||
2102 | fb_destroy_modedb(info->monspecs.modedb); | |
2103 | info->monspecs.modedb = NULL; | |
ce38cac4 GG |
2104 | |
2105 | pci_set_drvdata(pd, info); | |
2106 | riva_bl_init(info->par); | |
1da177e4 LT |
2107 | ret = register_framebuffer(info); |
2108 | if (ret < 0) { | |
2109 | printk(KERN_ERR PFX | |
2110 | "error registering riva framebuffer\n"); | |
2111 | goto err_iounmap_screen_base; | |
2112 | } | |
2113 | ||
1da177e4 LT |
2114 | printk(KERN_INFO PFX |
2115 | "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", | |
2116 | info->fix.id, | |
2117 | RIVAFB_VERSION, | |
2118 | info->fix.smem_len / (1024 * 1024), | |
2119 | info->fix.smem_start); | |
5474c120 | 2120 | |
1da177e4 LT |
2121 | NVTRACE_LEAVE(); |
2122 | return 0; | |
2123 | ||
2124 | err_iounmap_screen_base: | |
2125 | #ifdef CONFIG_FB_RIVA_I2C | |
f4a41836 | 2126 | riva_delete_i2c_busses(info->par); |
1da177e4 LT |
2127 | #endif |
2128 | iounmap(info->screen_base); | |
2129 | err_iounmap_pramin: | |
2130 | if (default_par->riva.Architecture == NV_ARCH_03) | |
2131 | iounmap(default_par->riva.PRAMIN); | |
2132 | err_iounmap_ctrl_base: | |
2133 | iounmap(default_par->ctrl_base); | |
2134 | err_release_region: | |
2135 | pci_release_regions(pd); | |
2136 | err_disable_device: | |
1da177e4 LT |
2137 | err_free_pixmap: |
2138 | kfree(info->pixmap.addr); | |
2139 | err_framebuffer_release: | |
2140 | framebuffer_release(info); | |
2141 | err_ret: | |
2142 | return ret; | |
2143 | } | |
2144 | ||
2145 | static void __exit rivafb_remove(struct pci_dev *pd) | |
2146 | { | |
2147 | struct fb_info *info = pci_get_drvdata(pd); | |
f4a41836 | 2148 | struct riva_par *par = info->par; |
1da177e4 LT |
2149 | |
2150 | NVTRACE_ENTER(); | |
1da177e4 | 2151 | |
5474c120 MH |
2152 | riva_bl_exit(par); |
2153 | ||
1da177e4 LT |
2154 | #ifdef CONFIG_FB_RIVA_I2C |
2155 | riva_delete_i2c_busses(par); | |
2156 | kfree(par->EDID); | |
2157 | #endif | |
2158 | ||
2159 | unregister_framebuffer(info); | |
2160 | #ifdef CONFIG_MTRR | |
2161 | if (par->mtrr.vram_valid) | |
2162 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | |
2163 | info->fix.smem_len); | |
2164 | #endif /* CONFIG_MTRR */ | |
2165 | ||
2166 | iounmap(par->ctrl_base); | |
2167 | iounmap(info->screen_base); | |
2168 | if (par->riva.Architecture == NV_ARCH_03) | |
2169 | iounmap(par->riva.PRAMIN); | |
2170 | pci_release_regions(pd); | |
1da177e4 LT |
2171 | kfree(info->pixmap.addr); |
2172 | framebuffer_release(info); | |
2173 | pci_set_drvdata(pd, NULL); | |
2174 | NVTRACE_LEAVE(); | |
2175 | } | |
2176 | ||
2177 | /* ------------------------------------------------------------------------- * | |
2178 | * | |
2179 | * initialization | |
2180 | * | |
2181 | * ------------------------------------------------------------------------- */ | |
2182 | ||
2183 | #ifndef MODULE | |
2184 | static int __init rivafb_setup(char *options) | |
2185 | { | |
2186 | char *this_opt; | |
2187 | ||
2188 | NVTRACE_ENTER(); | |
2189 | if (!options || !*options) | |
2190 | return 0; | |
2191 | ||
2192 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
2193 | if (!strncmp(this_opt, "forceCRTC", 9)) { | |
2194 | char *p; | |
2195 | ||
2196 | p = this_opt + 9; | |
2197 | if (!*p || !*(++p)) continue; | |
2198 | forceCRTC = *p - '0'; | |
2199 | if (forceCRTC < 0 || forceCRTC > 1) | |
2200 | forceCRTC = -1; | |
2201 | } else if (!strncmp(this_opt, "flatpanel", 9)) { | |
2202 | flatpanel = 1; | |
2203 | #ifdef CONFIG_MTRR | |
2204 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | |
2205 | nomtrr = 1; | |
2206 | #endif | |
2207 | } else if (!strncmp(this_opt, "strictmode", 10)) { | |
2208 | strictmode = 1; | |
2209 | } else if (!strncmp(this_opt, "noaccel", 7)) { | |
2210 | noaccel = 1; | |
2211 | } else | |
2212 | mode_option = this_opt; | |
2213 | } | |
2214 | NVTRACE_LEAVE(); | |
2215 | return 0; | |
2216 | } | |
2217 | #endif /* !MODULE */ | |
2218 | ||
2219 | static struct pci_driver rivafb_driver = { | |
2220 | .name = "rivafb", | |
2221 | .id_table = rivafb_pci_tbl, | |
2222 | .probe = rivafb_probe, | |
2223 | .remove = __exit_p(rivafb_remove), | |
2224 | }; | |
2225 | ||
2226 | ||
2227 | ||
2228 | /* ------------------------------------------------------------------------- * | |
2229 | * | |
2230 | * modularization | |
2231 | * | |
2232 | * ------------------------------------------------------------------------- */ | |
2233 | ||
2234 | static int __devinit rivafb_init(void) | |
2235 | { | |
2236 | #ifndef MODULE | |
2237 | char *option = NULL; | |
2238 | ||
2239 | if (fb_get_options("rivafb", &option)) | |
2240 | return -ENODEV; | |
2241 | rivafb_setup(option); | |
2242 | #endif | |
2243 | return pci_register_driver(&rivafb_driver); | |
2244 | } | |
2245 | ||
2246 | ||
2247 | module_init(rivafb_init); | |
2248 | ||
2249 | #ifdef MODULE | |
2250 | static void __exit rivafb_exit(void) | |
2251 | { | |
2252 | pci_unregister_driver(&rivafb_driver); | |
2253 | } | |
2254 | ||
2255 | module_exit(rivafb_exit); | |
2256 | #endif /* MODULE */ | |
2257 | ||
2258 | module_param(noaccel, bool, 0); | |
2259 | MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); | |
2260 | module_param(flatpanel, int, 0); | |
2261 | MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); | |
2262 | module_param(forceCRTC, int, 0); | |
2263 | MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); | |
2264 | #ifdef CONFIG_MTRR | |
2265 | module_param(nomtrr, bool, 0); | |
2266 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); | |
2267 | #endif | |
2268 | module_param(strictmode, bool, 0); | |
2269 | MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); | |
2270 | ||
2271 | MODULE_AUTHOR("Ani Joshi, maintainer"); | |
2272 | MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); | |
2273 | MODULE_LICENSE("GPL"); |