[mirror_ubuntu-jammy-kernel.git] / drivers / video / riva / rivafb-i2c.c

/*
 * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
 *
 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
 *
 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
 *
 * Based on radeonfb-i2c.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <linux/jiffies.h>

#include <asm/io.h>

#include "rivafb.h"
#include "../edid.h"

#define RIVA_DDC 	0x50

static void riva_gpio_setscl(void* data, int state)
{
	struct riva_i2c_chan 	*chan = data;
	struct riva_par 	*par = chan->par;
	u32			val;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;

	if (state)
		val |= 0x20;
	else
		val &= ~0x20;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}

static void riva_gpio_setsda(void* data, int state)
{
	struct riva_i2c_chan 	*chan = data;
	struct riva_par 	*par = chan->par;
	u32			val;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;

	if (state)
		val |= 0x10;
	else
		val &= ~0x10;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}

static int riva_gpio_getscl(void* data)
{
	struct riva_i2c_chan 	*chan = data;
	struct riva_par 	*par = chan->par;
	u32			val = 0;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
	if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
		val = 1;

	val = VGA_RD08(par->riva.PCIO, 0x3d5);

	return val;
}

static int riva_gpio_getsda(void* data)
{
	struct riva_i2c_chan 	*chan = data;
	struct riva_par 	*par = chan->par;
	u32			val = 0;

	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
	if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
		val = 1;

	return val;
}

static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name)
{
	int rc;

	strcpy(chan->adapter.name, name);
	chan->adapter.owner		= THIS_MODULE;
	chan->adapter.id		= I2C_HW_B_RIVA;
	chan->adapter.algo_data		= &chan->algo;
	chan->adapter.dev.parent	= &chan->par->pdev->dev;
	chan->algo.setsda		= riva_gpio_setsda;
	chan->algo.setscl		= riva_gpio_setscl;
	chan->algo.getsda		= riva_gpio_getsda;
	chan->algo.getscl		= riva_gpio_getscl;
	chan->algo.udelay		= 40;
	chan->algo.timeout		= msecs_to_jiffies(2);
	chan->algo.data 		= chan;

	i2c_set_adapdata(&chan->adapter, chan);

	/* Raise SCL and SDA */
	riva_gpio_setsda(chan, 1);
	riva_gpio_setscl(chan, 1);
	udelay(20);

	rc = i2c_bit_add_bus(&chan->adapter);
	if (rc == 0)
		dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
	else {
		dev_warn(&chan->par->pdev->dev,
			 "Failed to register I2C bus %s.\n", name);
		chan->par = NULL;
	}

	return rc;
}

void riva_create_i2c_busses(struct riva_par *par)
{
	par->bus = 3;

	par->chan[0].par	= par;
	par->chan[1].par	= par;
	par->chan[2].par        = par;

	par->chan[0].ddc_base = 0x3e;
	par->chan[1].ddc_base = 0x36;
	par->chan[2].ddc_base = 0x50;
	riva_setup_i2c_bus(&par->chan[0], "BUS1");
	riva_setup_i2c_bus(&par->chan[1], "BUS2");
	riva_setup_i2c_bus(&par->chan[2], "BUS3");
}

void riva_delete_i2c_busses(struct riva_par *par)
{
	if (par->chan[0].par)
		i2c_bit_del_bus(&par->chan[0].adapter);
	par->chan[0].par = NULL;

	if (par->chan[1].par)
		i2c_bit_del_bus(&par->chan[1].adapter);
	par->chan[1].par = NULL;

	if (par->chan[2].par)
		i2c_bit_del_bus(&par->chan[2].adapter);
	par->chan[2].par = NULL;
}

static u8 *riva_do_probe_i2c_edid(struct riva_i2c_chan *chan)
{
	u8 start = 0x0;
	struct i2c_msg msgs[] = {
		{
			.addr	= RIVA_DDC,
			.len	= 1,
			.buf	= &start,
		}, {
			.addr	= RIVA_DDC,
			.flags	= I2C_M_RD,
			.len	= EDID_LENGTH,
		},
	};
	u8 *buf;

	if (!chan->par)
		return NULL;

	buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
	if (!buf) {
		dev_warn(&chan->par->pdev->dev, "Out of memory!\n");
		return NULL;
	}
	msgs[1].buf = buf;

	if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
		return buf;
	dev_dbg(&chan->par->pdev->dev, "Unable to read EDID block.\n");
	kfree(buf);
	return NULL;
}

int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
{
	u8 *edid = NULL;
	int i;

	for (i = 0; i < 3; i++) {
		/* Do the real work */
		edid = riva_do_probe_i2c_edid(&par->chan[conn-1]);
		if (edid)
			break;
	}
	if (out_edid)
		*out_edid = edid;
	if (!edid)
		return 1;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
	3	*
	4	* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
	5	*
	6	* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
	7	*
	8	* Based on radeonfb-i2c.c
	9	*
	10	* This file is subject to the terms and conditions of the GNU General Public
	11	* License. See the file COPYING in the main directory of this archive
	12	* for more details.
	13	*/
	14
1da177e4 LT	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/sched.h>
	18	#include <linux/delay.h>
	19	#include <linux/pci.h>
	20	#include <linux/fb.h>
	21	#include <linux/jiffies.h>
	22
	23	#include <asm/io.h>
	24
	25	#include "rivafb.h"
	26	#include "../edid.h"
	27
	28	#define RIVA_DDC 0x50
	29
	30	static void riva_gpio_setscl(void* data, int state)
	31	{
f4a41836	32	struct riva_i2c_chan *chan = data;
1da177e4 LT	33	struct riva_par *par = chan->par;
	34	u32 val;
	35
	36	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	37	val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
	38
	39	if (state)
	40	val \|= 0x20;
	41	else
	42	val &= ~0x20;
	43
	44	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	45	VGA_WR08(par->riva.PCIO, 0x3d5, val \| 0x1);
	46	}
	47
	48	static void riva_gpio_setsda(void* data, int state)
	49	{
f4a41836	50	struct riva_i2c_chan *chan = data;
1da177e4 LT	51	struct riva_par *par = chan->par;
	52	u32 val;
	53
	54	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	55	val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
	56
	57	if (state)
	58	val \|= 0x10;
	59	else
	60	val &= ~0x10;
	61
	62	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
	63	VGA_WR08(par->riva.PCIO, 0x3d5, val \| 0x1);
	64	}
	65
	66	static int riva_gpio_getscl(void* data)
	67	{
f4a41836	68	struct riva_i2c_chan *chan = data;
1da177e4 LT	69	struct riva_par *par = chan->par;
	70	u32 val = 0;
	71
	72	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
	73	if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
	74	val = 1;
	75
	76	val = VGA_RD08(par->riva.PCIO, 0x3d5);
	77
	78	return val;
	79	}
	80
	81	static int riva_gpio_getsda(void* data)
	82	{
f4a41836	83	struct riva_i2c_chan *chan = data;
1da177e4 LT	84	struct riva_par *par = chan->par;
	85	u32 val = 0;
	86
	87	VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
	88	if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
	89	val = 1;
	90
	91	return val;
	92	}
	93
1da177e4 LT	94	static int riva_setup_i2c_bus(struct riva_i2c_chan chan, const char name)
	95	{
	96	int rc;
	97
	98	strcpy(chan->adapter.name, name);
	99	chan->adapter.owner = THIS_MODULE;
1684a984	100	chan->adapter.id = I2C_HW_B_RIVA;
1da177e4 LT	101	chan->adapter.algo_data = &chan->algo;
	102	chan->adapter.dev.parent = &chan->par->pdev->dev;
	103	chan->algo.setsda = riva_gpio_setsda;
	104	chan->algo.setscl = riva_gpio_setscl;
	105	chan->algo.getsda = riva_gpio_getsda;
	106	chan->algo.getscl = riva_gpio_getscl;
	107	chan->algo.udelay = 40;
	108	chan->algo.timeout = msecs_to_jiffies(2);
	109	chan->algo.data = chan;
	110
	111	i2c_set_adapdata(&chan->adapter, chan);
	112
	113	/* Raise SCL and SDA */
	114	riva_gpio_setsda(chan, 1);
	115	riva_gpio_setscl(chan, 1);
	116	udelay(20);
	117
	118	rc = i2c_bit_add_bus(&chan->adapter);
	119	if (rc == 0)
	120	dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
	121	else {
	122	dev_warn(&chan->par->pdev->dev,
	123	"Failed to register I2C bus %s.\n", name);
	124	chan->par = NULL;
	125	}
	126
	127	return rc;
	128	}
	129
	130	void riva_create_i2c_busses(struct riva_par *par)
	131	{
	132	par->bus = 3;
	133
	134	par->chan[0].par = par;
	135	par->chan[1].par = par;
	136	par->chan[2].par = par;
	137
	138	par->chan[0].ddc_base = 0x3e;
	139	par->chan[1].ddc_base = 0x36;
	140	par->chan[2].ddc_base = 0x50;
	141	riva_setup_i2c_bus(&par->chan[0], "BUS1");
	142	riva_setup_i2c_bus(&par->chan[1], "BUS2");
	143	riva_setup_i2c_bus(&par->chan[2], "BUS3");
	144	}
	145
	146	void riva_delete_i2c_busses(struct riva_par *par)
	147	{
	148	if (par->chan[0].par)
	149	i2c_bit_del_bus(&par->chan[0].adapter);
	150	par->chan[0].par = NULL;
	151
	152	if (par->chan[1].par)
	153	i2c_bit_del_bus(&par->chan[1].adapter);
	154	par->chan[1].par = NULL;
	155
	156	if (par->chan[2].par)
	157	i2c_bit_del_bus(&par->chan[2].adapter);
	158	par->chan[2].par = NULL;
	159	}
	160
	161	static u8 riva_do_probe_i2c_edid(struct riva_i2c_chan chan)
	162	{
	163	u8 start = 0x0;
	164	struct i2c_msg msgs[] = {
165	{
166	.addr = RIVA_DDC,
167	.len = 1,
168	.buf = &start,
169	}, {
170	.addr = RIVA_DDC,
171	.flags = I2C_M_RD,
172	.len = EDID_LENGTH,
173	},
174	};
175	u8 *buf;
176
177	if (!chan->par)
178	return NULL;
179
180	buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
181	if (!buf) {
182	dev_warn(&chan->par->pdev->dev, "Out of memory!\n");
183	return NULL;
184	}
185	msgs[1].buf = buf;
186
187	if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
188	return buf;
189	dev_dbg(&chan->par->pdev->dev, "Unable to read EDID block.\n");
190	kfree(buf);
191	return NULL;
192	}
193
194	int riva_probe_i2c_connector(struct riva_par par, int conn, u8 *out_edid)
195	{
196	u8 *edid = NULL;
197	int i;
198
199	for (i = 0; i < 3; i++) {
200	/* Do the real work */
201	edid = riva_do_probe_i2c_edid(&par->chan[conn-1]);
202	if (edid)
203	break;
204	}
205	if (out_edid)
206	*out_edid = edid;
207	if (!edid)
208	return 1;
209
210	return 0;
211	}
212