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6a0e4ec7 BD |
1 | /* linux/drivers/video/s3c2410fb.c |
2 | * Copyright (c) 2004,2005 Arnaud Patard | |
3 | * Copyright (c) 2004-2008 Ben Dooks | |
4 | * | |
5 | * S3C2410 LCD Framebuffer Driver | |
20fd5767 AP |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | * | |
6a0e4ec7 BD |
11 | * Driver based on skeletonfb.c, sa1100fb.c and others. |
12 | */ | |
20fd5767 AP |
13 | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/mm.h> | |
20fd5767 AP |
19 | #include <linux/slab.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/fb.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/dma-mapping.h> | |
20fd5767 | 24 | #include <linux/interrupt.h> |
d052d1be | 25 | #include <linux/platform_device.h> |
f8ce2547 | 26 | #include <linux/clk.h> |
20fd5767 AP |
27 | |
28 | #include <asm/io.h> | |
20fd5767 AP |
29 | #include <asm/div64.h> |
30 | ||
31 | #include <asm/mach/map.h> | |
a09e64fb RK |
32 | #include <mach/regs-lcd.h> |
33 | #include <mach/regs-gpio.h> | |
34 | #include <mach/fb.h> | |
20fd5767 AP |
35 | |
36 | #ifdef CONFIG_PM | |
37 | #include <linux/pm.h> | |
38 | #endif | |
39 | ||
40 | #include "s3c2410fb.h" | |
41 | ||
20fd5767 AP |
42 | /* Debugging stuff */ |
43 | #ifdef CONFIG_FB_S3C2410_DEBUG | |
b0831941 | 44 | static int debug = 1; |
20fd5767 | 45 | #else |
b0831941 | 46 | static int debug = 0; |
20fd5767 AP |
47 | #endif |
48 | ||
49 | #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); } | |
50 | ||
51 | /* useful functions */ | |
52 | ||
f62e770b BD |
53 | static int is_s3c2412(struct s3c2410fb_info *fbi) |
54 | { | |
55 | return (fbi->drv_type == DRV_S3C2412); | |
56 | } | |
57 | ||
20fd5767 AP |
58 | /* s3c2410fb_set_lcdaddr |
59 | * | |
60 | * initialise lcd controller address pointers | |
b0831941 | 61 | */ |
110c1fa7 | 62 | static void s3c2410fb_set_lcdaddr(struct fb_info *info) |
20fd5767 | 63 | { |
20fd5767 | 64 | unsigned long saddr1, saddr2, saddr3; |
7ee0fe41 KH |
65 | struct s3c2410fb_info *fbi = info->par; |
66 | void __iomem *regs = fbi->io; | |
20fd5767 | 67 | |
110c1fa7 KH |
68 | saddr1 = info->fix.smem_start >> 1; |
69 | saddr2 = info->fix.smem_start; | |
9fa7bc01 | 70 | saddr2 += info->fix.line_length * info->var.yres; |
b0831941 | 71 | saddr2 >>= 1; |
20fd5767 | 72 | |
b0831941 | 73 | saddr3 = S3C2410_OFFSIZE(0) | |
9fa7bc01 | 74 | S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff); |
20fd5767 AP |
75 | |
76 | dprintk("LCDSADDR1 = 0x%08lx\n", saddr1); | |
77 | dprintk("LCDSADDR2 = 0x%08lx\n", saddr2); | |
78 | dprintk("LCDSADDR3 = 0x%08lx\n", saddr3); | |
79 | ||
7ee0fe41 KH |
80 | writel(saddr1, regs + S3C2410_LCDSADDR1); |
81 | writel(saddr2, regs + S3C2410_LCDSADDR2); | |
82 | writel(saddr3, regs + S3C2410_LCDSADDR3); | |
20fd5767 AP |
83 | } |
84 | ||
85 | /* s3c2410fb_calc_pixclk() | |
86 | * | |
87 | * calculate divisor for clk->pixclk | |
b0831941 | 88 | */ |
20fd5767 AP |
89 | static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi, |
90 | unsigned long pixclk) | |
91 | { | |
92 | unsigned long clk = clk_get_rate(fbi->clk); | |
93 | unsigned long long div; | |
94 | ||
9fa7bc01 | 95 | /* pixclk is in picoseconds, our clock is in Hz |
20fd5767 AP |
96 | * |
97 | * Hz -> picoseconds is / 10^-12 | |
98 | */ | |
99 | ||
100 | div = (unsigned long long)clk * pixclk; | |
9fa7bc01 KH |
101 | div >>= 12; /* div / 2^12 */ |
102 | do_div(div, 625 * 625UL * 625); /* div / 5^12 */ | |
20fd5767 AP |
103 | |
104 | dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div); | |
105 | return div; | |
106 | } | |
107 | ||
108 | /* | |
109 | * s3c2410fb_check_var(): | |
110 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
111 | * if it's too big, return -EINVAL. | |
112 | * | |
113 | */ | |
114 | static int s3c2410fb_check_var(struct fb_var_screeninfo *var, | |
115 | struct fb_info *info) | |
116 | { | |
117 | struct s3c2410fb_info *fbi = info->par; | |
9fa7bc01 | 118 | struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data; |
09fe75f6 | 119 | struct s3c2410fb_display *display = NULL; |
e7076389 KH |
120 | struct s3c2410fb_display *default_display = mach_info->displays + |
121 | mach_info->default_display; | |
122 | int type = default_display->type; | |
09fe75f6 | 123 | unsigned i; |
20fd5767 AP |
124 | |
125 | dprintk("check_var(var=%p, info=%p)\n", var, info); | |
126 | ||
127 | /* validate x/y resolution */ | |
e7076389 KH |
128 | /* choose default mode if possible */ |
129 | if (var->yres == default_display->yres && | |
130 | var->xres == default_display->xres && | |
131 | var->bits_per_pixel == default_display->bpp) | |
132 | display = default_display; | |
133 | else | |
134 | for (i = 0; i < mach_info->num_displays; i++) | |
135 | if (type == mach_info->displays[i].type && | |
136 | var->yres == mach_info->displays[i].yres && | |
137 | var->xres == mach_info->displays[i].xres && | |
138 | var->bits_per_pixel == mach_info->displays[i].bpp) { | |
139 | display = mach_info->displays + i; | |
140 | break; | |
141 | } | |
20fd5767 | 142 | |
09fe75f6 KH |
143 | if (!display) { |
144 | dprintk("wrong resolution or depth %dx%d at %d bpp\n", | |
145 | var->xres, var->yres, var->bits_per_pixel); | |
146 | return -EINVAL; | |
147 | } | |
20fd5767 | 148 | |
9939a481 KH |
149 | /* it is always the size as the display */ |
150 | var->xres_virtual = display->xres; | |
151 | var->yres_virtual = display->yres; | |
9fa7bc01 KH |
152 | var->height = display->height; |
153 | var->width = display->width; | |
9939a481 KH |
154 | |
155 | /* copy lcd settings */ | |
69816699 | 156 | var->pixclock = display->pixclock; |
9939a481 KH |
157 | var->left_margin = display->left_margin; |
158 | var->right_margin = display->right_margin; | |
9fa7bc01 KH |
159 | var->upper_margin = display->upper_margin; |
160 | var->lower_margin = display->lower_margin; | |
161 | var->vsync_len = display->vsync_len; | |
162 | var->hsync_len = display->hsync_len; | |
163 | ||
9fa7bc01 KH |
164 | fbi->regs.lcdcon5 = display->lcdcon5; |
165 | /* set display type */ | |
36f31a70 | 166 | fbi->regs.lcdcon1 = display->type; |
9939a481 | 167 | |
b0831941 KH |
168 | var->transp.offset = 0; |
169 | var->transp.length = 0; | |
20fd5767 | 170 | /* set r/g/b positions */ |
357b819d | 171 | switch (var->bits_per_pixel) { |
b0831941 KH |
172 | case 1: |
173 | case 2: | |
174 | case 4: | |
175 | var->red.offset = 0; | |
176 | var->red.length = var->bits_per_pixel; | |
177 | var->green = var->red; | |
178 | var->blue = var->red; | |
179 | break; | |
180 | case 8: | |
09fe75f6 | 181 | if (display->type != S3C2410_LCDCON1_TFT) { |
b0831941 KH |
182 | /* 8 bpp 332 */ |
183 | var->red.length = 3; | |
184 | var->red.offset = 5; | |
185 | var->green.length = 3; | |
186 | var->green.offset = 2; | |
187 | var->blue.length = 2; | |
357b819d | 188 | var->blue.offset = 0; |
b0831941 KH |
189 | } else { |
190 | var->red.offset = 0; | |
357b819d | 191 | var->red.length = 8; |
b0831941 KH |
192 | var->green = var->red; |
193 | var->blue = var->red; | |
194 | } | |
195 | break; | |
196 | case 12: | |
197 | /* 12 bpp 444 */ | |
198 | var->red.length = 4; | |
199 | var->red.offset = 8; | |
200 | var->green.length = 4; | |
201 | var->green.offset = 4; | |
202 | var->blue.length = 4; | |
203 | var->blue.offset = 0; | |
204 | break; | |
205 | ||
206 | default: | |
207 | case 16: | |
f28ef573 | 208 | if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) { |
b0831941 KH |
209 | /* 16 bpp, 565 format */ |
210 | var->red.offset = 11; | |
211 | var->green.offset = 5; | |
357b819d | 212 | var->blue.offset = 0; |
b0831941 KH |
213 | var->red.length = 5; |
214 | var->green.length = 6; | |
215 | var->blue.length = 5; | |
216 | } else { | |
217 | /* 16 bpp, 5551 format */ | |
218 | var->red.offset = 11; | |
219 | var->green.offset = 6; | |
220 | var->blue.offset = 1; | |
221 | var->red.length = 5; | |
222 | var->green.length = 5; | |
223 | var->blue.length = 5; | |
224 | } | |
225 | break; | |
93613b9f KH |
226 | case 32: |
227 | /* 24 bpp 888 and 8 dummy */ | |
b0831941 KH |
228 | var->red.length = 8; |
229 | var->red.offset = 16; | |
230 | var->green.length = 8; | |
231 | var->green.offset = 8; | |
232 | var->blue.length = 8; | |
233 | var->blue.offset = 0; | |
234 | break; | |
357b819d | 235 | } |
20fd5767 AP |
236 | return 0; |
237 | } | |
238 | ||
9939a481 | 239 | /* s3c2410fb_calculate_stn_lcd_regs |
20fd5767 | 240 | * |
9939a481 | 241 | * calculate register values from var settings |
b0831941 | 242 | */ |
9939a481 KH |
243 | static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info, |
244 | struct s3c2410fb_hw *regs) | |
20fd5767 | 245 | { |
9939a481 KH |
246 | const struct s3c2410fb_info *fbi = info->par; |
247 | const struct fb_var_screeninfo *var = &info->var; | |
248 | int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT; | |
249 | int hs = var->xres >> 2; | |
250 | unsigned wdly = (var->left_margin >> 4) - 1; | |
93d11f5a | 251 | unsigned wlh = (var->hsync_len >> 4) - 1; |
20fd5767 | 252 | |
9939a481 KH |
253 | if (type != S3C2410_LCDCON1_STN4) |
254 | hs >>= 1; | |
357b819d | 255 | |
9939a481 KH |
256 | switch (var->bits_per_pixel) { |
257 | case 1: | |
258 | regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP; | |
259 | break; | |
260 | case 2: | |
261 | regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY; | |
262 | break; | |
263 | case 4: | |
264 | regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY; | |
265 | break; | |
266 | case 8: | |
267 | regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP; | |
268 | hs *= 3; | |
269 | break; | |
270 | case 12: | |
271 | regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP; | |
272 | hs *= 3; | |
273 | break; | |
20fd5767 | 274 | |
9939a481 KH |
275 | default: |
276 | /* invalid pixel depth */ | |
277 | dev_err(fbi->dev, "invalid bpp %d\n", | |
278 | var->bits_per_pixel); | |
279 | } | |
280 | /* update X/Y info */ | |
9939a481 KH |
281 | dprintk("setting horz: lft=%d, rt=%d, sync=%d\n", |
282 | var->left_margin, var->right_margin, var->hsync_len); | |
20fd5767 | 283 | |
3c9ffd05 | 284 | regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1); |
20fd5767 | 285 | |
9939a481 KH |
286 | if (wdly > 3) |
287 | wdly = 3; | |
20fd5767 | 288 | |
93d11f5a KH |
289 | if (wlh > 3) |
290 | wlh = 3; | |
291 | ||
9939a481 KH |
292 | regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) | |
293 | S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) | | |
294 | S3C2410_LCDCON3_HOZVAL(hs - 1); | |
93d11f5a | 295 | |
e92e7395 | 296 | regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh); |
9939a481 | 297 | } |
20fd5767 | 298 | |
9939a481 KH |
299 | /* s3c2410fb_calculate_tft_lcd_regs |
300 | * | |
301 | * calculate register values from var settings | |
302 | */ | |
303 | static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info, | |
304 | struct s3c2410fb_hw *regs) | |
305 | { | |
306 | const struct s3c2410fb_info *fbi = info->par; | |
307 | const struct fb_var_screeninfo *var = &info->var; | |
20fd5767 | 308 | |
9939a481 KH |
309 | switch (var->bits_per_pixel) { |
310 | case 1: | |
311 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP; | |
312 | break; | |
313 | case 2: | |
314 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP; | |
b0831941 | 315 | break; |
9939a481 KH |
316 | case 4: |
317 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP; | |
b0831941 | 318 | break; |
9939a481 KH |
319 | case 8: |
320 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP; | |
93613b9f KH |
321 | regs->lcdcon5 |= S3C2410_LCDCON5_BSWP | |
322 | S3C2410_LCDCON5_FRM565; | |
323 | regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP; | |
9939a481 KH |
324 | break; |
325 | case 16: | |
326 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP; | |
93613b9f KH |
327 | regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP; |
328 | regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP; | |
329 | break; | |
330 | case 32: | |
331 | regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP; | |
332 | regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP | | |
333 | S3C2410_LCDCON5_HWSWP | | |
334 | S3C2410_LCDCON5_BPP24BL); | |
b0831941 | 335 | break; |
9939a481 KH |
336 | default: |
337 | /* invalid pixel depth */ | |
338 | dev_err(fbi->dev, "invalid bpp %d\n", | |
339 | var->bits_per_pixel); | |
357b819d | 340 | } |
9939a481 KH |
341 | /* update X/Y info */ |
342 | dprintk("setting vert: up=%d, low=%d, sync=%d\n", | |
343 | var->upper_margin, var->lower_margin, var->vsync_len); | |
357b819d | 344 | |
9939a481 KH |
345 | dprintk("setting horz: lft=%d, rt=%d, sync=%d\n", |
346 | var->left_margin, var->right_margin, var->hsync_len); | |
357b819d | 347 | |
93d11f5a KH |
348 | regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) | |
349 | S3C2410_LCDCON2_VBPD(var->upper_margin - 1) | | |
350 | S3C2410_LCDCON2_VFPD(var->lower_margin - 1) | | |
351 | S3C2410_LCDCON2_VSPW(var->vsync_len - 1); | |
9939a481 KH |
352 | |
353 | regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) | | |
354 | S3C2410_LCDCON3_HFPD(var->left_margin - 1) | | |
355 | S3C2410_LCDCON3_HOZVAL(var->xres - 1); | |
93d11f5a | 356 | |
e92e7395 | 357 | regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1); |
9939a481 KH |
358 | } |
359 | ||
360 | /* s3c2410fb_activate_var | |
361 | * | |
362 | * activate (set) the controller from the given framebuffer | |
363 | * information | |
364 | */ | |
365 | static void s3c2410fb_activate_var(struct fb_info *info) | |
366 | { | |
367 | struct s3c2410fb_info *fbi = info->par; | |
7ee0fe41 | 368 | void __iomem *regs = fbi->io; |
9fa7bc01 | 369 | int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT; |
9939a481 | 370 | struct fb_var_screeninfo *var = &info->var; |
69816699 | 371 | int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2; |
9939a481 | 372 | |
5ae12170 HH |
373 | dprintk("%s: var->xres = %d\n", __func__, var->xres); |
374 | dprintk("%s: var->yres = %d\n", __func__, var->yres); | |
375 | dprintk("%s: var->bpp = %d\n", __func__, var->bits_per_pixel); | |
20fd5767 | 376 | |
69816699 | 377 | if (type == S3C2410_LCDCON1_TFT) { |
9939a481 | 378 | s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs); |
69816699 KH |
379 | --clkdiv; |
380 | if (clkdiv < 0) | |
381 | clkdiv = 0; | |
382 | } else { | |
9939a481 | 383 | s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs); |
69816699 KH |
384 | if (clkdiv < 2) |
385 | clkdiv = 2; | |
386 | } | |
387 | ||
69816699 | 388 | fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv); |
9939a481 | 389 | |
20fd5767 AP |
390 | /* write new registers */ |
391 | ||
392 | dprintk("new register set:\n"); | |
393 | dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1); | |
394 | dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2); | |
395 | dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3); | |
396 | dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4); | |
397 | dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5); | |
398 | ||
7ee0fe41 KH |
399 | writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, |
400 | regs + S3C2410_LCDCON1); | |
401 | writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2); | |
402 | writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3); | |
403 | writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4); | |
404 | writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5); | |
20fd5767 AP |
405 | |
406 | /* set lcd address pointers */ | |
110c1fa7 | 407 | s3c2410fb_set_lcdaddr(info); |
20fd5767 | 408 | |
9fa7bc01 | 409 | fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID, |
7ee0fe41 | 410 | writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1); |
20fd5767 AP |
411 | } |
412 | ||
20fd5767 | 413 | /* |
b0831941 | 414 | * s3c2410fb_set_par - Alters the hardware state. |
20fd5767 AP |
415 | * @info: frame buffer structure that represents a single frame buffer |
416 | * | |
417 | */ | |
418 | static int s3c2410fb_set_par(struct fb_info *info) | |
419 | { | |
20fd5767 AP |
420 | struct fb_var_screeninfo *var = &info->var; |
421 | ||
b0831941 | 422 | switch (var->bits_per_pixel) { |
93613b9f | 423 | case 32: |
b0831941 | 424 | case 16: |
93613b9f | 425 | case 12: |
b0831941 KH |
426 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
427 | break; | |
428 | case 1: | |
429 | info->fix.visual = FB_VISUAL_MONO01; | |
430 | break; | |
431 | default: | |
432 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
433 | break; | |
357b819d | 434 | } |
20fd5767 | 435 | |
a1033604 | 436 | info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8; |
20fd5767 AP |
437 | |
438 | /* activate this new configuration */ | |
439 | ||
9939a481 | 440 | s3c2410fb_activate_var(info); |
20fd5767 AP |
441 | return 0; |
442 | } | |
443 | ||
444 | static void schedule_palette_update(struct s3c2410fb_info *fbi, | |
445 | unsigned int regno, unsigned int val) | |
446 | { | |
447 | unsigned long flags; | |
448 | unsigned long irqen; | |
f62e770b | 449 | void __iomem *irq_base = fbi->irq_base; |
20fd5767 AP |
450 | |
451 | local_irq_save(flags); | |
452 | ||
453 | fbi->palette_buffer[regno] = val; | |
454 | ||
455 | if (!fbi->palette_ready) { | |
456 | fbi->palette_ready = 1; | |
457 | ||
458 | /* enable IRQ */ | |
f62e770b | 459 | irqen = readl(irq_base + S3C24XX_LCDINTMSK); |
20fd5767 | 460 | irqen &= ~S3C2410_LCDINT_FRSYNC; |
f62e770b | 461 | writel(irqen, irq_base + S3C24XX_LCDINTMSK); |
20fd5767 AP |
462 | } |
463 | ||
464 | local_irq_restore(flags); | |
465 | } | |
466 | ||
467 | /* from pxafb.c */ | |
b0831941 KH |
468 | static inline unsigned int chan_to_field(unsigned int chan, |
469 | struct fb_bitfield *bf) | |
20fd5767 AP |
470 | { |
471 | chan &= 0xffff; | |
472 | chan >>= 16 - bf->length; | |
473 | return chan << bf->offset; | |
474 | } | |
475 | ||
476 | static int s3c2410fb_setcolreg(unsigned regno, | |
477 | unsigned red, unsigned green, unsigned blue, | |
478 | unsigned transp, struct fb_info *info) | |
479 | { | |
480 | struct s3c2410fb_info *fbi = info->par; | |
7ee0fe41 | 481 | void __iomem *regs = fbi->io; |
20fd5767 AP |
482 | unsigned int val; |
483 | ||
b0831941 KH |
484 | /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", |
485 | regno, red, green, blue); */ | |
20fd5767 | 486 | |
b0831941 | 487 | switch (info->fix.visual) { |
20fd5767 | 488 | case FB_VISUAL_TRUECOLOR: |
b0831941 | 489 | /* true-colour, use pseudo-palette */ |
20fd5767 AP |
490 | |
491 | if (regno < 16) { | |
b0831941 | 492 | u32 *pal = info->pseudo_palette; |
20fd5767 | 493 | |
b0831941 KH |
494 | val = chan_to_field(red, &info->var.red); |
495 | val |= chan_to_field(green, &info->var.green); | |
496 | val |= chan_to_field(blue, &info->var.blue); | |
20fd5767 AP |
497 | |
498 | pal[regno] = val; | |
499 | } | |
500 | break; | |
501 | ||
502 | case FB_VISUAL_PSEUDOCOLOR: | |
503 | if (regno < 256) { | |
504 | /* currently assume RGB 5-6-5 mode */ | |
505 | ||
9fa7bc01 KH |
506 | val = (red >> 0) & 0xf800; |
507 | val |= (green >> 5) & 0x07e0; | |
508 | val |= (blue >> 11) & 0x001f; | |
20fd5767 | 509 | |
7ee0fe41 | 510 | writel(val, regs + S3C2410_TFTPAL(regno)); |
20fd5767 AP |
511 | schedule_palette_update(fbi, regno, val); |
512 | } | |
513 | ||
514 | break; | |
515 | ||
516 | default: | |
b0831941 | 517 | return 1; /* unknown type */ |
20fd5767 AP |
518 | } |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
673b4600 BD |
523 | /* s3c2410fb_lcd_enable |
524 | * | |
525 | * shutdown the lcd controller | |
526 | */ | |
527 | static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable) | |
528 | { | |
529 | unsigned long flags; | |
530 | ||
531 | local_irq_save(flags); | |
532 | ||
533 | if (enable) | |
534 | fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID; | |
535 | else | |
536 | fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID; | |
537 | ||
538 | writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1); | |
539 | ||
540 | local_irq_restore(flags); | |
541 | } | |
542 | ||
543 | ||
b0831941 | 544 | /* |
20fd5767 AP |
545 | * s3c2410fb_blank |
546 | * @blank_mode: the blank mode we want. | |
547 | * @info: frame buffer structure that represents a single frame buffer | |
548 | * | |
549 | * Blank the screen if blank_mode != 0, else unblank. Return 0 if | |
550 | * blanking succeeded, != 0 if un-/blanking failed due to e.g. a | |
551 | * video mode which doesn't support it. Implements VESA suspend | |
552 | * and powerdown modes on hardware that supports disabling hsync/vsync: | |
20fd5767 AP |
553 | * |
554 | * Returns negative errno on error, or zero on success. | |
555 | * | |
556 | */ | |
557 | static int s3c2410fb_blank(int blank_mode, struct fb_info *info) | |
558 | { | |
7ee0fe41 | 559 | struct s3c2410fb_info *fbi = info->par; |
f62e770b | 560 | void __iomem *tpal_reg = fbi->io; |
7ee0fe41 | 561 | |
20fd5767 AP |
562 | dprintk("blank(mode=%d, info=%p)\n", blank_mode, info); |
563 | ||
f62e770b BD |
564 | tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL; |
565 | ||
673b4600 BD |
566 | if (blank_mode == FB_BLANK_POWERDOWN) { |
567 | s3c2410fb_lcd_enable(fbi, 0); | |
568 | } else { | |
569 | s3c2410fb_lcd_enable(fbi, 1); | |
570 | } | |
571 | ||
20fd5767 | 572 | if (blank_mode == FB_BLANK_UNBLANK) |
f62e770b | 573 | writel(0x0, tpal_reg); |
20fd5767 AP |
574 | else { |
575 | dprintk("setting TPAL to output 0x000000\n"); | |
f62e770b | 576 | writel(S3C2410_TPAL_EN, tpal_reg); |
20fd5767 AP |
577 | } |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
b0831941 KH |
582 | static int s3c2410fb_debug_show(struct device *dev, |
583 | struct device_attribute *attr, char *buf) | |
20fd5767 AP |
584 | { |
585 | return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off"); | |
586 | } | |
9fa7bc01 | 587 | |
b0831941 KH |
588 | static int s3c2410fb_debug_store(struct device *dev, |
589 | struct device_attribute *attr, | |
590 | const char *buf, size_t len) | |
20fd5767 | 591 | { |
20fd5767 AP |
592 | if (len < 1) |
593 | return -EINVAL; | |
594 | ||
595 | if (strnicmp(buf, "on", 2) == 0 || | |
596 | strnicmp(buf, "1", 1) == 0) { | |
597 | debug = 1; | |
598 | printk(KERN_DEBUG "s3c2410fb: Debug On"); | |
599 | } else if (strnicmp(buf, "off", 3) == 0 || | |
600 | strnicmp(buf, "0", 1) == 0) { | |
601 | debug = 0; | |
602 | printk(KERN_DEBUG "s3c2410fb: Debug Off"); | |
603 | } else { | |
604 | return -EINVAL; | |
605 | } | |
606 | ||
607 | return len; | |
608 | } | |
609 | ||
b0831941 | 610 | static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store); |
20fd5767 AP |
611 | |
612 | static struct fb_ops s3c2410fb_ops = { | |
613 | .owner = THIS_MODULE, | |
614 | .fb_check_var = s3c2410fb_check_var, | |
615 | .fb_set_par = s3c2410fb_set_par, | |
616 | .fb_blank = s3c2410fb_blank, | |
617 | .fb_setcolreg = s3c2410fb_setcolreg, | |
618 | .fb_fillrect = cfb_fillrect, | |
619 | .fb_copyarea = cfb_copyarea, | |
620 | .fb_imageblit = cfb_imageblit, | |
20fd5767 AP |
621 | }; |
622 | ||
20fd5767 AP |
623 | /* |
624 | * s3c2410fb_map_video_memory(): | |
625 | * Allocates the DRAM memory for the frame buffer. This buffer is | |
626 | * remapped into a non-cached, non-buffered, memory region to | |
627 | * allow palette and pixel writes to occur without flushing the | |
628 | * cache. Once this area is remapped, all virtual memory | |
629 | * access to the video memory should occur at the new region. | |
630 | */ | |
110c1fa7 | 631 | static int __init s3c2410fb_map_video_memory(struct fb_info *info) |
20fd5767 | 632 | { |
110c1fa7 | 633 | struct s3c2410fb_info *fbi = info->par; |
9fa7bc01 KH |
634 | dma_addr_t map_dma; |
635 | unsigned map_size = PAGE_ALIGN(info->fix.smem_len); | |
110c1fa7 | 636 | |
38a02f56 | 637 | dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size); |
20fd5767 | 638 | |
9fa7bc01 KH |
639 | info->screen_base = dma_alloc_writecombine(fbi->dev, map_size, |
640 | &map_dma, GFP_KERNEL); | |
20fd5767 | 641 | |
9fa7bc01 | 642 | if (info->screen_base) { |
20fd5767 AP |
643 | /* prevent initial garbage on screen */ |
644 | dprintk("map_video_memory: clear %p:%08x\n", | |
9fa7bc01 | 645 | info->screen_base, map_size); |
c0d40335 | 646 | memset(info->screen_base, 0x00, map_size); |
20fd5767 | 647 | |
9fa7bc01 | 648 | info->fix.smem_start = map_dma; |
20fd5767 | 649 | |
9fa7bc01 KH |
650 | dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n", |
651 | info->fix.smem_start, info->screen_base, map_size); | |
20fd5767 AP |
652 | } |
653 | ||
9fa7bc01 | 654 | return info->screen_base ? 0 : -ENOMEM; |
20fd5767 AP |
655 | } |
656 | ||
9fa7bc01 | 657 | static inline void s3c2410fb_unmap_video_memory(struct fb_info *info) |
20fd5767 | 658 | { |
9fa7bc01 KH |
659 | struct s3c2410fb_info *fbi = info->par; |
660 | ||
661 | dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len), | |
662 | info->screen_base, info->fix.smem_start); | |
20fd5767 AP |
663 | } |
664 | ||
665 | static inline void modify_gpio(void __iomem *reg, | |
666 | unsigned long set, unsigned long mask) | |
667 | { | |
668 | unsigned long tmp; | |
669 | ||
670 | tmp = readl(reg) & ~mask; | |
671 | writel(tmp | set, reg); | |
672 | } | |
673 | ||
20fd5767 AP |
674 | /* |
675 | * s3c2410fb_init_registers - Initialise all LCD-related registers | |
676 | */ | |
110c1fa7 | 677 | static int s3c2410fb_init_registers(struct fb_info *info) |
20fd5767 | 678 | { |
110c1fa7 | 679 | struct s3c2410fb_info *fbi = info->par; |
9fa7bc01 | 680 | struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data; |
20fd5767 | 681 | unsigned long flags; |
aff39a85 | 682 | void __iomem *regs = fbi->io; |
f62e770b BD |
683 | void __iomem *tpal; |
684 | void __iomem *lpcsel; | |
685 | ||
686 | if (is_s3c2412(fbi)) { | |
687 | tpal = regs + S3C2412_TPAL; | |
688 | lpcsel = regs + S3C2412_TCONSEL; | |
689 | } else { | |
690 | tpal = regs + S3C2410_TPAL; | |
691 | lpcsel = regs + S3C2410_LPCSEL; | |
692 | } | |
20fd5767 AP |
693 | |
694 | /* Initialise LCD with values from haret */ | |
695 | ||
696 | local_irq_save(flags); | |
697 | ||
698 | /* modify the gpio(s) with interrupts set (bjd) */ | |
699 | ||
700 | modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask); | |
701 | modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask); | |
702 | modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask); | |
703 | modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask); | |
704 | ||
705 | local_irq_restore(flags); | |
706 | ||
20fd5767 | 707 | dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel); |
f62e770b | 708 | writel(mach_info->lpcsel, lpcsel); |
20fd5767 | 709 | |
f62e770b | 710 | dprintk("replacing TPAL %08x\n", readl(tpal)); |
20fd5767 AP |
711 | |
712 | /* ensure temporary palette disabled */ | |
f62e770b | 713 | writel(0x00, tpal); |
20fd5767 | 714 | |
20fd5767 AP |
715 | return 0; |
716 | } | |
717 | ||
718 | static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi) | |
719 | { | |
720 | unsigned int i; | |
aff39a85 | 721 | void __iomem *regs = fbi->io; |
20fd5767 AP |
722 | |
723 | fbi->palette_ready = 0; | |
724 | ||
725 | for (i = 0; i < 256; i++) { | |
b0831941 KH |
726 | unsigned long ent = fbi->palette_buffer[i]; |
727 | if (ent == PALETTE_BUFF_CLEAR) | |
20fd5767 AP |
728 | continue; |
729 | ||
aff39a85 | 730 | writel(ent, regs + S3C2410_TFTPAL(i)); |
20fd5767 AP |
731 | |
732 | /* it seems the only way to know exactly | |
733 | * if the palette wrote ok, is to check | |
734 | * to see if the value verifies ok | |
735 | */ | |
736 | ||
aff39a85 | 737 | if (readw(regs + S3C2410_TFTPAL(i)) == ent) |
20fd5767 AP |
738 | fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR; |
739 | else | |
740 | fbi->palette_ready = 1; /* retry */ | |
741 | } | |
742 | } | |
743 | ||
7d12e780 | 744 | static irqreturn_t s3c2410fb_irq(int irq, void *dev_id) |
20fd5767 AP |
745 | { |
746 | struct s3c2410fb_info *fbi = dev_id; | |
f62e770b BD |
747 | void __iomem *irq_base = fbi->irq_base; |
748 | unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND); | |
20fd5767 AP |
749 | |
750 | if (lcdirq & S3C2410_LCDINT_FRSYNC) { | |
751 | if (fbi->palette_ready) | |
752 | s3c2410fb_write_palette(fbi); | |
753 | ||
f62e770b BD |
754 | writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND); |
755 | writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND); | |
20fd5767 AP |
756 | } |
757 | ||
758 | return IRQ_HANDLED; | |
759 | } | |
760 | ||
b0831941 | 761 | static char driver_name[] = "s3c2410fb"; |
20fd5767 | 762 | |
f62e770b BD |
763 | static int __init s3c24xxfb_probe(struct platform_device *pdev, |
764 | enum s3c_drv_type drv_type) | |
20fd5767 AP |
765 | { |
766 | struct s3c2410fb_info *info; | |
09fe75f6 | 767 | struct s3c2410fb_display *display; |
b0831941 | 768 | struct fb_info *fbinfo; |
9fa7bc01 | 769 | struct s3c2410fb_mach_info *mach_info; |
aff39a85 | 770 | struct resource *res; |
20fd5767 AP |
771 | int ret; |
772 | int irq; | |
773 | int i; | |
aff39a85 | 774 | int size; |
6931a764 | 775 | u32 lcdcon1; |
20fd5767 | 776 | |
3ae5eaec | 777 | mach_info = pdev->dev.platform_data; |
20fd5767 | 778 | if (mach_info == NULL) { |
b0831941 KH |
779 | dev_err(&pdev->dev, |
780 | "no platform data for lcd, cannot attach\n"); | |
20fd5767 AP |
781 | return -EINVAL; |
782 | } | |
783 | ||
e8973637 BD |
784 | if (mach_info->default_display >= mach_info->num_displays) { |
785 | dev_err(&pdev->dev, "default is %d but only %d displays\n", | |
786 | mach_info->default_display, mach_info->num_displays); | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
09fe75f6 | 790 | display = mach_info->displays + mach_info->default_display; |
20fd5767 AP |
791 | |
792 | irq = platform_get_irq(pdev, 0); | |
793 | if (irq < 0) { | |
3ae5eaec | 794 | dev_err(&pdev->dev, "no irq for device\n"); |
20fd5767 AP |
795 | return -ENOENT; |
796 | } | |
797 | ||
3ae5eaec | 798 | fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev); |
b0831941 | 799 | if (!fbinfo) |
20fd5767 | 800 | return -ENOMEM; |
20fd5767 | 801 | |
9fa7bc01 KH |
802 | platform_set_drvdata(pdev, fbinfo); |
803 | ||
20fd5767 | 804 | info = fbinfo->par; |
0187f221 | 805 | info->dev = &pdev->dev; |
f62e770b | 806 | info->drv_type = drv_type; |
0187f221 | 807 | |
aff39a85 BD |
808 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
809 | if (res == NULL) { | |
b0831941 | 810 | dev_err(&pdev->dev, "failed to get memory registers\n"); |
aff39a85 BD |
811 | ret = -ENXIO; |
812 | goto dealloc_fb; | |
813 | } | |
814 | ||
b0831941 | 815 | size = (res->end - res->start) + 1; |
aff39a85 BD |
816 | info->mem = request_mem_region(res->start, size, pdev->name); |
817 | if (info->mem == NULL) { | |
818 | dev_err(&pdev->dev, "failed to get memory region\n"); | |
819 | ret = -ENOENT; | |
820 | goto dealloc_fb; | |
821 | } | |
822 | ||
823 | info->io = ioremap(res->start, size); | |
824 | if (info->io == NULL) { | |
825 | dev_err(&pdev->dev, "ioremap() of registers failed\n"); | |
826 | ret = -ENXIO; | |
827 | goto release_mem; | |
828 | } | |
829 | ||
f62e770b BD |
830 | info->irq_base = info->io + ((drv_type == DRV_S3C2412) ? S3C2412_LCDINTBASE : S3C2410_LCDINTBASE); |
831 | ||
20fd5767 AP |
832 | dprintk("devinit\n"); |
833 | ||
834 | strcpy(fbinfo->fix.id, driver_name); | |
835 | ||
9fa7bc01 | 836 | /* Stop the video */ |
aff39a85 BD |
837 | lcdcon1 = readl(info->io + S3C2410_LCDCON1); |
838 | writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1); | |
6931a764 | 839 | |
20fd5767 AP |
840 | fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; |
841 | fbinfo->fix.type_aux = 0; | |
842 | fbinfo->fix.xpanstep = 0; | |
843 | fbinfo->fix.ypanstep = 0; | |
844 | fbinfo->fix.ywrapstep = 0; | |
845 | fbinfo->fix.accel = FB_ACCEL_NONE; | |
846 | ||
847 | fbinfo->var.nonstd = 0; | |
848 | fbinfo->var.activate = FB_ACTIVATE_NOW; | |
20fd5767 AP |
849 | fbinfo->var.accel_flags = 0; |
850 | fbinfo->var.vmode = FB_VMODE_NONINTERLACED; | |
851 | ||
852 | fbinfo->fbops = &s3c2410fb_ops; | |
853 | fbinfo->flags = FBINFO_FLAG_DEFAULT; | |
854 | fbinfo->pseudo_palette = &info->pseudo_pal; | |
855 | ||
20fd5767 AP |
856 | for (i = 0; i < 256; i++) |
857 | info->palette_buffer[i] = PALETTE_BUFF_CLEAR; | |
858 | ||
63a43399 | 859 | ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info); |
20fd5767 | 860 | if (ret) { |
3ae5eaec | 861 | dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret); |
20fd5767 | 862 | ret = -EBUSY; |
aff39a85 | 863 | goto release_regs; |
20fd5767 AP |
864 | } |
865 | ||
866 | info->clk = clk_get(NULL, "lcd"); | |
867 | if (!info->clk || IS_ERR(info->clk)) { | |
868 | printk(KERN_ERR "failed to get lcd clock source\n"); | |
869 | ret = -ENOENT; | |
870 | goto release_irq; | |
871 | } | |
872 | ||
20fd5767 AP |
873 | clk_enable(info->clk); |
874 | dprintk("got and enabled clock\n"); | |
875 | ||
876 | msleep(1); | |
877 | ||
9fa7bc01 KH |
878 | /* find maximum required memory size for display */ |
879 | for (i = 0; i < mach_info->num_displays; i++) { | |
880 | unsigned long smem_len = mach_info->displays[i].xres; | |
881 | ||
882 | smem_len *= mach_info->displays[i].yres; | |
883 | smem_len *= mach_info->displays[i].bpp; | |
884 | smem_len >>= 3; | |
885 | if (fbinfo->fix.smem_len < smem_len) | |
886 | fbinfo->fix.smem_len = smem_len; | |
887 | } | |
888 | ||
20fd5767 | 889 | /* Initialize video memory */ |
110c1fa7 | 890 | ret = s3c2410fb_map_video_memory(fbinfo); |
20fd5767 | 891 | if (ret) { |
b0831941 | 892 | printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret); |
20fd5767 AP |
893 | ret = -ENOMEM; |
894 | goto release_clock; | |
895 | } | |
aff39a85 | 896 | |
20fd5767 AP |
897 | dprintk("got video memory\n"); |
898 | ||
9fa7bc01 KH |
899 | fbinfo->var.xres = display->xres; |
900 | fbinfo->var.yres = display->yres; | |
901 | fbinfo->var.bits_per_pixel = display->bpp; | |
902 | ||
110c1fa7 | 903 | s3c2410fb_init_registers(fbinfo); |
20fd5767 | 904 | |
b0831941 | 905 | s3c2410fb_check_var(&fbinfo->var, fbinfo); |
20fd5767 AP |
906 | |
907 | ret = register_framebuffer(fbinfo); | |
908 | if (ret < 0) { | |
b0831941 KH |
909 | printk(KERN_ERR "Failed to register framebuffer device: %d\n", |
910 | ret); | |
20fd5767 AP |
911 | goto free_video_memory; |
912 | } | |
913 | ||
914 | /* create device files */ | |
d585dfe8 BD |
915 | ret = device_create_file(&pdev->dev, &dev_attr_debug); |
916 | if (ret) { | |
917 | printk(KERN_ERR "failed to add debug attribute\n"); | |
918 | } | |
20fd5767 AP |
919 | |
920 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | |
921 | fbinfo->node, fbinfo->fix.id); | |
922 | ||
923 | return 0; | |
924 | ||
925 | free_video_memory: | |
9fa7bc01 | 926 | s3c2410fb_unmap_video_memory(fbinfo); |
20fd5767 AP |
927 | release_clock: |
928 | clk_disable(info->clk); | |
20fd5767 AP |
929 | clk_put(info->clk); |
930 | release_irq: | |
b0831941 | 931 | free_irq(irq, info); |
aff39a85 BD |
932 | release_regs: |
933 | iounmap(info->io); | |
20fd5767 | 934 | release_mem: |
aff39a85 BD |
935 | release_resource(info->mem); |
936 | kfree(info->mem); | |
20fd5767 | 937 | dealloc_fb: |
9fa7bc01 | 938 | platform_set_drvdata(pdev, NULL); |
20fd5767 AP |
939 | framebuffer_release(fbinfo); |
940 | return ret; | |
941 | } | |
942 | ||
f62e770b BD |
943 | static int __init s3c2410fb_probe(struct platform_device *pdev) |
944 | { | |
945 | return s3c24xxfb_probe(pdev, DRV_S3C2410); | |
946 | } | |
947 | ||
948 | static int __init s3c2412fb_probe(struct platform_device *pdev) | |
949 | { | |
950 | return s3c24xxfb_probe(pdev, DRV_S3C2412); | |
951 | } | |
952 | ||
20fd5767 AP |
953 | |
954 | /* | |
955 | * Cleanup | |
956 | */ | |
3ae5eaec | 957 | static int s3c2410fb_remove(struct platform_device *pdev) |
20fd5767 | 958 | { |
b0831941 | 959 | struct fb_info *fbinfo = platform_get_drvdata(pdev); |
20fd5767 AP |
960 | struct s3c2410fb_info *info = fbinfo->par; |
961 | int irq; | |
962 | ||
9fa7bc01 KH |
963 | unregister_framebuffer(fbinfo); |
964 | ||
673b4600 | 965 | s3c2410fb_lcd_enable(info, 0); |
20fd5767 AP |
966 | msleep(1); |
967 | ||
9fa7bc01 | 968 | s3c2410fb_unmap_video_memory(fbinfo); |
20fd5767 | 969 | |
b0831941 KH |
970 | if (info->clk) { |
971 | clk_disable(info->clk); | |
972 | clk_put(info->clk); | |
973 | info->clk = NULL; | |
20fd5767 AP |
974 | } |
975 | ||
976 | irq = platform_get_irq(pdev, 0); | |
b0831941 | 977 | free_irq(irq, info); |
aff39a85 | 978 | |
9fa7bc01 KH |
979 | iounmap(info->io); |
980 | ||
aff39a85 BD |
981 | release_resource(info->mem); |
982 | kfree(info->mem); | |
9fa7bc01 KH |
983 | |
984 | platform_set_drvdata(pdev, NULL); | |
985 | framebuffer_release(fbinfo); | |
20fd5767 AP |
986 | |
987 | return 0; | |
988 | } | |
989 | ||
990 | #ifdef CONFIG_PM | |
991 | ||
992 | /* suspend and resume support for the lcd controller */ | |
3ae5eaec | 993 | static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state) |
20fd5767 | 994 | { |
3ae5eaec | 995 | struct fb_info *fbinfo = platform_get_drvdata(dev); |
20fd5767 AP |
996 | struct s3c2410fb_info *info = fbinfo->par; |
997 | ||
673b4600 | 998 | s3c2410fb_lcd_enable(info, 0); |
20fd5767 | 999 | |
9480e307 RK |
1000 | /* sleep before disabling the clock, we need to ensure |
1001 | * the LCD DMA engine is not going to get back on the bus | |
1002 | * before the clock goes off again (bjd) */ | |
20fd5767 | 1003 | |
9480e307 RK |
1004 | msleep(1); |
1005 | clk_disable(info->clk); | |
20fd5767 AP |
1006 | |
1007 | return 0; | |
1008 | } | |
1009 | ||
3ae5eaec | 1010 | static int s3c2410fb_resume(struct platform_device *dev) |
20fd5767 | 1011 | { |
3ae5eaec | 1012 | struct fb_info *fbinfo = platform_get_drvdata(dev); |
20fd5767 AP |
1013 | struct s3c2410fb_info *info = fbinfo->par; |
1014 | ||
9480e307 RK |
1015 | clk_enable(info->clk); |
1016 | msleep(1); | |
20fd5767 | 1017 | |
f0466441 | 1018 | s3c2410fb_init_registers(fbinfo); |
20fd5767 AP |
1019 | |
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | #else | |
1024 | #define s3c2410fb_suspend NULL | |
1025 | #define s3c2410fb_resume NULL | |
1026 | #endif | |
1027 | ||
3ae5eaec | 1028 | static struct platform_driver s3c2410fb_driver = { |
20fd5767 | 1029 | .probe = s3c2410fb_probe, |
3ae5eaec | 1030 | .remove = s3c2410fb_remove, |
20fd5767 AP |
1031 | .suspend = s3c2410fb_suspend, |
1032 | .resume = s3c2410fb_resume, | |
3ae5eaec RK |
1033 | .driver = { |
1034 | .name = "s3c2410-lcd", | |
1035 | .owner = THIS_MODULE, | |
1036 | }, | |
20fd5767 AP |
1037 | }; |
1038 | ||
f62e770b BD |
1039 | static struct platform_driver s3c2412fb_driver = { |
1040 | .probe = s3c2412fb_probe, | |
1041 | .remove = s3c2410fb_remove, | |
1042 | .suspend = s3c2410fb_suspend, | |
1043 | .resume = s3c2410fb_resume, | |
1044 | .driver = { | |
1045 | .name = "s3c2412-lcd", | |
1046 | .owner = THIS_MODULE, | |
1047 | }, | |
1048 | }; | |
1049 | ||
9fa7bc01 | 1050 | int __init s3c2410fb_init(void) |
20fd5767 | 1051 | { |
f62e770b BD |
1052 | int ret = platform_driver_register(&s3c2410fb_driver); |
1053 | ||
1054 | if (ret == 0) | |
1055 | ret = platform_driver_register(&s3c2412fb_driver);; | |
1056 | ||
1057 | return ret; | |
20fd5767 AP |
1058 | } |
1059 | ||
1060 | static void __exit s3c2410fb_cleanup(void) | |
1061 | { | |
3ae5eaec | 1062 | platform_driver_unregister(&s3c2410fb_driver); |
f62e770b | 1063 | platform_driver_unregister(&s3c2412fb_driver); |
20fd5767 AP |
1064 | } |
1065 | ||
20fd5767 AP |
1066 | module_init(s3c2410fb_init); |
1067 | module_exit(s3c2410fb_cleanup); | |
1068 | ||
b0831941 KH |
1069 | MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, " |
1070 | "Ben Dooks <ben-linux@fluff.org>"); | |
20fd5767 AP |
1071 | MODULE_DESCRIPTION("Framebuffer driver for the s3c2410"); |
1072 | MODULE_LICENSE("GPL"); | |
ee29420a BD |
1073 | MODULE_ALIAS("platform:s3c2410-lcd"); |
1074 | MODULE_ALIAS("platform:s3c2412-lcd"); |