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a268422d OZ |
1 | /* |
2 | * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge | |
3 | * | |
4 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | * | |
10 | * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) | |
11 | * which is based on the code of neofb. | |
12 | */ | |
13 | ||
a268422d OZ |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/tty.h> | |
a268422d OZ |
20 | #include <linux/delay.h> |
21 | #include <linux/fb.h> | |
22 | #include <linux/svga.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/pci.h> | |
ac751efa | 25 | #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ |
a268422d OZ |
26 | #include <video/vga.h> |
27 | ||
28 | #ifdef CONFIG_MTRR | |
29 | #include <asm/mtrr.h> | |
30 | #endif | |
31 | ||
32 | struct s3fb_info { | |
33 | int chip, rev, mclk_freq; | |
34 | int mtrr_reg; | |
35 | struct vgastate state; | |
36 | struct mutex open_lock; | |
37 | unsigned int ref_count; | |
38 | u32 pseudo_palette[16]; | |
39 | }; | |
40 | ||
41 | ||
42 | /* ------------------------------------------------------------------------- */ | |
43 | ||
44 | static const struct svga_fb_format s3fb_formats[] = { | |
45 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
46 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, | |
c26d7b29 | 47 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, |
a268422d | 48 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
c26d7b29 | 49 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, |
a268422d | 50 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
c26d7b29 | 51 | { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
a268422d OZ |
52 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, |
53 | {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
54 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
55 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
56 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, | |
57 | {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
58 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
59 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
60 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, | |
61 | SVGA_FORMAT_END | |
62 | }; | |
63 | ||
64 | ||
65 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, | |
249bdbbf | 66 | 35000, 240000, 14318}; |
5694f9ce OZ |
67 | static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, |
68 | 230000, 460000, 14318}; | |
a268422d OZ |
69 | |
70 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; | |
71 | ||
72 | static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", | |
73 | "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", | |
74 | "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", | |
75 | "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", | |
9966c4fe | 76 | "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P", |
5694f9ce OZ |
77 | "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", |
78 | "S3 Trio3D"}; | |
a268422d OZ |
79 | |
80 | #define CHIP_UNKNOWN 0x00 | |
81 | #define CHIP_732_TRIO32 0x01 | |
82 | #define CHIP_764_TRIO64 0x02 | |
83 | #define CHIP_765_TRIO64VP 0x03 | |
84 | #define CHIP_767_TRIO64UVP 0x04 | |
85 | #define CHIP_775_TRIO64V2_DX 0x05 | |
86 | #define CHIP_785_TRIO64V2_GX 0x06 | |
87 | #define CHIP_551_PLATO_PX 0x07 | |
88 | #define CHIP_M65_AURORA64VP 0x08 | |
89 | #define CHIP_325_VIRGE 0x09 | |
90 | #define CHIP_988_VIRGE_VX 0x0A | |
91 | #define CHIP_375_VIRGE_DX 0x0B | |
92 | #define CHIP_385_VIRGE_GX 0x0C | |
93 | #define CHIP_356_VIRGE_GX2 0x0D | |
94 | #define CHIP_357_VIRGE_GX2P 0x0E | |
95 | #define CHIP_359_VIRGE_GX2P 0x0F | |
9966c4fe OZ |
96 | #define CHIP_360_TRIO3D_1X 0x10 |
97 | #define CHIP_362_TRIO3D_2X 0x11 | |
98 | #define CHIP_368_TRIO3D_2X 0x12 | |
5694f9ce | 99 | #define CHIP_365_TRIO3D 0x13 |
a268422d OZ |
100 | |
101 | #define CHIP_XXX_TRIO 0x80 | |
102 | #define CHIP_XXX_TRIO64V2_DXGX 0x81 | |
103 | #define CHIP_XXX_VIRGE_DXGX 0x82 | |
9966c4fe | 104 | #define CHIP_36X_TRIO3D_1X_2X 0x83 |
a268422d OZ |
105 | |
106 | #define CHIP_UNDECIDED_FLAG 0x80 | |
107 | #define CHIP_MASK 0xFF | |
108 | ||
109 | /* CRT timing register sets */ | |
110 | ||
111 | static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; | |
112 | static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; | |
113 | static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; | |
114 | static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; | |
115 | static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; | |
116 | static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; | |
117 | ||
118 | static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; | |
119 | static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; | |
120 | static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; | |
121 | static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; | |
122 | static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; | |
123 | static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; | |
124 | ||
125 | static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; | |
126 | static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; | |
127 | static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ | |
128 | ||
129 | static const struct svga_timing_regs s3_timing_regs = { | |
130 | s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, | |
131 | s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, | |
132 | s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, | |
133 | s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, | |
134 | }; | |
135 | ||
136 | ||
137 | /* ------------------------------------------------------------------------- */ | |
138 | ||
139 | /* Module parameters */ | |
140 | ||
141 | ||
a8140543 | 142 | static char *mode_option __devinitdata = "640x480-8@60"; |
a268422d OZ |
143 | |
144 | #ifdef CONFIG_MTRR | |
a8140543 | 145 | static int mtrr __devinitdata = 1; |
a268422d OZ |
146 | #endif |
147 | ||
148 | static int fasttext = 1; | |
149 | ||
150 | ||
151 | MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); | |
152 | MODULE_LICENSE("GPL"); | |
153 | MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); | |
154 | ||
a8140543 KH |
155 | module_param(mode_option, charp, 0444); |
156 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); | |
157 | module_param_named(mode, mode_option, charp, 0444); | |
158 | MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); | |
a268422d OZ |
159 | |
160 | #ifdef CONFIG_MTRR | |
161 | module_param(mtrr, int, 0444); | |
162 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); | |
163 | #endif | |
164 | ||
165 | module_param(fasttext, int, 0644); | |
166 | MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); | |
167 | ||
168 | ||
169 | /* ------------------------------------------------------------------------- */ | |
170 | ||
171 | /* Set font in S3 fast text mode */ | |
172 | ||
173 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | |
174 | { | |
175 | const u8 *font = map->data; | |
75814d87 | 176 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
a268422d OZ |
177 | int i, c; |
178 | ||
179 | if ((map->width != 8) || (map->height != 16) || | |
180 | (map->depth != 1) || (map->length != 256)) { | |
181 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", | |
182 | info->node, map->width, map->height, map->depth, map->length); | |
183 | return; | |
184 | } | |
185 | ||
186 | fb += 2; | |
187 | for (i = 0; i < map->height; i++) { | |
188 | for (c = 0; c < map->length; c++) { | |
75814d87 | 189 | fb_writeb(font[c * map->height + i], fb + c * 4); |
a268422d OZ |
190 | } |
191 | fb += 1024; | |
192 | } | |
193 | } | |
194 | ||
55db0923 DM |
195 | static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) |
196 | { | |
197 | struct s3fb_info *par = info->par; | |
198 | ||
199 | svga_tilecursor(par->state.vgabase, info, cursor); | |
200 | } | |
201 | ||
a268422d OZ |
202 | static struct fb_tile_ops s3fb_tile_ops = { |
203 | .fb_settile = svga_settile, | |
204 | .fb_tilecopy = svga_tilecopy, | |
205 | .fb_tilefill = svga_tilefill, | |
206 | .fb_tileblit = svga_tileblit, | |
55db0923 | 207 | .fb_tilecursor = s3fb_tilecursor, |
34ed25f5 | 208 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
209 | }; |
210 | ||
211 | static struct fb_tile_ops s3fb_fast_tile_ops = { | |
212 | .fb_settile = s3fb_settile_fast, | |
213 | .fb_tilecopy = svga_tilecopy, | |
214 | .fb_tilefill = svga_tilefill, | |
215 | .fb_tileblit = svga_tileblit, | |
55db0923 | 216 | .fb_tilecursor = s3fb_tilecursor, |
34ed25f5 | 217 | .fb_get_tilemax = svga_get_tilemax, |
a268422d OZ |
218 | }; |
219 | ||
220 | ||
221 | /* ------------------------------------------------------------------------- */ | |
222 | ||
223 | /* image data is MSB-first, fb structure is MSB-first too */ | |
224 | static inline u32 expand_color(u32 c) | |
225 | { | |
226 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; | |
227 | } | |
228 | ||
229 | /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
230 | static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) | |
231 | { | |
232 | u32 fg = expand_color(image->fg_color); | |
233 | u32 bg = expand_color(image->bg_color); | |
234 | const u8 *src1, *src; | |
235 | u8 __iomem *dst1; | |
236 | u32 __iomem *dst; | |
237 | u32 val; | |
238 | int x, y; | |
239 | ||
240 | src1 = image->data; | |
241 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
242 | + ((image->dx / 8) * 4); | |
243 | ||
244 | for (y = 0; y < image->height; y++) { | |
245 | src = src1; | |
246 | dst = (u32 __iomem *) dst1; | |
247 | for (x = 0; x < image->width; x += 8) { | |
248 | val = *(src++) * 0x01010101; | |
249 | val = (val & fg) | (~val & bg); | |
250 | fb_writel(val, dst++); | |
251 | } | |
252 | src1 += image->width / 8; | |
253 | dst1 += info->fix.line_length; | |
254 | } | |
255 | ||
256 | } | |
257 | ||
258 | /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ | |
259 | static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
260 | { | |
261 | u32 fg = expand_color(rect->color); | |
262 | u8 __iomem *dst1; | |
263 | u32 __iomem *dst; | |
264 | int x, y; | |
265 | ||
266 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) | |
267 | + ((rect->dx / 8) * 4); | |
268 | ||
269 | for (y = 0; y < rect->height; y++) { | |
270 | dst = (u32 __iomem *) dst1; | |
271 | for (x = 0; x < rect->width; x += 8) { | |
272 | fb_writel(fg, dst++); | |
273 | } | |
274 | dst1 += info->fix.line_length; | |
275 | } | |
276 | } | |
277 | ||
278 | ||
279 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ | |
280 | static inline u32 expand_pixel(u32 c) | |
281 | { | |
282 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | | |
283 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; | |
284 | } | |
285 | ||
286 | /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
287 | static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) | |
288 | { | |
289 | u32 fg = image->fg_color * 0x11111111; | |
290 | u32 bg = image->bg_color * 0x11111111; | |
291 | const u8 *src1, *src; | |
292 | u8 __iomem *dst1; | |
293 | u32 __iomem *dst; | |
294 | u32 val; | |
295 | int x, y; | |
296 | ||
297 | src1 = image->data; | |
298 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
299 | + ((image->dx / 8) * 4); | |
300 | ||
301 | for (y = 0; y < image->height; y++) { | |
302 | src = src1; | |
303 | dst = (u32 __iomem *) dst1; | |
304 | for (x = 0; x < image->width; x += 8) { | |
305 | val = expand_pixel(*(src++)); | |
306 | val = (val & fg) | (~val & bg); | |
307 | fb_writel(val, dst++); | |
308 | } | |
309 | src1 += image->width / 8; | |
310 | dst1 += info->fix.line_length; | |
311 | } | |
312 | } | |
313 | ||
314 | static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
315 | { | |
316 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) | |
317 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { | |
318 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) | |
319 | s3fb_iplan_imageblit(info, image); | |
320 | else | |
321 | s3fb_cfb4_imageblit(info, image); | |
322 | } else | |
323 | cfb_imageblit(info, image); | |
324 | } | |
325 | ||
326 | static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
327 | { | |
328 | if ((info->var.bits_per_pixel == 4) | |
329 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) | |
330 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) | |
331 | s3fb_iplan_fillrect(info, rect); | |
332 | else | |
333 | cfb_fillrect(info, rect); | |
334 | } | |
335 | ||
336 | ||
337 | ||
338 | /* ------------------------------------------------------------------------- */ | |
339 | ||
340 | ||
341 | static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |
342 | { | |
9966c4fe | 343 | struct s3fb_info *par = info->par; |
a268422d OZ |
344 | u16 m, n, r; |
345 | u8 regval; | |
249bdbbf | 346 | int rv; |
a268422d | 347 | |
5694f9ce OZ |
348 | rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, |
349 | 1000000000 / pixclock, &m, &n, &r, info->node); | |
249bdbbf OZ |
350 | if (rv < 0) { |
351 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | |
352 | return; | |
353 | } | |
a268422d OZ |
354 | |
355 | /* Set VGA misc register */ | |
f8645933 DM |
356 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
357 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | |
a268422d OZ |
358 | |
359 | /* Set S3 clock registers */ | |
9966c4fe OZ |
360 | if (par->chip == CHIP_360_TRIO3D_1X || |
361 | par->chip == CHIP_362_TRIO3D_2X || | |
362 | par->chip == CHIP_368_TRIO3D_2X) { | |
f8645933 DM |
363 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ |
364 | vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ | |
9966c4fe | 365 | } else |
f8645933 DM |
366 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); |
367 | vga_wseq(par->state.vgabase, 0x13, m - 2); | |
a268422d OZ |
368 | |
369 | udelay(1000); | |
370 | ||
371 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ | |
f8645933 DM |
372 | regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ |
373 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); | |
374 | vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); | |
375 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); | |
a268422d OZ |
376 | } |
377 | ||
378 | ||
379 | /* Open framebuffer */ | |
380 | ||
381 | static int s3fb_open(struct fb_info *info, int user) | |
382 | { | |
383 | struct s3fb_info *par = info->par; | |
384 | ||
385 | mutex_lock(&(par->open_lock)); | |
386 | if (par->ref_count == 0) { | |
3ff259f2 DM |
387 | void __iomem *vgabase = par->state.vgabase; |
388 | ||
a268422d | 389 | memset(&(par->state), 0, sizeof(struct vgastate)); |
3ff259f2 | 390 | par->state.vgabase = vgabase; |
a268422d OZ |
391 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; |
392 | par->state.num_crtc = 0x70; | |
393 | par->state.num_seq = 0x20; | |
394 | save_vga(&(par->state)); | |
395 | } | |
396 | ||
397 | par->ref_count++; | |
398 | mutex_unlock(&(par->open_lock)); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /* Close framebuffer */ | |
404 | ||
405 | static int s3fb_release(struct fb_info *info, int user) | |
406 | { | |
407 | struct s3fb_info *par = info->par; | |
408 | ||
409 | mutex_lock(&(par->open_lock)); | |
410 | if (par->ref_count == 0) { | |
411 | mutex_unlock(&(par->open_lock)); | |
412 | return -EINVAL; | |
413 | } | |
414 | ||
415 | if (par->ref_count == 1) | |
416 | restore_vga(&(par->state)); | |
417 | ||
418 | par->ref_count--; | |
419 | mutex_unlock(&(par->open_lock)); | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | /* Validate passed in var */ | |
425 | ||
426 | static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
427 | { | |
428 | struct s3fb_info *par = info->par; | |
429 | int rv, mem, step; | |
c3ca34f9 | 430 | u16 m, n, r; |
a268422d OZ |
431 | |
432 | /* Find appropriate format */ | |
433 | rv = svga_match_format (s3fb_formats, var, NULL); | |
d4b766a0 OZ |
434 | |
435 | /* 32bpp mode is not supported on VIRGE VX, | |
436 | 24bpp is not supported on others */ | |
437 | if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) | |
438 | rv = -EINVAL; | |
439 | ||
440 | if (rv < 0) { | |
a268422d OZ |
441 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); |
442 | return rv; | |
443 | } | |
444 | ||
445 | /* Do not allow to have real resoulution larger than virtual */ | |
446 | if (var->xres > var->xres_virtual) | |
447 | var->xres_virtual = var->xres; | |
448 | ||
449 | if (var->yres > var->yres_virtual) | |
450 | var->yres_virtual = var->yres; | |
451 | ||
452 | /* Round up xres_virtual to have proper alignment of lines */ | |
453 | step = s3fb_formats[rv].xresstep - 1; | |
454 | var->xres_virtual = (var->xres_virtual+step) & ~step; | |
455 | ||
456 | /* Check whether have enough memory */ | |
457 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | |
c3ca34f9 | 458 | if (mem > info->screen_size) { |
a268422d OZ |
459 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", |
460 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | rv = svga_check_timings (&s3_timing_regs, var, info->node); | |
c3ca34f9 | 465 | if (rv < 0) { |
a268422d OZ |
466 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); |
467 | return rv; | |
468 | } | |
469 | ||
c3ca34f9 KH |
470 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
471 | info->node); | |
472 | if (rv < 0) { | |
473 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", | |
474 | info->node); | |
475 | return rv; | |
476 | } | |
477 | ||
a268422d OZ |
478 | return 0; |
479 | } | |
480 | ||
481 | /* Set video mode from par */ | |
482 | ||
483 | static int s3fb_set_par(struct fb_info *info) | |
484 | { | |
485 | struct s3fb_info *par = info->par; | |
9966c4fe | 486 | u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; |
a268422d OZ |
487 | u32 bpp = info->var.bits_per_pixel; |
488 | ||
489 | if (bpp != 0) { | |
490 | info->fix.ypanstep = 1; | |
491 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; | |
492 | ||
493 | info->flags &= ~FBINFO_MISC_TILEBLITTING; | |
494 | info->tileops = NULL; | |
495 | ||
34ed25f5 OZ |
496 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ |
497 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); | |
8db51668 | 498 | info->pixmap.blit_y = ~(u32)0; |
34ed25f5 | 499 | |
a268422d OZ |
500 | offset_value = (info->var.xres_virtual * bpp) / 64; |
501 | screen_size = info->var.yres_virtual * info->fix.line_length; | |
502 | } else { | |
503 | info->fix.ypanstep = 16; | |
504 | info->fix.line_length = 0; | |
505 | ||
506 | info->flags |= FBINFO_MISC_TILEBLITTING; | |
507 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; | |
34ed25f5 | 508 | |
8db51668 AD |
509 | /* supports 8x16 tiles only */ |
510 | info->pixmap.blit_x = 1 << (8 - 1); | |
511 | info->pixmap.blit_y = 1 << (16 - 1); | |
a268422d OZ |
512 | |
513 | offset_value = info->var.xres_virtual / 16; | |
514 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; | |
515 | } | |
516 | ||
517 | info->var.xoffset = 0; | |
518 | info->var.yoffset = 0; | |
519 | info->var.activate = FB_ACTIVATE_NOW; | |
520 | ||
521 | /* Unlock registers */ | |
f8645933 DM |
522 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
523 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); | |
524 | vga_wseq(par->state.vgabase, 0x08, 0x06); | |
ea770789 | 525 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
a268422d OZ |
526 | |
527 | /* Blank screen and turn off sync */ | |
d907ec04 | 528 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
ea770789 | 529 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
a268422d OZ |
530 | |
531 | /* Set default values */ | |
e2fade2c | 532 | svga_set_default_gfx_regs(par->state.vgabase); |
f51a14dd | 533 | svga_set_default_atc_regs(par->state.vgabase); |
a4ade839 | 534 | svga_set_default_seq_regs(par->state.vgabase); |
1d28fcad | 535 | svga_set_default_crt_regs(par->state.vgabase); |
21da386d DM |
536 | svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); |
537 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); | |
a268422d OZ |
538 | |
539 | /* S3 specific initialization */ | |
ea770789 DM |
540 | svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ |
541 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ | |
a268422d | 542 | |
ea770789 DM |
543 | /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ |
544 | /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ | |
545 | svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ | |
546 | svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ | |
a268422d | 547 | |
ea770789 | 548 | svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ |
a268422d | 549 | |
ea770789 | 550 | /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ |
a268422d | 551 | |
ea770789 DM |
552 | /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ |
553 | /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ | |
a268422d OZ |
554 | |
555 | ||
556 | /* Set the offset register */ | |
557 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | |
21da386d | 558 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); |
a268422d | 559 | |
9966c4fe OZ |
560 | if (par->chip != CHIP_360_TRIO3D_1X && |
561 | par->chip != CHIP_362_TRIO3D_2X && | |
562 | par->chip != CHIP_368_TRIO3D_2X) { | |
f8645933 DM |
563 | vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ |
564 | vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ | |
565 | vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ | |
566 | vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ | |
9966c4fe | 567 | } |
a268422d | 568 | |
f8645933 | 569 | vga_wcrt(par->state.vgabase, 0x3A, 0x35); |
f6b0cc47 | 570 | svga_wattr(par->state.vgabase, 0x33, 0x00); |
a268422d OZ |
571 | |
572 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
ea770789 | 573 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); |
a268422d | 574 | else |
ea770789 | 575 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); |
a268422d OZ |
576 | |
577 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
ea770789 | 578 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); |
a268422d | 579 | else |
ea770789 | 580 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); |
a268422d OZ |
581 | |
582 | /* Disable hardware graphics cursor */ | |
ea770789 | 583 | svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); |
a268422d | 584 | /* Disable Streams engine */ |
ea770789 | 585 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); |
a268422d OZ |
586 | |
587 | mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); | |
588 | ||
589 | /* S3 virge DX hack */ | |
590 | if (par->chip == CHIP_375_VIRGE_DX) { | |
f8645933 DM |
591 | vga_wcrt(par->state.vgabase, 0x86, 0x80); |
592 | vga_wcrt(par->state.vgabase, 0x90, 0x00); | |
a268422d OZ |
593 | } |
594 | ||
595 | /* S3 virge VX hack */ | |
596 | if (par->chip == CHIP_988_VIRGE_VX) { | |
f8645933 DM |
597 | vga_wcrt(par->state.vgabase, 0x50, 0x00); |
598 | vga_wcrt(par->state.vgabase, 0x67, 0x50); | |
a268422d | 599 | |
f8645933 DM |
600 | vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); |
601 | vga_wcrt(par->state.vgabase, 0x66, 0x90); | |
a268422d OZ |
602 | } |
603 | ||
9966c4fe OZ |
604 | if (par->chip == CHIP_360_TRIO3D_1X || |
605 | par->chip == CHIP_362_TRIO3D_2X || | |
5694f9ce OZ |
606 | par->chip == CHIP_368_TRIO3D_2X || |
607 | par->chip == CHIP_365_TRIO3D) { | |
9966c4fe | 608 | dbytes = info->var.xres * ((bpp+7)/8); |
f8645933 DM |
609 | vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); |
610 | vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); | |
9966c4fe | 611 | |
f8645933 | 612 | vga_wcrt(par->state.vgabase, 0x66, 0x81); |
9966c4fe OZ |
613 | } |
614 | ||
ea770789 | 615 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); |
a268422d OZ |
616 | multiplex = 0; |
617 | hmul = 1; | |
618 | ||
619 | /* Set mode-specific register values */ | |
620 | switch (mode) { | |
621 | case 0: | |
622 | pr_debug("fb%d: text mode\n", info->node); | |
9c96394b | 623 | svga_set_textmode_vga_regs(par->state.vgabase); |
a268422d OZ |
624 | |
625 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
626 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
627 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
628 | |
629 | /* Disable enhanced mode */ | |
ea770789 | 630 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
631 | |
632 | if (fasttext) { | |
633 | pr_debug("fb%d: high speed text mode set\n", info->node); | |
ea770789 | 634 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); |
a268422d OZ |
635 | } |
636 | break; | |
637 | case 1: | |
638 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | |
f8645933 | 639 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
a268422d OZ |
640 | |
641 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
642 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
643 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
644 | |
645 | /* disable enhanced mode */ | |
ea770789 | 646 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
647 | break; |
648 | case 2: | |
649 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | |
650 | ||
651 | /* Set additional registers like in 8-bit mode */ | |
ea770789 DM |
652 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
653 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); | |
a268422d OZ |
654 | |
655 | /* disable enhanced mode */ | |
ea770789 | 656 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
a268422d OZ |
657 | break; |
658 | case 3: | |
659 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | |
ea770789 | 660 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
9966c4fe OZ |
661 | if (info->var.pixclock > 20000 || |
662 | par->chip == CHIP_360_TRIO3D_1X || | |
663 | par->chip == CHIP_362_TRIO3D_2X || | |
664 | par->chip == CHIP_368_TRIO3D_2X) | |
ea770789 | 665 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
9966c4fe | 666 | else { |
ea770789 | 667 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); |
a268422d OZ |
668 | multiplex = 1; |
669 | } | |
670 | break; | |
671 | case 4: | |
672 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | |
673 | if (par->chip == CHIP_988_VIRGE_VX) { | |
674 | if (info->var.pixclock > 20000) | |
ea770789 | 675 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
a268422d | 676 | else |
ea770789 | 677 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
a268422d | 678 | } else { |
ea770789 DM |
679 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
680 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); | |
9966c4fe OZ |
681 | if (par->chip != CHIP_360_TRIO3D_1X && |
682 | par->chip != CHIP_362_TRIO3D_2X && | |
683 | par->chip != CHIP_368_TRIO3D_2X) | |
684 | hmul = 2; | |
a268422d OZ |
685 | } |
686 | break; | |
687 | case 5: | |
688 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | |
689 | if (par->chip == CHIP_988_VIRGE_VX) { | |
690 | if (info->var.pixclock > 20000) | |
ea770789 | 691 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
a268422d | 692 | else |
ea770789 | 693 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
a268422d | 694 | } else { |
ea770789 DM |
695 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
696 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); | |
9966c4fe OZ |
697 | if (par->chip != CHIP_360_TRIO3D_1X && |
698 | par->chip != CHIP_362_TRIO3D_2X && | |
699 | par->chip != CHIP_368_TRIO3D_2X) | |
700 | hmul = 2; | |
a268422d OZ |
701 | } |
702 | break; | |
703 | case 6: | |
704 | /* VIRGE VX case */ | |
705 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | |
ea770789 | 706 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
a268422d OZ |
707 | break; |
708 | case 7: | |
709 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | |
ea770789 DM |
710 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); |
711 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); | |
a268422d OZ |
712 | break; |
713 | default: | |
714 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); | |
715 | return -EINVAL; | |
716 | } | |
717 | ||
718 | if (par->chip != CHIP_988_VIRGE_VX) { | |
d907ec04 DM |
719 | svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); |
720 | svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); | |
a268422d OZ |
721 | } |
722 | ||
723 | s3_set_pixclock(info, info->var.pixclock); | |
38d2620e | 724 | svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, |
a268422d OZ |
725 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, |
726 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, | |
727 | hmul, info->node); | |
728 | ||
729 | /* Set interlaced mode start/end register */ | |
730 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; | |
731 | value = ((value * hmul) / 8) - 5; | |
f8645933 | 732 | vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2); |
a268422d | 733 | |
75814d87 | 734 | memset_io(info->screen_base, 0x00, screen_size); |
a268422d | 735 | /* Device and screen back on */ |
ea770789 | 736 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
d907ec04 | 737 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
a268422d OZ |
738 | |
739 | return 0; | |
740 | } | |
741 | ||
742 | /* Set a colour register */ | |
743 | ||
744 | static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
745 | u_int transp, struct fb_info *fb) | |
746 | { | |
747 | switch (fb->var.bits_per_pixel) { | |
748 | case 0: | |
749 | case 4: | |
750 | if (regno >= 16) | |
751 | return -EINVAL; | |
752 | ||
753 | if ((fb->var.bits_per_pixel == 4) && | |
754 | (fb->var.nonstd == 0)) { | |
755 | outb(0xF0, VGA_PEL_MSK); | |
756 | outb(regno*16, VGA_PEL_IW); | |
757 | } else { | |
758 | outb(0x0F, VGA_PEL_MSK); | |
759 | outb(regno, VGA_PEL_IW); | |
760 | } | |
761 | outb(red >> 10, VGA_PEL_D); | |
762 | outb(green >> 10, VGA_PEL_D); | |
763 | outb(blue >> 10, VGA_PEL_D); | |
764 | break; | |
765 | case 8: | |
766 | if (regno >= 256) | |
767 | return -EINVAL; | |
768 | ||
769 | outb(0xFF, VGA_PEL_MSK); | |
770 | outb(regno, VGA_PEL_IW); | |
771 | outb(red >> 10, VGA_PEL_D); | |
772 | outb(green >> 10, VGA_PEL_D); | |
773 | outb(blue >> 10, VGA_PEL_D); | |
774 | break; | |
775 | case 16: | |
776 | if (regno >= 16) | |
249bdbbf | 777 | return 0; |
a268422d OZ |
778 | |
779 | if (fb->var.green.length == 5) | |
780 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | | |
781 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); | |
782 | else if (fb->var.green.length == 6) | |
783 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | | |
784 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); | |
785 | else return -EINVAL; | |
786 | break; | |
787 | case 24: | |
788 | case 32: | |
789 | if (regno >= 16) | |
249bdbbf | 790 | return 0; |
a268422d | 791 | |
249bdbbf | 792 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
a268422d OZ |
793 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
794 | break; | |
795 | default: | |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | ||
803 | /* Set the display blanking state */ | |
804 | ||
805 | static int s3fb_blank(int blank_mode, struct fb_info *info) | |
806 | { | |
d907ec04 DM |
807 | struct s3fb_info *par = info->par; |
808 | ||
a268422d OZ |
809 | switch (blank_mode) { |
810 | case FB_BLANK_UNBLANK: | |
811 | pr_debug("fb%d: unblank\n", info->node); | |
ea770789 | 812 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
d907ec04 | 813 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
a268422d OZ |
814 | break; |
815 | case FB_BLANK_NORMAL: | |
816 | pr_debug("fb%d: blank\n", info->node); | |
ea770789 | 817 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
d907ec04 | 818 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
819 | break; |
820 | case FB_BLANK_HSYNC_SUSPEND: | |
821 | pr_debug("fb%d: hsync\n", info->node); | |
ea770789 | 822 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); |
d907ec04 | 823 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
824 | break; |
825 | case FB_BLANK_VSYNC_SUSPEND: | |
826 | pr_debug("fb%d: vsync\n", info->node); | |
ea770789 | 827 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); |
d907ec04 | 828 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
829 | break; |
830 | case FB_BLANK_POWERDOWN: | |
831 | pr_debug("fb%d: sync down\n", info->node); | |
ea770789 | 832 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); |
d907ec04 | 833 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
a268422d OZ |
834 | break; |
835 | } | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | ||
841 | /* Pan the display */ | |
842 | ||
21da386d DM |
843 | static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
844 | { | |
845 | struct s3fb_info *par = info->par; | |
a268422d OZ |
846 | unsigned int offset; |
847 | ||
a268422d OZ |
848 | /* Calculate the offset */ |
849 | if (var->bits_per_pixel == 0) { | |
850 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); | |
851 | offset = offset >> 2; | |
852 | } else { | |
853 | offset = (var->yoffset * info->fix.line_length) + | |
854 | (var->xoffset * var->bits_per_pixel / 8); | |
855 | offset = offset >> 2; | |
856 | } | |
857 | ||
858 | /* Set the offset */ | |
21da386d | 859 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); |
a268422d OZ |
860 | |
861 | return 0; | |
862 | } | |
863 | ||
864 | /* ------------------------------------------------------------------------- */ | |
865 | ||
866 | /* Frame buffer operations */ | |
867 | ||
868 | static struct fb_ops s3fb_ops = { | |
869 | .owner = THIS_MODULE, | |
870 | .fb_open = s3fb_open, | |
871 | .fb_release = s3fb_release, | |
872 | .fb_check_var = s3fb_check_var, | |
873 | .fb_set_par = s3fb_set_par, | |
874 | .fb_setcolreg = s3fb_setcolreg, | |
875 | .fb_blank = s3fb_blank, | |
876 | .fb_pan_display = s3fb_pan_display, | |
877 | .fb_fillrect = s3fb_fillrect, | |
878 | .fb_copyarea = cfb_copyarea, | |
879 | .fb_imageblit = s3fb_imageblit, | |
5a87ede9 | 880 | .fb_get_caps = svga_get_caps, |
a268422d OZ |
881 | }; |
882 | ||
883 | /* ------------------------------------------------------------------------- */ | |
884 | ||
f8645933 | 885 | static int __devinit s3_identification(struct s3fb_info *par) |
a268422d | 886 | { |
f8645933 DM |
887 | int chip = par->chip; |
888 | ||
a268422d | 889 | if (chip == CHIP_XXX_TRIO) { |
f8645933 DM |
890 | u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); |
891 | u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); | |
892 | u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); | |
a268422d OZ |
893 | |
894 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { | |
895 | if (cr2e == 0x10) | |
896 | return CHIP_732_TRIO32; | |
897 | if (cr2e == 0x11) { | |
898 | if (! (cr2f & 0x40)) | |
899 | return CHIP_764_TRIO64; | |
900 | else | |
901 | return CHIP_765_TRIO64VP; | |
902 | } | |
903 | } | |
904 | } | |
905 | ||
906 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { | |
f8645933 | 907 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
a268422d OZ |
908 | |
909 | if (! (cr6f & 0x01)) | |
910 | return CHIP_775_TRIO64V2_DX; | |
911 | else | |
912 | return CHIP_785_TRIO64V2_GX; | |
913 | } | |
914 | ||
915 | if (chip == CHIP_XXX_VIRGE_DXGX) { | |
f8645933 | 916 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
a268422d OZ |
917 | |
918 | if (! (cr6f & 0x01)) | |
919 | return CHIP_375_VIRGE_DX; | |
920 | else | |
921 | return CHIP_385_VIRGE_GX; | |
922 | } | |
923 | ||
9966c4fe | 924 | if (chip == CHIP_36X_TRIO3D_1X_2X) { |
f8645933 | 925 | switch (vga_rcrt(par->state.vgabase, 0x2f)) { |
9966c4fe OZ |
926 | case 0x00: |
927 | return CHIP_360_TRIO3D_1X; | |
928 | case 0x01: | |
929 | return CHIP_362_TRIO3D_2X; | |
930 | case 0x02: | |
931 | return CHIP_368_TRIO3D_2X; | |
932 | } | |
933 | } | |
934 | ||
a268422d OZ |
935 | return CHIP_UNKNOWN; |
936 | } | |
937 | ||
938 | ||
939 | /* PCI probe */ | |
940 | ||
941 | static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
942 | { | |
94c322c3 DM |
943 | struct pci_bus_region bus_reg; |
944 | struct resource vga_res; | |
a268422d OZ |
945 | struct fb_info *info; |
946 | struct s3fb_info *par; | |
947 | int rc; | |
948 | u8 regval, cr38, cr39; | |
949 | ||
950 | /* Ignore secondary VGA device because there is no VGA arbitration */ | |
951 | if (! svga_primary_device(dev)) { | |
952 | dev_info(&(dev->dev), "ignoring secondary device\n"); | |
953 | return -ENODEV; | |
954 | } | |
955 | ||
956 | /* Allocate and fill driver data structure */ | |
20e061fb | 957 | info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); |
a268422d OZ |
958 | if (!info) { |
959 | dev_err(&(dev->dev), "cannot allocate memory\n"); | |
960 | return -ENOMEM; | |
961 | } | |
962 | ||
963 | par = info->par; | |
964 | mutex_init(&par->open_lock); | |
965 | ||
966 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; | |
967 | info->fbops = &s3fb_ops; | |
968 | ||
969 | /* Prepare PCI device */ | |
970 | rc = pci_enable_device(dev); | |
971 | if (rc < 0) { | |
594a8819 | 972 | dev_err(info->device, "cannot enable PCI device\n"); |
a268422d OZ |
973 | goto err_enable_device; |
974 | } | |
975 | ||
976 | rc = pci_request_regions(dev, "s3fb"); | |
977 | if (rc < 0) { | |
594a8819 | 978 | dev_err(info->device, "cannot reserve framebuffer region\n"); |
a268422d OZ |
979 | goto err_request_regions; |
980 | } | |
981 | ||
982 | ||
983 | info->fix.smem_start = pci_resource_start(dev, 0); | |
984 | info->fix.smem_len = pci_resource_len(dev, 0); | |
985 | ||
986 | /* Map physical IO memory address into kernel space */ | |
987 | info->screen_base = pci_iomap(dev, 0, 0); | |
988 | if (! info->screen_base) { | |
989 | rc = -ENOMEM; | |
594a8819 | 990 | dev_err(info->device, "iomap for framebuffer failed\n"); |
a268422d OZ |
991 | goto err_iomap; |
992 | } | |
993 | ||
94c322c3 DM |
994 | bus_reg.start = 0; |
995 | bus_reg.end = 64 * 1024; | |
996 | ||
997 | vga_res.flags = IORESOURCE_IO; | |
998 | ||
999 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | |
1000 | ||
1001 | par->state.vgabase = (void __iomem *) vga_res.start; | |
1002 | ||
a268422d | 1003 | /* Unlock regs */ |
f8645933 DM |
1004 | cr38 = vga_rcrt(par->state.vgabase, 0x38); |
1005 | cr39 = vga_rcrt(par->state.vgabase, 0x39); | |
1006 | vga_wseq(par->state.vgabase, 0x08, 0x06); | |
1007 | vga_wcrt(par->state.vgabase, 0x38, 0x48); | |
1008 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); | |
a268422d | 1009 | |
9966c4fe | 1010 | /* Identify chip type */ |
a268422d | 1011 | par->chip = id->driver_data & CHIP_MASK; |
f8645933 | 1012 | par->rev = vga_rcrt(par->state.vgabase, 0x2f); |
a268422d | 1013 | if (par->chip & CHIP_UNDECIDED_FLAG) |
f8645933 | 1014 | par->chip = s3_identification(par); |
a268422d | 1015 | |
9966c4fe OZ |
1016 | /* Find how many physical memory there is on card */ |
1017 | /* 0x36 register is accessible even if other registers are locked */ | |
f8645933 | 1018 | regval = vga_rcrt(par->state.vgabase, 0x36); |
9966c4fe OZ |
1019 | if (par->chip == CHIP_360_TRIO3D_1X || |
1020 | par->chip == CHIP_362_TRIO3D_2X || | |
5694f9ce OZ |
1021 | par->chip == CHIP_368_TRIO3D_2X || |
1022 | par->chip == CHIP_365_TRIO3D) { | |
9966c4fe OZ |
1023 | switch ((regval & 0xE0) >> 5) { |
1024 | case 0: /* 8MB -- only 4MB usable for display */ | |
1025 | case 1: /* 4MB with 32-bit bus */ | |
1026 | case 2: /* 4MB */ | |
1027 | info->screen_size = 4 << 20; | |
1028 | break; | |
5694f9ce | 1029 | case 4: /* 2MB on 365 Trio3D */ |
9966c4fe OZ |
1030 | case 6: /* 2MB */ |
1031 | info->screen_size = 2 << 20; | |
1032 | break; | |
1033 | } | |
1034 | } else | |
1035 | info->screen_size = s3_memsizes[regval >> 5] << 10; | |
1036 | info->fix.smem_len = info->screen_size; | |
1037 | ||
a268422d | 1038 | /* Find MCLK frequency */ |
f8645933 DM |
1039 | regval = vga_rseq(par->state.vgabase, 0x10); |
1040 | par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); | |
a268422d OZ |
1041 | par->mclk_freq = par->mclk_freq >> (regval >> 5); |
1042 | ||
1043 | /* Restore locks */ | |
f8645933 DM |
1044 | vga_wcrt(par->state.vgabase, 0x38, cr38); |
1045 | vga_wcrt(par->state.vgabase, 0x39, cr39); | |
a268422d OZ |
1046 | |
1047 | strcpy(info->fix.id, s3_names [par->chip]); | |
1048 | info->fix.mmio_start = 0; | |
1049 | info->fix.mmio_len = 0; | |
1050 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
1051 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
1052 | info->fix.ypanstep = 0; | |
1053 | info->fix.accel = FB_ACCEL_NONE; | |
1054 | info->pseudo_palette = (void*) (par->pseudo_palette); | |
1055 | ||
1056 | /* Prepare startup mode */ | |
a8140543 | 1057 | rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); |
a268422d OZ |
1058 | if (! ((rc == 1) || (rc == 2))) { |
1059 | rc = -EINVAL; | |
594a8819 | 1060 | dev_err(info->device, "mode %s not found\n", mode_option); |
a268422d OZ |
1061 | goto err_find_mode; |
1062 | } | |
1063 | ||
99d054d8 OZ |
1064 | /* maximize virtual vertical size for fast scrolling */ |
1065 | info->var.yres_virtual = info->fix.smem_len * 8 / | |
1066 | (info->var.bits_per_pixel * info->var.xres_virtual); | |
1067 | if (info->var.yres_virtual < info->var.yres) { | |
1068 | dev_err(info->device, "virtual vertical size smaller than real\n"); | |
1069 | goto err_find_mode; | |
1070 | } | |
1071 | ||
a268422d OZ |
1072 | rc = fb_alloc_cmap(&info->cmap, 256, 0); |
1073 | if (rc < 0) { | |
594a8819 | 1074 | dev_err(info->device, "cannot allocate colormap\n"); |
a268422d OZ |
1075 | goto err_alloc_cmap; |
1076 | } | |
1077 | ||
1078 | rc = register_framebuffer(info); | |
1079 | if (rc < 0) { | |
594a8819 | 1080 | dev_err(info->device, "cannot register framebuffer\n"); |
a268422d OZ |
1081 | goto err_reg_fb; |
1082 | } | |
1083 | ||
1084 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, | |
1085 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); | |
1086 | ||
1087 | if (par->chip == CHIP_UNKNOWN) | |
1088 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", | |
f8645933 DM |
1089 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), |
1090 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); | |
a268422d OZ |
1091 | |
1092 | /* Record a reference to the driver data */ | |
1093 | pci_set_drvdata(dev, info); | |
1094 | ||
1095 | #ifdef CONFIG_MTRR | |
1096 | if (mtrr) { | |
1097 | par->mtrr_reg = -1; | |
1098 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); | |
1099 | } | |
1100 | #endif | |
1101 | ||
1102 | return 0; | |
1103 | ||
1104 | /* Error handling */ | |
1105 | err_reg_fb: | |
1106 | fb_dealloc_cmap(&info->cmap); | |
1107 | err_alloc_cmap: | |
1108 | err_find_mode: | |
1109 | pci_iounmap(dev, info->screen_base); | |
1110 | err_iomap: | |
1111 | pci_release_regions(dev); | |
1112 | err_request_regions: | |
1113 | /* pci_disable_device(dev); */ | |
1114 | err_enable_device: | |
1115 | framebuffer_release(info); | |
1116 | return rc; | |
1117 | } | |
1118 | ||
1119 | ||
1120 | /* PCI remove */ | |
1121 | ||
1122 | static void __devexit s3_pci_remove(struct pci_dev *dev) | |
1123 | { | |
1124 | struct fb_info *info = pci_get_drvdata(dev); | |
a268422d OZ |
1125 | |
1126 | if (info) { | |
1127 | ||
1128 | #ifdef CONFIG_MTRR | |
47ebea83 AB |
1129 | struct s3fb_info *par = info->par; |
1130 | ||
a268422d OZ |
1131 | if (par->mtrr_reg >= 0) { |
1132 | mtrr_del(par->mtrr_reg, 0, 0); | |
1133 | par->mtrr_reg = -1; | |
1134 | } | |
1135 | #endif | |
1136 | ||
1137 | unregister_framebuffer(info); | |
1138 | fb_dealloc_cmap(&info->cmap); | |
1139 | ||
1140 | pci_iounmap(dev, info->screen_base); | |
1141 | pci_release_regions(dev); | |
1142 | /* pci_disable_device(dev); */ | |
1143 | ||
1144 | pci_set_drvdata(dev, NULL); | |
1145 | framebuffer_release(info); | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | /* PCI suspend */ | |
1150 | ||
1151 | static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) | |
1152 | { | |
1153 | struct fb_info *info = pci_get_drvdata(dev); | |
1154 | struct s3fb_info *par = info->par; | |
1155 | ||
594a8819 | 1156 | dev_info(info->device, "suspend\n"); |
a268422d | 1157 | |
ac751efa | 1158 | console_lock(); |
a268422d OZ |
1159 | mutex_lock(&(par->open_lock)); |
1160 | ||
1161 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { | |
1162 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1163 | console_unlock(); |
a268422d OZ |
1164 | return 0; |
1165 | } | |
1166 | ||
1167 | fb_set_suspend(info, 1); | |
1168 | ||
1169 | pci_save_state(dev); | |
1170 | pci_disable_device(dev); | |
1171 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1172 | ||
1173 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1174 | console_unlock(); |
a268422d OZ |
1175 | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | ||
1180 | /* PCI resume */ | |
1181 | ||
1182 | static int s3_pci_resume(struct pci_dev* dev) | |
1183 | { | |
1184 | struct fb_info *info = pci_get_drvdata(dev); | |
1185 | struct s3fb_info *par = info->par; | |
6314db41 | 1186 | int err; |
a268422d | 1187 | |
594a8819 | 1188 | dev_info(info->device, "resume\n"); |
a268422d | 1189 | |
ac751efa | 1190 | console_lock(); |
a268422d OZ |
1191 | mutex_lock(&(par->open_lock)); |
1192 | ||
1193 | if (par->ref_count == 0) { | |
1194 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1195 | console_unlock(); |
a268422d OZ |
1196 | return 0; |
1197 | } | |
1198 | ||
1199 | pci_set_power_state(dev, PCI_D0); | |
1200 | pci_restore_state(dev); | |
6314db41 RD |
1201 | err = pci_enable_device(dev); |
1202 | if (err) { | |
1203 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1204 | console_unlock(); |
594a8819 | 1205 | dev_err(info->device, "error %d enabling device for resume\n", err); |
6314db41 RD |
1206 | return err; |
1207 | } | |
a268422d OZ |
1208 | pci_set_master(dev); |
1209 | ||
1210 | s3fb_set_par(info); | |
1211 | fb_set_suspend(info, 0); | |
1212 | ||
1213 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 1214 | console_unlock(); |
a268422d OZ |
1215 | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | ||
1220 | /* List of boards that we are trying to support */ | |
1221 | ||
1222 | static struct pci_device_id s3_devices[] __devinitdata = { | |
1223 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, | |
1224 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, | |
1225 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, | |
1226 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, | |
1227 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, | |
1228 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, | |
1229 | ||
1230 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, | |
1231 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, | |
1232 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, | |
1233 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, | |
1234 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, | |
1235 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, | |
9966c4fe | 1236 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, |
5694f9ce | 1237 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, |
a268422d OZ |
1238 | |
1239 | {0, 0, 0, 0, 0, 0, 0} | |
1240 | }; | |
1241 | ||
1242 | ||
1243 | MODULE_DEVICE_TABLE(pci, s3_devices); | |
1244 | ||
1245 | static struct pci_driver s3fb_pci_driver = { | |
1246 | .name = "s3fb", | |
1247 | .id_table = s3_devices, | |
1248 | .probe = s3_pci_probe, | |
1249 | .remove = __devexit_p(s3_pci_remove), | |
1250 | .suspend = s3_pci_suspend, | |
1251 | .resume = s3_pci_resume, | |
1252 | }; | |
1253 | ||
1254 | /* Parse user speficied options */ | |
1255 | ||
1256 | #ifndef MODULE | |
1257 | static int __init s3fb_setup(char *options) | |
1258 | { | |
1259 | char *opt; | |
1260 | ||
1261 | if (!options || !*options) | |
1262 | return 0; | |
1263 | ||
1264 | while ((opt = strsep(&options, ",")) != NULL) { | |
1265 | ||
1266 | if (!*opt) | |
1267 | continue; | |
1268 | #ifdef CONFIG_MTRR | |
62fa4dc7 | 1269 | else if (!strncmp(opt, "mtrr:", 5)) |
a268422d OZ |
1270 | mtrr = simple_strtoul(opt + 5, NULL, 0); |
1271 | #endif | |
62fa4dc7 OZ |
1272 | else if (!strncmp(opt, "fasttext:", 9)) |
1273 | fasttext = simple_strtoul(opt + 9, NULL, 0); | |
a268422d | 1274 | else |
a8140543 | 1275 | mode_option = opt; |
a268422d OZ |
1276 | } |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | #endif | |
1281 | ||
1282 | /* Cleanup */ | |
1283 | ||
1284 | static void __exit s3fb_cleanup(void) | |
1285 | { | |
1286 | pr_debug("s3fb: cleaning up\n"); | |
1287 | pci_unregister_driver(&s3fb_pci_driver); | |
1288 | } | |
1289 | ||
1290 | /* Driver Initialisation */ | |
1291 | ||
1292 | static int __init s3fb_init(void) | |
1293 | { | |
1294 | ||
1295 | #ifndef MODULE | |
1296 | char *option = NULL; | |
1297 | ||
1298 | if (fb_get_options("s3fb", &option)) | |
1299 | return -ENODEV; | |
1300 | s3fb_setup(option); | |
1301 | #endif | |
1302 | ||
1303 | pr_debug("s3fb: initializing\n"); | |
1304 | return pci_register_driver(&s3fb_pci_driver); | |
1305 | } | |
1306 | ||
1307 | /* ------------------------------------------------------------------------- */ | |
1308 | ||
1309 | /* Modularization */ | |
1310 | ||
1311 | module_init(s3fb_init); | |
1312 | module_exit(s3fb_cleanup); |