[mirror_ubuntu-bionic-kernel.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/bitmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#include "sh_mobile_lcdcfb.h"

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define VMLEN2		0x002c
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	struct sh_mobile_lcdc_entity entity;

	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct platform_device *pdev;
};

#define to_sh_mipi(e)	container_of(e, struct sh_mipi, entity)

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));

	sh_mipi_dsi_enable(mipi, false);
}

static int sh_mipi_setup(struct sh_mipi *mipi, struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2;
	u32 tmp, top, bottom, delay, div;
	bool yuv;
	int bpp;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_modes[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_modes[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_modes[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	if (!pdata->lane)
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on */
	iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 */
	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	tmp |= 0x00003700;
	iowrite32(tmp, base + SYSCONF);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	vmctr2 = 0;
	if (pdata->flags & SH_MIPI_DSI_VSEE)
		vmctr2 |= 1 << 23;
	if (pdata->flags & SH_MIPI_DSI_HSEE)
		vmctr2 |= 1 << 22;
	if (pdata->flags & SH_MIPI_DSI_HSAE)
		vmctr2 |= 1 << 21;
	if (pdata->flags & SH_MIPI_DSI_BL2E)
		vmctr2 |= 1 << 17;
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	if (pdata->flags & SH_MIPI_DSI_HFPBM)
		vmctr2 |= 1 << 3;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * VMLEN1 = RGBLEN | HSALEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top = linelength << 16; /* RGBLEN */
	bottom = 0x00000001;
	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
		bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
	iowrite32(top | bottom , mipi->linkbase + VMLEN1);

	/*
	 * VMLEN2 = HBPLEN | HFPLEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top	= 0x00010000;
	bottom	= 0x00000001;
	delay	= 0;

	div = 1;	/* HSbyteCLK is calculation base
			 * HS4divCLK = HSbyteCLK/2
			 * HS6divCLK is not supported for now */
	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
		div = 2;

	if (pdata->flags & SH_MIPI_DSI_HFPBM) {	/* HBPLEN */
		top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
		top = ((pdata->lane * top / div) - 10) << 16;
	}
	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
		bottom = ch->lcd_modes[0].right_margin;
		bottom = (pdata->lane * bottom / div) - 12;
	}

	bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
	if ((pdata->lane / div) > bpp) {
		tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
		tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
		delay = (pdata->lane * tmp);
	}

	iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);

	return 0;
}

static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
{
	struct sh_mipi *mipi = to_sh_mipi(entity);
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	int ret;

	pm_runtime_get_sync(&mipi->pdev->dev);

	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	if (ret < 0)
		goto mipi_display_on_fail1;

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto mipi_display_on_fail2;

	sh_mipi_dsi_enable(mipi, true);

	return SH_MOBILE_LCDC_DISPLAY_CONNECTED;

mipi_display_on_fail1:
	pm_runtime_put_sync(&mipi->pdev->dev);
mipi_display_on_fail2:
	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);

	return ret;
}

static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
{
	struct sh_mipi *mipi = to_sh_mipi(entity);
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;

	sh_mipi_dsi_enable(mipi, false);

	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);

	pm_runtime_put_sync(&mipi->pdev->dev);
}

static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
	.display_on = mipi_display_on,
	.display_off = mipi_display_off,
};

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	if (!pdata->set_dot_clock)
		return -EINVAL;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	mipi->entity.owner = THIS_MODULE;
	mipi->entity.ops = &mipi_ops;

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->pdev = pdev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, &mipi->entity);

	return 0;

eclkton:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __devexit sh_mipi_remove(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);

	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __devexit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
26c3d7ac	11	#include <linux/bitmap.h>
9fd04fe3 GL	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
236782a5	17	#include <linux/pm_runtime.h>
9fd04fe3 GL	18	#include <linux/slab.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
355b200b	21	#include <linux/module.h>
9fd04fe3 GL	22
	23	#include <video/mipi_display.h>
	24	#include <video/sh_mipi_dsi.h>
	25	#include <video/sh_mobile_lcdc.h>
	26
732bbcc4 LP	27	#include "sh_mobile_lcdcfb.h"
732bbcc4 LP	28
71b146c8 MD	29	#define SYSCTRL 0x0000
	30	#define SYSCONF 0x0004
	31	#define TIMSET 0x0008
	32	#define RESREQSET0 0x0018
	33	#define RESREQSET1 0x001c
	34	#define HSTTOVSET 0x0020
	35	#define LPRTOVSET 0x0024
	36	#define TATOVSET 0x0028
	37	#define PRTOVSET 0x002c
	38	#define DSICTRL 0x0030
	39	#define DSIINTE 0x0060
	40	#define PHYCTRL 0x0070
	41
deaba190 MD	42	/* relative to linkbase */
	43	#define DTCTR 0x0000
	44	#define VMCTR1 0x0020
	45	#define VMCTR2 0x0024
	46	#define VMLEN1 0x0028
08750617	47	#define VMLEN2 0x002c
deaba190 MD	48	#define CMTSRTREQ 0x0070
deaba190 MD	49	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	50
	51	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	52	#define MAX_SH_MIPI_DSI 2
	53
	54	struct sh_mipi {
732bbcc4 LP	55	struct sh_mobile_lcdc_entity entity;
732bbcc4 LP	56
9fd04fe3	57	void __iomem *base;
deaba190	58	void __iomem *linkbase;
9fd04fe3	59	struct clk *dsit_clk;
7d9f88b4	60	struct platform_device *pdev;
9fd04fe3 GL	61	};
9fd04fe3 GL	62
732bbcc4 LP	63	#define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
732bbcc4 LP	64
9fd04fe3 GL	65	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	66
	67	/* Protect the above array */
	68	static DEFINE_MUTEX(array_lock);
	69
	70	static struct sh_mipi *sh_mipi_by_handle(int handle)
	71	{
	72	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	73	return NULL;
	74
	75	return mipi_dsi[handle];
	76	}
	77
	78	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	79	u8 cmd, u8 param)
	80	{
	81	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	82	int cnt = 100;
	83
	84	/* transmit a short packet to LCD panel */
deaba190 MD	85	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	86	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	87
deaba190	88	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	89	udelay(1);
	90
	91	return cnt ? 0 : -ETIMEDOUT;
	92	}
	93
	94	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	95	-EINVAL : (c) - 1)
	96
	97	static int sh_mipi_dcs(int handle, u8 cmd)
	98	{
	99	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	100	if (!mipi)
	101	return -ENODEV;
	102	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	103	}
	104
	105	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	106	{
	107	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	108	if (!mipi)
	109	return -ENODEV;
	110	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	111	param);
	112	}
	113
	114	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	115	{
	116	/*
	117	* enable LCDC data tx, transition to LPS after completion of each HS
	118	* packet
	119	*/
deaba190	120	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	121	}
	122
	123	static void sh_mipi_shutdown(struct platform_device *pdev)
	124	{
732bbcc4	125	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
9fd04fe3 GL	126
	127	sh_mipi_dsi_enable(mipi, false);
	128	}
	129
e6765ffa	130	static int sh_mipi_setup(struct sh_mipi mipi, struct sh_mipi_dsi_info pdata)
9fd04fe3 GL	131	{
	132	void __iomem *base = mipi->base;
	133	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
f832906a	134	u32 pctype, datatype, pixfmt, linelength, vmctr2;
a2e62971	135	u32 tmp, top, bottom, delay, div;
9fd04fe3	136	bool yuv;
08750617	137	int bpp;
9fd04fe3	138
44432407 GL	139	/*
	140	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	141	* the default videomode. If this ever becomes a problem, We'll have to
	142	* move this to mipi_display_on() above and use info->var.xres
	143	*/
9fd04fe3 GL	144	switch (pdata->data_format) {
	145	case MIPI_RGB888:
	146	pctype = 0;
	147	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	148	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	149	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	150	yuv = false;
	151	break;
	152	case MIPI_RGB565:
	153	pctype = 1;
	154	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	155	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	156	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	157	yuv = false;
	158	break;
	159	case MIPI_RGB666_LP:
	160	pctype = 2;
	161	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	162	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	163	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	164	yuv = false;
	165	break;
	166	case MIPI_RGB666:
	167	pctype = 3;
	168	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	169	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
93ff2598	170	linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
9fd04fe3 GL	171	yuv = false;
	172	break;
	173	case MIPI_BGR888:
	174	pctype = 8;
	175	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	176	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	177	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	178	yuv = false;
	179	break;
	180	case MIPI_BGR565:
	181	pctype = 9;
	182	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	183	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	184	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	185	yuv = false;
	186	break;
	187	case MIPI_BGR666_LP:
	188	pctype = 0xa;
	189	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	190	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
93ff2598	191	linelength = ch->lcd_modes[0].xres * 3;
9fd04fe3 GL	192	yuv = false;
	193	break;
	194	case MIPI_BGR666:
	195	pctype = 0xb;
	196	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	197	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
93ff2598	198	linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
9fd04fe3 GL	199	yuv = false;
	200	break;
	201	case MIPI_YUYV:
	202	pctype = 4;
	203	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	204	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	205	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	206	yuv = true;
	207	break;
	208	case MIPI_UYVY:
	209	pctype = 5;
	210	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	211	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
93ff2598	212	linelength = ch->lcd_modes[0].xres * 2;
9fd04fe3 GL	213	yuv = true;
	214	break;
	215	case MIPI_YUV420_L:
	216	pctype = 6;
	217	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	218	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
93ff2598	219	linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
9fd04fe3 GL	220	yuv = true;
	221	break;
	222	case MIPI_YUV420:
	223	pctype = 7;
	224	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	225	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	226	/* Length of U/V line */
93ff2598	227	linelength = (ch->lcd_modes[0].xres + 1) / 2;
9fd04fe3 GL	228	yuv = true;
	229	break;
	230	default:
	231	return -EINVAL;
	232	}
	233
	234	if ((yuv && ch->interface_type != YUV422) \|\|
	235	(!yuv && ch->interface_type != RGB24))
	236	return -EINVAL;
	237
26c3d7ac KM	238	if (!pdata->lane)
	239	return -EINVAL;
	240
9fd04fe3	241	/* reset DSI link */
71b146c8	242	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	243	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	244	udelay(50);
71b146c8	245	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	246
	247	/* setup DSI link */
	248
9fd04fe3 GL	249	/*
	250	* T_wakeup = 0x7000
	251	* T_hs-trail = 3
	252	* T_hs-prepare = 3
	253	* T_clk-trail = 3
	254	* T_clk-prepare = 2
	255	*/
71b146c8	256	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	257	/* no responses requested */
71b146c8	258	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	259	/* request response to packets of type 0x28 */
71b146c8	260	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	261	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	262	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	263	/* LP reception timeout, default 0xffffffff */
71b146c8	264	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	265	/* Turn-around timeout, default 0xffffffff */
71b146c8	266	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	267	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	268	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3 GL	269	/* Interrupts not used, disable all */
	270	iowrite32(0, base + DSIINTE);
	271	/* DSI-Tx bias on */
71b146c8	272	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3	273	udelay(200);
5e47431a	274	/* Deassert resets, power on */
8f9c60f2	275	iowrite32(0x03070001 \| pdata->phyctrl, base + PHYCTRL);
9fd04fe3	276
a2065a36 KM	277	/*
	278	* Default = ULPS enable \|
	279	* Contention detection enabled \|
	280	* EoT packet transmission enable \|
	281	* CRC check enable \|
	282	* ECC check enable
	283	*/
	284	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	285	tmp \|= 0x00003700;
	286	iowrite32(tmp, base + SYSCONF);
	287
9fd04fe3 GL	288	/* setup l-bridge */
	289
	290	/*
	291	* Enable transmission of all packets,
	292	* transmit LPS after each HS packet completion
	293	*/
deaba190	294	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	295	/* VSYNC width = 2 (<< 17) */
93ff2598	296	iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6	297	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	298	mipi->linkbase + VMCTR1);
14bbb7c6	299
9fd04fe3 GL	300	/*
	301	* Non-burst mode with sync pulses: VSE and HSE are output,
	302	* HSA period allowed, no commands in LP
	303	*/
f832906a KM	304	vmctr2 = 0;
	305	if (pdata->flags & SH_MIPI_DSI_VSEE)
	306	vmctr2 \|= 1 << 23;
	307	if (pdata->flags & SH_MIPI_DSI_HSEE)
	308	vmctr2 \|= 1 << 22;
	309	if (pdata->flags & SH_MIPI_DSI_HSAE)
	310	vmctr2 \|= 1 << 21;
d07a9d2a KM	311	if (pdata->flags & SH_MIPI_DSI_BL2E)
d07a9d2a KM	312	vmctr2 \|= 1 << 17;
14bbb7c6	313	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	314	vmctr2 \|= 1 << 5;
32ba95c6	315	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	316	vmctr2 \|= 1 << 4;
f7b0af68 KM	317	if (pdata->flags & SH_MIPI_DSI_HFPBM)
f7b0af68 KM	318	vmctr2 \|= 1 << 3;
14bbb7c6 GL	319	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	320
9fd04fe3	321	/*
08750617 KM	322	* VMLEN1 = RGBLEN \| HSALEN
	323	*
	324	* see
	325	* Video mode - Blanking Packet setting
9fd04fe3	326	*/
08750617 KM	327	top = linelength << 16; /* RGBLEN */
	328	bottom = 0x00000001;
	329	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
93ff2598	330	bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
08750617 KM	331	iowrite32(top \| bottom , mipi->linkbase + VMLEN1);
	332
	333	/*
	334	* VMLEN2 = HBPLEN \| HFPLEN
	335	*
	336	* see
	337	* Video mode - Blanking Packet setting
	338	*/
	339	top = 0x00010000;
	340	bottom = 0x00000001;
	341	delay = 0;
	342
a2e62971 KM	343	div = 1; /* HSbyteCLK is calculation base
	344	* HS4divCLK = HSbyteCLK/2
	345	* HS6divCLK is not supported for now */
	346	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
	347	div = 2;
	348
08750617	349	if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
93ff2598	350	top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
a2e62971	351	top = ((pdata->lane * top / div) - 10) << 16;
08750617 KM	352	}
08750617 KM	353	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
93ff2598	354	bottom = ch->lcd_modes[0].right_margin;
a2e62971	355	bottom = (pdata->lane * bottom / div) - 12;
08750617 KM	356	}
08750617 KM	357
93ff2598	358	bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
a2e62971	359	if ((pdata->lane / div) > bpp) {
93ff2598 LP	360	tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
93ff2598 LP	361	tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
08750617 KM	362	delay = (pdata->lane * tmp);
	363	}
	364
	365	iowrite32(top \| (bottom + delay) , mipi->linkbase + VMLEN2);
9fd04fe3 GL	366
	367	msleep(5);
	368
	369	/* setup LCD panel */
	370
	371	/* cf. drivers/video/omap/lcd_mipid.c */
	372	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	373	msleep(120);
	374	/*
	375	* [7] - Page Address Mode
	376	* [6] - Column Address Mode
	377	* [5] - Page / Column Address Mode
	378	* [4] - Display Device Line Refresh Order
	379	* [3] - RGB/BGR Order
	380	* [2] - Display Data Latch Data Order
	381	* [1] - Flip Horizontal
	382	* [0] - Flip Vertical
	383	*/
	384	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	385	/* cf. set_data_lines() */
	386	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	387	pixfmt << 4);
	388	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	389
97cab455 KM	390	/* Enable timeout counters */
	391	iowrite32(0x00000f00, base + DSICTRL);
	392
9fd04fe3 GL	393	return 0;
	394	}
	395
5864ace1	396	static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
c2658b70	397	{
732bbcc4	398	struct sh_mipi *mipi = to_sh_mipi(entity);
c2658b70 KM	399	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	400	int ret;
	401
	402	pm_runtime_get_sync(&mipi->pdev->dev);
	403
	404	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	405	if (ret < 0)
	406	goto mipi_display_on_fail1;
	407
	408	ret = sh_mipi_setup(mipi, pdata);
	409	if (ret < 0)
	410	goto mipi_display_on_fail2;
	411
	412	sh_mipi_dsi_enable(mipi, true);
	413
458981c3	414	return SH_MOBILE_LCDC_DISPLAY_CONNECTED;
c2658b70 KM	415
	416	mipi_display_on_fail1:
	417	pm_runtime_put_sync(&mipi->pdev->dev);
	418	mipi_display_on_fail2:
	419	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
732bbcc4 LP	420
732bbcc4 LP	421	return ret;
c2658b70 KM	422	}
c2658b70 KM	423
d2c594a0	424	static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
732bbcc4 LP	425	{
	426	struct sh_mipi *mipi = to_sh_mipi(entity);
	427	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
c2658b70 KM	428
	429	sh_mipi_dsi_enable(mipi, false);
	430
	431	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
	432
	433	pm_runtime_put_sync(&mipi->pdev->dev);
	434	}
	435
732bbcc4	436	static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
d2c594a0 LP	437	.display_on = mipi_display_on,
d2c594a0 LP	438	.display_off = mipi_display_off,
732bbcc4 LP	439	};
732bbcc4 LP	440
9fd04fe3 GL	441	static int __init sh_mipi_probe(struct platform_device *pdev)
	442	{
	443	struct sh_mipi *mipi;
	444	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	445	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	446	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	447	unsigned long rate, f_current;
9fd04fe3 GL	448	int idx = pdev->id, ret;
9fd04fe3	449
deaba190	450	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	451	return -ENODEV;
9fd04fe3 GL	452
5e47431a KM	453	if (!pdata->set_dot_clock)
	454	return -EINVAL;
	455
9fd04fe3 GL	456	mutex_lock(&array_lock);
	457	if (idx < 0)
	458	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	459	;
	460
	461	if (idx == ARRAY_SIZE(mipi_dsi)) {
	462	ret = -EBUSY;
	463	goto efindslot;
	464	}
	465
	466	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	467	if (!mipi) {
	468	ret = -ENOMEM;
	469	goto ealloc;
	470	}
	471
732bbcc4 LP	472	mipi->entity.owner = THIS_MODULE;
	473	mipi->entity.ops = &mipi_ops;
	474
9fd04fe3 GL	475	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	476	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	477	ret = -EBUSY;
	478	goto ereqreg;
	479	}
	480
	481	mipi->base = ioremap(res->start, resource_size(res));
	482	if (!mipi->base) {
	483	ret = -ENOMEM;
	484	goto emap;
	485	}
	486
deaba190 MD	487	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	488	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	489	ret = -EBUSY;
	490	goto ereqreg2;
	491	}
	492
	493	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	494	if (!mipi->linkbase) {
	495	ret = -ENOMEM;
	496	goto emap2;
	497	}
	498
7d9f88b4	499	mipi->pdev = pdev;
236782a5	500
9fd04fe3 GL	501	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	502	if (IS_ERR(mipi->dsit_clk)) {
	503	ret = PTR_ERR(mipi->dsit_clk);
	504	goto eclktget;
	505	}
	506
	507	f_current = clk_get_rate(mipi->dsit_clk);
	508	/* 80MHz required by the datasheet */
	509	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	510	if (rate > 0 && rate != f_current)
	511	ret = clk_set_rate(mipi->dsit_clk, rate);
	512	else
	513	ret = rate;
	514	if (ret < 0)
	515	goto esettrate;
	516
	517	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	518
9fd04fe3 GL	519	ret = clk_enable(mipi->dsit_clk);
	520	if (ret < 0)
	521	goto eclkton;
	522
9fd04fe3 GL	523	mipi_dsi[idx] = mipi;
9fd04fe3 GL	524
236782a5 GL	525	pm_runtime_enable(&pdev->dev);
	526	pm_runtime_resume(&pdev->dev);
	527
9fd04fe3	528	mutex_unlock(&array_lock);
732bbcc4	529	platform_set_drvdata(pdev, &mipi->entity);
9fd04fe3	530
9fd04fe3 GL	531	return 0;
9fd04fe3 GL	532
9fd04fe3	533	eclkton:
9fd04fe3 GL	534	esettrate:
	535	clk_put(mipi->dsit_clk);
	536	eclktget:
deaba190 MD	537	iounmap(mipi->linkbase);
	538	emap2:
	539	release_mem_region(res2->start, resource_size(res2));
	540	ereqreg2:
9fd04fe3 GL	541	iounmap(mipi->base);
	542	emap:
	543	release_mem_region(res->start, resource_size(res));
	544	ereqreg:
	545	kfree(mipi);
	546	ealloc:
	547	efindslot:
	548	mutex_unlock(&array_lock);
	549
	550	return ret;
	551	}
	552
e6765ffa	553	static int __devexit sh_mipi_remove(struct platform_device *pdev)
9fd04fe3	554	{
9fd04fe3	555	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	556	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
732bbcc4	557	struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
9fd04fe3 GL	558	int i, ret;
	559
	560	mutex_lock(&array_lock);
	561
	562	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	563	;
	564
	565	if (i == ARRAY_SIZE(mipi_dsi)) {
	566	ret = -EINVAL;
	567	} else {
	568	ret = 0;
	569	mipi_dsi[i] = NULL;
	570	}
	571
	572	mutex_unlock(&array_lock);
	573
	574	if (ret < 0)
	575	return ret;
	576
236782a5	577	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	578	clk_disable(mipi->dsit_clk);
9fd04fe3 GL	579	clk_put(mipi->dsit_clk);
5e47431a	580
deaba190 MD	581	iounmap(mipi->linkbase);
	582	if (res2)
	583	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	584	iounmap(mipi->base);
	585	if (res)
	586	release_mem_region(res->start, resource_size(res));
	587	platform_set_drvdata(pdev, NULL);
	588	kfree(mipi);
	589
	590	return 0;
	591	}
	592
	593	static struct platform_driver sh_mipi_driver = {
e6765ffa	594	.remove = __devexit_p(sh_mipi_remove),
9fd04fe3 GL	595	.shutdown = sh_mipi_shutdown,
	596	.driver = {
	597	.name = "sh-mipi-dsi",
	598	},
	599	};
	600
	601	static int __init sh_mipi_init(void)
	602	{
	603	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	604	}
	605	module_init(sh_mipi_init);
	606
	607	static void __exit sh_mipi_exit(void)
	608	{
	609	platform_driver_unregister(&sh_mipi_driver);
	610	}
	611	module_exit(sh_mipi_exit);
	612
	613	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	614	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	615	MODULE_LICENSE("GPL v2");