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Commit | Line | Data |
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9fd04fe3 GL |
1 | /* |
2 | * Renesas SH-mobile MIPI DSI support | |
3 | * | |
4 | * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
5 | * | |
6 | * This is free software; you can redistribute it and/or modify | |
7 | * it under the terms of version 2 of the GNU General Public License as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
236782a5 | 16 | #include <linux/pm_runtime.h> |
9fd04fe3 GL |
17 | #include <linux/slab.h> |
18 | #include <linux/string.h> | |
19 | #include <linux/types.h> | |
20 | ||
21 | #include <video/mipi_display.h> | |
22 | #include <video/sh_mipi_dsi.h> | |
23 | #include <video/sh_mobile_lcdc.h> | |
24 | ||
71b146c8 MD |
25 | #define SYSCTRL 0x0000 |
26 | #define SYSCONF 0x0004 | |
27 | #define TIMSET 0x0008 | |
28 | #define RESREQSET0 0x0018 | |
29 | #define RESREQSET1 0x001c | |
30 | #define HSTTOVSET 0x0020 | |
31 | #define LPRTOVSET 0x0024 | |
32 | #define TATOVSET 0x0028 | |
33 | #define PRTOVSET 0x002c | |
34 | #define DSICTRL 0x0030 | |
35 | #define DSIINTE 0x0060 | |
36 | #define PHYCTRL 0x0070 | |
37 | ||
deaba190 MD |
38 | /* relative to linkbase */ |
39 | #define DTCTR 0x0000 | |
40 | #define VMCTR1 0x0020 | |
41 | #define VMCTR2 0x0024 | |
42 | #define VMLEN1 0x0028 | |
43 | #define CMTSRTREQ 0x0070 | |
44 | #define CMTSRTCTR 0x00d0 | |
9fd04fe3 GL |
45 | |
46 | /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */ | |
47 | #define MAX_SH_MIPI_DSI 2 | |
48 | ||
49 | struct sh_mipi { | |
50 | void __iomem *base; | |
deaba190 | 51 | void __iomem *linkbase; |
9fd04fe3 GL |
52 | struct clk *dsit_clk; |
53 | struct clk *dsip_clk; | |
236782a5 GL |
54 | struct device *dev; |
55 | ||
56 | void *next_board_data; | |
57 | void (*next_display_on)(void *board_data, struct fb_info *info); | |
58 | void (*next_display_off)(void *board_data); | |
9fd04fe3 GL |
59 | }; |
60 | ||
61 | static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI]; | |
62 | ||
63 | /* Protect the above array */ | |
64 | static DEFINE_MUTEX(array_lock); | |
65 | ||
66 | static struct sh_mipi *sh_mipi_by_handle(int handle) | |
67 | { | |
68 | if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0) | |
69 | return NULL; | |
70 | ||
71 | return mipi_dsi[handle]; | |
72 | } | |
73 | ||
74 | static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd, | |
75 | u8 cmd, u8 param) | |
76 | { | |
77 | u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8); | |
78 | int cnt = 100; | |
79 | ||
80 | /* transmit a short packet to LCD panel */ | |
deaba190 MD |
81 | iowrite32(1 | data, mipi->linkbase + CMTSRTCTR); |
82 | iowrite32(1, mipi->linkbase + CMTSRTREQ); | |
9fd04fe3 | 83 | |
deaba190 | 84 | while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt) |
9fd04fe3 GL |
85 | udelay(1); |
86 | ||
87 | return cnt ? 0 : -ETIMEDOUT; | |
88 | } | |
89 | ||
90 | #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \ | |
91 | -EINVAL : (c) - 1) | |
92 | ||
93 | static int sh_mipi_dcs(int handle, u8 cmd) | |
94 | { | |
95 | struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle)); | |
96 | if (!mipi) | |
97 | return -ENODEV; | |
98 | return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0); | |
99 | } | |
100 | ||
101 | static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param) | |
102 | { | |
103 | struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle)); | |
104 | if (!mipi) | |
105 | return -ENODEV; | |
106 | return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd, | |
107 | param); | |
108 | } | |
109 | ||
110 | static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable) | |
111 | { | |
112 | /* | |
113 | * enable LCDC data tx, transition to LPS after completion of each HS | |
114 | * packet | |
115 | */ | |
deaba190 | 116 | iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR); |
9fd04fe3 GL |
117 | } |
118 | ||
119 | static void sh_mipi_shutdown(struct platform_device *pdev) | |
120 | { | |
121 | struct sh_mipi *mipi = platform_get_drvdata(pdev); | |
122 | ||
123 | sh_mipi_dsi_enable(mipi, false); | |
124 | } | |
125 | ||
c2439398 | 126 | static void mipi_display_on(void *arg, struct fb_info *info) |
9fd04fe3 GL |
127 | { |
128 | struct sh_mipi *mipi = arg; | |
129 | ||
236782a5 | 130 | pm_runtime_get_sync(mipi->dev); |
9fd04fe3 | 131 | sh_mipi_dsi_enable(mipi, true); |
6722a401 MD |
132 | |
133 | if (mipi->next_display_on) | |
134 | mipi->next_display_on(mipi->next_board_data, info); | |
9fd04fe3 GL |
135 | } |
136 | ||
137 | static void mipi_display_off(void *arg) | |
138 | { | |
139 | struct sh_mipi *mipi = arg; | |
140 | ||
6722a401 MD |
141 | if (mipi->next_display_off) |
142 | mipi->next_display_off(mipi->next_board_data); | |
143 | ||
9fd04fe3 | 144 | sh_mipi_dsi_enable(mipi, false); |
236782a5 | 145 | pm_runtime_put(mipi->dev); |
9fd04fe3 GL |
146 | } |
147 | ||
148 | static int __init sh_mipi_setup(struct sh_mipi *mipi, | |
149 | struct sh_mipi_dsi_info *pdata) | |
150 | { | |
151 | void __iomem *base = mipi->base; | |
152 | struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan; | |
153 | u32 pctype, datatype, pixfmt; | |
154 | u32 linelength; | |
155 | bool yuv; | |
156 | ||
44432407 GL |
157 | /* |
158 | * Select data format. MIPI DSI is not hot-pluggable, so, we just use | |
159 | * the default videomode. If this ever becomes a problem, We'll have to | |
160 | * move this to mipi_display_on() above and use info->var.xres | |
161 | */ | |
9fd04fe3 GL |
162 | switch (pdata->data_format) { |
163 | case MIPI_RGB888: | |
164 | pctype = 0; | |
165 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
166 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 167 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
168 | yuv = false; |
169 | break; | |
170 | case MIPI_RGB565: | |
171 | pctype = 1; | |
172 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
173 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 174 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
175 | yuv = false; |
176 | break; | |
177 | case MIPI_RGB666_LP: | |
178 | pctype = 2; | |
179 | datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
180 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 181 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
182 | yuv = false; |
183 | break; | |
184 | case MIPI_RGB666: | |
185 | pctype = 3; | |
186 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
187 | pixfmt = MIPI_DCS_PIXEL_FMT_18BIT; | |
44432407 | 188 | linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8; |
9fd04fe3 GL |
189 | yuv = false; |
190 | break; | |
191 | case MIPI_BGR888: | |
192 | pctype = 8; | |
193 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
194 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 195 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
196 | yuv = false; |
197 | break; | |
198 | case MIPI_BGR565: | |
199 | pctype = 9; | |
200 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
201 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 202 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
203 | yuv = false; |
204 | break; | |
205 | case MIPI_BGR666_LP: | |
206 | pctype = 0xa; | |
207 | datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
208 | pixfmt = MIPI_DCS_PIXEL_FMT_24BIT; | |
44432407 | 209 | linelength = ch->lcd_cfg[0].xres * 3; |
9fd04fe3 GL |
210 | yuv = false; |
211 | break; | |
212 | case MIPI_BGR666: | |
213 | pctype = 0xb; | |
214 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
215 | pixfmt = MIPI_DCS_PIXEL_FMT_18BIT; | |
44432407 | 216 | linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8; |
9fd04fe3 GL |
217 | yuv = false; |
218 | break; | |
219 | case MIPI_YUYV: | |
220 | pctype = 4; | |
221 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16; | |
222 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 223 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
224 | yuv = true; |
225 | break; | |
226 | case MIPI_UYVY: | |
227 | pctype = 5; | |
228 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16; | |
229 | pixfmt = MIPI_DCS_PIXEL_FMT_16BIT; | |
44432407 | 230 | linelength = ch->lcd_cfg[0].xres * 2; |
9fd04fe3 GL |
231 | yuv = true; |
232 | break; | |
233 | case MIPI_YUV420_L: | |
234 | pctype = 6; | |
235 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12; | |
236 | pixfmt = MIPI_DCS_PIXEL_FMT_12BIT; | |
44432407 | 237 | linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8; |
9fd04fe3 GL |
238 | yuv = true; |
239 | break; | |
240 | case MIPI_YUV420: | |
241 | pctype = 7; | |
242 | datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12; | |
243 | pixfmt = MIPI_DCS_PIXEL_FMT_12BIT; | |
244 | /* Length of U/V line */ | |
44432407 | 245 | linelength = (ch->lcd_cfg[0].xres + 1) / 2; |
9fd04fe3 GL |
246 | yuv = true; |
247 | break; | |
248 | default: | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | if ((yuv && ch->interface_type != YUV422) || | |
253 | (!yuv && ch->interface_type != RGB24)) | |
254 | return -EINVAL; | |
255 | ||
256 | /* reset DSI link */ | |
71b146c8 | 257 | iowrite32(0x00000001, base + SYSCTRL); |
9fd04fe3 GL |
258 | /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */ |
259 | udelay(50); | |
71b146c8 | 260 | iowrite32(0x00000000, base + SYSCTRL); |
9fd04fe3 GL |
261 | |
262 | /* setup DSI link */ | |
263 | ||
264 | /* | |
265 | * Default = ULPS enable | | |
266 | * Contention detection enabled | | |
267 | * EoT packet transmission enable | | |
268 | * CRC check enable | | |
269 | * ECC check enable | |
270 | * additionally enable first two lanes | |
271 | */ | |
71b146c8 | 272 | iowrite32(0x00003703, base + SYSCONF); |
9fd04fe3 GL |
273 | /* |
274 | * T_wakeup = 0x7000 | |
275 | * T_hs-trail = 3 | |
276 | * T_hs-prepare = 3 | |
277 | * T_clk-trail = 3 | |
278 | * T_clk-prepare = 2 | |
279 | */ | |
71b146c8 | 280 | iowrite32(0x70003332, base + TIMSET); |
9fd04fe3 | 281 | /* no responses requested */ |
71b146c8 | 282 | iowrite32(0x00000000, base + RESREQSET0); |
9fd04fe3 | 283 | /* request response to packets of type 0x28 */ |
71b146c8 | 284 | iowrite32(0x00000100, base + RESREQSET1); |
9fd04fe3 | 285 | /* High-speed transmission timeout, default 0xffffffff */ |
71b146c8 | 286 | iowrite32(0x0fffffff, base + HSTTOVSET); |
9fd04fe3 | 287 | /* LP reception timeout, default 0xffffffff */ |
71b146c8 | 288 | iowrite32(0x0fffffff, base + LPRTOVSET); |
9fd04fe3 | 289 | /* Turn-around timeout, default 0xffffffff */ |
71b146c8 | 290 | iowrite32(0x0fffffff, base + TATOVSET); |
9fd04fe3 | 291 | /* Peripheral reset timeout, default 0xffffffff */ |
71b146c8 | 292 | iowrite32(0x0fffffff, base + PRTOVSET); |
9fd04fe3 | 293 | /* Enable timeout counters */ |
71b146c8 | 294 | iowrite32(0x00000f00, base + DSICTRL); |
9fd04fe3 GL |
295 | /* Interrupts not used, disable all */ |
296 | iowrite32(0, base + DSIINTE); | |
297 | /* DSI-Tx bias on */ | |
71b146c8 | 298 | iowrite32(0x00000001, base + PHYCTRL); |
9fd04fe3 GL |
299 | udelay(200); |
300 | /* Deassert resets, power on, set multiplier */ | |
71b146c8 | 301 | iowrite32(0x03070b01, base + PHYCTRL); |
9fd04fe3 GL |
302 | |
303 | /* setup l-bridge */ | |
304 | ||
305 | /* | |
306 | * Enable transmission of all packets, | |
307 | * transmit LPS after each HS packet completion | |
308 | */ | |
deaba190 | 309 | iowrite32(0x00000006, mipi->linkbase + DTCTR); |
9fd04fe3 | 310 | /* VSYNC width = 2 (<< 17) */ |
deaba190 MD |
311 | iowrite32(0x00040000 | (pctype << 12) | datatype, |
312 | mipi->linkbase + VMCTR1); | |
9fd04fe3 GL |
313 | /* |
314 | * Non-burst mode with sync pulses: VSE and HSE are output, | |
315 | * HSA period allowed, no commands in LP | |
316 | */ | |
deaba190 | 317 | iowrite32(0x00e00000, mipi->linkbase + VMCTR2); |
9fd04fe3 GL |
318 | /* |
319 | * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see | |
44432407 | 320 | * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default |
9fd04fe3 GL |
321 | * (unused, since VMCTR2[HSABM] = 0) |
322 | */ | |
deaba190 | 323 | iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1); |
9fd04fe3 GL |
324 | |
325 | msleep(5); | |
326 | ||
327 | /* setup LCD panel */ | |
328 | ||
329 | /* cf. drivers/video/omap/lcd_mipid.c */ | |
330 | sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE); | |
331 | msleep(120); | |
332 | /* | |
333 | * [7] - Page Address Mode | |
334 | * [6] - Column Address Mode | |
335 | * [5] - Page / Column Address Mode | |
336 | * [4] - Display Device Line Refresh Order | |
337 | * [3] - RGB/BGR Order | |
338 | * [2] - Display Data Latch Data Order | |
339 | * [1] - Flip Horizontal | |
340 | * [0] - Flip Vertical | |
341 | */ | |
342 | sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00); | |
343 | /* cf. set_data_lines() */ | |
344 | sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT, | |
345 | pixfmt << 4); | |
346 | sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static int __init sh_mipi_probe(struct platform_device *pdev) | |
352 | { | |
353 | struct sh_mipi *mipi; | |
354 | struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; | |
355 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
deaba190 | 356 | struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
9fd04fe3 GL |
357 | unsigned long rate, f_current; |
358 | int idx = pdev->id, ret; | |
359 | char dsip_clk[] = "dsi.p_clk"; | |
360 | ||
deaba190 | 361 | if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata) |
9fd04fe3 GL |
362 | return -ENODEV; |
363 | ||
364 | mutex_lock(&array_lock); | |
365 | if (idx < 0) | |
366 | for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++) | |
367 | ; | |
368 | ||
369 | if (idx == ARRAY_SIZE(mipi_dsi)) { | |
370 | ret = -EBUSY; | |
371 | goto efindslot; | |
372 | } | |
373 | ||
374 | mipi = kzalloc(sizeof(*mipi), GFP_KERNEL); | |
375 | if (!mipi) { | |
376 | ret = -ENOMEM; | |
377 | goto ealloc; | |
378 | } | |
379 | ||
380 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
381 | dev_err(&pdev->dev, "MIPI register region already claimed\n"); | |
382 | ret = -EBUSY; | |
383 | goto ereqreg; | |
384 | } | |
385 | ||
386 | mipi->base = ioremap(res->start, resource_size(res)); | |
387 | if (!mipi->base) { | |
388 | ret = -ENOMEM; | |
389 | goto emap; | |
390 | } | |
391 | ||
deaba190 MD |
392 | if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) { |
393 | dev_err(&pdev->dev, "MIPI register region 2 already claimed\n"); | |
394 | ret = -EBUSY; | |
395 | goto ereqreg2; | |
396 | } | |
397 | ||
398 | mipi->linkbase = ioremap(res2->start, resource_size(res2)); | |
399 | if (!mipi->linkbase) { | |
400 | ret = -ENOMEM; | |
401 | goto emap2; | |
402 | } | |
403 | ||
236782a5 GL |
404 | mipi->dev = &pdev->dev; |
405 | ||
9fd04fe3 GL |
406 | mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk"); |
407 | if (IS_ERR(mipi->dsit_clk)) { | |
408 | ret = PTR_ERR(mipi->dsit_clk); | |
409 | goto eclktget; | |
410 | } | |
411 | ||
412 | f_current = clk_get_rate(mipi->dsit_clk); | |
413 | /* 80MHz required by the datasheet */ | |
414 | rate = clk_round_rate(mipi->dsit_clk, 80000000); | |
415 | if (rate > 0 && rate != f_current) | |
416 | ret = clk_set_rate(mipi->dsit_clk, rate); | |
417 | else | |
418 | ret = rate; | |
419 | if (ret < 0) | |
420 | goto esettrate; | |
421 | ||
422 | dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate); | |
423 | ||
424 | sprintf(dsip_clk, "dsi%1.1dp_clk", idx); | |
425 | mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk); | |
426 | if (IS_ERR(mipi->dsip_clk)) { | |
427 | ret = PTR_ERR(mipi->dsip_clk); | |
428 | goto eclkpget; | |
429 | } | |
430 | ||
431 | f_current = clk_get_rate(mipi->dsip_clk); | |
432 | /* Between 10 and 50MHz */ | |
433 | rate = clk_round_rate(mipi->dsip_clk, 24000000); | |
434 | if (rate > 0 && rate != f_current) | |
435 | ret = clk_set_rate(mipi->dsip_clk, rate); | |
436 | else | |
437 | ret = rate; | |
438 | if (ret < 0) | |
439 | goto esetprate; | |
440 | ||
441 | dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate); | |
442 | ||
443 | msleep(10); | |
444 | ||
445 | ret = clk_enable(mipi->dsit_clk); | |
446 | if (ret < 0) | |
447 | goto eclkton; | |
448 | ||
449 | ret = clk_enable(mipi->dsip_clk); | |
450 | if (ret < 0) | |
451 | goto eclkpon; | |
452 | ||
453 | mipi_dsi[idx] = mipi; | |
454 | ||
236782a5 GL |
455 | pm_runtime_enable(&pdev->dev); |
456 | pm_runtime_resume(&pdev->dev); | |
457 | ||
9fd04fe3 GL |
458 | ret = sh_mipi_setup(mipi, pdata); |
459 | if (ret < 0) | |
460 | goto emipisetup; | |
461 | ||
462 | mutex_unlock(&array_lock); | |
463 | platform_set_drvdata(pdev, mipi); | |
464 | ||
6722a401 MD |
465 | /* Save original LCDC callbacks */ |
466 | mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data; | |
467 | mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on; | |
468 | mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off; | |
469 | ||
9fd04fe3 GL |
470 | /* Set up LCDC callbacks */ |
471 | pdata->lcd_chan->board_cfg.board_data = mipi; | |
472 | pdata->lcd_chan->board_cfg.display_on = mipi_display_on; | |
473 | pdata->lcd_chan->board_cfg.display_off = mipi_display_off; | |
236782a5 | 474 | pdata->lcd_chan->board_cfg.owner = THIS_MODULE; |
9fd04fe3 GL |
475 | |
476 | return 0; | |
477 | ||
478 | emipisetup: | |
479 | mipi_dsi[idx] = NULL; | |
236782a5 | 480 | pm_runtime_disable(&pdev->dev); |
9fd04fe3 GL |
481 | clk_disable(mipi->dsip_clk); |
482 | eclkpon: | |
483 | clk_disable(mipi->dsit_clk); | |
484 | eclkton: | |
485 | esetprate: | |
486 | clk_put(mipi->dsip_clk); | |
487 | eclkpget: | |
488 | esettrate: | |
489 | clk_put(mipi->dsit_clk); | |
490 | eclktget: | |
deaba190 MD |
491 | iounmap(mipi->linkbase); |
492 | emap2: | |
493 | release_mem_region(res2->start, resource_size(res2)); | |
494 | ereqreg2: | |
9fd04fe3 GL |
495 | iounmap(mipi->base); |
496 | emap: | |
497 | release_mem_region(res->start, resource_size(res)); | |
498 | ereqreg: | |
499 | kfree(mipi); | |
500 | ealloc: | |
501 | efindslot: | |
502 | mutex_unlock(&array_lock); | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
507 | static int __exit sh_mipi_remove(struct platform_device *pdev) | |
508 | { | |
509 | struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; | |
510 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
deaba190 | 511 | struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
9fd04fe3 GL |
512 | struct sh_mipi *mipi = platform_get_drvdata(pdev); |
513 | int i, ret; | |
514 | ||
515 | mutex_lock(&array_lock); | |
516 | ||
517 | for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++) | |
518 | ; | |
519 | ||
520 | if (i == ARRAY_SIZE(mipi_dsi)) { | |
521 | ret = -EINVAL; | |
522 | } else { | |
523 | ret = 0; | |
524 | mipi_dsi[i] = NULL; | |
525 | } | |
526 | ||
527 | mutex_unlock(&array_lock); | |
528 | ||
529 | if (ret < 0) | |
530 | return ret; | |
531 | ||
236782a5 | 532 | pdata->lcd_chan->board_cfg.owner = NULL; |
9fd04fe3 GL |
533 | pdata->lcd_chan->board_cfg.display_on = NULL; |
534 | pdata->lcd_chan->board_cfg.display_off = NULL; | |
535 | pdata->lcd_chan->board_cfg.board_data = NULL; | |
536 | ||
236782a5 | 537 | pm_runtime_disable(&pdev->dev); |
9fd04fe3 GL |
538 | clk_disable(mipi->dsip_clk); |
539 | clk_disable(mipi->dsit_clk); | |
540 | clk_put(mipi->dsit_clk); | |
541 | clk_put(mipi->dsip_clk); | |
deaba190 MD |
542 | iounmap(mipi->linkbase); |
543 | if (res2) | |
544 | release_mem_region(res2->start, resource_size(res2)); | |
9fd04fe3 GL |
545 | iounmap(mipi->base); |
546 | if (res) | |
547 | release_mem_region(res->start, resource_size(res)); | |
548 | platform_set_drvdata(pdev, NULL); | |
549 | kfree(mipi); | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static struct platform_driver sh_mipi_driver = { | |
555 | .remove = __exit_p(sh_mipi_remove), | |
556 | .shutdown = sh_mipi_shutdown, | |
557 | .driver = { | |
558 | .name = "sh-mipi-dsi", | |
559 | }, | |
560 | }; | |
561 | ||
562 | static int __init sh_mipi_init(void) | |
563 | { | |
564 | return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe); | |
565 | } | |
566 | module_init(sh_mipi_init); | |
567 | ||
568 | static void __exit sh_mipi_exit(void) | |
569 | { | |
570 | platform_driver_unregister(&sh_mipi_driver); | |
571 | } | |
572 | module_exit(sh_mipi_exit); | |
573 | ||
574 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); | |
575 | MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver"); | |
576 | MODULE_LICENSE("GPL v2"); |