[mirror_ubuntu-bionic-kernel.git] / drivers / video / sh_mobile_lcdcfb.c

/*
 * SuperH Mobile LCDC Framebuffer
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <video/sh_mobile_lcdc.h>

#define PALETTE_NR 16

struct sh_mobile_lcdc_priv;
struct sh_mobile_lcdc_chan {
	struct sh_mobile_lcdc_priv *lcdc;
	unsigned long *reg_offs;
	unsigned long ldmt1r_value;
	unsigned long enabled; /* ME and SE in LDCNT2R */
	struct sh_mobile_lcdc_chan_cfg cfg;
	u32 pseudo_palette[PALETTE_NR];
	struct fb_info info;
	dma_addr_t dma_handle;
};

struct sh_mobile_lcdc_priv {
	void __iomem *base;
#ifdef CONFIG_HAVE_CLK
	struct clk *dot_clk;
	struct clk *clk;
#endif
	unsigned long lddckr;
	struct sh_mobile_lcdc_chan ch[2];
};

/* shared registers */
#define _LDDCKR 0x410
#define _LDDCKSTPR 0x414
#define _LDINTR 0x468
#define _LDSR 0x46c
#define _LDCNT1R 0x470
#define _LDCNT2R 0x474
#define _LDDDSR 0x47c
#define _LDDWD0R 0x800
#define _LDDRDR 0x840
#define _LDDWAR 0x900
#define _LDDRAR 0x904

/* per-channel registers */
enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
       LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };

static unsigned long lcdc_offs_mainlcd[] = {
	[LDDCKPAT1R] = 0x400,
	[LDDCKPAT2R] = 0x404,
	[LDMT1R] = 0x418,
	[LDMT2R] = 0x41c,
	[LDMT3R] = 0x420,
	[LDDFR] = 0x424,
	[LDSM1R] = 0x428,
	[LDSA1R] = 0x430,
	[LDMLSR] = 0x438,
	[LDHCNR] = 0x448,
	[LDHSYNR] = 0x44c,
	[LDVLNR] = 0x450,
	[LDVSYNR] = 0x454,
	[LDPMR] = 0x460,
};

static unsigned long lcdc_offs_sublcd[] = {
	[LDDCKPAT1R] = 0x408,
	[LDDCKPAT2R] = 0x40c,
	[LDMT1R] = 0x600,
	[LDMT2R] = 0x604,
	[LDMT3R] = 0x608,
	[LDDFR] = 0x60c,
	[LDSM1R] = 0x610,
	[LDSA1R] = 0x618,
	[LDMLSR] = 0x620,
	[LDHCNR] = 0x624,
	[LDHSYNR] = 0x628,
	[LDVLNR] = 0x62c,
	[LDVSYNR] = 0x630,
	[LDPMR] = 0x63c,
};

#define START_LCDC	0x00000001
#define LCDC_RESET	0x00000100
#define DISPLAY_BEU	0x00000008
#define LCDC_ENABLE	0x00000001

static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
			    int reg_nr, unsigned long data)
{
	iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
}

static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
				    int reg_nr)
{
	return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
}

static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
		       unsigned long reg_offs, unsigned long data)
{
	iowrite32(data, priv->base + reg_offs);
}

static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
			       unsigned long reg_offs)
{
	return ioread32(priv->base + reg_offs);
}

static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
			  unsigned long reg_offs,
			  unsigned long mask, unsigned long until)
{
	while ((lcdc_read(priv, reg_offs) & mask) != until)
		cpu_relax();
}

static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
{
	return chan->cfg.chan == LCDC_CHAN_SUBLCD;
}

static void lcdc_sys_write_index(void *handle, unsigned long data)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
}

static void lcdc_sys_write_data(void *handle, unsigned long data)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
}

static unsigned long lcdc_sys_read_data(void *handle)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
	udelay(1);

	return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
}

struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
	lcdc_sys_write_index,
	lcdc_sys_write_data,
	lcdc_sys_read_data,
};

static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
				      int start)
{
	unsigned long tmp = lcdc_read(priv, _LDCNT2R);
	int k;

	/* start or stop the lcdc */
	if (start)
		lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
	else
		lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);

	/* wait until power is applied/stopped on all channels */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
		if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
			while (1) {
				tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
				if (start && tmp == 3)
					break;
				if (!start && tmp == 0)
					break;
				cpu_relax();
			}

	if (!start)
		lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
}

static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
{
	struct sh_mobile_lcdc_chan *ch;
	struct fb_videomode *lcd_cfg;
	struct sh_mobile_lcdc_board_cfg	*board_cfg;
	unsigned long tmp;
	int k, m;
	int ret = 0;

#ifdef CONFIG_HAVE_CLK
	clk_enable(priv->clk);
	if (priv->dot_clk)
		clk_enable(priv->dot_clk);
#endif
	/* reset */
	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
	lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);

	/* enable LCDC channels */
	tmp = lcdc_read(priv, _LDCNT2R);
	tmp |= priv->ch[0].enabled;
	tmp |= priv->ch[1].enabled;
	lcdc_write(priv, _LDCNT2R, tmp);

	/* read data from external memory, avoid using the BEU for now */
	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);

	/* stop the lcdc first */
	sh_mobile_lcdc_start_stop(priv, 0);

	/* configure clocks */
	tmp = priv->lddckr;
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];

		if (!priv->ch[k].enabled)
			continue;

		m = ch->cfg.clock_divider;
		if (!m)
			continue;

		if (m == 1)
			m = 1 << 6;
		tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);

		lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
		lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
	}

	lcdc_write(priv, _LDDCKR, tmp);

	/* start dotclock again */
	lcdc_write(priv, _LDDCKSTPR, 0);
	lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);

	/* interrupts are disabled */
	lcdc_write(priv, _LDINTR, 0);

	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		lcd_cfg = &ch->cfg.lcd_cfg;

		if (!ch->enabled)
			continue;

		tmp = ch->ldmt1r_value;
		tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
		tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
		tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
		tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
		tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
		tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
		tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
		lcdc_write_chan(ch, LDMT1R, tmp);

		/* setup SYS bus */
		lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
		lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);

		/* horizontal configuration */
		tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
		tmp += lcd_cfg->left_margin;
		tmp += lcd_cfg->right_margin;
		tmp /= 8; /* HTCN */
		tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
		lcdc_write_chan(ch, LDHCNR, tmp);

		tmp = lcd_cfg->xres;
		tmp += lcd_cfg->right_margin;
		tmp /= 8; /* HSYNP */
		tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
		lcdc_write_chan(ch, LDHSYNR, tmp);

		/* power supply */
		lcdc_write_chan(ch, LDPMR, 0);

		/* vertical configuration */
		tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
		tmp += lcd_cfg->upper_margin;
		tmp += lcd_cfg->lower_margin; /* VTLN */
		tmp |= lcd_cfg->yres << 16; /* VDLN */
		lcdc_write_chan(ch, LDVLNR, tmp);

		tmp = lcd_cfg->yres;
		tmp += lcd_cfg->lower_margin; /* VSYNP */
		tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
		lcdc_write_chan(ch, LDVSYNR, tmp);

		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->setup_sys)
			ret = board_cfg->setup_sys(board_cfg->board_data, ch,
						   &sh_mobile_lcdc_sys_bus_ops);
		if (ret)
			return ret;
	}

	/* --- display_lcdc_data() --- */
	lcdc_write(priv, _LDINTR, 0x00000f00);

	/* word and long word swap */
	lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);

	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];

		if (!priv->ch[k].enabled)
			continue;

		/* set bpp format in PKF[4:0] */
		tmp = lcdc_read_chan(ch, LDDFR);
		tmp &= ~(0x0001001f);
		tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
		lcdc_write_chan(ch, LDDFR, tmp);

		/* point out our frame buffer */
		lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);

		/* set line size */
		lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);

		/* continuous read mode */
		lcdc_write_chan(ch, LDSM1R, 0);
	}

	/* display output */
	lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);

	/* start the lcdc */
	sh_mobile_lcdc_start_stop(priv, 1);

	/* tell the board code to enable the panel */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->display_on)
			board_cfg->display_on(board_cfg->board_data);
	}

	return 0;
}

static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
{
	struct sh_mobile_lcdc_chan *ch;
	struct sh_mobile_lcdc_board_cfg	*board_cfg;
	int k;

	/* tell the board code to disable the panel */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->display_off)
			board_cfg->display_off(board_cfg->board_data);
	}

	/* stop the lcdc */
	sh_mobile_lcdc_start_stop(priv, 0);

#ifdef CONFIG_HAVE_CLK
	if (priv->dot_clk)
		clk_disable(priv->dot_clk);
	clk_disable(priv->clk);
#endif
}

static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
{
	int ifm, miftyp;

	switch (ch->cfg.interface_type) {
	case RGB8: ifm = 0; miftyp = 0; break;
	case RGB9: ifm = 0; miftyp = 4; break;
	case RGB12A: ifm = 0; miftyp = 5; break;
	case RGB12B: ifm = 0; miftyp = 6; break;
	case RGB16: ifm = 0; miftyp = 7; break;
	case RGB18: ifm = 0; miftyp = 10; break;
	case RGB24: ifm = 0; miftyp = 11; break;
	case SYS8A: ifm = 1; miftyp = 0; break;
	case SYS8B: ifm = 1; miftyp = 1; break;
	case SYS8C: ifm = 1; miftyp = 2; break;
	case SYS8D: ifm = 1; miftyp = 3; break;
	case SYS9: ifm = 1; miftyp = 4; break;
	case SYS12: ifm = 1; miftyp = 5; break;
	case SYS16A: ifm = 1; miftyp = 7; break;
	case SYS16B: ifm = 1; miftyp = 8; break;
	case SYS16C: ifm = 1; miftyp = 9; break;
	case SYS18: ifm = 1; miftyp = 10; break;
	case SYS24: ifm = 1; miftyp = 11; break;
	default: goto bad;
	}

	/* SUBLCD only supports SYS interface */
	if (lcdc_chan_is_sublcd(ch)) {
		if (ifm == 0)
			goto bad;
		else
			ifm = 0;
	}

	ch->ldmt1r_value = (ifm << 12) | miftyp;
	return 0;
 bad:
	return -EINVAL;
}

static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
				       int clock_source,
				       struct sh_mobile_lcdc_priv *priv)
{
#ifdef CONFIG_HAVE_CLK
	char clk_name[8];
#endif
	char *str;
	int icksel;

	switch (clock_source) {
	case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
	case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
	case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
	default:
		return -EINVAL;
	}

	priv->lddckr = icksel << 16;

#ifdef CONFIG_HAVE_CLK
	snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
	priv->clk = clk_get(&pdev->dev, clk_name);
	if (IS_ERR(priv->clk)) {
		dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
		return PTR_ERR(priv->clk);
	}
	
	if (str) {
		priv->dot_clk = clk_get(&pdev->dev, str);
		if (IS_ERR(priv->dot_clk)) {
			dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
			clk_put(priv->clk);
			return PTR_ERR(priv->dot_clk);
		}
	}
#endif

	return 0;
}

static int sh_mobile_lcdc_setcolreg(u_int regno,
				    u_int red, u_int green, u_int blue,
				    u_int transp, struct fb_info *info)
{
	u32 *palette = info->pseudo_palette;

	if (regno >= PALETTE_NR)
		return -EINVAL;

	/* only FB_VISUAL_TRUECOLOR supported */

	red >>= 16 - info->var.red.length;
	green >>= 16 - info->var.green.length;
	blue >>= 16 - info->var.blue.length;
	transp >>= 16 - info->var.transp.length;

	palette[regno] = (red << info->var.red.offset) |
	  (green << info->var.green.offset) |
	  (blue << info->var.blue.offset) |
	  (transp << info->var.transp.offset);

	return 0;
}

static struct fb_fix_screeninfo sh_mobile_lcdc_fix  = {
	.id =		"SH Mobile LCDC",
	.type =		FB_TYPE_PACKED_PIXELS,
	.visual =	FB_VISUAL_TRUECOLOR,
	.accel =	FB_ACCEL_NONE,
};

static struct fb_ops sh_mobile_lcdc_ops = {
	.fb_setcolreg	= sh_mobile_lcdc_setcolreg,
	.fb_read        = fb_sys_read,
	.fb_write       = fb_sys_write,
	.fb_fillrect	= sys_fillrect,
	.fb_copyarea	= sys_copyarea,
	.fb_imageblit	= sys_imageblit,
};

static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
{
	switch (bpp) {
	case 16: /* PKF[4:0] = 00011 - RGB 565 */
		var->red.offset = 11;
		var->red.length = 5;
		var->green.offset = 5;
		var->green.length = 6;
		var->blue.offset = 0;
		var->blue.length = 5;
		var->transp.offset = 0;
		var->transp.length = 0;
		break;

	case 32: /* PKF[4:0] = 00000 - RGB 888
		  * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
		  * this may be because LDDDSR has word swap enabled..
		  */
		var->red.offset = 0;
		var->red.length = 8;
		var->green.offset = 24;
		var->green.length = 8;
		var->blue.offset = 16;
		var->blue.length = 8;
		var->transp.offset = 0;
		var->transp.length = 0;
		break;
	default:
		return -EINVAL;
	}
	var->bits_per_pixel = bpp;
	var->red.msb_right = 0;
	var->green.msb_right = 0;
	var->blue.msb_right = 0;
	var->transp.msb_right = 0;
	return 0;
}

static int sh_mobile_lcdc_remove(struct platform_device *pdev);

static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
{
	struct fb_info *info;
	struct sh_mobile_lcdc_priv *priv;
	struct sh_mobile_lcdc_info *pdata;
	struct sh_mobile_lcdc_chan_cfg *cfg;
	struct resource *res;
	int error;
	void *buf;
	int i, j;

	if (!pdev->dev.platform_data) {
		dev_err(&pdev->dev, "no platform data defined\n");
		error = -EINVAL;
		goto err0;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "cannot find IO resource\n");
		error = -ENOENT;
		goto err0;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "cannot allocate device data\n");
		error = -ENOMEM;
		goto err0;
	}

	platform_set_drvdata(pdev, priv);
	pdata = pdev->dev.platform_data;

	j = 0;
	for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
		priv->ch[j].lcdc = priv;
		memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));

		error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
		if (error) {
			dev_err(&pdev->dev, "unsupported interface type\n");
			goto err1;
		}

		switch (pdata->ch[i].chan) {
		case LCDC_CHAN_MAINLCD:
			priv->ch[j].enabled = 1 << 1;
			priv->ch[j].reg_offs = lcdc_offs_mainlcd;
			j++;
			break;
		case LCDC_CHAN_SUBLCD:
			priv->ch[j].enabled = 1 << 2;
			priv->ch[j].reg_offs = lcdc_offs_sublcd;
			j++;
			break;
		}
	}

	if (!j) {
		dev_err(&pdev->dev, "no channels defined\n");
		error = -EINVAL;
		goto err1;
	}

	error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
	if (error) {
		dev_err(&pdev->dev, "unable to setup clocks\n");
		goto err1;
	}

	priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);

	for (i = 0; i < j; i++) {
		info = &priv->ch[i].info;
		cfg = &priv->ch[i].cfg;

		info->fbops = &sh_mobile_lcdc_ops;
		info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
		info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
		info->var.width = cfg->lcd_size_cfg.width;
		info->var.height = cfg->lcd_size_cfg.height;
		info->var.activate = FB_ACTIVATE_NOW;
		error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
		if (error)
			break;

		info->fix = sh_mobile_lcdc_fix;
		info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
		info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;

		buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
					 &priv->ch[i].dma_handle, GFP_KERNEL);
		if (!buf) {
			dev_err(&pdev->dev, "unable to allocate buffer\n");
			error = -ENOMEM;
			break;
		}

		info->pseudo_palette = &priv->ch[i].pseudo_palette;
		info->flags = FBINFO_FLAG_DEFAULT;

		error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
		if (error < 0) {
			dev_err(&pdev->dev, "unable to allocate cmap\n");
			dma_free_coherent(&pdev->dev, info->fix.smem_len,
					  buf, priv->ch[i].dma_handle);
			break;
		}

		memset(buf, 0, info->fix.smem_len);
		info->fix.smem_start = priv->ch[i].dma_handle;
		info->screen_base = buf;
		info->device = &pdev->dev;
	}

	if (error)
		goto err1;

	error = sh_mobile_lcdc_start(priv);
	if (error) {
		dev_err(&pdev->dev, "unable to start hardware\n");
		goto err1;
	}

	for (i = 0; i < j; i++) {
		error = register_framebuffer(&priv->ch[i].info);
		if (error < 0)
			goto err1;
	}

	for (i = 0; i < j; i++) {
		info = &priv->ch[i].info;
		dev_info(info->dev,
			 "registered %s/%s as %dx%d %dbpp.\n",
			 pdev->name,
			 (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
			 "mainlcd" : "sublcd",
			 (int) priv->ch[i].cfg.lcd_cfg.xres,
			 (int) priv->ch[i].cfg.lcd_cfg.yres,
			 priv->ch[i].cfg.bpp);
	}

	return 0;
 err1:
	sh_mobile_lcdc_remove(pdev);
 err0:
	return error;
}

static int sh_mobile_lcdc_remove(struct platform_device *pdev)
{
	struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
	struct fb_info *info;
	int i;

	for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
		if (priv->ch[i].info.dev)
			unregister_framebuffer(&priv->ch[i].info);

	sh_mobile_lcdc_stop(priv);

	for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
		info = &priv->ch[i].info;

		if (!info->device)
			continue;

		dma_free_coherent(&pdev->dev, info->fix.smem_len,
				  info->screen_base, priv->ch[i].dma_handle);
		fb_dealloc_cmap(&info->cmap);
	}

#ifdef CONFIG_HAVE_CLK
	if (priv->dot_clk)
		clk_put(priv->dot_clk);
	clk_put(priv->clk);
#endif

	if (priv->base)
		iounmap(priv->base);

	kfree(priv);
	return 0;
}

static struct platform_driver sh_mobile_lcdc_driver = {
	.driver		= {
		.name		= "sh_mobile_lcdc_fb",
		.owner		= THIS_MODULE,
	},
	.probe		= sh_mobile_lcdc_probe,
	.remove		= sh_mobile_lcdc_remove,
};

static int __init sh_mobile_lcdc_init(void)
{
	return platform_driver_register(&sh_mobile_lcdc_driver);
}

static void __exit sh_mobile_lcdc_exit(void)
{
	platform_driver_unregister(&sh_mobile_lcdc_driver);
}

module_init(sh_mobile_lcdc_init);
module_exit(sh_mobile_lcdc_exit);

MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
cfb4f5d1 MD	1	/*
	2	* SuperH Mobile LCDC Framebuffer
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/delay.h>
	14	#include <linux/mm.h>
	15	#include <linux/fb.h>
	16	#include <linux/clk.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/dma-mapping.h>
225c9a8d	19	#include <video/sh_mobile_lcdc.h>
cfb4f5d1 MD	20
	21	#define PALETTE_NR 16
	22
	23	struct sh_mobile_lcdc_priv;
	24	struct sh_mobile_lcdc_chan {
	25	struct sh_mobile_lcdc_priv *lcdc;
	26	unsigned long *reg_offs;
	27	unsigned long ldmt1r_value;
	28	unsigned long enabled; /* ME and SE in LDCNT2R */
	29	struct sh_mobile_lcdc_chan_cfg cfg;
	30	u32 pseudo_palette[PALETTE_NR];
	31	struct fb_info info;
	32	dma_addr_t dma_handle;
	33	};
	34
	35	struct sh_mobile_lcdc_priv {
	36	void __iomem *base;
225c9a8d	37	#ifdef CONFIG_HAVE_CLK
b51339ff	38	struct clk *dot_clk;
cfb4f5d1	39	struct clk *clk;
225c9a8d	40	#endif
cfb4f5d1 MD	41	unsigned long lddckr;
	42	struct sh_mobile_lcdc_chan ch[2];
	43	};
	44
	45	/* shared registers */
	46	#define _LDDCKR 0x410
	47	#define _LDDCKSTPR 0x414
	48	#define _LDINTR 0x468
	49	#define _LDSR 0x46c
	50	#define _LDCNT1R 0x470
	51	#define _LDCNT2R 0x474
	52	#define _LDDDSR 0x47c
	53	#define _LDDWD0R 0x800
	54	#define _LDDRDR 0x840
	55	#define _LDDWAR 0x900
	56	#define _LDDRAR 0x904
	57
	58	/* per-channel registers */
	59	enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
	60	LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
	61
	62	static unsigned long lcdc_offs_mainlcd[] = {
	63	[LDDCKPAT1R] = 0x400,
	64	[LDDCKPAT2R] = 0x404,
	65	[LDMT1R] = 0x418,
	66	[LDMT2R] = 0x41c,
	67	[LDMT3R] = 0x420,
	68	[LDDFR] = 0x424,
	69	[LDSM1R] = 0x428,
	70	[LDSA1R] = 0x430,
	71	[LDMLSR] = 0x438,
	72	[LDHCNR] = 0x448,
	73	[LDHSYNR] = 0x44c,
	74	[LDVLNR] = 0x450,
	75	[LDVSYNR] = 0x454,
	76	[LDPMR] = 0x460,
	77	};
	78
	79	static unsigned long lcdc_offs_sublcd[] = {
	80	[LDDCKPAT1R] = 0x408,
	81	[LDDCKPAT2R] = 0x40c,
	82	[LDMT1R] = 0x600,
	83	[LDMT2R] = 0x604,
	84	[LDMT3R] = 0x608,
	85	[LDDFR] = 0x60c,
	86	[LDSM1R] = 0x610,
	87	[LDSA1R] = 0x618,
	88	[LDMLSR] = 0x620,
	89	[LDHCNR] = 0x624,
	90	[LDHSYNR] = 0x628,
	91	[LDVLNR] = 0x62c,
	92	[LDVSYNR] = 0x630,
	93	[LDPMR] = 0x63c,
	94	};
	95
	96	#define START_LCDC 0x00000001
	97	#define LCDC_RESET 0x00000100
	98	#define DISPLAY_BEU 0x00000008
	99	#define LCDC_ENABLE 0x00000001
	100
	101	static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
	102	int reg_nr, unsigned long data)
	103	{
	104	iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
105	}
106
107	static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
108	int reg_nr)
109	{
110	return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
111	}
112
113	static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
114	unsigned long reg_offs, unsigned long data)
115	{
116	iowrite32(data, priv->base + reg_offs);
117	}
118
119	static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
120	unsigned long reg_offs)
121	{
122	return ioread32(priv->base + reg_offs);
123	}
124
125	static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
126	unsigned long reg_offs,
127	unsigned long mask, unsigned long until)
128	{
129	while ((lcdc_read(priv, reg_offs) & mask) != until)
130	cpu_relax();
131	}
132
133	static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
134	{
135	return chan->cfg.chan == LCDC_CHAN_SUBLCD;
136	}
137
138	static void lcdc_sys_write_index(void *handle, unsigned long data)
139	{
140	struct sh_mobile_lcdc_chan *ch = handle;
141
142	lcdc_write(ch->lcdc, _LDDWD0R, data \| 0x10000000);
143	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
144	lcdc_write(ch->lcdc, _LDDWAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
145	}
146
147	static void lcdc_sys_write_data(void *handle, unsigned long data)
148	{
149	struct sh_mobile_lcdc_chan *ch = handle;
150
151	lcdc_write(ch->lcdc, _LDDWD0R, data \| 0x11000000);
152	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
153	lcdc_write(ch->lcdc, _LDDWAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
154	}
155
156	static unsigned long lcdc_sys_read_data(void *handle)
157	{
158	struct sh_mobile_lcdc_chan *ch = handle;
159
160	lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
161	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
162	lcdc_write(ch->lcdc, _LDDRAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
163	udelay(1);
164
165	return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
166	}
167
168	struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
169	lcdc_sys_write_index,
170	lcdc_sys_write_data,
171	lcdc_sys_read_data,
172	};
173
174	static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
175	int start)
176	{
177	unsigned long tmp = lcdc_read(priv, _LDCNT2R);
178	int k;
179
180	/* start or stop the lcdc */
181	if (start)
182	lcdc_write(priv, _LDCNT2R, tmp \| START_LCDC);
183	else
184	lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
185
186	/* wait until power is applied/stopped on all channels */
187	for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
188	if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
189	while (1) {
190	tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
191	if (start && tmp == 3)
192	break;
193	if (!start && tmp == 0)
194	break;
195	cpu_relax();
196	}
197
198	if (!start)
199	lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
200	}
201
202	static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
203	{
204	struct sh_mobile_lcdc_chan *ch;
205	struct fb_videomode *lcd_cfg;
206	struct sh_mobile_lcdc_board_cfg *board_cfg;
207	unsigned long tmp;
208	int k, m;
209	int ret = 0;
210
b51339ff MD	211	#ifdef CONFIG_HAVE_CLK
	212	clk_enable(priv->clk);
	213	if (priv->dot_clk)
	214	clk_enable(priv->dot_clk);
	215	#endif
cfb4f5d1 MD	216	/* reset */
	217	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) \| LCDC_RESET);
	218	lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
	219
	220	/* enable LCDC channels */
	221	tmp = lcdc_read(priv, _LDCNT2R);
	222	tmp \|= priv->ch[0].enabled;
	223	tmp \|= priv->ch[1].enabled;
	224	lcdc_write(priv, _LDCNT2R, tmp);
	225
	226	/* read data from external memory, avoid using the BEU for now */
	227	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
	228
	229	/* stop the lcdc first */
	230	sh_mobile_lcdc_start_stop(priv, 0);
	231
	232	/* configure clocks */
	233	tmp = priv->lddckr;
	234	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
	235	ch = &priv->ch[k];
	236
	237	if (!priv->ch[k].enabled)
	238	continue;
	239
	240	m = ch->cfg.clock_divider;
	241	if (!m)
	242	continue;
	243
	244	if (m == 1)
	245	m = 1 << 6;
	246	tmp \|= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
	247
	248	lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
	249	lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
	250	}
	251
	252	lcdc_write(priv, _LDDCKR, tmp);
	253
	254	/* start dotclock again */
	255	lcdc_write(priv, _LDDCKSTPR, 0);
	256	lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
	257
	258	/* interrupts are disabled */
	259	lcdc_write(priv, _LDINTR, 0);
	260
	261	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
	262	ch = &priv->ch[k];
	263	lcd_cfg = &ch->cfg.lcd_cfg;
	264
	265	if (!ch->enabled)
	266	continue;
	267
	268	tmp = ch->ldmt1r_value;
	269	tmp \|= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
	270	tmp \|= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
f400f510 MD	271	tmp \|= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
	272	tmp \|= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
	273	tmp \|= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
	274	tmp \|= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
	275	tmp \|= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
cfb4f5d1 MD	276	lcdc_write_chan(ch, LDMT1R, tmp);
	277
	278	/* setup SYS bus */
	279	lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
	280	lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
	281
	282	/* horizontal configuration */
	283	tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
	284	tmp += lcd_cfg->left_margin;
	285	tmp += lcd_cfg->right_margin;
	286	tmp /= 8; /* HTCN */
	287	tmp \|= (lcd_cfg->xres / 8) << 16; /* HDCN */
	288	lcdc_write_chan(ch, LDHCNR, tmp);
	289
	290	tmp = lcd_cfg->xres;
	291	tmp += lcd_cfg->right_margin;
	292	tmp /= 8; /* HSYNP */
	293	tmp \|= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
	294	lcdc_write_chan(ch, LDHSYNR, tmp);
	295
	296	/* power supply */
	297	lcdc_write_chan(ch, LDPMR, 0);
	298
	299	/* vertical configuration */
	300	tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
	301	tmp += lcd_cfg->upper_margin;
	302	tmp += lcd_cfg->lower_margin; /* VTLN */
	303	tmp \|= lcd_cfg->yres << 16; /* VDLN */
	304	lcdc_write_chan(ch, LDVLNR, tmp);
	305
	306	tmp = lcd_cfg->yres;
	307	tmp += lcd_cfg->lower_margin; /* VSYNP */
	308	tmp \|= lcd_cfg->vsync_len << 16; /* VSYNW */
	309	lcdc_write_chan(ch, LDVSYNR, tmp);
	310
	311	board_cfg = &ch->cfg.board_cfg;
	312	if (board_cfg->setup_sys)
	313	ret = board_cfg->setup_sys(board_cfg->board_data, ch,
	314	&sh_mobile_lcdc_sys_bus_ops);
	315	if (ret)
	316	return ret;
	317	}
	318
	319	/* --- display_lcdc_data() --- */
	320	lcdc_write(priv, _LDINTR, 0x00000f00);
	321
	322	/* word and long word swap */
	323	lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) \| 6);
	324
	325	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
	326	ch = &priv->ch[k];
	327
	328	if (!priv->ch[k].enabled)
	329	continue;
	330
	331	/* set bpp format in PKF[4:0] */
	332	tmp = lcdc_read_chan(ch, LDDFR);
	333	tmp &= ~(0x0001001f);
	334	tmp \|= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
	335	lcdc_write_chan(ch, LDDFR, tmp);
	336
	337	/* point out our frame buffer */
	338	lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
	339
340	/* set line size */
341	lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
342
343	/* continuous read mode */
344	lcdc_write_chan(ch, LDSM1R, 0);
345	}
346
347	/* display output */
348	lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
349
350	/* start the lcdc */
351	sh_mobile_lcdc_start_stop(priv, 1);
352
353	/* tell the board code to enable the panel */
354	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
355	ch = &priv->ch[k];
356	board_cfg = &ch->cfg.board_cfg;
357	if (board_cfg->display_on)
358	board_cfg->display_on(board_cfg->board_data);
359	}
360
361	return 0;
362	}
363
364	static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
365	{
366	struct sh_mobile_lcdc_chan *ch;
367	struct sh_mobile_lcdc_board_cfg *board_cfg;
368	int k;
369
370	/* tell the board code to disable the panel */
371	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
372	ch = &priv->ch[k];
373	board_cfg = &ch->cfg.board_cfg;
374	if (board_cfg->display_off)
375	board_cfg->display_off(board_cfg->board_data);
376	}
377
378	/* stop the lcdc */
379	sh_mobile_lcdc_start_stop(priv, 0);
b51339ff MD	380
	381	#ifdef CONFIG_HAVE_CLK
	382	if (priv->dot_clk)
	383	clk_disable(priv->dot_clk);
	384	clk_disable(priv->clk);
	385	#endif
cfb4f5d1 MD	386	}
	387
	388	static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
	389	{
	390	int ifm, miftyp;
	391
	392	switch (ch->cfg.interface_type) {
	393	case RGB8: ifm = 0; miftyp = 0; break;
	394	case RGB9: ifm = 0; miftyp = 4; break;
	395	case RGB12A: ifm = 0; miftyp = 5; break;
	396	case RGB12B: ifm = 0; miftyp = 6; break;
	397	case RGB16: ifm = 0; miftyp = 7; break;
	398	case RGB18: ifm = 0; miftyp = 10; break;
	399	case RGB24: ifm = 0; miftyp = 11; break;
	400	case SYS8A: ifm = 1; miftyp = 0; break;
	401	case SYS8B: ifm = 1; miftyp = 1; break;
	402	case SYS8C: ifm = 1; miftyp = 2; break;
	403	case SYS8D: ifm = 1; miftyp = 3; break;
	404	case SYS9: ifm = 1; miftyp = 4; break;
	405	case SYS12: ifm = 1; miftyp = 5; break;
	406	case SYS16A: ifm = 1; miftyp = 7; break;
	407	case SYS16B: ifm = 1; miftyp = 8; break;
	408	case SYS16C: ifm = 1; miftyp = 9; break;
	409	case SYS18: ifm = 1; miftyp = 10; break;
	410	case SYS24: ifm = 1; miftyp = 11; break;
	411	default: goto bad;
	412	}
	413
	414	/* SUBLCD only supports SYS interface */
	415	if (lcdc_chan_is_sublcd(ch)) {
	416	if (ifm == 0)
	417	goto bad;
	418	else
	419	ifm = 0;
	420	}
	421
	422	ch->ldmt1r_value = (ifm << 12) \| miftyp;
	423	return 0;
	424	bad:
	425	return -EINVAL;
	426	}
	427
b51339ff MD	428	static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
b51339ff MD	429	int clock_source,
cfb4f5d1 MD	430	struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 MD	431	{
b51339ff MD	432	#ifdef CONFIG_HAVE_CLK
	433	char clk_name[8];
	434	#endif
cfb4f5d1 MD	435	char *str;
	436	int icksel;
	437
	438	switch (clock_source) {
	439	case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
	440	case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
	441	case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
	442	default:
	443	return -EINVAL;
	444	}
	445
	446	priv->lddckr = icksel << 16;
	447
225c9a8d	448	#ifdef CONFIG_HAVE_CLK
b51339ff MD	449	snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
	450	priv->clk = clk_get(&pdev->dev, clk_name);
	451	if (IS_ERR(priv->clk)) {
	452	dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
	453	return PTR_ERR(priv->clk);
	454	}
	455
cfb4f5d1	456	if (str) {
b51339ff MD	457	priv->dot_clk = clk_get(&pdev->dev, str);
	458	if (IS_ERR(priv->dot_clk)) {
	459	dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
	460	clk_put(priv->clk);
	461	return PTR_ERR(priv->dot_clk);
cfb4f5d1	462	}
cfb4f5d1	463	}
225c9a8d	464	#endif
cfb4f5d1 MD	465
	466	return 0;
	467	}
	468
	469	static int sh_mobile_lcdc_setcolreg(u_int regno,
	470	u_int red, u_int green, u_int blue,
	471	u_int transp, struct fb_info *info)
	472	{
	473	u32 *palette = info->pseudo_palette;
	474
	475	if (regno >= PALETTE_NR)
	476	return -EINVAL;
	477
	478	/* only FB_VISUAL_TRUECOLOR supported */
	479
	480	red >>= 16 - info->var.red.length;
	481	green >>= 16 - info->var.green.length;
	482	blue >>= 16 - info->var.blue.length;
	483	transp >>= 16 - info->var.transp.length;
	484
	485	palette[regno] = (red << info->var.red.offset) \|
	486	(green << info->var.green.offset) \|
	487	(blue << info->var.blue.offset) \|
	488	(transp << info->var.transp.offset);
	489
	490	return 0;
	491	}
	492
	493	static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
	494	.id = "SH Mobile LCDC",
	495	.type = FB_TYPE_PACKED_PIXELS,
	496	.visual = FB_VISUAL_TRUECOLOR,
	497	.accel = FB_ACCEL_NONE,
	498	};
	499
	500	static struct fb_ops sh_mobile_lcdc_ops = {
	501	.fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111 MD	502	.fb_read = fb_sys_read,
	503	.fb_write = fb_sys_write,
	504	.fb_fillrect = sys_fillrect,
	505	.fb_copyarea = sys_copyarea,
	506	.fb_imageblit = sys_imageblit,
cfb4f5d1 MD	507	};
	508
	509	static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
	510	{
	511	switch (bpp) {
	512	case 16: /* PKF[4:0] = 00011 - RGB 565 */
	513	var->red.offset = 11;
	514	var->red.length = 5;
	515	var->green.offset = 5;
	516	var->green.length = 6;
	517	var->blue.offset = 0;
	518	var->blue.length = 5;
	519	var->transp.offset = 0;
	520	var->transp.length = 0;
	521	break;
	522
	523	case 32: /* PKF[4:0] = 00000 - RGB 888
	524	* sh7722 pdf says 00RRGGBB but reality is GGBB00RR
	525	* this may be because LDDDSR has word swap enabled..
	526	*/
	527	var->red.offset = 0;
	528	var->red.length = 8;
	529	var->green.offset = 24;
	530	var->green.length = 8;
	531	var->blue.offset = 16;
	532	var->blue.length = 8;
	533	var->transp.offset = 0;
	534	var->transp.length = 0;
	535	break;
	536	default:
	537	return -EINVAL;
	538	}
	539	var->bits_per_pixel = bpp;
	540	var->red.msb_right = 0;
	541	var->green.msb_right = 0;
	542	var->blue.msb_right = 0;
	543	var->transp.msb_right = 0;
	544	return 0;
	545	}
	546
	547	static int sh_mobile_lcdc_remove(struct platform_device *pdev);
	548
	549	static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
	550	{
	551	struct fb_info *info;
	552	struct sh_mobile_lcdc_priv *priv;
	553	struct sh_mobile_lcdc_info *pdata;
	554	struct sh_mobile_lcdc_chan_cfg *cfg;
	555	struct resource *res;
	556	int error;
	557	void *buf;
	558	int i, j;
	559
	560	if (!pdev->dev.platform_data) {
	561	dev_err(&pdev->dev, "no platform data defined\n");
	562	error = -EINVAL;
	563	goto err0;
	564	}
	565
	566	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	567	if (res == NULL) {
	568	dev_err(&pdev->dev, "cannot find IO resource\n");
	569	error = -ENOENT;
	570	goto err0;
571	}
572
573	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
574	if (!priv) {
575	dev_err(&pdev->dev, "cannot allocate device data\n");
576	error = -ENOMEM;
577	goto err0;
578	}
579
580	platform_set_drvdata(pdev, priv);
581	pdata = pdev->dev.platform_data;
582
583	j = 0;
584	for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
585	priv->ch[j].lcdc = priv;
586	memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
587
588	error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
589	if (error) {
590	dev_err(&pdev->dev, "unsupported interface type\n");
591	goto err1;
592	}
593
594	switch (pdata->ch[i].chan) {
595	case LCDC_CHAN_MAINLCD:
596	priv->ch[j].enabled = 1 << 1;
597	priv->ch[j].reg_offs = lcdc_offs_mainlcd;
598	j++;
599	break;
600	case LCDC_CHAN_SUBLCD:
601	priv->ch[j].enabled = 1 << 2;
602	priv->ch[j].reg_offs = lcdc_offs_sublcd;
603	j++;
604	break;
605	}
606	}
607
608	if (!j) {
609	dev_err(&pdev->dev, "no channels defined\n");
610	error = -EINVAL;
611	goto err1;
612	}
613
b51339ff	614	error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1 MD	615	if (error) {
	616	dev_err(&pdev->dev, "unable to setup clocks\n");
	617	goto err1;
	618	}
	619
cfb4f5d1 MD	620	priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
	621
	622	for (i = 0; i < j; i++) {
	623	info = &priv->ch[i].info;
	624	cfg = &priv->ch[i].cfg;
	625
	626	info->fbops = &sh_mobile_lcdc_ops;
	627	info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
	628	info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
ce9c008c MD	629	info->var.width = cfg->lcd_size_cfg.width;
ce9c008c MD	630	info->var.height = cfg->lcd_size_cfg.height;
cfb4f5d1 MD	631	info->var.activate = FB_ACTIVATE_NOW;
	632	error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
	633	if (error)
	634	break;
	635
	636	info->fix = sh_mobile_lcdc_fix;
	637	info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
	638	info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
	639
	640	buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
	641	&priv->ch[i].dma_handle, GFP_KERNEL);
	642	if (!buf) {
	643	dev_err(&pdev->dev, "unable to allocate buffer\n");
	644	error = -ENOMEM;
	645	break;
	646	}
	647
	648	info->pseudo_palette = &priv->ch[i].pseudo_palette;
	649	info->flags = FBINFO_FLAG_DEFAULT;
	650
	651	error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
	652	if (error < 0) {
	653	dev_err(&pdev->dev, "unable to allocate cmap\n");
	654	dma_free_coherent(&pdev->dev, info->fix.smem_len,
	655	buf, priv->ch[i].dma_handle);
	656	break;
	657	}
	658
	659	memset(buf, 0, info->fix.smem_len);
	660	info->fix.smem_start = priv->ch[i].dma_handle;
	661	info->screen_base = buf;
	662	info->device = &pdev->dev;
	663	}
	664
	665	if (error)
	666	goto err1;
	667
	668	error = sh_mobile_lcdc_start(priv);
	669	if (error) {
	670	dev_err(&pdev->dev, "unable to start hardware\n");
	671	goto err1;
	672	}
	673
	674	for (i = 0; i < j; i++) {
	675	error = register_framebuffer(&priv->ch[i].info);
	676	if (error < 0)
	677	goto err1;
	678	}
	679
	680	for (i = 0; i < j; i++) {
	681	info = &priv->ch[i].info;
	682	dev_info(info->dev,
	683	"registered %s/%s as %dx%d %dbpp.\n",
	684	pdev->name,
	685	(priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
	686	"mainlcd" : "sublcd",
	687	(int) priv->ch[i].cfg.lcd_cfg.xres,
	688	(int) priv->ch[i].cfg.lcd_cfg.yres,
	689	priv->ch[i].cfg.bpp);
	690	}
	691
	692	return 0;
	693	err1:
	694	sh_mobile_lcdc_remove(pdev);
695	err0:
696	return error;
697	}
698
699	static int sh_mobile_lcdc_remove(struct platform_device *pdev)
700	{
701	struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
702	struct fb_info *info;
703	int i;
704
705	for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
706	if (priv->ch[i].info.dev)
707	unregister_framebuffer(&priv->ch[i].info);
708
709	sh_mobile_lcdc_stop(priv);
710
711	for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
712	info = &priv->ch[i].info;
713
714	if (!info->device)
715	continue;
716
717	dma_free_coherent(&pdev->dev, info->fix.smem_len,
718	info->screen_base, priv->ch[i].dma_handle);
719	fb_dealloc_cmap(&info->cmap);
720	}
721
225c9a8d	722	#ifdef CONFIG_HAVE_CLK
b51339ff MD	723	if (priv->dot_clk)
	724	clk_put(priv->dot_clk);
	725	clk_put(priv->clk);
225c9a8d	726	#endif
cfb4f5d1 MD	727
	728	if (priv->base)
	729	iounmap(priv->base);
	730
	731	kfree(priv);
	732	return 0;
	733	}
	734
	735	static struct platform_driver sh_mobile_lcdc_driver = {
	736	.driver = {
	737	.name = "sh_mobile_lcdc_fb",
	738	.owner = THIS_MODULE,
	739	},
	740	.probe = sh_mobile_lcdc_probe,
	741	.remove = sh_mobile_lcdc_remove,
	742	};
	743
	744	static int __init sh_mobile_lcdc_init(void)
	745	{
	746	return platform_driver_register(&sh_mobile_lcdc_driver);
	747	}
	748
	749	static void __exit sh_mobile_lcdc_exit(void)
	750	{
	751	platform_driver_unregister(&sh_mobile_lcdc_driver);
	752	}
	753
	754	module_init(sh_mobile_lcdc_init);
	755	module_exit(sh_mobile_lcdc_exit);
	756
	757	MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
	758	MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
	759	MODULE_LICENSE("GPL v2");