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fbdev: sh_mobile_lcdc: Move pm runtime enable to probe()
[mirror_ubuntu-hirsute-kernel.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
cfb4f5d1 15#include <linux/dma-mapping.h>
f1f60b5f
LP		 16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
8564557a 19#include <linux/interrupt.h>
40331b21 20#include <linux/ioctl.h>
f1f60b5f
LP		 21#include <linux/kernel.h>
22#include <linux/mm.h>
355b200b 23#include <linux/module.h>
f1f60b5f
LP		 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/videodev2.h>
28#include <linux/vmalloc.h>
29
225c9a8d 30#include <video/sh_mobile_lcdc.h>
8a20974f 31#include <video/sh_mobile_meram.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
a6f15ade
PE		 35#define SIDE_B_OFFSET 0x1000
36#define MIRROR_OFFSET 0x2000
cfb4f5d1 37
d2ecbab5
GL		 38#define MAX_XRES 1920
39#define MAX_YRES 1080
cfb4f5d1 40
f1f60b5f
LP		 41struct sh_mobile_lcdc_priv {
42 void __iomem *base;
43 int irq;
44 atomic_t hw_usecnt;
45 struct device *dev;
46 struct clk *dot_clk;
47 unsigned long lddckr;
48 struct sh_mobile_lcdc_chan ch[2];
49 struct notifier_block notifier;
50 int started;
51 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
52 struct sh_mobile_meram_info *meram_dev;
53};
54
55/* -----------------------------------------------------------------------------
56 * Registers access
57 */
58
0246c471 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 60 [LDDCKPAT1R] = 0x400,
61 [LDDCKPAT2R] = 0x404,
62 [LDMT1R] = 0x418,
63 [LDMT2R] = 0x41c,
64 [LDMT3R] = 0x420,
65 [LDDFR] = 0x424,
66 [LDSM1R] = 0x428,
8564557a 67 [LDSM2R] = 0x42c,
cfb4f5d1 68 [LDSA1R] = 0x430,
53b50314 69 [LDSA2R] = 0x434,
cfb4f5d1
MD		 70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
6011bdea 76 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 77};
78
0246c471 79static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 80 [LDDCKPAT1R] = 0x408,
81 [LDDCKPAT2R] = 0x40c,
82 [LDMT1R] = 0x600,
83 [LDMT2R] = 0x604,
84 [LDMT3R] = 0x608,
85 [LDDFR] = 0x60c,
86 [LDSM1R] = 0x610,
8564557a 87 [LDSM2R] = 0x614,
cfb4f5d1
MD		 88 [LDSA1R] = 0x618,
89 [LDMLSR] = 0x620,
90 [LDHCNR] = 0x624,
91 [LDHSYNR] = 0x628,
92 [LDVLNR] = 0x62c,
93 [LDVSYNR] = 0x630,
94 [LDPMR] = 0x63c,
95};
96
a6f15ade
PE		 97static bool banked(int reg_nr)
98{
99 switch (reg_nr) {
100 case LDMT1R:
101 case LDMT2R:
102 case LDMT3R:
103 case LDDFR:
104 case LDSM1R:
105 case LDSA1R:
53b50314 106 case LDSA2R:
a6f15ade
PE		 107 case LDMLSR:
108 case LDHCNR:
109 case LDHSYNR:
110 case LDVLNR:
111 case LDVSYNR:
112 return true;
113 }
114 return false;
115}
116
f1f60b5f
LP		 117static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
118{
119 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
120}
121
cfb4f5d1
MD		 122static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
123 int reg_nr, unsigned long data)
124{
125 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 126 if (banked(reg_nr))
127 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
128 SIDE_B_OFFSET);
129}
130
131static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
132 int reg_nr, unsigned long data)
133{
134 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
135 MIRROR_OFFSET);
cfb4f5d1
MD		 136}
137
138static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
139 int reg_nr)
140{
141 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
142}
143
144static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
145 unsigned long reg_offs, unsigned long data)
146{
147 iowrite32(data, priv->base + reg_offs);
148}
149
150static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
151 unsigned long reg_offs)
152{
153 return ioread32(priv->base + reg_offs);
154}
155
156static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
157 unsigned long reg_offs,
158 unsigned long mask, unsigned long until)
159{
160 while ((lcdc_read(priv, reg_offs) & mask) != until)
161 cpu_relax();
162}
163
f1f60b5f
LP		 164/* -----------------------------------------------------------------------------
165 * Clock management
166 */
167
168static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 169{
f1f60b5f
LP		 170 if (atomic_inc_and_test(&priv->hw_usecnt)) {
171 if (priv->dot_clk)
172 clk_enable(priv->dot_clk);
173 pm_runtime_get_sync(priv->dev);
174 if (priv->meram_dev && priv->meram_dev->pdev)
175 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
176 }
cfb4f5d1
MD		 177}
178
f1f60b5f
LP		 179static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
180{
181 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
182 if (priv->meram_dev && priv->meram_dev->pdev)
183 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
184 pm_runtime_put(priv->dev);
185 if (priv->dot_clk)
186 clk_disable(priv->dot_clk);
187 }
188}
189
190static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
191 int clock_source,
192 struct sh_mobile_lcdc_priv *priv)
193{
4774c12a 194 struct clk *clk;
f1f60b5f
LP		 195 char *str;
196
197 switch (clock_source) {
198 case LCDC_CLK_BUS:
199 str = "bus_clk";
200 priv->lddckr = LDDCKR_ICKSEL_BUS;
201 break;
202 case LCDC_CLK_PERIPHERAL:
203 str = "peripheral_clk";
204 priv->lddckr = LDDCKR_ICKSEL_MIPI;
205 break;
206 case LCDC_CLK_EXTERNAL:
207 str = NULL;
208 priv->lddckr = LDDCKR_ICKSEL_HDMI;
209 break;
210 default:
211 return -EINVAL;
212 }
213
4774c12a
LP		 214 if (str == NULL)
215 return 0;
216
217 clk = clk_get(&pdev->dev, str);
218 if (IS_ERR(clk)) {
219 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
220 return PTR_ERR(clk);
f1f60b5f
LP		 221 }
222
4774c12a 223 priv->dot_clk = clk;
f1f60b5f
LP		 224 return 0;
225}
226
227/* -----------------------------------------------------------------------------
228 * Sys panel and deferred I/O
229 */
230
cfb4f5d1
MD		 231static void lcdc_sys_write_index(void *handle, unsigned long data)
232{
233 struct sh_mobile_lcdc_chan *ch = handle;
234
ce1c0b08
LP		 235 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
236 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
237 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
238 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
239 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 240}
241
242static void lcdc_sys_write_data(void *handle, unsigned long data)
243{
244 struct sh_mobile_lcdc_chan *ch = handle;
245
ce1c0b08
LP		 246 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
247 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
248 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
249 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
250 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 251}
252
253static unsigned long lcdc_sys_read_data(void *handle)
254{
255 struct sh_mobile_lcdc_chan *ch = handle;
256
ce1c0b08
LP		 257 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
258 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
259 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
260 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 261 udelay(1);
ce1c0b08 262 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 263
ce1c0b08 264 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 265}
266
267struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
268 lcdc_sys_write_index,
269 lcdc_sys_write_data,
270 lcdc_sys_read_data,
271};
272
1c6a307a
PM		 273static int sh_mobile_lcdc_sginit(struct fb_info *info,
274 struct list_head *pagelist)
275{
276 struct sh_mobile_lcdc_chan *ch = info->par;
277 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
278 struct page *page;
279 int nr_pages = 0;
280
281 sg_init_table(ch->sglist, nr_pages_max);
282
283 list_for_each_entry(page, pagelist, lru)
284 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
285
286 return nr_pages;
287}
288
8564557a
MD		 289static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
290 struct list_head *pagelist)
291{
292 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 293 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 294
295 /* enable clocks before accessing hardware */
296 sh_mobile_lcdc_clk_on(ch->lcdc);
297
5c1a56b5
PM		 298 /*
299 * It's possible to get here without anything on the pagelist via
300 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
301 * invocation. In the former case, the acceleration routines are
302 * stepped in to when using the framebuffer console causing the
303 * workqueue to be scheduled without any dirty pages on the list.
304 *
305 * Despite this, a panel update is still needed given that the
306 * acceleration routines have their own methods for writing in
307 * that still need to be updated.
308 *
309 * The fsync() and empty pagelist case could be optimized for,
310 * but we don't bother, as any application exhibiting such
311 * behaviour is fundamentally broken anyways.
312 */
313 if (!list_empty(pagelist)) {
314 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
315
316 /* trigger panel update */
317 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 318 if (bcfg->start_transfer)
319 bcfg->start_transfer(bcfg->board_data, ch,
320 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 321 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
5c1a56b5 322 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 323 } else {
324 if (bcfg->start_transfer)
325 bcfg->start_transfer(bcfg->board_data, ch,
326 &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 327 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 328 }
8564557a
MD		 329}
330
331static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
332{
333 struct fb_deferred_io *fbdefio = info->fbdefio;
334
335 if (fbdefio)
336 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
337}
338
f1f60b5f
LP		 339/* -----------------------------------------------------------------------------
340 * Format helpers
341 */
342
343static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
344{
345 if (var->grayscale > 1)
346 return var->grayscale;
347
348 switch (var->bits_per_pixel) {
349 case 16:
350 return V4L2_PIX_FMT_RGB565;
351 case 24:
352 return V4L2_PIX_FMT_BGR24;
353 case 32:
354 return V4L2_PIX_FMT_BGR32;
355 default:
356 return 0;
357 }
358}
359
360static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
361{
362 return var->grayscale > 1;
363}
364
365static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var)
366{
367 if (var->grayscale <= 1)
368 return false;
369
370 switch (var->grayscale) {
371 case V4L2_PIX_FMT_NV12:
372 case V4L2_PIX_FMT_NV21:
373 case V4L2_PIX_FMT_NV16:
374 case V4L2_PIX_FMT_NV61:
375 case V4L2_PIX_FMT_NV24:
376 case V4L2_PIX_FMT_NV42:
377 return true;
378
379 default:
380 return false;
381 }
382}
383
384/* -----------------------------------------------------------------------------
385 * Start, stop and IRQ
386 */
387
8564557a
MD		 388static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
389{
390 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 391 struct sh_mobile_lcdc_chan *ch;
9dd38819 392 unsigned long ldintr;
2feb075a
MD		 393 int is_sub;
394 int k;
8564557a 395
dc48665f
LP		 396 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
397 ldintr = lcdc_read(priv, _LDINTR);
398 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 399
2feb075a 400 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 401 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 402
9dd38819 403 /* wake up channel and disable clocks */
2feb075a
MD		 404 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
405 ch = &priv->ch[k];
406
407 if (!ch->enabled)
408 continue;
409
dc48665f 410 /* Frame End */
9dd38819
PE		 411 if (ldintr & LDINTR_FS) {
412 if (is_sub == lcdc_chan_is_sublcd(ch)) {
413 ch->frame_end = 1;
414 wake_up(&ch->frame_end_wait);
2feb075a 415
9dd38819
PE		 416 sh_mobile_lcdc_clk_off(priv);
417 }
418 }
419
420 /* VSYNC End */
40331b21
PE		 421 if (ldintr & LDINTR_VES)
422 complete(&ch->vsync_completion);
2feb075a
MD		 423 }
424
8564557a
MD		 425 return IRQ_HANDLED;
426}
427
cfb4f5d1
MD		 428static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
429 int start)
430{
431 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
432 int k;
433
434 /* start or stop the lcdc */
435 if (start)
ce1c0b08 436 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 437 else
ce1c0b08 438 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 439
440 /* wait until power is applied/stopped on all channels */
441 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
442 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
443 while (1) {
ce1c0b08
LP		 444 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
445 & LDPMR_LPS;
446 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 447 break;
448 if (!start && tmp == 0)
449 break;
450 cpu_relax();
451 }
452
453 if (!start)
454 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
455}
456
6011bdea
GL		 457static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
458{
1c120deb
GL		 459 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
460 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 461 u32 tmp;
462
463 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 464 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
465 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
466 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
467 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
468 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
469 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
470 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 471 lcdc_write_chan(ch, LDMT1R, tmp);
472
473 /* setup SYS bus */
474 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
475 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
476
477 /* horizontal configuration */
1c120deb
GL		 478 h_total = display_var->xres + display_var->hsync_len +
479 display_var->left_margin + display_var->right_margin;
6011bdea 480 tmp = h_total / 8; /* HTCN */
1c120deb 481 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 482 lcdc_write_chan(ch, LDHCNR, tmp);
483
1c120deb 484 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 485 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 486 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 487 lcdc_write_chan(ch, LDHSYNR, tmp);
488
489 /* vertical configuration */
1c120deb
GL		 490 tmp = display_var->yres + display_var->vsync_len +
491 display_var->upper_margin + display_var->lower_margin; /* VTLN */
492 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 493 lcdc_write_chan(ch, LDVLNR, tmp);
494
1c120deb
GL		 495 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
496 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 497 lcdc_write_chan(ch, LDVSYNR, tmp);
498
499 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 500 display_h_total = display_var->xres + display_var->hsync_len +
501 display_var->left_margin + display_var->right_margin;
502 tmp = ((display_var->xres & 7) << 24) |
503 ((display_h_total & 7) << 16) |
504 ((display_var->hsync_len & 7) << 8) |
41e583c2 505 (hsync_pos & 7);
6011bdea
GL		 506 lcdc_write_chan(ch, LDHAJR, tmp);
507}
508
9a217e34
LP		 509/*
510 * __sh_mobile_lcdc_start - Configure and tart the LCDC
511 * @priv: LCDC device
512 *
513 * Configure all enabled channels and start the LCDC device. All external
514 * devices (clocks, MERAM, panels, ...) are not touched by this function.
515 */
516static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 517{
518 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 519 unsigned long tmp;
9a217e34 520 int k, m;
8564557a 521
9a217e34
LP		 522 /* Enable LCDC channels. Read data from external memory, avoid using the
523 * BEU for now.
524 */
525 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 526
9a217e34 527 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 528 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 529 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 530
9a217e34 531 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 532 tmp = priv->lddckr;
533 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
534 ch = &priv->ch[k];
9a217e34 535 if (!ch->enabled)
cfb4f5d1
MD		 536 continue;
537
9a217e34
LP		 538 /* Power supply */
539 lcdc_write_chan(ch, LDPMR, 0);
540
cfb4f5d1
MD		 541 m = ch->cfg.clock_divider;
542 if (!m)
543 continue;
544
505c7de5
LP		 545 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
546 * denominator.
547 */
548 lcdc_write_chan(ch, LDDCKPAT1R, 0);
549 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
550
cfb4f5d1 551 if (m == 1)
ce1c0b08 552 m = LDDCKR_MOSEL;
cfb4f5d1 553 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 554 }
555
556 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 557 lcdc_write(priv, _LDDCKSTPR, 0);
558 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
559
9a217e34 560 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 561 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
562 ch = &priv->ch[k];
cfb4f5d1
MD		 563 if (!ch->enabled)
564 continue;
565
6011bdea 566 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 567
edd153a3
LP		 568 switch (sh_mobile_format_fourcc(&ch->info->var)) {
569 case V4L2_PIX_FMT_RGB565:
570 tmp = LDDFR_PKF_RGB16;
571 break;
572 case V4L2_PIX_FMT_BGR24:
573 tmp = LDDFR_PKF_RGB24;
574 break;
575 case V4L2_PIX_FMT_BGR32:
576 tmp = LDDFR_PKF_ARGB32;
577 break;
578 case V4L2_PIX_FMT_NV12:
579 case V4L2_PIX_FMT_NV21:
580 tmp = LDDFR_CC | LDDFR_YF_420;
581 break;
582 case V4L2_PIX_FMT_NV16:
583 case V4L2_PIX_FMT_NV61:
584 tmp = LDDFR_CC | LDDFR_YF_422;
585 break;
586 case V4L2_PIX_FMT_NV24:
587 case V4L2_PIX_FMT_NV42:
588 tmp = LDDFR_CC | LDDFR_YF_444;
589 break;
590 }
591
592 if (sh_mobile_format_is_yuv(&ch->info->var)) {
593 switch (ch->info->var.colorspace) {
594 case V4L2_COLORSPACE_REC709:
595 tmp |= LDDFR_CF1;
53b50314 596 break;
edd153a3
LP		 597 case V4L2_COLORSPACE_JPEG:
598 tmp |= LDDFR_CF0;
53b50314
DHG		 599 break;
600 }
417d4827 601 }
7caa4342 602
9a217e34
LP		 603 lcdc_write_chan(ch, LDDFR, tmp);
604 lcdc_write_chan(ch, LDMLSR, ch->pitch);
605 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
edd153a3 606 if (sh_mobile_format_is_yuv(&ch->info->var))
9a217e34 607 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 608
9a217e34
LP		 609 /* When using deferred I/O mode, configure the LCDC for one-shot
610 * operation and enable the frame end interrupt. Otherwise use
611 * continuous read mode.
612 */
613 if (ch->ldmt1r_value & LDMT1R_IFM &&
614 ch->cfg.sys_bus_cfg.deferred_io_msec) {
615 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
616 lcdc_write(priv, _LDINTR, LDINTR_FE);
617 } else {
618 lcdc_write_chan(ch, LDSM1R, 0);
619 }
620 }
7caa4342 621
9a217e34 622 /* Word and long word swap. */
edd153a3
LP		 623 switch (sh_mobile_format_fourcc(&priv->ch[0].info->var)) {
624 case V4L2_PIX_FMT_RGB565:
625 case V4L2_PIX_FMT_NV21:
626 case V4L2_PIX_FMT_NV61:
627 case V4L2_PIX_FMT_NV42:
628 tmp = LDDDSR_LS | LDDDSR_WS;
629 break;
630 case V4L2_PIX_FMT_BGR24:
631 case V4L2_PIX_FMT_NV12:
632 case V4L2_PIX_FMT_NV16:
633 case V4L2_PIX_FMT_NV24:
9a217e34 634 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 635 break;
636 case V4L2_PIX_FMT_BGR32:
637 default:
638 tmp = LDDDSR_LS;
639 break;
9a217e34
LP		 640 }
641 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 642
9a217e34
LP		 643 /* Enable the display output. */
644 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
645 sh_mobile_lcdc_start_stop(priv, 1);
646 priv->started = 1;
647}
cfb4f5d1 648
9a217e34
LP		 649static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
650{
651 struct sh_mobile_meram_info *mdev = priv->meram_dev;
652 struct sh_mobile_lcdc_board_cfg *board_cfg;
653 struct sh_mobile_lcdc_chan *ch;
654 unsigned long tmp;
655 int ret;
656 int k;
cfb4f5d1 657
9a217e34
LP		 658 /* enable clocks before accessing the hardware */
659 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
660 if (priv->ch[k].enabled)
661 sh_mobile_lcdc_clk_on(priv);
662 }
8564557a 663
9a217e34
LP		 664 /* reset */
665 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
666 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 667
9a217e34
LP		 668 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
669 ch = &priv->ch[k];
8564557a 670
9a217e34
LP		 671 if (!ch->enabled)
672 continue;
673
674 board_cfg = &ch->cfg.board_cfg;
675 if (board_cfg->setup_sys) {
676 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
677 &sh_mobile_lcdc_sys_bus_ops);
678 if (ret)
679 return ret;
8564557a 680 }
cfb4f5d1
MD		 681 }
682
9a217e34
LP		 683 /* Compute frame buffer base address and pitch for each channel. */
684 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
685 struct sh_mobile_meram_cfg *cfg;
686 int pixelformat;
cfb4f5d1 687
9a217e34
LP		 688 ch = &priv->ch[k];
689 if (!ch->enabled)
690 continue;
cfb4f5d1 691
9a217e34
LP		 692 ch->base_addr_y = ch->info->fix.smem_start;
693 ch->base_addr_c = ch->base_addr_y
694 + ch->info->var.xres
695 * ch->info->var.yres_virtual;
696 ch->pitch = ch->info->fix.line_length;
697
698 /* Enable MERAM if possible. */
699 cfg = ch->cfg.meram_cfg;
700 if (mdev == NULL || mdev->ops == NULL || cfg == NULL)
701 continue;
702
703 /* we need to de-init configured ICBs before we can
704 * re-initialize them.
705 */
706 if (ch->meram_enabled) {
707 mdev->ops->meram_unregister(mdev, cfg);
708 ch->meram_enabled = 0;
709 }
710
edd153a3
LP		 711 switch (sh_mobile_format_fourcc(&ch->info->var)) {
712 case V4L2_PIX_FMT_NV12:
713 case V4L2_PIX_FMT_NV21:
714 case V4L2_PIX_FMT_NV16:
715 case V4L2_PIX_FMT_NV61:
9a217e34 716 pixelformat = SH_MOBILE_MERAM_PF_NV;
edd153a3
LP		 717 break;
718 case V4L2_PIX_FMT_NV24:
719 case V4L2_PIX_FMT_NV42:
720 pixelformat = SH_MOBILE_MERAM_PF_NV24;
721 break;
722 case V4L2_PIX_FMT_RGB565:
723 case V4L2_PIX_FMT_BGR24:
724 case V4L2_PIX_FMT_BGR32:
725 default:
726 pixelformat = SH_MOBILE_MERAM_PF_RGB;
727 break;
728 }
9a217e34
LP		 729
730 ret = mdev->ops->meram_register(mdev, cfg, ch->pitch,
731 ch->info->var.yres, pixelformat,
732 ch->base_addr_y, ch->base_addr_c,
733 &ch->base_addr_y, &ch->base_addr_c,
734 &ch->pitch);
735 if (!ret)
736 ch->meram_enabled = 1;
737 }
738
739 /* Start the LCDC. */
740 __sh_mobile_lcdc_start(priv);
741
742 /* Setup deferred I/O, tell the board code to enable the panels, and
743 * turn backlight on.
744 */
cfb4f5d1
MD		 745 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
746 ch = &priv->ch[k];
21bc1f02
MD		 747 if (!ch->enabled)
748 continue;
749
9a217e34
LP		 750 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
751 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
752 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
753 ch->defio.delay = msecs_to_jiffies(tmp);
754 ch->info->fbdefio = &ch->defio;
755 fb_deferred_io_init(ch->info);
756 }
757
cfb4f5d1 758 board_cfg = &ch->cfg.board_cfg;
247f9938 759 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 760 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 761 module_put(board_cfg->owner);
762 }
3b0fd9d7
AC		 763
764 if (ch->bl) {
765 ch->bl->props.power = FB_BLANK_UNBLANK;
766 backlight_update_status(ch->bl);
767 }
cfb4f5d1
MD		 768 }
769
770 return 0;
771}
772
773static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
774{
775 struct sh_mobile_lcdc_chan *ch;
776 struct sh_mobile_lcdc_board_cfg *board_cfg;
777 int k;
778
2feb075a 779 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 780 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
781 ch = &priv->ch[k];
21bc1f02
MD		 782 if (!ch->enabled)
783 continue;
8564557a 784
2feb075a
MD		 785 /* deferred io mode:
786 * flush frame, and wait for frame end interrupt
787 * clean up deferred io and enable clock
788 */
5ef6b505 789 if (ch->info && ch->info->fbdefio) {
2feb075a 790 ch->frame_end = 0;
e33afddc 791 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 792 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 793 fb_deferred_io_cleanup(ch->info);
794 ch->info->fbdefio = NULL;
2feb075a 795 sh_mobile_lcdc_clk_on(priv);
8564557a 796 }
2feb075a 797
3b0fd9d7
AC		 798 if (ch->bl) {
799 ch->bl->props.power = FB_BLANK_POWERDOWN;
800 backlight_update_status(ch->bl);
801 }
802
2feb075a 803 board_cfg = &ch->cfg.board_cfg;
247f9938 804 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 805 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 806 module_put(board_cfg->owner);
807 }
7caa4342
DHG		 808
809 /* disable the meram */
810 if (ch->meram_enabled) {
811 struct sh_mobile_meram_cfg *cfg;
812 struct sh_mobile_meram_info *mdev;
813 cfg = ch->cfg.meram_cfg;
814 mdev = priv->meram_dev;
815 mdev->ops->meram_unregister(mdev, cfg);
816 ch->meram_enabled = 0;
817 }
818
cfb4f5d1
MD		 819 }
820
821 /* stop the lcdc */
8e9bb19e
MD		 822 if (priv->started) {
823 sh_mobile_lcdc_start_stop(priv, 0);
824 priv->started = 0;
825 }
b51339ff 826
8564557a
MD		 827 /* stop clocks */
828 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
829 if (priv->ch[k].enabled)
830 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 831}
832
f1f60b5f
LP		 833/* -----------------------------------------------------------------------------
834 * Frame buffer operations
835 */
cfb4f5d1
MD		 836
837static int sh_mobile_lcdc_setcolreg(u_int regno,
838 u_int red, u_int green, u_int blue,
839 u_int transp, struct fb_info *info)
840{
841 u32 *palette = info->pseudo_palette;
842
843 if (regno >= PALETTE_NR)
844 return -EINVAL;
845
846 /* only FB_VISUAL_TRUECOLOR supported */
847
848 red >>= 16 - info->var.red.length;
849 green >>= 16 - info->var.green.length;
850 blue >>= 16 - info->var.blue.length;
851 transp >>= 16 - info->var.transp.length;
852
853 palette[regno] = (red << info->var.red.offset) |
854 (green << info->var.green.offset) |
855 (blue << info->var.blue.offset) |
856 (transp << info->var.transp.offset);
857
858 return 0;
859}
860
861static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
862 .id = "SH Mobile LCDC",
863 .type = FB_TYPE_PACKED_PIXELS,
864 .visual = FB_VISUAL_TRUECOLOR,
865 .accel = FB_ACCEL_NONE,
9dd38819
PE		 866 .xpanstep = 0,
867 .ypanstep = 1,
868 .ywrapstep = 0,
edd153a3 869 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 870};
871
8564557a
MD		 872static void sh_mobile_lcdc_fillrect(struct fb_info *info,
873 const struct fb_fillrect *rect)
874{
875 sys_fillrect(info, rect);
876 sh_mobile_lcdc_deferred_io_touch(info);
877}
878
879static void sh_mobile_lcdc_copyarea(struct fb_info *info,
880 const struct fb_copyarea *area)
881{
882 sys_copyarea(info, area);
883 sh_mobile_lcdc_deferred_io_touch(info);
884}
885
886static void sh_mobile_lcdc_imageblit(struct fb_info *info,
887 const struct fb_image *image)
888{
889 sys_imageblit(info, image);
890 sh_mobile_lcdc_deferred_io_touch(info);
891}
892
9dd38819
PE		 893static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
894 struct fb_info *info)
895{
896 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 897 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
898 unsigned long ldrcntr;
899 unsigned long new_pan_offset;
53b50314
DHG		 900 unsigned long base_addr_y, base_addr_c;
901 unsigned long c_offset;
edd153a3 902 bool yuv = sh_mobile_format_is_yuv(&info->var);
92e1f9a7 903
edd153a3 904 if (!yuv)
dc1d5ada
LP		 905 new_pan_offset = var->yoffset * info->fix.line_length
906 + var->xoffset * (info->var.bits_per_pixel / 8);
53b50314 907 else
dc1d5ada
LP		 908 new_pan_offset = var->yoffset * info->fix.line_length
909 + var->xoffset;
9dd38819 910
92e1f9a7 911 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 912 return 0; /* No change, do nothing */
913
92e1f9a7 914 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 915
92e1f9a7 916 /* Set the source address for the next refresh */
53b50314 917 base_addr_y = ch->dma_handle + new_pan_offset;
edd153a3 918 if (yuv) {
53b50314 919 /* Set y offset */
dc1d5ada
LP		 920 c_offset = var->yoffset * info->fix.line_length
921 * (info->var.bits_per_pixel - 8) / 8;
922 base_addr_c = ch->dma_handle
923 + info->var.xres * info->var.yres_virtual
924 + c_offset;
53b50314 925 /* Set x offset */
edd153a3 926 if (sh_mobile_format_fourcc(&info->var) == V4L2_PIX_FMT_NV24)
53b50314
DHG		 927 base_addr_c += 2 * var->xoffset;
928 else
929 base_addr_c += var->xoffset;
49d79ba2 930 }
53b50314 931
49d79ba2 932 if (ch->meram_enabled) {
7caa4342
DHG		 933 struct sh_mobile_meram_cfg *cfg;
934 struct sh_mobile_meram_info *mdev;
7caa4342
DHG		 935 int ret;
936
937 cfg = ch->cfg.meram_cfg;
938 mdev = priv->meram_dev;
939 ret = mdev->ops->meram_update(mdev, cfg,
940 base_addr_y, base_addr_c,
49d79ba2 941 &base_addr_y, &base_addr_c);
7caa4342
DHG		 942 if (ret)
943 return ret;
49d79ba2 944 }
7caa4342 945
49d79ba2
LP		 946 ch->base_addr_y = base_addr_y;
947 ch->base_addr_c = base_addr_c;
7caa4342 948
49d79ba2 949 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
edd153a3 950 if (yuv)
49d79ba2 951 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 952
92e1f9a7
PE		 953 if (lcdc_chan_is_sublcd(ch))
954 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
955 else
956 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
957
958 ch->pan_offset = new_pan_offset;
959
960 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 961
962 return 0;
963}
964
40331b21
PE		 965static int sh_mobile_wait_for_vsync(struct fb_info *info)
966{
967 struct sh_mobile_lcdc_chan *ch = info->par;
968 unsigned long ldintr;
969 int ret;
970
dc48665f
LP		 971 /* Enable VSync End interrupt and be careful not to acknowledge any
972 * pending interrupt.
973 */
40331b21 974 ldintr = lcdc_read(ch->lcdc, _LDINTR);
dc48665f 975 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
40331b21
PE		 976 lcdc_write(ch->lcdc, _LDINTR, ldintr);
977
978 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
979 msecs_to_jiffies(100));
980 if (!ret)
981 return -ETIMEDOUT;
982
983 return 0;
984}
985
986static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
987 unsigned long arg)
988{
989 int retval;
990
991 switch (cmd) {
992 case FBIO_WAITFORVSYNC:
993 retval = sh_mobile_wait_for_vsync(info);
994 break;
995
996 default:
997 retval = -ENOIOCTLCMD;
998 break;
999 }
1000 return retval;
1001}
1002
dd210503
GL		 1003static void sh_mobile_fb_reconfig(struct fb_info *info)
1004{
1005 struct sh_mobile_lcdc_chan *ch = info->par;
1006 struct fb_videomode mode1, mode2;
1007 struct fb_event event;
1008 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1009
1010 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1011 /* More framebuffer users are active */
1012 return;
1013
1014 fb_var_to_videomode(&mode1, &ch->display_var);
1015 fb_var_to_videomode(&mode2, &info->var);
1016
1017 if (fb_mode_is_equal(&mode1, &mode2))
1018 return;
1019
1020 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1021 if (fb_set_var(info, &ch->display_var) < 0)
1022 /* Couldn't reconfigure, hopefully, can continue as before */
1023 return;
1024
dd210503
GL		 1025 /*
1026 * fb_set_var() calls the notifier change internally, only if
1027 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1028 * user event, we have to call the chain ourselves.
1029 */
1030 event.info = info;
cc267ec5 1031 event.data = &mode1;
dd210503
GL		 1032 fb_notifier_call_chain(evnt, &event);
1033}
1034
1035/*
1036 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1037 * user == 1, or with console sem held, if user == 0.
1038 */
1039static int sh_mobile_release(struct fb_info *info, int user)
1040{
1041 struct sh_mobile_lcdc_chan *ch = info->par;
1042
1043 mutex_lock(&ch->open_lock);
1044 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1045
1046 ch->use_count--;
1047
1048 /* Nothing to reconfigure, when called from fbcon */
1049 if (user) {
ac751efa 1050 console_lock();
dd210503 1051 sh_mobile_fb_reconfig(info);
ac751efa 1052 console_unlock();
dd210503
GL		 1053 }
1054
1055 mutex_unlock(&ch->open_lock);
1056
1057 return 0;
1058}
1059
1060static int sh_mobile_open(struct fb_info *info, int user)
1061{
1062 struct sh_mobile_lcdc_chan *ch = info->par;
1063
1064 mutex_lock(&ch->open_lock);
1065 ch->use_count++;
1066
1067 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1068 mutex_unlock(&ch->open_lock);
1069
1070 return 0;
1071}
1072
1073static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1074{
1075 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1076 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1077 unsigned int best_dist = (unsigned int)-1;
1078 unsigned int best_xres = 0;
1079 unsigned int best_yres = 0;
1080 unsigned int i;
dd210503 1081
03862194 1082 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
dd210503 1083 return -EINVAL;
03862194
LP		 1084
1085 /* If board code provides us with a list of available modes, make sure
1086 * we use one of them. Find the mode closest to the requested one. The
1087 * distance between two modes is defined as the size of the
1088 * non-overlapping parts of the two rectangles.
1089 */
1090 for (i = 0; i < ch->cfg.num_cfg; ++i) {
1091 const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i];
1092 unsigned int dist;
1093
1094 /* We can only round up. */
1095 if (var->xres > mode->xres || var->yres > mode->yres)
1096 continue;
1097
1098 dist = var->xres * var->yres + mode->xres * mode->yres
1099 - 2 * min(var->xres, mode->xres)
1100 * min(var->yres, mode->yres);
1101
1102 if (dist < best_dist) {
1103 best_xres = mode->xres;
1104 best_yres = mode->yres;
1105 best_dist = dist;
1106 }
dd210503 1107 }
417d4827 1108
03862194
LP		 1109 /* If no available mode can be used, return an error. */
1110 if (ch->cfg.num_cfg != 0) {
1111 if (best_dist == (unsigned int)-1)
1112 return -EINVAL;
1113
1114 var->xres = best_xres;
1115 var->yres = best_yres;
1116 }
1117
1118 /* Make sure the virtual resolution is at least as big as the visible
1119 * resolution.
1120 */
1121 if (var->xres_virtual < var->xres)
1122 var->xres_virtual = var->xres;
1123 if (var->yres_virtual < var->yres)
1124 var->yres_virtual = var->yres;
1125
edd153a3
LP		 1126 if (sh_mobile_format_is_fourcc(var)) {
1127 switch (var->grayscale) {
1128 case V4L2_PIX_FMT_NV12:
1129 case V4L2_PIX_FMT_NV21:
1130 var->bits_per_pixel = 12;
1131 break;
1132 case V4L2_PIX_FMT_RGB565:
1133 case V4L2_PIX_FMT_NV16:
1134 case V4L2_PIX_FMT_NV61:
1135 var->bits_per_pixel = 16;
1136 break;
1137 case V4L2_PIX_FMT_BGR24:
1138 case V4L2_PIX_FMT_NV24:
1139 case V4L2_PIX_FMT_NV42:
1140 var->bits_per_pixel = 24;
1141 break;
1142 case V4L2_PIX_FMT_BGR32:
1143 var->bits_per_pixel = 32;
1144 break;
1145 default:
1146 return -EINVAL;
1147 }
1148
1149 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1150 * respectively.
1151 */
1152 if (!sh_mobile_format_is_yuv(var))
1153 var->colorspace = V4L2_COLORSPACE_SRGB;
1154 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1155 var->colorspace = V4L2_COLORSPACE_JPEG;
1156 } else {
1157 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1158 var->bits_per_pixel = 16;
1159 var->red.offset = 11;
1160 var->red.length = 5;
1161 var->green.offset = 5;
1162 var->green.length = 6;
1163 var->blue.offset = 0;
1164 var->blue.length = 5;
1165 var->transp.offset = 0;
1166 var->transp.length = 0;
1167 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1168 var->bits_per_pixel = 24;
1169 var->red.offset = 16;
1170 var->red.length = 8;
1171 var->green.offset = 8;
1172 var->green.length = 8;
1173 var->blue.offset = 0;
1174 var->blue.length = 8;
1175 var->transp.offset = 0;
1176 var->transp.length = 0;
1177 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1178 var->bits_per_pixel = 32;
1179 var->red.offset = 16;
1180 var->red.length = 8;
1181 var->green.offset = 8;
1182 var->green.length = 8;
1183 var->blue.offset = 0;
1184 var->blue.length = 8;
1185 var->transp.offset = 24;
1186 var->transp.length = 8;
1187 } else
1188 return -EINVAL;
417d4827 1189
edd153a3
LP		 1190 var->red.msb_right = 0;
1191 var->green.msb_right = 0;
1192 var->blue.msb_right = 0;
1193 var->transp.msb_right = 0;
1194 }
03862194
LP		 1195
1196 /* Make sure we don't exceed our allocated memory. */
1197 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1198 info->fix.smem_len)
1199 return -EINVAL;
1200
edd153a3
LP		 1201 /* only accept the forced_fourcc for dual channel configurations */
1202 if (p->forced_fourcc &&
1203 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1204 return -EINVAL;
417d4827 1205
dd210503
GL		 1206 return 0;
1207}
40331b21 1208
ed5bebf2
LP		 1209static int sh_mobile_set_par(struct fb_info *info)
1210{
1211 struct sh_mobile_lcdc_chan *ch = info->par;
91fba48d 1212 u32 line_length = info->fix.line_length;
ed5bebf2
LP		 1213 int ret;
1214
1215 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1216
edd153a3 1217 if (sh_mobile_format_is_yuv(&info->var))
91fba48d
LP		 1218 info->fix.line_length = info->var.xres;
1219 else
1220 info->fix.line_length = info->var.xres
1221 * info->var.bits_per_pixel / 8;
1222
ed5bebf2 1223 ret = sh_mobile_lcdc_start(ch->lcdc);
91fba48d 1224 if (ret < 0) {
ed5bebf2 1225 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
91fba48d
LP		 1226 info->fix.line_length = line_length;
1227 }
ed5bebf2 1228
edd153a3
LP		 1229 if (sh_mobile_format_is_fourcc(&info->var)) {
1230 info->fix.type = FB_TYPE_FOURCC;
1231 info->fix.visual = FB_VISUAL_FOURCC;
1232 } else {
1233 info->fix.type = FB_TYPE_PACKED_PIXELS;
1234 info->fix.visual = FB_VISUAL_TRUECOLOR;
1235 }
1236
ed5bebf2
LP		 1237 return ret;
1238}
1239
8857b9aa
AC		 1240/*
1241 * Screen blanking. Behavior is as follows:
1242 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1243 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1244 * FB_BLANK_VSYNC,
1245 * FB_BLANK_HSYNC,
1246 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1247 */
1248static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1249{
1250 struct sh_mobile_lcdc_chan *ch = info->par;
1251 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1252
1253 /* blank the screen? */
1254 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1255 struct fb_fillrect rect = {
1256 .width = info->var.xres,
1257 .height = info->var.yres,
1258 };
1259 sh_mobile_lcdc_fillrect(info, &rect);
1260 }
1261 /* turn clocks on? */
1262 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1263 sh_mobile_lcdc_clk_on(p);
1264 }
1265 /* turn clocks off? */
1266 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1267 /* make sure the screen is updated with the black fill before
1268 * switching the clocks off. one vsync is not enough since
1269 * blanking may occur in the middle of a refresh. deferred io
1270 * mode will reenable the clocks and update the screen in time,
1271 * so it does not need this. */
1272 if (!info->fbdefio) {
1273 sh_mobile_wait_for_vsync(info);
1274 sh_mobile_wait_for_vsync(info);
1275 }
1276 sh_mobile_lcdc_clk_off(p);
1277 }
1278
1279 ch->blank_status = blank;
1280 return 0;
1281}
1282
cfb4f5d1 1283static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1284 .owner = THIS_MODULE,
cfb4f5d1 1285 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1286 .fb_read = fb_sys_read,
1287 .fb_write = fb_sys_write,
8564557a
MD		 1288 .fb_fillrect = sh_mobile_lcdc_fillrect,
1289 .fb_copyarea = sh_mobile_lcdc_copyarea,
1290 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1291 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1292 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1293 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1294 .fb_open = sh_mobile_open,
1295 .fb_release = sh_mobile_release,
1296 .fb_check_var = sh_mobile_check_var,
ed5bebf2 1297 .fb_set_par = sh_mobile_set_par,
cfb4f5d1
MD		 1298};
1299
f1f60b5f
LP		 1300/* -----------------------------------------------------------------------------
1301 * Backlight
1302 */
1303
3b0fd9d7
AC		 1304static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1305{
1306 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1307 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1308 int brightness = bdev->props.brightness;
1309
1310 if (bdev->props.power != FB_BLANK_UNBLANK ||
1311 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1312 brightness = 0;
1313
1314 return cfg->set_brightness(cfg->board_data, brightness);
1315}
1316
1317static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1318{
1319 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1320 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1321
1322 return cfg->get_brightness(cfg->board_data);
1323}
1324
1325static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1326 struct fb_info *info)
1327{
1328 return (info->bl_dev == bdev);
1329}
1330
1331static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1332 .options = BL_CORE_SUSPENDRESUME,
1333 .update_status = sh_mobile_lcdc_update_bl,
1334 .get_brightness = sh_mobile_lcdc_get_brightness,
1335 .check_fb = sh_mobile_lcdc_check_fb,
1336};
1337
1338static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1339 struct sh_mobile_lcdc_chan *ch)
1340{
1341 struct backlight_device *bl;
1342
1343 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1344 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1345 if (IS_ERR(bl)) {
1346 dev_err(parent, "unable to register backlight device: %ld\n",
1347 PTR_ERR(bl));
3b0fd9d7
AC		 1348 return NULL;
1349 }
1350
1351 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1352 bl->props.brightness = bl->props.max_brightness;
1353 backlight_update_status(bl);
1354
1355 return bl;
1356}
1357
1358static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1359{
1360 backlight_device_unregister(bdev);
1361}
1362
f1f60b5f
LP		 1363/* -----------------------------------------------------------------------------
1364 * Power management
1365 */
1366
2feb075a
MD		 1367static int sh_mobile_lcdc_suspend(struct device *dev)
1368{
1369 struct platform_device *pdev = to_platform_device(dev);
1370
1371 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1372 return 0;
1373}
1374
1375static int sh_mobile_lcdc_resume(struct device *dev)
1376{
1377 struct platform_device *pdev = to_platform_device(dev);
1378
1379 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1380}
1381
0246c471
MD		 1382static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1383{
1384 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1385 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471
MD		 1386
1387 /* turn off LCDC hardware */
2427bb24
LP		 1388 lcdc_write(priv, _LDCNT1R, 0);
1389
0246c471
MD		 1390 return 0;
1391}
1392
1393static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1394{
1395 struct platform_device *pdev = to_platform_device(dev);
2427bb24 1396 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471 1397
2427bb24 1398 __sh_mobile_lcdc_start(priv);
0246c471
MD		 1399
1400 return 0;
1401}
1402
47145210 1403static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1404 .suspend = sh_mobile_lcdc_suspend,
1405 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1406 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1407 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1408};
1409
f1f60b5f
LP		 1410/* -----------------------------------------------------------------------------
1411 * Framebuffer notifier
1412 */
1413
6de9edd5 1414/* locking: called with info->lock held */
6011bdea
GL		 1415static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1416 unsigned long action, void *data)
1417{
1418 struct fb_event *event = data;
1419 struct fb_info *info = event->info;
1420 struct sh_mobile_lcdc_chan *ch = info->par;
1421 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
6011bdea
GL		 1422
1423 if (&ch->lcdc->notifier != nb)
baf16374 1424 return NOTIFY_DONE;
6011bdea
GL		 1425
1426 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1427 __func__, action, event->data);
1428
1429 switch(action) {
1430 case FB_EVENT_SUSPEND:
247f9938 1431 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1432 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1433 module_put(board_cfg->owner);
1434 }
afe417c0 1435 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1436 break;
1437 case FB_EVENT_RESUME:
dd210503
GL		 1438 mutex_lock(&ch->open_lock);
1439 sh_mobile_fb_reconfig(info);
1440 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1441
1442 /* HDMI must be enabled before LCDC configuration */
247f9938 1443 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1444 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1445 module_put(board_cfg->owner);
6011bdea
GL		 1446 }
1447
ebe5e12d 1448 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1449 }
1450
baf16374 1451 return NOTIFY_OK;
6011bdea
GL		 1452}
1453
f1f60b5f
LP		 1454/* -----------------------------------------------------------------------------
1455 * Probe/remove and driver init/exit
1456 */
1457
217e9c43 1458static const struct fb_videomode default_720p __devinitconst = {
f1f60b5f
LP		 1459 .name = "HDMI 720p",
1460 .xres = 1280,
1461 .yres = 720,
1462
1463 .left_margin = 220,
1464 .right_margin = 110,
1465 .hsync_len = 40,
1466
1467 .upper_margin = 20,
1468 .lower_margin = 5,
1469 .vsync_len = 5,
1470
1471 .pixclock = 13468,
1472 .refresh = 60,
1473 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
1474};
1475
b4bee692
LP		 1476static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1477{
1478 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1479 struct fb_info *info;
1480 int i;
1481
1482 fb_unregister_client(&priv->notifier);
1483
1484 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1485 if (priv->ch[i].info && priv->ch[i].info->dev)
1486 unregister_framebuffer(priv->ch[i].info);
1487
1488 sh_mobile_lcdc_stop(priv);
1489
1490 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1491 info = priv->ch[i].info;
1492
1493 if (!info || !info->device)
1494 continue;
1495
1496 if (priv->ch[i].sglist)
1497 vfree(priv->ch[i].sglist);
1498
1499 if (info->screen_base)
1500 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1501 info->screen_base,
1502 priv->ch[i].dma_handle);
1503 fb_dealloc_cmap(&info->cmap);
1504 framebuffer_release(info);
1505 }
1506
1507 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1508 if (priv->ch[i].bl)
1509 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1510 }
1511
4774c12a
LP		 1512 if (priv->dot_clk) {
1513 pm_runtime_disable(&pdev->dev);
b4bee692 1514 clk_put(priv->dot_clk);
4774c12a 1515 }
b4bee692
LP		 1516
1517 if (priv->base)
1518 iounmap(priv->base);
1519
1520 if (priv->irq)
1521 free_irq(priv->irq, priv);
1522 kfree(priv);
1523 return 0;
1524}
cfb4f5d1 1525
217e9c43 1526static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f
LP		 1527{
1528 int interface_type = ch->cfg.interface_type;
1529
1530 switch (interface_type) {
1531 case RGB8:
1532 case RGB9:
1533 case RGB12A:
1534 case RGB12B:
1535 case RGB16:
1536 case RGB18:
1537 case RGB24:
1538 case SYS8A:
1539 case SYS8B:
1540 case SYS8C:
1541 case SYS8D:
1542 case SYS9:
1543 case SYS12:
1544 case SYS16A:
1545 case SYS16B:
1546 case SYS16C:
1547 case SYS18:
1548 case SYS24:
1549 break;
1550 default:
1551 return -EINVAL;
1552 }
1553
1554 /* SUBLCD only supports SYS interface */
1555 if (lcdc_chan_is_sublcd(ch)) {
1556 if (!(interface_type & LDMT1R_IFM))
1557 return -EINVAL;
1558
1559 interface_type &= ~LDMT1R_IFM;
1560 }
1561
1562 ch->ldmt1r_value = interface_type;
1563 return 0;
1564}
1565
3ce05599
LP		 1566static int __devinit sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_chan *ch,
1567 struct device *dev)
cfb4f5d1 1568{
3ce05599
LP		 1569 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1570 const struct fb_videomode *max_mode;
1571 const struct fb_videomode *mode;
1572 struct fb_var_screeninfo *var;
cfb4f5d1 1573 struct fb_info *info;
3ce05599
LP		 1574 unsigned int max_size;
1575 int num_cfg;
1576 void *buf;
1577 int ret;
1578 int i;
1579
a67472ad
LP		 1580 mutex_init(&ch->open_lock);
1581
1582 /* Allocate the frame buffer device. */
3ce05599
LP		 1583 ch->info = framebuffer_alloc(0, dev);
1584 if (!ch->info) {
1585 dev_err(dev, "unable to allocate fb_info\n");
1586 return -ENOMEM;
1587 }
1588
1589 info = ch->info;
3ce05599
LP		 1590 info->fbops = &sh_mobile_lcdc_ops;
1591 info->par = ch;
a67472ad
LP		 1592 info->pseudo_palette = &ch->pseudo_palette;
1593 info->flags = FBINFO_FLAG_DEFAULT;
3ce05599
LP		 1594
1595 /* Iterate through the modes to validate them and find the highest
1596 * resolution.
1597 */
1598 max_mode = NULL;
1599 max_size = 0;
1600
1601 for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) {
1602 unsigned int size = mode->yres * mode->xres;
1603
edd153a3
LP		 1604 /* NV12/NV21 buffers must have even number of lines */
1605 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1606 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
3ce05599
LP		 1607 dev_err(dev, "yres must be multiple of 2 for YCbCr420 "
1608 "mode.\n");
1609 return -EINVAL;
1610 }
1611
1612 if (size > max_size) {
1613 max_mode = mode;
1614 max_size = size;
1615 }
1616 }
1617
1618 if (!max_size)
1619 max_size = MAX_XRES * MAX_YRES;
1620 else
1621 dev_dbg(dev, "Found largest videomode %ux%u\n",
1622 max_mode->xres, max_mode->yres);
1623
a67472ad 1624 /* Create the mode list. */
3ce05599
LP		 1625 if (cfg->lcd_cfg == NULL) {
1626 mode = &default_720p;
1627 num_cfg = 1;
1628 } else {
1629 mode = cfg->lcd_cfg;
1630 num_cfg = cfg->num_cfg;
1631 }
1632
1633 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
1634
a67472ad
LP		 1635 /* Initialize variable screen information using the first mode as
1636 * default. The default Y virtual resolution is twice the panel size to
1637 * allow for double-buffering.
1638 */
1639 var = &info->var;
3ce05599
LP		 1640 fb_videomode_to_var(var, mode);
1641 var->width = cfg->lcd_size_cfg.width;
1642 var->height = cfg->lcd_size_cfg.height;
3ce05599
LP		 1643 var->yres_virtual = var->yres * 2;
1644 var->activate = FB_ACTIVATE_NOW;
1645
edd153a3
LP		 1646 switch (cfg->fourcc) {
1647 case V4L2_PIX_FMT_RGB565:
1648 var->bits_per_pixel = 16;
1649 break;
1650 case V4L2_PIX_FMT_BGR24:
1651 var->bits_per_pixel = 24;
1652 break;
1653 case V4L2_PIX_FMT_BGR32:
1654 var->bits_per_pixel = 32;
1655 break;
1656 default:
1657 var->grayscale = cfg->fourcc;
1658 break;
1659 }
1660
1661 /* Make sure the memory size check won't fail. smem_len is initialized
1662 * later based on var.
1663 */
1664 info->fix.smem_len = UINT_MAX;
a67472ad 1665 ret = sh_mobile_check_var(var, info);
3ce05599
LP		 1666 if (ret)
1667 return ret;
1668
edd153a3
LP		 1669 max_size = max_size * var->bits_per_pixel / 8 * 2;
1670
a67472ad 1671 /* Allocate frame buffer memory and color map. */
edd153a3 1672 buf = dma_alloc_coherent(dev, max_size, &ch->dma_handle, GFP_KERNEL);
3ce05599
LP		 1673 if (!buf) {
1674 dev_err(dev, "unable to allocate buffer\n");
1675 return -ENOMEM;
1676 }
1677
3ce05599
LP		 1678 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1679 if (ret < 0) {
1680 dev_err(dev, "unable to allocate cmap\n");
edd153a3 1681 dma_free_coherent(dev, max_size, buf, ch->dma_handle);
3ce05599
LP		 1682 return ret;
1683 }
1684
edd153a3
LP		 1685 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1686 * for NV12 and NV21.
1687 */
1688 info->fix = sh_mobile_lcdc_fix;
3ce05599 1689 info->fix.smem_start = ch->dma_handle;
edd153a3
LP		 1690 info->fix.smem_len = max_size;
1691 if (cfg->fourcc == V4L2_PIX_FMT_NV12 ||
1692 cfg->fourcc == V4L2_PIX_FMT_NV21)
1693 info->fix.ypanstep = 2;
1694
1695 if (sh_mobile_format_is_yuv(var)) {
3ce05599 1696 info->fix.line_length = var->xres;
edd153a3
LP		 1697 info->fix.visual = FB_VISUAL_FOURCC;
1698 } else {
1699 info->fix.line_length = var->xres * var->bits_per_pixel / 8;
1700 info->fix.visual = FB_VISUAL_TRUECOLOR;
1701 }
3ce05599
LP		 1702
1703 info->screen_base = buf;
1704 info->device = dev;
1705 ch->display_var = *var;
1706
1707 return 0;
1708}
1709
1710static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1711{
01ac25b5 1712 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 1713 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 1714 struct resource *res;
3ce05599 1715 int num_channels;
cfb4f5d1 1716 int error;
3ce05599 1717 int i;
cfb4f5d1 1718
01ac25b5 1719 if (!pdata) {
cfb4f5d1 1720 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1721 return -EINVAL;
cfb4f5d1
MD		 1722 }
1723
1724 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1725 i = platform_get_irq(pdev, 0);
1726 if (!res || i < 0) {
1727 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1728 return -ENOENT;
cfb4f5d1
MD		 1729 }
1730
1731 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1732 if (!priv) {
1733 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1734 return -ENOMEM;
cfb4f5d1
MD		 1735 }
1736
4774c12a
LP		 1737 priv->dev = &pdev->dev;
1738 priv->meram_dev = pdata->meram_dev;
8bed9055
GL		 1739 platform_set_drvdata(pdev, priv);
1740
f8798ccb 1741 error = request_irq(i, sh_mobile_lcdc_irq, 0,
7ad33e74 1742 dev_name(&pdev->dev), priv);
8564557a
MD		 1743 if (error) {
1744 dev_err(&pdev->dev, "unable to request irq\n");
1745 goto err1;
1746 }
1747
1748 priv->irq = i;
5ef6b505 1749 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 1750
3ce05599
LP		 1751 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1752 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 1753
01ac25b5
GL		 1754 ch->lcdc = priv;
1755 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1756
01ac25b5 1757 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1758 if (error) {
1759 dev_err(&pdev->dev, "unsupported interface type\n");
1760 goto err1;
1761 }
01ac25b5
GL		 1762 init_waitqueue_head(&ch->frame_end_wait);
1763 init_completion(&ch->vsync_completion);
1764 ch->pan_offset = 0;
cfb4f5d1 1765
3b0fd9d7
AC		 1766 /* probe the backlight is there is one defined */
1767 if (ch->cfg.bl_info.max_brightness)
1768 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1769
cfb4f5d1
MD		 1770 switch (pdata->ch[i].chan) {
1771 case LCDC_CHAN_MAINLCD:
ce1c0b08 1772 ch->enabled = LDCNT2R_ME;
01ac25b5 1773 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 1774 num_channels++;
cfb4f5d1
MD		 1775 break;
1776 case LCDC_CHAN_SUBLCD:
ce1c0b08 1777 ch->enabled = LDCNT2R_SE;
01ac25b5 1778 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 1779 num_channels++;
cfb4f5d1
MD		 1780 break;
1781 }
1782 }
1783
3ce05599 1784 if (!num_channels) {
cfb4f5d1
MD		 1785 dev_err(&pdev->dev, "no channels defined\n");
1786 error = -EINVAL;
1787 goto err1;
1788 }
1789
edd153a3 1790 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 1791 if (num_channels == 2)
edd153a3 1792 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 1793
dba6f385
GL		 1794 priv->base = ioremap_nocache(res->start, resource_size(res));
1795 if (!priv->base)
1796 goto err1;
1797
b51339ff 1798 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1799 if (error) {
1800 dev_err(&pdev->dev, "unable to setup clocks\n");
1801 goto err1;
1802 }
1803
4774c12a
LP		 1804 /* Enable runtime PM. */
1805 pm_runtime_enable(&pdev->dev);
7caa4342 1806
3ce05599 1807 for (i = 0; i < num_channels; i++) {
01ac25b5 1808 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76 1809
3ce05599 1810 error = sh_mobile_lcdc_channel_init(ch, &pdev->dev);
cfb4f5d1 1811 if (error)
3ce05599 1812 goto err1;
cfb4f5d1
MD		 1813 }
1814
cfb4f5d1
MD		 1815 error = sh_mobile_lcdc_start(priv);
1816 if (error) {
1817 dev_err(&pdev->dev, "unable to start hardware\n");
1818 goto err1;
1819 }
1820
3ce05599 1821 for (i = 0; i < num_channels; i++) {
1c6a307a 1822 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
3ce05599 1823 struct fb_info *info = ch->info;
1c6a307a
PM		 1824
1825 if (info->fbdefio) {
8bed9055 1826 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1827 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1828 if (!ch->sglist) {
1c6a307a
PM		 1829 dev_err(&pdev->dev, "cannot allocate sglist\n");
1830 goto err1;
1831 }
1832 }
1833
3b0fd9d7
AC		 1834 info->bl_dev = ch->bl;
1835
1c6a307a 1836 error = register_framebuffer(info);
cfb4f5d1
MD		 1837 if (error < 0)
1838 goto err1;
cfb4f5d1 1839
edd153a3
LP		 1840 dev_info(info->dev, "registered %s/%s as %dx%d %dbpp.\n",
1841 pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1842 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
1843 info->var.bits_per_pixel);
8564557a
MD		 1844
1845 /* deferred io mode: disable clock to save power */
6011bdea 1846 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1847 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1848 }
1849
6011bdea
GL		 1850 /* Failure ignored */
1851 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1852 fb_register_client(&priv->notifier);
1853
cfb4f5d1 1854 return 0;
8bed9055 1855err1:
cfb4f5d1 1856 sh_mobile_lcdc_remove(pdev);
8bed9055 1857
cfb4f5d1
MD		 1858 return error;
1859}
1860
cfb4f5d1
MD		 1861static struct platform_driver sh_mobile_lcdc_driver = {
1862 .driver = {
1863 .name = "sh_mobile_lcdc_fb",
1864 .owner = THIS_MODULE,
2feb075a 1865 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1866 },
1867 .probe = sh_mobile_lcdc_probe,
1868 .remove = sh_mobile_lcdc_remove,
1869};
1870
4277f2c4 1871module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 1872
1873MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1874MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1875MODULE_LICENSE("GPL v2");
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