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Commit | Line | Data |
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cfb4f5d1 MD |
1 | /* |
2 | * SuperH Mobile LCDC Framebuffer | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
f1f60b5f LP |
11 | #include <linux/atomic.h> |
12 | #include <linux/backlight.h> | |
cfb4f5d1 | 13 | #include <linux/clk.h> |
f1f60b5f | 14 | #include <linux/console.h> |
cfb4f5d1 | 15 | #include <linux/dma-mapping.h> |
f1f60b5f LP |
16 | #include <linux/delay.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8564557a | 19 | #include <linux/interrupt.h> |
40331b21 | 20 | #include <linux/ioctl.h> |
f1f60b5f LP |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
355b200b | 23 | #include <linux/module.h> |
f1f60b5f LP |
24 | #include <linux/platform_device.h> |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <linux/vmalloc.h> | |
29 | ||
225c9a8d | 30 | #include <video/sh_mobile_lcdc.h> |
8a20974f | 31 | #include <video/sh_mobile_meram.h> |
cfb4f5d1 | 32 | |
6de9edd5 GL |
33 | #include "sh_mobile_lcdcfb.h" |
34 | ||
a6f15ade PE |
35 | #define SIDE_B_OFFSET 0x1000 |
36 | #define MIRROR_OFFSET 0x2000 | |
cfb4f5d1 | 37 | |
d2ecbab5 GL |
38 | #define MAX_XRES 1920 |
39 | #define MAX_YRES 1080 | |
cfb4f5d1 | 40 | |
f1f60b5f LP |
41 | struct sh_mobile_lcdc_priv { |
42 | void __iomem *base; | |
43 | int irq; | |
44 | atomic_t hw_usecnt; | |
45 | struct device *dev; | |
46 | struct clk *dot_clk; | |
47 | unsigned long lddckr; | |
48 | struct sh_mobile_lcdc_chan ch[2]; | |
49 | struct notifier_block notifier; | |
50 | int started; | |
51 | int forced_fourcc; /* 2 channel LCDC must share fourcc setting */ | |
52 | struct sh_mobile_meram_info *meram_dev; | |
53 | }; | |
54 | ||
55 | /* ----------------------------------------------------------------------------- | |
56 | * Registers access | |
57 | */ | |
58 | ||
0246c471 | 59 | static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
60 | [LDDCKPAT1R] = 0x400, |
61 | [LDDCKPAT2R] = 0x404, | |
62 | [LDMT1R] = 0x418, | |
63 | [LDMT2R] = 0x41c, | |
64 | [LDMT3R] = 0x420, | |
65 | [LDDFR] = 0x424, | |
66 | [LDSM1R] = 0x428, | |
8564557a | 67 | [LDSM2R] = 0x42c, |
cfb4f5d1 | 68 | [LDSA1R] = 0x430, |
53b50314 | 69 | [LDSA2R] = 0x434, |
cfb4f5d1 MD |
70 | [LDMLSR] = 0x438, |
71 | [LDHCNR] = 0x448, | |
72 | [LDHSYNR] = 0x44c, | |
73 | [LDVLNR] = 0x450, | |
74 | [LDVSYNR] = 0x454, | |
75 | [LDPMR] = 0x460, | |
6011bdea | 76 | [LDHAJR] = 0x4a0, |
cfb4f5d1 MD |
77 | }; |
78 | ||
0246c471 | 79 | static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
80 | [LDDCKPAT1R] = 0x408, |
81 | [LDDCKPAT2R] = 0x40c, | |
82 | [LDMT1R] = 0x600, | |
83 | [LDMT2R] = 0x604, | |
84 | [LDMT3R] = 0x608, | |
85 | [LDDFR] = 0x60c, | |
86 | [LDSM1R] = 0x610, | |
8564557a | 87 | [LDSM2R] = 0x614, |
cfb4f5d1 MD |
88 | [LDSA1R] = 0x618, |
89 | [LDMLSR] = 0x620, | |
90 | [LDHCNR] = 0x624, | |
91 | [LDHSYNR] = 0x628, | |
92 | [LDVLNR] = 0x62c, | |
93 | [LDVSYNR] = 0x630, | |
94 | [LDPMR] = 0x63c, | |
95 | }; | |
96 | ||
a6f15ade PE |
97 | static bool banked(int reg_nr) |
98 | { | |
99 | switch (reg_nr) { | |
100 | case LDMT1R: | |
101 | case LDMT2R: | |
102 | case LDMT3R: | |
103 | case LDDFR: | |
104 | case LDSM1R: | |
105 | case LDSA1R: | |
53b50314 | 106 | case LDSA2R: |
a6f15ade PE |
107 | case LDMLSR: |
108 | case LDHCNR: | |
109 | case LDHSYNR: | |
110 | case LDVLNR: | |
111 | case LDVSYNR: | |
112 | return true; | |
113 | } | |
114 | return false; | |
115 | } | |
116 | ||
f1f60b5f LP |
117 | static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan) |
118 | { | |
119 | return chan->cfg.chan == LCDC_CHAN_SUBLCD; | |
120 | } | |
121 | ||
cfb4f5d1 MD |
122 | static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan, |
123 | int reg_nr, unsigned long data) | |
124 | { | |
125 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); | |
a6f15ade PE |
126 | if (banked(reg_nr)) |
127 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
128 | SIDE_B_OFFSET); | |
129 | } | |
130 | ||
131 | static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan, | |
132 | int reg_nr, unsigned long data) | |
133 | { | |
134 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
135 | MIRROR_OFFSET); | |
cfb4f5d1 MD |
136 | } |
137 | ||
138 | static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan, | |
139 | int reg_nr) | |
140 | { | |
141 | return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); | |
142 | } | |
143 | ||
144 | static void lcdc_write(struct sh_mobile_lcdc_priv *priv, | |
145 | unsigned long reg_offs, unsigned long data) | |
146 | { | |
147 | iowrite32(data, priv->base + reg_offs); | |
148 | } | |
149 | ||
150 | static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv, | |
151 | unsigned long reg_offs) | |
152 | { | |
153 | return ioread32(priv->base + reg_offs); | |
154 | } | |
155 | ||
156 | static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv, | |
157 | unsigned long reg_offs, | |
158 | unsigned long mask, unsigned long until) | |
159 | { | |
160 | while ((lcdc_read(priv, reg_offs) & mask) != until) | |
161 | cpu_relax(); | |
162 | } | |
163 | ||
f1f60b5f LP |
164 | /* ----------------------------------------------------------------------------- |
165 | * Clock management | |
166 | */ | |
167 | ||
168 | static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) | |
cfb4f5d1 | 169 | { |
f1f60b5f LP |
170 | if (atomic_inc_and_test(&priv->hw_usecnt)) { |
171 | if (priv->dot_clk) | |
172 | clk_enable(priv->dot_clk); | |
173 | pm_runtime_get_sync(priv->dev); | |
174 | if (priv->meram_dev && priv->meram_dev->pdev) | |
175 | pm_runtime_get_sync(&priv->meram_dev->pdev->dev); | |
176 | } | |
cfb4f5d1 MD |
177 | } |
178 | ||
f1f60b5f LP |
179 | static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) |
180 | { | |
181 | if (atomic_sub_return(1, &priv->hw_usecnt) == -1) { | |
182 | if (priv->meram_dev && priv->meram_dev->pdev) | |
183 | pm_runtime_put_sync(&priv->meram_dev->pdev->dev); | |
184 | pm_runtime_put(priv->dev); | |
185 | if (priv->dot_clk) | |
186 | clk_disable(priv->dot_clk); | |
187 | } | |
188 | } | |
189 | ||
0a7f17aa LP |
190 | static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv, |
191 | int clock_source) | |
f1f60b5f | 192 | { |
4774c12a | 193 | struct clk *clk; |
f1f60b5f LP |
194 | char *str; |
195 | ||
196 | switch (clock_source) { | |
197 | case LCDC_CLK_BUS: | |
198 | str = "bus_clk"; | |
199 | priv->lddckr = LDDCKR_ICKSEL_BUS; | |
200 | break; | |
201 | case LCDC_CLK_PERIPHERAL: | |
202 | str = "peripheral_clk"; | |
203 | priv->lddckr = LDDCKR_ICKSEL_MIPI; | |
204 | break; | |
205 | case LCDC_CLK_EXTERNAL: | |
206 | str = NULL; | |
207 | priv->lddckr = LDDCKR_ICKSEL_HDMI; | |
208 | break; | |
209 | default: | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
4774c12a LP |
213 | if (str == NULL) |
214 | return 0; | |
215 | ||
0a7f17aa | 216 | clk = clk_get(priv->dev, str); |
4774c12a | 217 | if (IS_ERR(clk)) { |
0a7f17aa | 218 | dev_err(priv->dev, "cannot get dot clock %s\n", str); |
4774c12a | 219 | return PTR_ERR(clk); |
f1f60b5f LP |
220 | } |
221 | ||
4774c12a | 222 | priv->dot_clk = clk; |
f1f60b5f LP |
223 | return 0; |
224 | } | |
225 | ||
226 | /* ----------------------------------------------------------------------------- | |
37c5dcc2 | 227 | * Display, panel and deferred I/O |
f1f60b5f LP |
228 | */ |
229 | ||
cfb4f5d1 MD |
230 | static void lcdc_sys_write_index(void *handle, unsigned long data) |
231 | { | |
232 | struct sh_mobile_lcdc_chan *ch = handle; | |
233 | ||
ce1c0b08 LP |
234 | lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); |
235 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
236 | lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | | |
237 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
238 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
cfb4f5d1 MD |
239 | } |
240 | ||
241 | static void lcdc_sys_write_data(void *handle, unsigned long data) | |
242 | { | |
243 | struct sh_mobile_lcdc_chan *ch = handle; | |
244 | ||
ce1c0b08 LP |
245 | lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW); |
246 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
247 | lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | | |
248 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
249 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
cfb4f5d1 MD |
250 | } |
251 | ||
252 | static unsigned long lcdc_sys_read_data(void *handle) | |
253 | { | |
254 | struct sh_mobile_lcdc_chan *ch = handle; | |
255 | ||
ce1c0b08 LP |
256 | lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR); |
257 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
258 | lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA | | |
259 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
cfb4f5d1 | 260 | udelay(1); |
ce1c0b08 | 261 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); |
cfb4f5d1 | 262 | |
ce1c0b08 | 263 | return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK; |
cfb4f5d1 MD |
264 | } |
265 | ||
266 | struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = { | |
267 | lcdc_sys_write_index, | |
268 | lcdc_sys_write_data, | |
269 | lcdc_sys_read_data, | |
270 | }; | |
271 | ||
1c6a307a PM |
272 | static int sh_mobile_lcdc_sginit(struct fb_info *info, |
273 | struct list_head *pagelist) | |
274 | { | |
275 | struct sh_mobile_lcdc_chan *ch = info->par; | |
276 | unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT; | |
277 | struct page *page; | |
278 | int nr_pages = 0; | |
279 | ||
280 | sg_init_table(ch->sglist, nr_pages_max); | |
281 | ||
282 | list_for_each_entry(page, pagelist, lru) | |
283 | sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0); | |
284 | ||
285 | return nr_pages; | |
286 | } | |
287 | ||
8564557a MD |
288 | static void sh_mobile_lcdc_deferred_io(struct fb_info *info, |
289 | struct list_head *pagelist) | |
290 | { | |
291 | struct sh_mobile_lcdc_chan *ch = info->par; | |
ef61aae4 | 292 | struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg; |
8564557a MD |
293 | |
294 | /* enable clocks before accessing hardware */ | |
295 | sh_mobile_lcdc_clk_on(ch->lcdc); | |
296 | ||
5c1a56b5 PM |
297 | /* |
298 | * It's possible to get here without anything on the pagelist via | |
299 | * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync() | |
300 | * invocation. In the former case, the acceleration routines are | |
301 | * stepped in to when using the framebuffer console causing the | |
302 | * workqueue to be scheduled without any dirty pages on the list. | |
303 | * | |
304 | * Despite this, a panel update is still needed given that the | |
305 | * acceleration routines have their own methods for writing in | |
306 | * that still need to be updated. | |
307 | * | |
308 | * The fsync() and empty pagelist case could be optimized for, | |
309 | * but we don't bother, as any application exhibiting such | |
310 | * behaviour is fundamentally broken anyways. | |
311 | */ | |
312 | if (!list_empty(pagelist)) { | |
313 | unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist); | |
314 | ||
315 | /* trigger panel update */ | |
316 | dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
ef61aae4 MD |
317 | if (bcfg->start_transfer) |
318 | bcfg->start_transfer(bcfg->board_data, ch, | |
319 | &sh_mobile_lcdc_sys_bus_ops); | |
ce1c0b08 | 320 | lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG); |
5c1a56b5 | 321 | dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); |
ef61aae4 MD |
322 | } else { |
323 | if (bcfg->start_transfer) | |
324 | bcfg->start_transfer(bcfg->board_data, ch, | |
325 | &sh_mobile_lcdc_sys_bus_ops); | |
ce1c0b08 | 326 | lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG); |
ef61aae4 | 327 | } |
8564557a MD |
328 | } |
329 | ||
330 | static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info) | |
331 | { | |
332 | struct fb_deferred_io *fbdefio = info->fbdefio; | |
333 | ||
334 | if (fbdefio) | |
335 | schedule_delayed_work(&info->deferred_work, fbdefio->delay); | |
336 | } | |
337 | ||
37c5dcc2 LP |
338 | static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch) |
339 | { | |
340 | struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg; | |
341 | ||
342 | /* HDMI must be enabled before LCDC configuration */ | |
343 | if (board_cfg->display_on && try_module_get(board_cfg->owner)) { | |
344 | board_cfg->display_on(board_cfg->board_data, ch->info); | |
345 | module_put(board_cfg->owner); | |
346 | } | |
347 | } | |
348 | ||
349 | static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch) | |
350 | { | |
351 | struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg; | |
352 | ||
353 | if (board_cfg->display_off && try_module_get(board_cfg->owner)) { | |
354 | board_cfg->display_off(board_cfg->board_data); | |
355 | module_put(board_cfg->owner); | |
356 | } | |
357 | } | |
358 | ||
f1f60b5f LP |
359 | /* ----------------------------------------------------------------------------- |
360 | * Format helpers | |
361 | */ | |
362 | ||
363 | static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var) | |
364 | { | |
365 | if (var->grayscale > 1) | |
366 | return var->grayscale; | |
367 | ||
368 | switch (var->bits_per_pixel) { | |
369 | case 16: | |
370 | return V4L2_PIX_FMT_RGB565; | |
371 | case 24: | |
372 | return V4L2_PIX_FMT_BGR24; | |
373 | case 32: | |
374 | return V4L2_PIX_FMT_BGR32; | |
375 | default: | |
376 | return 0; | |
377 | } | |
378 | } | |
379 | ||
380 | static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var) | |
381 | { | |
382 | return var->grayscale > 1; | |
383 | } | |
384 | ||
385 | static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var) | |
386 | { | |
387 | if (var->grayscale <= 1) | |
388 | return false; | |
389 | ||
390 | switch (var->grayscale) { | |
391 | case V4L2_PIX_FMT_NV12: | |
392 | case V4L2_PIX_FMT_NV21: | |
393 | case V4L2_PIX_FMT_NV16: | |
394 | case V4L2_PIX_FMT_NV61: | |
395 | case V4L2_PIX_FMT_NV24: | |
396 | case V4L2_PIX_FMT_NV42: | |
397 | return true; | |
398 | ||
399 | default: | |
400 | return false; | |
401 | } | |
402 | } | |
403 | ||
404 | /* ----------------------------------------------------------------------------- | |
405 | * Start, stop and IRQ | |
406 | */ | |
407 | ||
8564557a MD |
408 | static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data) |
409 | { | |
410 | struct sh_mobile_lcdc_priv *priv = data; | |
2feb075a | 411 | struct sh_mobile_lcdc_chan *ch; |
9dd38819 | 412 | unsigned long ldintr; |
2feb075a MD |
413 | int is_sub; |
414 | int k; | |
8564557a | 415 | |
dc48665f LP |
416 | /* Acknowledge interrupts and disable further VSYNC End IRQs. */ |
417 | ldintr = lcdc_read(priv, _LDINTR); | |
418 | lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE); | |
8564557a | 419 | |
2feb075a | 420 | /* figure out if this interrupt is for main or sub lcd */ |
ce1c0b08 | 421 | is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0; |
2feb075a | 422 | |
9dd38819 | 423 | /* wake up channel and disable clocks */ |
2feb075a MD |
424 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
425 | ch = &priv->ch[k]; | |
426 | ||
427 | if (!ch->enabled) | |
428 | continue; | |
429 | ||
dc48665f | 430 | /* Frame End */ |
9dd38819 PE |
431 | if (ldintr & LDINTR_FS) { |
432 | if (is_sub == lcdc_chan_is_sublcd(ch)) { | |
433 | ch->frame_end = 1; | |
434 | wake_up(&ch->frame_end_wait); | |
2feb075a | 435 | |
9dd38819 PE |
436 | sh_mobile_lcdc_clk_off(priv); |
437 | } | |
438 | } | |
439 | ||
440 | /* VSYNC End */ | |
40331b21 PE |
441 | if (ldintr & LDINTR_VES) |
442 | complete(&ch->vsync_completion); | |
2feb075a MD |
443 | } |
444 | ||
8564557a MD |
445 | return IRQ_HANDLED; |
446 | } | |
447 | ||
cfb4f5d1 MD |
448 | static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv, |
449 | int start) | |
450 | { | |
451 | unsigned long tmp = lcdc_read(priv, _LDCNT2R); | |
452 | int k; | |
453 | ||
454 | /* start or stop the lcdc */ | |
455 | if (start) | |
ce1c0b08 | 456 | lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO); |
cfb4f5d1 | 457 | else |
ce1c0b08 | 458 | lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO); |
cfb4f5d1 MD |
459 | |
460 | /* wait until power is applied/stopped on all channels */ | |
461 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
462 | if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled) | |
463 | while (1) { | |
ce1c0b08 LP |
464 | tmp = lcdc_read_chan(&priv->ch[k], LDPMR) |
465 | & LDPMR_LPS; | |
466 | if (start && tmp == LDPMR_LPS) | |
cfb4f5d1 MD |
467 | break; |
468 | if (!start && tmp == 0) | |
469 | break; | |
470 | cpu_relax(); | |
471 | } | |
472 | ||
473 | if (!start) | |
474 | lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */ | |
475 | } | |
476 | ||
6011bdea GL |
477 | static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch) |
478 | { | |
1c120deb GL |
479 | struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var; |
480 | unsigned long h_total, hsync_pos, display_h_total; | |
6011bdea GL |
481 | u32 tmp; |
482 | ||
483 | tmp = ch->ldmt1r_value; | |
ce1c0b08 LP |
484 | tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL; |
485 | tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL; | |
486 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0; | |
487 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0; | |
488 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0; | |
489 | tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0; | |
490 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0; | |
6011bdea GL |
491 | lcdc_write_chan(ch, LDMT1R, tmp); |
492 | ||
493 | /* setup SYS bus */ | |
494 | lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r); | |
495 | lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r); | |
496 | ||
497 | /* horizontal configuration */ | |
1c120deb GL |
498 | h_total = display_var->xres + display_var->hsync_len + |
499 | display_var->left_margin + display_var->right_margin; | |
6011bdea | 500 | tmp = h_total / 8; /* HTCN */ |
1c120deb | 501 | tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */ |
6011bdea GL |
502 | lcdc_write_chan(ch, LDHCNR, tmp); |
503 | ||
1c120deb | 504 | hsync_pos = display_var->xres + display_var->right_margin; |
6011bdea | 505 | tmp = hsync_pos / 8; /* HSYNP */ |
1c120deb | 506 | tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */ |
6011bdea GL |
507 | lcdc_write_chan(ch, LDHSYNR, tmp); |
508 | ||
509 | /* vertical configuration */ | |
1c120deb GL |
510 | tmp = display_var->yres + display_var->vsync_len + |
511 | display_var->upper_margin + display_var->lower_margin; /* VTLN */ | |
512 | tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */ | |
6011bdea GL |
513 | lcdc_write_chan(ch, LDVLNR, tmp); |
514 | ||
1c120deb GL |
515 | tmp = display_var->yres + display_var->lower_margin; /* VSYNP */ |
516 | tmp |= display_var->vsync_len << 16; /* VSYNW */ | |
6011bdea GL |
517 | lcdc_write_chan(ch, LDVSYNR, tmp); |
518 | ||
519 | /* Adjust horizontal synchronisation for HDMI */ | |
1c120deb GL |
520 | display_h_total = display_var->xres + display_var->hsync_len + |
521 | display_var->left_margin + display_var->right_margin; | |
522 | tmp = ((display_var->xres & 7) << 24) | | |
523 | ((display_h_total & 7) << 16) | | |
524 | ((display_var->hsync_len & 7) << 8) | | |
41e583c2 | 525 | (hsync_pos & 7); |
6011bdea GL |
526 | lcdc_write_chan(ch, LDHAJR, tmp); |
527 | } | |
528 | ||
9a217e34 LP |
529 | /* |
530 | * __sh_mobile_lcdc_start - Configure and tart the LCDC | |
531 | * @priv: LCDC device | |
532 | * | |
533 | * Configure all enabled channels and start the LCDC device. All external | |
534 | * devices (clocks, MERAM, panels, ...) are not touched by this function. | |
535 | */ | |
536 | static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) | |
cfb4f5d1 MD |
537 | { |
538 | struct sh_mobile_lcdc_chan *ch; | |
cfb4f5d1 | 539 | unsigned long tmp; |
9a217e34 | 540 | int k, m; |
8564557a | 541 | |
9a217e34 LP |
542 | /* Enable LCDC channels. Read data from external memory, avoid using the |
543 | * BEU for now. | |
544 | */ | |
545 | lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled); | |
cfb4f5d1 | 546 | |
9a217e34 | 547 | /* Stop the LCDC first and disable all interrupts. */ |
cfb4f5d1 | 548 | sh_mobile_lcdc_start_stop(priv, 0); |
9a217e34 | 549 | lcdc_write(priv, _LDINTR, 0); |
cfb4f5d1 | 550 | |
9a217e34 | 551 | /* Configure power supply, dot clocks and start them. */ |
cfb4f5d1 MD |
552 | tmp = priv->lddckr; |
553 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
554 | ch = &priv->ch[k]; | |
9a217e34 | 555 | if (!ch->enabled) |
cfb4f5d1 MD |
556 | continue; |
557 | ||
9a217e34 LP |
558 | /* Power supply */ |
559 | lcdc_write_chan(ch, LDPMR, 0); | |
560 | ||
cfb4f5d1 MD |
561 | m = ch->cfg.clock_divider; |
562 | if (!m) | |
563 | continue; | |
564 | ||
505c7de5 LP |
565 | /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider |
566 | * denominator. | |
567 | */ | |
568 | lcdc_write_chan(ch, LDDCKPAT1R, 0); | |
569 | lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1); | |
570 | ||
cfb4f5d1 | 571 | if (m == 1) |
ce1c0b08 | 572 | m = LDDCKR_MOSEL; |
cfb4f5d1 | 573 | tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0); |
cfb4f5d1 MD |
574 | } |
575 | ||
576 | lcdc_write(priv, _LDDCKR, tmp); | |
cfb4f5d1 MD |
577 | lcdc_write(priv, _LDDCKSTPR, 0); |
578 | lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0); | |
579 | ||
9a217e34 | 580 | /* Setup geometry, format, frame buffer memory and operation mode. */ |
cfb4f5d1 MD |
581 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
582 | ch = &priv->ch[k]; | |
cfb4f5d1 MD |
583 | if (!ch->enabled) |
584 | continue; | |
585 | ||
6011bdea | 586 | sh_mobile_lcdc_geometry(ch); |
cfb4f5d1 | 587 | |
edd153a3 LP |
588 | switch (sh_mobile_format_fourcc(&ch->info->var)) { |
589 | case V4L2_PIX_FMT_RGB565: | |
590 | tmp = LDDFR_PKF_RGB16; | |
591 | break; | |
592 | case V4L2_PIX_FMT_BGR24: | |
593 | tmp = LDDFR_PKF_RGB24; | |
594 | break; | |
595 | case V4L2_PIX_FMT_BGR32: | |
596 | tmp = LDDFR_PKF_ARGB32; | |
597 | break; | |
598 | case V4L2_PIX_FMT_NV12: | |
599 | case V4L2_PIX_FMT_NV21: | |
600 | tmp = LDDFR_CC | LDDFR_YF_420; | |
601 | break; | |
602 | case V4L2_PIX_FMT_NV16: | |
603 | case V4L2_PIX_FMT_NV61: | |
604 | tmp = LDDFR_CC | LDDFR_YF_422; | |
605 | break; | |
606 | case V4L2_PIX_FMT_NV24: | |
607 | case V4L2_PIX_FMT_NV42: | |
608 | tmp = LDDFR_CC | LDDFR_YF_444; | |
609 | break; | |
610 | } | |
611 | ||
612 | if (sh_mobile_format_is_yuv(&ch->info->var)) { | |
613 | switch (ch->info->var.colorspace) { | |
614 | case V4L2_COLORSPACE_REC709: | |
615 | tmp |= LDDFR_CF1; | |
53b50314 | 616 | break; |
edd153a3 LP |
617 | case V4L2_COLORSPACE_JPEG: |
618 | tmp |= LDDFR_CF0; | |
53b50314 DHG |
619 | break; |
620 | } | |
417d4827 | 621 | } |
7caa4342 | 622 | |
9a217e34 LP |
623 | lcdc_write_chan(ch, LDDFR, tmp); |
624 | lcdc_write_chan(ch, LDMLSR, ch->pitch); | |
625 | lcdc_write_chan(ch, LDSA1R, ch->base_addr_y); | |
edd153a3 | 626 | if (sh_mobile_format_is_yuv(&ch->info->var)) |
9a217e34 | 627 | lcdc_write_chan(ch, LDSA2R, ch->base_addr_c); |
7caa4342 | 628 | |
9a217e34 LP |
629 | /* When using deferred I/O mode, configure the LCDC for one-shot |
630 | * operation and enable the frame end interrupt. Otherwise use | |
631 | * continuous read mode. | |
632 | */ | |
633 | if (ch->ldmt1r_value & LDMT1R_IFM && | |
634 | ch->cfg.sys_bus_cfg.deferred_io_msec) { | |
635 | lcdc_write_chan(ch, LDSM1R, LDSM1R_OS); | |
636 | lcdc_write(priv, _LDINTR, LDINTR_FE); | |
637 | } else { | |
638 | lcdc_write_chan(ch, LDSM1R, 0); | |
639 | } | |
640 | } | |
7caa4342 | 641 | |
9a217e34 | 642 | /* Word and long word swap. */ |
edd153a3 LP |
643 | switch (sh_mobile_format_fourcc(&priv->ch[0].info->var)) { |
644 | case V4L2_PIX_FMT_RGB565: | |
645 | case V4L2_PIX_FMT_NV21: | |
646 | case V4L2_PIX_FMT_NV61: | |
647 | case V4L2_PIX_FMT_NV42: | |
648 | tmp = LDDDSR_LS | LDDDSR_WS; | |
649 | break; | |
650 | case V4L2_PIX_FMT_BGR24: | |
651 | case V4L2_PIX_FMT_NV12: | |
652 | case V4L2_PIX_FMT_NV16: | |
653 | case V4L2_PIX_FMT_NV24: | |
9a217e34 | 654 | tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS; |
edd153a3 LP |
655 | break; |
656 | case V4L2_PIX_FMT_BGR32: | |
657 | default: | |
658 | tmp = LDDDSR_LS; | |
659 | break; | |
9a217e34 LP |
660 | } |
661 | lcdc_write(priv, _LDDDSR, tmp); | |
7caa4342 | 662 | |
9a217e34 LP |
663 | /* Enable the display output. */ |
664 | lcdc_write(priv, _LDCNT1R, LDCNT1R_DE); | |
665 | sh_mobile_lcdc_start_stop(priv, 1); | |
666 | priv->started = 1; | |
667 | } | |
cfb4f5d1 | 668 | |
9a217e34 LP |
669 | static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) |
670 | { | |
671 | struct sh_mobile_meram_info *mdev = priv->meram_dev; | |
9a217e34 LP |
672 | struct sh_mobile_lcdc_chan *ch; |
673 | unsigned long tmp; | |
674 | int ret; | |
675 | int k; | |
cfb4f5d1 | 676 | |
9a217e34 LP |
677 | /* enable clocks before accessing the hardware */ |
678 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
679 | if (priv->ch[k].enabled) | |
680 | sh_mobile_lcdc_clk_on(priv); | |
681 | } | |
8564557a | 682 | |
9a217e34 LP |
683 | /* reset */ |
684 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR); | |
685 | lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0); | |
8564557a | 686 | |
9a217e34 | 687 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
37c5dcc2 | 688 | struct sh_mobile_lcdc_board_cfg *board_cfg; |
8564557a | 689 | |
37c5dcc2 | 690 | ch = &priv->ch[k]; |
9a217e34 LP |
691 | if (!ch->enabled) |
692 | continue; | |
693 | ||
694 | board_cfg = &ch->cfg.board_cfg; | |
695 | if (board_cfg->setup_sys) { | |
696 | ret = board_cfg->setup_sys(board_cfg->board_data, ch, | |
697 | &sh_mobile_lcdc_sys_bus_ops); | |
698 | if (ret) | |
699 | return ret; | |
8564557a | 700 | } |
cfb4f5d1 MD |
701 | } |
702 | ||
9a217e34 LP |
703 | /* Compute frame buffer base address and pitch for each channel. */ |
704 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
705 | struct sh_mobile_meram_cfg *cfg; | |
706 | int pixelformat; | |
cfb4f5d1 | 707 | |
9a217e34 LP |
708 | ch = &priv->ch[k]; |
709 | if (!ch->enabled) | |
710 | continue; | |
cfb4f5d1 | 711 | |
9a217e34 LP |
712 | ch->base_addr_y = ch->info->fix.smem_start; |
713 | ch->base_addr_c = ch->base_addr_y | |
714 | + ch->info->var.xres | |
715 | * ch->info->var.yres_virtual; | |
716 | ch->pitch = ch->info->fix.line_length; | |
717 | ||
718 | /* Enable MERAM if possible. */ | |
719 | cfg = ch->cfg.meram_cfg; | |
720 | if (mdev == NULL || mdev->ops == NULL || cfg == NULL) | |
721 | continue; | |
722 | ||
723 | /* we need to de-init configured ICBs before we can | |
724 | * re-initialize them. | |
725 | */ | |
726 | if (ch->meram_enabled) { | |
727 | mdev->ops->meram_unregister(mdev, cfg); | |
728 | ch->meram_enabled = 0; | |
729 | } | |
730 | ||
edd153a3 LP |
731 | switch (sh_mobile_format_fourcc(&ch->info->var)) { |
732 | case V4L2_PIX_FMT_NV12: | |
733 | case V4L2_PIX_FMT_NV21: | |
734 | case V4L2_PIX_FMT_NV16: | |
735 | case V4L2_PIX_FMT_NV61: | |
9a217e34 | 736 | pixelformat = SH_MOBILE_MERAM_PF_NV; |
edd153a3 LP |
737 | break; |
738 | case V4L2_PIX_FMT_NV24: | |
739 | case V4L2_PIX_FMT_NV42: | |
740 | pixelformat = SH_MOBILE_MERAM_PF_NV24; | |
741 | break; | |
742 | case V4L2_PIX_FMT_RGB565: | |
743 | case V4L2_PIX_FMT_BGR24: | |
744 | case V4L2_PIX_FMT_BGR32: | |
745 | default: | |
746 | pixelformat = SH_MOBILE_MERAM_PF_RGB; | |
747 | break; | |
748 | } | |
9a217e34 LP |
749 | |
750 | ret = mdev->ops->meram_register(mdev, cfg, ch->pitch, | |
751 | ch->info->var.yres, pixelformat, | |
752 | ch->base_addr_y, ch->base_addr_c, | |
753 | &ch->base_addr_y, &ch->base_addr_c, | |
754 | &ch->pitch); | |
755 | if (!ret) | |
756 | ch->meram_enabled = 1; | |
757 | } | |
758 | ||
759 | /* Start the LCDC. */ | |
760 | __sh_mobile_lcdc_start(priv); | |
761 | ||
762 | /* Setup deferred I/O, tell the board code to enable the panels, and | |
763 | * turn backlight on. | |
764 | */ | |
cfb4f5d1 MD |
765 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
766 | ch = &priv->ch[k]; | |
21bc1f02 MD |
767 | if (!ch->enabled) |
768 | continue; | |
769 | ||
9a217e34 LP |
770 | tmp = ch->cfg.sys_bus_cfg.deferred_io_msec; |
771 | if (ch->ldmt1r_value & LDMT1R_IFM && tmp) { | |
772 | ch->defio.deferred_io = sh_mobile_lcdc_deferred_io; | |
773 | ch->defio.delay = msecs_to_jiffies(tmp); | |
774 | ch->info->fbdefio = &ch->defio; | |
775 | fb_deferred_io_init(ch->info); | |
776 | } | |
777 | ||
37c5dcc2 | 778 | sh_mobile_lcdc_display_on(ch); |
3b0fd9d7 AC |
779 | |
780 | if (ch->bl) { | |
781 | ch->bl->props.power = FB_BLANK_UNBLANK; | |
782 | backlight_update_status(ch->bl); | |
783 | } | |
cfb4f5d1 MD |
784 | } |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |
790 | { | |
791 | struct sh_mobile_lcdc_chan *ch; | |
cfb4f5d1 MD |
792 | int k; |
793 | ||
2feb075a | 794 | /* clean up deferred io and ask board code to disable panel */ |
cfb4f5d1 MD |
795 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
796 | ch = &priv->ch[k]; | |
21bc1f02 MD |
797 | if (!ch->enabled) |
798 | continue; | |
8564557a | 799 | |
2feb075a MD |
800 | /* deferred io mode: |
801 | * flush frame, and wait for frame end interrupt | |
802 | * clean up deferred io and enable clock | |
803 | */ | |
5ef6b505 | 804 | if (ch->info && ch->info->fbdefio) { |
2feb075a | 805 | ch->frame_end = 0; |
e33afddc | 806 | schedule_delayed_work(&ch->info->deferred_work, 0); |
2feb075a | 807 | wait_event(ch->frame_end_wait, ch->frame_end); |
e33afddc PM |
808 | fb_deferred_io_cleanup(ch->info); |
809 | ch->info->fbdefio = NULL; | |
2feb075a | 810 | sh_mobile_lcdc_clk_on(priv); |
8564557a | 811 | } |
2feb075a | 812 | |
3b0fd9d7 AC |
813 | if (ch->bl) { |
814 | ch->bl->props.power = FB_BLANK_POWERDOWN; | |
815 | backlight_update_status(ch->bl); | |
816 | } | |
817 | ||
37c5dcc2 | 818 | sh_mobile_lcdc_display_off(ch); |
7caa4342 DHG |
819 | |
820 | /* disable the meram */ | |
821 | if (ch->meram_enabled) { | |
822 | struct sh_mobile_meram_cfg *cfg; | |
823 | struct sh_mobile_meram_info *mdev; | |
824 | cfg = ch->cfg.meram_cfg; | |
825 | mdev = priv->meram_dev; | |
826 | mdev->ops->meram_unregister(mdev, cfg); | |
827 | ch->meram_enabled = 0; | |
828 | } | |
829 | ||
cfb4f5d1 MD |
830 | } |
831 | ||
832 | /* stop the lcdc */ | |
8e9bb19e MD |
833 | if (priv->started) { |
834 | sh_mobile_lcdc_start_stop(priv, 0); | |
835 | priv->started = 0; | |
836 | } | |
b51339ff | 837 | |
8564557a MD |
838 | /* stop clocks */ |
839 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
840 | if (priv->ch[k].enabled) | |
841 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
842 | } |
843 | ||
f1f60b5f LP |
844 | /* ----------------------------------------------------------------------------- |
845 | * Frame buffer operations | |
846 | */ | |
cfb4f5d1 MD |
847 | |
848 | static int sh_mobile_lcdc_setcolreg(u_int regno, | |
849 | u_int red, u_int green, u_int blue, | |
850 | u_int transp, struct fb_info *info) | |
851 | { | |
852 | u32 *palette = info->pseudo_palette; | |
853 | ||
854 | if (regno >= PALETTE_NR) | |
855 | return -EINVAL; | |
856 | ||
857 | /* only FB_VISUAL_TRUECOLOR supported */ | |
858 | ||
859 | red >>= 16 - info->var.red.length; | |
860 | green >>= 16 - info->var.green.length; | |
861 | blue >>= 16 - info->var.blue.length; | |
862 | transp >>= 16 - info->var.transp.length; | |
863 | ||
864 | palette[regno] = (red << info->var.red.offset) | | |
865 | (green << info->var.green.offset) | | |
866 | (blue << info->var.blue.offset) | | |
867 | (transp << info->var.transp.offset); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | static struct fb_fix_screeninfo sh_mobile_lcdc_fix = { | |
873 | .id = "SH Mobile LCDC", | |
874 | .type = FB_TYPE_PACKED_PIXELS, | |
875 | .visual = FB_VISUAL_TRUECOLOR, | |
876 | .accel = FB_ACCEL_NONE, | |
9dd38819 PE |
877 | .xpanstep = 0, |
878 | .ypanstep = 1, | |
879 | .ywrapstep = 0, | |
edd153a3 | 880 | .capabilities = FB_CAP_FOURCC, |
cfb4f5d1 MD |
881 | }; |
882 | ||
8564557a MD |
883 | static void sh_mobile_lcdc_fillrect(struct fb_info *info, |
884 | const struct fb_fillrect *rect) | |
885 | { | |
886 | sys_fillrect(info, rect); | |
887 | sh_mobile_lcdc_deferred_io_touch(info); | |
888 | } | |
889 | ||
890 | static void sh_mobile_lcdc_copyarea(struct fb_info *info, | |
891 | const struct fb_copyarea *area) | |
892 | { | |
893 | sys_copyarea(info, area); | |
894 | sh_mobile_lcdc_deferred_io_touch(info); | |
895 | } | |
896 | ||
897 | static void sh_mobile_lcdc_imageblit(struct fb_info *info, | |
898 | const struct fb_image *image) | |
899 | { | |
900 | sys_imageblit(info, image); | |
901 | sh_mobile_lcdc_deferred_io_touch(info); | |
902 | } | |
903 | ||
9dd38819 PE |
904 | static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var, |
905 | struct fb_info *info) | |
906 | { | |
907 | struct sh_mobile_lcdc_chan *ch = info->par; | |
92e1f9a7 PE |
908 | struct sh_mobile_lcdc_priv *priv = ch->lcdc; |
909 | unsigned long ldrcntr; | |
910 | unsigned long new_pan_offset; | |
53b50314 DHG |
911 | unsigned long base_addr_y, base_addr_c; |
912 | unsigned long c_offset; | |
edd153a3 | 913 | bool yuv = sh_mobile_format_is_yuv(&info->var); |
92e1f9a7 | 914 | |
edd153a3 | 915 | if (!yuv) |
dc1d5ada LP |
916 | new_pan_offset = var->yoffset * info->fix.line_length |
917 | + var->xoffset * (info->var.bits_per_pixel / 8); | |
53b50314 | 918 | else |
dc1d5ada LP |
919 | new_pan_offset = var->yoffset * info->fix.line_length |
920 | + var->xoffset; | |
9dd38819 | 921 | |
92e1f9a7 | 922 | if (new_pan_offset == ch->pan_offset) |
9dd38819 PE |
923 | return 0; /* No change, do nothing */ |
924 | ||
92e1f9a7 | 925 | ldrcntr = lcdc_read(priv, _LDRCNTR); |
9dd38819 | 926 | |
92e1f9a7 | 927 | /* Set the source address for the next refresh */ |
53b50314 | 928 | base_addr_y = ch->dma_handle + new_pan_offset; |
edd153a3 | 929 | if (yuv) { |
53b50314 | 930 | /* Set y offset */ |
dc1d5ada LP |
931 | c_offset = var->yoffset * info->fix.line_length |
932 | * (info->var.bits_per_pixel - 8) / 8; | |
933 | base_addr_c = ch->dma_handle | |
934 | + info->var.xres * info->var.yres_virtual | |
935 | + c_offset; | |
53b50314 | 936 | /* Set x offset */ |
edd153a3 | 937 | if (sh_mobile_format_fourcc(&info->var) == V4L2_PIX_FMT_NV24) |
53b50314 DHG |
938 | base_addr_c += 2 * var->xoffset; |
939 | else | |
940 | base_addr_c += var->xoffset; | |
49d79ba2 | 941 | } |
53b50314 | 942 | |
49d79ba2 | 943 | if (ch->meram_enabled) { |
7caa4342 DHG |
944 | struct sh_mobile_meram_cfg *cfg; |
945 | struct sh_mobile_meram_info *mdev; | |
7caa4342 DHG |
946 | int ret; |
947 | ||
948 | cfg = ch->cfg.meram_cfg; | |
949 | mdev = priv->meram_dev; | |
950 | ret = mdev->ops->meram_update(mdev, cfg, | |
951 | base_addr_y, base_addr_c, | |
49d79ba2 | 952 | &base_addr_y, &base_addr_c); |
7caa4342 DHG |
953 | if (ret) |
954 | return ret; | |
49d79ba2 | 955 | } |
7caa4342 | 956 | |
49d79ba2 LP |
957 | ch->base_addr_y = base_addr_y; |
958 | ch->base_addr_c = base_addr_c; | |
7caa4342 | 959 | |
49d79ba2 | 960 | lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y); |
edd153a3 | 961 | if (yuv) |
49d79ba2 | 962 | lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c); |
53b50314 | 963 | |
92e1f9a7 PE |
964 | if (lcdc_chan_is_sublcd(ch)) |
965 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); | |
966 | else | |
967 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS); | |
968 | ||
969 | ch->pan_offset = new_pan_offset; | |
970 | ||
971 | sh_mobile_lcdc_deferred_io_touch(info); | |
9dd38819 PE |
972 | |
973 | return 0; | |
974 | } | |
975 | ||
40331b21 PE |
976 | static int sh_mobile_wait_for_vsync(struct fb_info *info) |
977 | { | |
978 | struct sh_mobile_lcdc_chan *ch = info->par; | |
979 | unsigned long ldintr; | |
980 | int ret; | |
981 | ||
dc48665f LP |
982 | /* Enable VSync End interrupt and be careful not to acknowledge any |
983 | * pending interrupt. | |
984 | */ | |
40331b21 | 985 | ldintr = lcdc_read(ch->lcdc, _LDINTR); |
dc48665f | 986 | ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK; |
40331b21 PE |
987 | lcdc_write(ch->lcdc, _LDINTR, ldintr); |
988 | ||
989 | ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion, | |
990 | msecs_to_jiffies(100)); | |
991 | if (!ret) | |
992 | return -ETIMEDOUT; | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd, | |
998 | unsigned long arg) | |
999 | { | |
1000 | int retval; | |
1001 | ||
1002 | switch (cmd) { | |
1003 | case FBIO_WAITFORVSYNC: | |
1004 | retval = sh_mobile_wait_for_vsync(info); | |
1005 | break; | |
1006 | ||
1007 | default: | |
1008 | retval = -ENOIOCTLCMD; | |
1009 | break; | |
1010 | } | |
1011 | return retval; | |
1012 | } | |
1013 | ||
dd210503 GL |
1014 | static void sh_mobile_fb_reconfig(struct fb_info *info) |
1015 | { | |
1016 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1017 | struct fb_videomode mode1, mode2; | |
1018 | struct fb_event event; | |
1019 | int evnt = FB_EVENT_MODE_CHANGE_ALL; | |
1020 | ||
1021 | if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par)) | |
1022 | /* More framebuffer users are active */ | |
1023 | return; | |
1024 | ||
1025 | fb_var_to_videomode(&mode1, &ch->display_var); | |
1026 | fb_var_to_videomode(&mode2, &info->var); | |
1027 | ||
1028 | if (fb_mode_is_equal(&mode1, &mode2)) | |
1029 | return; | |
1030 | ||
1031 | /* Display has been re-plugged, framebuffer is free now, reconfigure */ | |
1032 | if (fb_set_var(info, &ch->display_var) < 0) | |
1033 | /* Couldn't reconfigure, hopefully, can continue as before */ | |
1034 | return; | |
1035 | ||
dd210503 GL |
1036 | /* |
1037 | * fb_set_var() calls the notifier change internally, only if | |
1038 | * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a | |
1039 | * user event, we have to call the chain ourselves. | |
1040 | */ | |
1041 | event.info = info; | |
cc267ec5 | 1042 | event.data = &mode1; |
dd210503 GL |
1043 | fb_notifier_call_chain(evnt, &event); |
1044 | } | |
1045 | ||
1046 | /* | |
1047 | * Locking: both .fb_release() and .fb_open() are called with info->lock held if | |
1048 | * user == 1, or with console sem held, if user == 0. | |
1049 | */ | |
1050 | static int sh_mobile_release(struct fb_info *info, int user) | |
1051 | { | |
1052 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1053 | ||
1054 | mutex_lock(&ch->open_lock); | |
1055 | dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count); | |
1056 | ||
1057 | ch->use_count--; | |
1058 | ||
1059 | /* Nothing to reconfigure, when called from fbcon */ | |
1060 | if (user) { | |
ac751efa | 1061 | console_lock(); |
dd210503 | 1062 | sh_mobile_fb_reconfig(info); |
ac751efa | 1063 | console_unlock(); |
dd210503 GL |
1064 | } |
1065 | ||
1066 | mutex_unlock(&ch->open_lock); | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | static int sh_mobile_open(struct fb_info *info, int user) | |
1072 | { | |
1073 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1074 | ||
1075 | mutex_lock(&ch->open_lock); | |
1076 | ch->use_count++; | |
1077 | ||
1078 | dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count); | |
1079 | mutex_unlock(&ch->open_lock); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
1085 | { | |
1086 | struct sh_mobile_lcdc_chan *ch = info->par; | |
417d4827 | 1087 | struct sh_mobile_lcdc_priv *p = ch->lcdc; |
03862194 LP |
1088 | unsigned int best_dist = (unsigned int)-1; |
1089 | unsigned int best_xres = 0; | |
1090 | unsigned int best_yres = 0; | |
1091 | unsigned int i; | |
dd210503 | 1092 | |
03862194 | 1093 | if (var->xres > MAX_XRES || var->yres > MAX_YRES) |
dd210503 | 1094 | return -EINVAL; |
03862194 LP |
1095 | |
1096 | /* If board code provides us with a list of available modes, make sure | |
1097 | * we use one of them. Find the mode closest to the requested one. The | |
1098 | * distance between two modes is defined as the size of the | |
1099 | * non-overlapping parts of the two rectangles. | |
1100 | */ | |
1101 | for (i = 0; i < ch->cfg.num_cfg; ++i) { | |
1102 | const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i]; | |
1103 | unsigned int dist; | |
1104 | ||
1105 | /* We can only round up. */ | |
1106 | if (var->xres > mode->xres || var->yres > mode->yres) | |
1107 | continue; | |
1108 | ||
1109 | dist = var->xres * var->yres + mode->xres * mode->yres | |
1110 | - 2 * min(var->xres, mode->xres) | |
1111 | * min(var->yres, mode->yres); | |
1112 | ||
1113 | if (dist < best_dist) { | |
1114 | best_xres = mode->xres; | |
1115 | best_yres = mode->yres; | |
1116 | best_dist = dist; | |
1117 | } | |
dd210503 | 1118 | } |
417d4827 | 1119 | |
03862194 LP |
1120 | /* If no available mode can be used, return an error. */ |
1121 | if (ch->cfg.num_cfg != 0) { | |
1122 | if (best_dist == (unsigned int)-1) | |
1123 | return -EINVAL; | |
1124 | ||
1125 | var->xres = best_xres; | |
1126 | var->yres = best_yres; | |
1127 | } | |
1128 | ||
1129 | /* Make sure the virtual resolution is at least as big as the visible | |
1130 | * resolution. | |
1131 | */ | |
1132 | if (var->xres_virtual < var->xres) | |
1133 | var->xres_virtual = var->xres; | |
1134 | if (var->yres_virtual < var->yres) | |
1135 | var->yres_virtual = var->yres; | |
1136 | ||
edd153a3 LP |
1137 | if (sh_mobile_format_is_fourcc(var)) { |
1138 | switch (var->grayscale) { | |
1139 | case V4L2_PIX_FMT_NV12: | |
1140 | case V4L2_PIX_FMT_NV21: | |
1141 | var->bits_per_pixel = 12; | |
1142 | break; | |
1143 | case V4L2_PIX_FMT_RGB565: | |
1144 | case V4L2_PIX_FMT_NV16: | |
1145 | case V4L2_PIX_FMT_NV61: | |
1146 | var->bits_per_pixel = 16; | |
1147 | break; | |
1148 | case V4L2_PIX_FMT_BGR24: | |
1149 | case V4L2_PIX_FMT_NV24: | |
1150 | case V4L2_PIX_FMT_NV42: | |
1151 | var->bits_per_pixel = 24; | |
1152 | break; | |
1153 | case V4L2_PIX_FMT_BGR32: | |
1154 | var->bits_per_pixel = 32; | |
1155 | break; | |
1156 | default: | |
1157 | return -EINVAL; | |
1158 | } | |
1159 | ||
1160 | /* Default to RGB and JPEG color-spaces for RGB and YUV formats | |
1161 | * respectively. | |
1162 | */ | |
1163 | if (!sh_mobile_format_is_yuv(var)) | |
1164 | var->colorspace = V4L2_COLORSPACE_SRGB; | |
1165 | else if (var->colorspace != V4L2_COLORSPACE_REC709) | |
1166 | var->colorspace = V4L2_COLORSPACE_JPEG; | |
1167 | } else { | |
1168 | if (var->bits_per_pixel <= 16) { /* RGB 565 */ | |
1169 | var->bits_per_pixel = 16; | |
1170 | var->red.offset = 11; | |
1171 | var->red.length = 5; | |
1172 | var->green.offset = 5; | |
1173 | var->green.length = 6; | |
1174 | var->blue.offset = 0; | |
1175 | var->blue.length = 5; | |
1176 | var->transp.offset = 0; | |
1177 | var->transp.length = 0; | |
1178 | } else if (var->bits_per_pixel <= 24) { /* RGB 888 */ | |
1179 | var->bits_per_pixel = 24; | |
1180 | var->red.offset = 16; | |
1181 | var->red.length = 8; | |
1182 | var->green.offset = 8; | |
1183 | var->green.length = 8; | |
1184 | var->blue.offset = 0; | |
1185 | var->blue.length = 8; | |
1186 | var->transp.offset = 0; | |
1187 | var->transp.length = 0; | |
1188 | } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */ | |
1189 | var->bits_per_pixel = 32; | |
1190 | var->red.offset = 16; | |
1191 | var->red.length = 8; | |
1192 | var->green.offset = 8; | |
1193 | var->green.length = 8; | |
1194 | var->blue.offset = 0; | |
1195 | var->blue.length = 8; | |
1196 | var->transp.offset = 24; | |
1197 | var->transp.length = 8; | |
1198 | } else | |
1199 | return -EINVAL; | |
417d4827 | 1200 | |
edd153a3 LP |
1201 | var->red.msb_right = 0; |
1202 | var->green.msb_right = 0; | |
1203 | var->blue.msb_right = 0; | |
1204 | var->transp.msb_right = 0; | |
1205 | } | |
03862194 LP |
1206 | |
1207 | /* Make sure we don't exceed our allocated memory. */ | |
1208 | if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 > | |
1209 | info->fix.smem_len) | |
1210 | return -EINVAL; | |
1211 | ||
edd153a3 LP |
1212 | /* only accept the forced_fourcc for dual channel configurations */ |
1213 | if (p->forced_fourcc && | |
1214 | p->forced_fourcc != sh_mobile_format_fourcc(var)) | |
417d4827 | 1215 | return -EINVAL; |
417d4827 | 1216 | |
dd210503 GL |
1217 | return 0; |
1218 | } | |
40331b21 | 1219 | |
ed5bebf2 LP |
1220 | static int sh_mobile_set_par(struct fb_info *info) |
1221 | { | |
1222 | struct sh_mobile_lcdc_chan *ch = info->par; | |
91fba48d | 1223 | u32 line_length = info->fix.line_length; |
ed5bebf2 LP |
1224 | int ret; |
1225 | ||
1226 | sh_mobile_lcdc_stop(ch->lcdc); | |
91fba48d | 1227 | |
edd153a3 | 1228 | if (sh_mobile_format_is_yuv(&info->var)) |
91fba48d LP |
1229 | info->fix.line_length = info->var.xres; |
1230 | else | |
1231 | info->fix.line_length = info->var.xres | |
1232 | * info->var.bits_per_pixel / 8; | |
1233 | ||
ed5bebf2 | 1234 | ret = sh_mobile_lcdc_start(ch->lcdc); |
91fba48d | 1235 | if (ret < 0) { |
ed5bebf2 | 1236 | dev_err(info->dev, "%s: unable to restart LCDC\n", __func__); |
91fba48d LP |
1237 | info->fix.line_length = line_length; |
1238 | } | |
ed5bebf2 | 1239 | |
edd153a3 LP |
1240 | if (sh_mobile_format_is_fourcc(&info->var)) { |
1241 | info->fix.type = FB_TYPE_FOURCC; | |
1242 | info->fix.visual = FB_VISUAL_FOURCC; | |
1243 | } else { | |
1244 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
1245 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
1246 | } | |
1247 | ||
ed5bebf2 LP |
1248 | return ret; |
1249 | } | |
1250 | ||
8857b9aa AC |
1251 | /* |
1252 | * Screen blanking. Behavior is as follows: | |
1253 | * FB_BLANK_UNBLANK: screen unblanked, clocks enabled | |
1254 | * FB_BLANK_NORMAL: screen blanked, clocks enabled | |
1255 | * FB_BLANK_VSYNC, | |
1256 | * FB_BLANK_HSYNC, | |
1257 | * FB_BLANK_POWEROFF: screen blanked, clocks disabled | |
1258 | */ | |
1259 | static int sh_mobile_lcdc_blank(int blank, struct fb_info *info) | |
1260 | { | |
1261 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1262 | struct sh_mobile_lcdc_priv *p = ch->lcdc; | |
1263 | ||
1264 | /* blank the screen? */ | |
1265 | if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) { | |
1266 | struct fb_fillrect rect = { | |
1267 | .width = info->var.xres, | |
1268 | .height = info->var.yres, | |
1269 | }; | |
1270 | sh_mobile_lcdc_fillrect(info, &rect); | |
1271 | } | |
1272 | /* turn clocks on? */ | |
1273 | if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) { | |
1274 | sh_mobile_lcdc_clk_on(p); | |
1275 | } | |
1276 | /* turn clocks off? */ | |
1277 | if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) { | |
1278 | /* make sure the screen is updated with the black fill before | |
1279 | * switching the clocks off. one vsync is not enough since | |
1280 | * blanking may occur in the middle of a refresh. deferred io | |
1281 | * mode will reenable the clocks and update the screen in time, | |
1282 | * so it does not need this. */ | |
1283 | if (!info->fbdefio) { | |
1284 | sh_mobile_wait_for_vsync(info); | |
1285 | sh_mobile_wait_for_vsync(info); | |
1286 | } | |
1287 | sh_mobile_lcdc_clk_off(p); | |
1288 | } | |
1289 | ||
1290 | ch->blank_status = blank; | |
1291 | return 0; | |
1292 | } | |
1293 | ||
cfb4f5d1 | 1294 | static struct fb_ops sh_mobile_lcdc_ops = { |
9dd38819 | 1295 | .owner = THIS_MODULE, |
cfb4f5d1 | 1296 | .fb_setcolreg = sh_mobile_lcdc_setcolreg, |
2540c111 MD |
1297 | .fb_read = fb_sys_read, |
1298 | .fb_write = fb_sys_write, | |
8564557a MD |
1299 | .fb_fillrect = sh_mobile_lcdc_fillrect, |
1300 | .fb_copyarea = sh_mobile_lcdc_copyarea, | |
1301 | .fb_imageblit = sh_mobile_lcdc_imageblit, | |
8857b9aa | 1302 | .fb_blank = sh_mobile_lcdc_blank, |
9dd38819 | 1303 | .fb_pan_display = sh_mobile_fb_pan_display, |
40331b21 | 1304 | .fb_ioctl = sh_mobile_ioctl, |
dd210503 GL |
1305 | .fb_open = sh_mobile_open, |
1306 | .fb_release = sh_mobile_release, | |
1307 | .fb_check_var = sh_mobile_check_var, | |
ed5bebf2 | 1308 | .fb_set_par = sh_mobile_set_par, |
cfb4f5d1 MD |
1309 | }; |
1310 | ||
f1f60b5f LP |
1311 | /* ----------------------------------------------------------------------------- |
1312 | * Backlight | |
1313 | */ | |
1314 | ||
3b0fd9d7 AC |
1315 | static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev) |
1316 | { | |
1317 | struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev); | |
1318 | struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg; | |
1319 | int brightness = bdev->props.brightness; | |
1320 | ||
1321 | if (bdev->props.power != FB_BLANK_UNBLANK || | |
1322 | bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) | |
1323 | brightness = 0; | |
1324 | ||
1325 | return cfg->set_brightness(cfg->board_data, brightness); | |
1326 | } | |
1327 | ||
1328 | static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev) | |
1329 | { | |
1330 | struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev); | |
1331 | struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg; | |
1332 | ||
1333 | return cfg->get_brightness(cfg->board_data); | |
1334 | } | |
1335 | ||
1336 | static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev, | |
1337 | struct fb_info *info) | |
1338 | { | |
1339 | return (info->bl_dev == bdev); | |
1340 | } | |
1341 | ||
1342 | static struct backlight_ops sh_mobile_lcdc_bl_ops = { | |
1343 | .options = BL_CORE_SUSPENDRESUME, | |
1344 | .update_status = sh_mobile_lcdc_update_bl, | |
1345 | .get_brightness = sh_mobile_lcdc_get_brightness, | |
1346 | .check_fb = sh_mobile_lcdc_check_fb, | |
1347 | }; | |
1348 | ||
1349 | static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent, | |
1350 | struct sh_mobile_lcdc_chan *ch) | |
1351 | { | |
1352 | struct backlight_device *bl; | |
1353 | ||
1354 | bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch, | |
1355 | &sh_mobile_lcdc_bl_ops, NULL); | |
beee1f20 DC |
1356 | if (IS_ERR(bl)) { |
1357 | dev_err(parent, "unable to register backlight device: %ld\n", | |
1358 | PTR_ERR(bl)); | |
3b0fd9d7 AC |
1359 | return NULL; |
1360 | } | |
1361 | ||
1362 | bl->props.max_brightness = ch->cfg.bl_info.max_brightness; | |
1363 | bl->props.brightness = bl->props.max_brightness; | |
1364 | backlight_update_status(bl); | |
1365 | ||
1366 | return bl; | |
1367 | } | |
1368 | ||
1369 | static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev) | |
1370 | { | |
1371 | backlight_device_unregister(bdev); | |
1372 | } | |
1373 | ||
f1f60b5f LP |
1374 | /* ----------------------------------------------------------------------------- |
1375 | * Power management | |
1376 | */ | |
1377 | ||
2feb075a MD |
1378 | static int sh_mobile_lcdc_suspend(struct device *dev) |
1379 | { | |
1380 | struct platform_device *pdev = to_platform_device(dev); | |
1381 | ||
1382 | sh_mobile_lcdc_stop(platform_get_drvdata(pdev)); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | static int sh_mobile_lcdc_resume(struct device *dev) | |
1387 | { | |
1388 | struct platform_device *pdev = to_platform_device(dev); | |
1389 | ||
1390 | return sh_mobile_lcdc_start(platform_get_drvdata(pdev)); | |
1391 | } | |
1392 | ||
0246c471 MD |
1393 | static int sh_mobile_lcdc_runtime_suspend(struct device *dev) |
1394 | { | |
1395 | struct platform_device *pdev = to_platform_device(dev); | |
2427bb24 | 1396 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); |
0246c471 MD |
1397 | |
1398 | /* turn off LCDC hardware */ | |
2427bb24 LP |
1399 | lcdc_write(priv, _LDCNT1R, 0); |
1400 | ||
0246c471 MD |
1401 | return 0; |
1402 | } | |
1403 | ||
1404 | static int sh_mobile_lcdc_runtime_resume(struct device *dev) | |
1405 | { | |
1406 | struct platform_device *pdev = to_platform_device(dev); | |
2427bb24 | 1407 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); |
0246c471 | 1408 | |
2427bb24 | 1409 | __sh_mobile_lcdc_start(priv); |
0246c471 MD |
1410 | |
1411 | return 0; | |
1412 | } | |
1413 | ||
47145210 | 1414 | static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { |
2feb075a MD |
1415 | .suspend = sh_mobile_lcdc_suspend, |
1416 | .resume = sh_mobile_lcdc_resume, | |
0246c471 MD |
1417 | .runtime_suspend = sh_mobile_lcdc_runtime_suspend, |
1418 | .runtime_resume = sh_mobile_lcdc_runtime_resume, | |
2feb075a MD |
1419 | }; |
1420 | ||
f1f60b5f LP |
1421 | /* ----------------------------------------------------------------------------- |
1422 | * Framebuffer notifier | |
1423 | */ | |
1424 | ||
6de9edd5 | 1425 | /* locking: called with info->lock held */ |
6011bdea GL |
1426 | static int sh_mobile_lcdc_notify(struct notifier_block *nb, |
1427 | unsigned long action, void *data) | |
1428 | { | |
1429 | struct fb_event *event = data; | |
1430 | struct fb_info *info = event->info; | |
1431 | struct sh_mobile_lcdc_chan *ch = info->par; | |
6011bdea GL |
1432 | |
1433 | if (&ch->lcdc->notifier != nb) | |
baf16374 | 1434 | return NOTIFY_DONE; |
6011bdea GL |
1435 | |
1436 | dev_dbg(info->dev, "%s(): action = %lu, data = %p\n", | |
1437 | __func__, action, event->data); | |
1438 | ||
1439 | switch(action) { | |
1440 | case FB_EVENT_SUSPEND: | |
37c5dcc2 | 1441 | sh_mobile_lcdc_display_off(ch); |
afe417c0 | 1442 | sh_mobile_lcdc_stop(ch->lcdc); |
6011bdea GL |
1443 | break; |
1444 | case FB_EVENT_RESUME: | |
dd210503 GL |
1445 | mutex_lock(&ch->open_lock); |
1446 | sh_mobile_fb_reconfig(info); | |
1447 | mutex_unlock(&ch->open_lock); | |
6011bdea | 1448 | |
37c5dcc2 | 1449 | sh_mobile_lcdc_display_on(ch); |
ebe5e12d | 1450 | sh_mobile_lcdc_start(ch->lcdc); |
6011bdea GL |
1451 | } |
1452 | ||
baf16374 | 1453 | return NOTIFY_OK; |
6011bdea GL |
1454 | } |
1455 | ||
f1f60b5f LP |
1456 | /* ----------------------------------------------------------------------------- |
1457 | * Probe/remove and driver init/exit | |
1458 | */ | |
1459 | ||
217e9c43 | 1460 | static const struct fb_videomode default_720p __devinitconst = { |
f1f60b5f LP |
1461 | .name = "HDMI 720p", |
1462 | .xres = 1280, | |
1463 | .yres = 720, | |
1464 | ||
1465 | .left_margin = 220, | |
1466 | .right_margin = 110, | |
1467 | .hsync_len = 40, | |
1468 | ||
1469 | .upper_margin = 20, | |
1470 | .lower_margin = 5, | |
1471 | .vsync_len = 5, | |
1472 | ||
1473 | .pixclock = 13468, | |
1474 | .refresh = 60, | |
1475 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, | |
1476 | }; | |
1477 | ||
b4bee692 LP |
1478 | static int sh_mobile_lcdc_remove(struct platform_device *pdev) |
1479 | { | |
1480 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); | |
1481 | struct fb_info *info; | |
1482 | int i; | |
1483 | ||
1484 | fb_unregister_client(&priv->notifier); | |
1485 | ||
1486 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) | |
1487 | if (priv->ch[i].info && priv->ch[i].info->dev) | |
1488 | unregister_framebuffer(priv->ch[i].info); | |
1489 | ||
1490 | sh_mobile_lcdc_stop(priv); | |
1491 | ||
1492 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
1493 | info = priv->ch[i].info; | |
1494 | ||
1495 | if (!info || !info->device) | |
1496 | continue; | |
1497 | ||
1498 | if (priv->ch[i].sglist) | |
1499 | vfree(priv->ch[i].sglist); | |
1500 | ||
1501 | if (info->screen_base) | |
1502 | dma_free_coherent(&pdev->dev, info->fix.smem_len, | |
1503 | info->screen_base, | |
1504 | priv->ch[i].dma_handle); | |
1505 | fb_dealloc_cmap(&info->cmap); | |
1506 | framebuffer_release(info); | |
1507 | } | |
1508 | ||
1509 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
1510 | if (priv->ch[i].bl) | |
1511 | sh_mobile_lcdc_bl_remove(priv->ch[i].bl); | |
1512 | } | |
1513 | ||
4774c12a LP |
1514 | if (priv->dot_clk) { |
1515 | pm_runtime_disable(&pdev->dev); | |
b4bee692 | 1516 | clk_put(priv->dot_clk); |
4774c12a | 1517 | } |
b4bee692 LP |
1518 | |
1519 | if (priv->base) | |
1520 | iounmap(priv->base); | |
1521 | ||
1522 | if (priv->irq) | |
1523 | free_irq(priv->irq, priv); | |
1524 | kfree(priv); | |
1525 | return 0; | |
1526 | } | |
cfb4f5d1 | 1527 | |
217e9c43 | 1528 | static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch) |
f1f60b5f LP |
1529 | { |
1530 | int interface_type = ch->cfg.interface_type; | |
1531 | ||
1532 | switch (interface_type) { | |
1533 | case RGB8: | |
1534 | case RGB9: | |
1535 | case RGB12A: | |
1536 | case RGB12B: | |
1537 | case RGB16: | |
1538 | case RGB18: | |
1539 | case RGB24: | |
1540 | case SYS8A: | |
1541 | case SYS8B: | |
1542 | case SYS8C: | |
1543 | case SYS8D: | |
1544 | case SYS9: | |
1545 | case SYS12: | |
1546 | case SYS16A: | |
1547 | case SYS16B: | |
1548 | case SYS16C: | |
1549 | case SYS18: | |
1550 | case SYS24: | |
1551 | break; | |
1552 | default: | |
1553 | return -EINVAL; | |
1554 | } | |
1555 | ||
1556 | /* SUBLCD only supports SYS interface */ | |
1557 | if (lcdc_chan_is_sublcd(ch)) { | |
1558 | if (!(interface_type & LDMT1R_IFM)) | |
1559 | return -EINVAL; | |
1560 | ||
1561 | interface_type &= ~LDMT1R_IFM; | |
1562 | } | |
1563 | ||
1564 | ch->ldmt1r_value = interface_type; | |
1565 | return 0; | |
1566 | } | |
1567 | ||
0a7f17aa LP |
1568 | static int __devinit |
1569 | sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_priv *priv, | |
1570 | struct sh_mobile_lcdc_chan *ch) | |
cfb4f5d1 | 1571 | { |
3ce05599 LP |
1572 | struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg; |
1573 | const struct fb_videomode *max_mode; | |
1574 | const struct fb_videomode *mode; | |
1575 | struct fb_var_screeninfo *var; | |
cfb4f5d1 | 1576 | struct fb_info *info; |
3ce05599 LP |
1577 | unsigned int max_size; |
1578 | int num_cfg; | |
1579 | void *buf; | |
1580 | int ret; | |
1581 | int i; | |
1582 | ||
a67472ad LP |
1583 | mutex_init(&ch->open_lock); |
1584 | ||
1585 | /* Allocate the frame buffer device. */ | |
0a7f17aa | 1586 | ch->info = framebuffer_alloc(0, priv->dev); |
3ce05599 | 1587 | if (!ch->info) { |
0a7f17aa | 1588 | dev_err(priv->dev, "unable to allocate fb_info\n"); |
3ce05599 LP |
1589 | return -ENOMEM; |
1590 | } | |
1591 | ||
1592 | info = ch->info; | |
3ce05599 LP |
1593 | info->fbops = &sh_mobile_lcdc_ops; |
1594 | info->par = ch; | |
a67472ad LP |
1595 | info->pseudo_palette = &ch->pseudo_palette; |
1596 | info->flags = FBINFO_FLAG_DEFAULT; | |
3ce05599 LP |
1597 | |
1598 | /* Iterate through the modes to validate them and find the highest | |
1599 | * resolution. | |
1600 | */ | |
1601 | max_mode = NULL; | |
1602 | max_size = 0; | |
1603 | ||
1604 | for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) { | |
1605 | unsigned int size = mode->yres * mode->xres; | |
1606 | ||
edd153a3 LP |
1607 | /* NV12/NV21 buffers must have even number of lines */ |
1608 | if ((cfg->fourcc == V4L2_PIX_FMT_NV12 || | |
1609 | cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) { | |
0a7f17aa LP |
1610 | dev_err(priv->dev, "yres must be multiple of 2 for " |
1611 | "YCbCr420 mode.\n"); | |
3ce05599 LP |
1612 | return -EINVAL; |
1613 | } | |
1614 | ||
1615 | if (size > max_size) { | |
1616 | max_mode = mode; | |
1617 | max_size = size; | |
1618 | } | |
1619 | } | |
1620 | ||
1621 | if (!max_size) | |
1622 | max_size = MAX_XRES * MAX_YRES; | |
1623 | else | |
0a7f17aa | 1624 | dev_dbg(priv->dev, "Found largest videomode %ux%u\n", |
3ce05599 LP |
1625 | max_mode->xres, max_mode->yres); |
1626 | ||
a67472ad | 1627 | /* Create the mode list. */ |
3ce05599 LP |
1628 | if (cfg->lcd_cfg == NULL) { |
1629 | mode = &default_720p; | |
1630 | num_cfg = 1; | |
1631 | } else { | |
1632 | mode = cfg->lcd_cfg; | |
1633 | num_cfg = cfg->num_cfg; | |
1634 | } | |
1635 | ||
1636 | fb_videomode_to_modelist(mode, num_cfg, &info->modelist); | |
1637 | ||
a67472ad LP |
1638 | /* Initialize variable screen information using the first mode as |
1639 | * default. The default Y virtual resolution is twice the panel size to | |
1640 | * allow for double-buffering. | |
1641 | */ | |
1642 | var = &info->var; | |
3ce05599 LP |
1643 | fb_videomode_to_var(var, mode); |
1644 | var->width = cfg->lcd_size_cfg.width; | |
1645 | var->height = cfg->lcd_size_cfg.height; | |
3ce05599 LP |
1646 | var->yres_virtual = var->yres * 2; |
1647 | var->activate = FB_ACTIVATE_NOW; | |
1648 | ||
edd153a3 LP |
1649 | switch (cfg->fourcc) { |
1650 | case V4L2_PIX_FMT_RGB565: | |
1651 | var->bits_per_pixel = 16; | |
1652 | break; | |
1653 | case V4L2_PIX_FMT_BGR24: | |
1654 | var->bits_per_pixel = 24; | |
1655 | break; | |
1656 | case V4L2_PIX_FMT_BGR32: | |
1657 | var->bits_per_pixel = 32; | |
1658 | break; | |
1659 | default: | |
1660 | var->grayscale = cfg->fourcc; | |
1661 | break; | |
1662 | } | |
1663 | ||
1664 | /* Make sure the memory size check won't fail. smem_len is initialized | |
1665 | * later based on var. | |
1666 | */ | |
1667 | info->fix.smem_len = UINT_MAX; | |
a67472ad | 1668 | ret = sh_mobile_check_var(var, info); |
3ce05599 LP |
1669 | if (ret) |
1670 | return ret; | |
1671 | ||
edd153a3 LP |
1672 | max_size = max_size * var->bits_per_pixel / 8 * 2; |
1673 | ||
a67472ad | 1674 | /* Allocate frame buffer memory and color map. */ |
0a7f17aa LP |
1675 | buf = dma_alloc_coherent(priv->dev, max_size, &ch->dma_handle, |
1676 | GFP_KERNEL); | |
3ce05599 | 1677 | if (!buf) { |
0a7f17aa | 1678 | dev_err(priv->dev, "unable to allocate buffer\n"); |
3ce05599 LP |
1679 | return -ENOMEM; |
1680 | } | |
1681 | ||
3ce05599 LP |
1682 | ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0); |
1683 | if (ret < 0) { | |
0a7f17aa LP |
1684 | dev_err(priv->dev, "unable to allocate cmap\n"); |
1685 | dma_free_coherent(priv->dev, max_size, buf, ch->dma_handle); | |
3ce05599 LP |
1686 | return ret; |
1687 | } | |
1688 | ||
edd153a3 LP |
1689 | /* Initialize fixed screen information. Restrict pan to 2 lines steps |
1690 | * for NV12 and NV21. | |
1691 | */ | |
1692 | info->fix = sh_mobile_lcdc_fix; | |
3ce05599 | 1693 | info->fix.smem_start = ch->dma_handle; |
edd153a3 LP |
1694 | info->fix.smem_len = max_size; |
1695 | if (cfg->fourcc == V4L2_PIX_FMT_NV12 || | |
1696 | cfg->fourcc == V4L2_PIX_FMT_NV21) | |
1697 | info->fix.ypanstep = 2; | |
1698 | ||
1699 | if (sh_mobile_format_is_yuv(var)) { | |
3ce05599 | 1700 | info->fix.line_length = var->xres; |
edd153a3 LP |
1701 | info->fix.visual = FB_VISUAL_FOURCC; |
1702 | } else { | |
1703 | info->fix.line_length = var->xres * var->bits_per_pixel / 8; | |
1704 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
1705 | } | |
3ce05599 LP |
1706 | |
1707 | info->screen_base = buf; | |
0a7f17aa | 1708 | info->device = priv->dev; |
3ce05599 LP |
1709 | ch->display_var = *var; |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev) | |
1715 | { | |
01ac25b5 | 1716 | struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data; |
3ce05599 | 1717 | struct sh_mobile_lcdc_priv *priv; |
cfb4f5d1 | 1718 | struct resource *res; |
3ce05599 | 1719 | int num_channels; |
cfb4f5d1 | 1720 | int error; |
3ce05599 | 1721 | int i; |
cfb4f5d1 | 1722 | |
01ac25b5 | 1723 | if (!pdata) { |
cfb4f5d1 | 1724 | dev_err(&pdev->dev, "no platform data defined\n"); |
8bed9055 | 1725 | return -EINVAL; |
cfb4f5d1 MD |
1726 | } |
1727 | ||
1728 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8564557a MD |
1729 | i = platform_get_irq(pdev, 0); |
1730 | if (!res || i < 0) { | |
1731 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
8bed9055 | 1732 | return -ENOENT; |
cfb4f5d1 MD |
1733 | } |
1734 | ||
1735 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1736 | if (!priv) { | |
1737 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
8bed9055 | 1738 | return -ENOMEM; |
cfb4f5d1 MD |
1739 | } |
1740 | ||
4774c12a LP |
1741 | priv->dev = &pdev->dev; |
1742 | priv->meram_dev = pdata->meram_dev; | |
8bed9055 GL |
1743 | platform_set_drvdata(pdev, priv); |
1744 | ||
f8798ccb | 1745 | error = request_irq(i, sh_mobile_lcdc_irq, 0, |
7ad33e74 | 1746 | dev_name(&pdev->dev), priv); |
8564557a MD |
1747 | if (error) { |
1748 | dev_err(&pdev->dev, "unable to request irq\n"); | |
1749 | goto err1; | |
1750 | } | |
1751 | ||
1752 | priv->irq = i; | |
5ef6b505 | 1753 | atomic_set(&priv->hw_usecnt, -1); |
cfb4f5d1 | 1754 | |
3ce05599 LP |
1755 | for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) { |
1756 | struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels; | |
cfb4f5d1 | 1757 | |
01ac25b5 GL |
1758 | ch->lcdc = priv; |
1759 | memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i])); | |
cfb4f5d1 | 1760 | |
01ac25b5 | 1761 | error = sh_mobile_lcdc_check_interface(ch); |
cfb4f5d1 MD |
1762 | if (error) { |
1763 | dev_err(&pdev->dev, "unsupported interface type\n"); | |
1764 | goto err1; | |
1765 | } | |
01ac25b5 GL |
1766 | init_waitqueue_head(&ch->frame_end_wait); |
1767 | init_completion(&ch->vsync_completion); | |
1768 | ch->pan_offset = 0; | |
cfb4f5d1 | 1769 | |
3b0fd9d7 AC |
1770 | /* probe the backlight is there is one defined */ |
1771 | if (ch->cfg.bl_info.max_brightness) | |
1772 | ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch); | |
1773 | ||
cfb4f5d1 MD |
1774 | switch (pdata->ch[i].chan) { |
1775 | case LCDC_CHAN_MAINLCD: | |
ce1c0b08 | 1776 | ch->enabled = LDCNT2R_ME; |
01ac25b5 | 1777 | ch->reg_offs = lcdc_offs_mainlcd; |
3ce05599 | 1778 | num_channels++; |
cfb4f5d1 MD |
1779 | break; |
1780 | case LCDC_CHAN_SUBLCD: | |
ce1c0b08 | 1781 | ch->enabled = LDCNT2R_SE; |
01ac25b5 | 1782 | ch->reg_offs = lcdc_offs_sublcd; |
3ce05599 | 1783 | num_channels++; |
cfb4f5d1 MD |
1784 | break; |
1785 | } | |
1786 | } | |
1787 | ||
3ce05599 | 1788 | if (!num_channels) { |
cfb4f5d1 MD |
1789 | dev_err(&pdev->dev, "no channels defined\n"); |
1790 | error = -EINVAL; | |
1791 | goto err1; | |
1792 | } | |
1793 | ||
edd153a3 | 1794 | /* for dual channel LCDC (MAIN + SUB) force shared format setting */ |
3ce05599 | 1795 | if (num_channels == 2) |
edd153a3 | 1796 | priv->forced_fourcc = pdata->ch[0].fourcc; |
417d4827 | 1797 | |
dba6f385 GL |
1798 | priv->base = ioremap_nocache(res->start, resource_size(res)); |
1799 | if (!priv->base) | |
1800 | goto err1; | |
1801 | ||
0a7f17aa | 1802 | error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source); |
cfb4f5d1 MD |
1803 | if (error) { |
1804 | dev_err(&pdev->dev, "unable to setup clocks\n"); | |
1805 | goto err1; | |
1806 | } | |
1807 | ||
4774c12a LP |
1808 | /* Enable runtime PM. */ |
1809 | pm_runtime_enable(&pdev->dev); | |
7caa4342 | 1810 | |
3ce05599 | 1811 | for (i = 0; i < num_channels; i++) { |
01ac25b5 | 1812 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
c44f9f76 | 1813 | |
0a7f17aa | 1814 | error = sh_mobile_lcdc_channel_init(priv, ch); |
cfb4f5d1 | 1815 | if (error) |
3ce05599 | 1816 | goto err1; |
cfb4f5d1 MD |
1817 | } |
1818 | ||
cfb4f5d1 MD |
1819 | error = sh_mobile_lcdc_start(priv); |
1820 | if (error) { | |
1821 | dev_err(&pdev->dev, "unable to start hardware\n"); | |
1822 | goto err1; | |
1823 | } | |
1824 | ||
3ce05599 | 1825 | for (i = 0; i < num_channels; i++) { |
1c6a307a | 1826 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
3ce05599 | 1827 | struct fb_info *info = ch->info; |
1c6a307a PM |
1828 | |
1829 | if (info->fbdefio) { | |
8bed9055 | 1830 | ch->sglist = vmalloc(sizeof(struct scatterlist) * |
1c6a307a | 1831 | info->fix.smem_len >> PAGE_SHIFT); |
8bed9055 | 1832 | if (!ch->sglist) { |
1c6a307a PM |
1833 | dev_err(&pdev->dev, "cannot allocate sglist\n"); |
1834 | goto err1; | |
1835 | } | |
1836 | } | |
1837 | ||
3b0fd9d7 AC |
1838 | info->bl_dev = ch->bl; |
1839 | ||
1c6a307a | 1840 | error = register_framebuffer(info); |
cfb4f5d1 MD |
1841 | if (error < 0) |
1842 | goto err1; | |
cfb4f5d1 | 1843 | |
0a7f17aa | 1844 | dev_info(&pdev->dev, "registered %s/%s as %dx%d %dbpp.\n", |
edd153a3 LP |
1845 | pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ? |
1846 | "mainlcd" : "sublcd", info->var.xres, info->var.yres, | |
1847 | info->var.bits_per_pixel); | |
8564557a MD |
1848 | |
1849 | /* deferred io mode: disable clock to save power */ | |
6011bdea | 1850 | if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED) |
8564557a | 1851 | sh_mobile_lcdc_clk_off(priv); |
cfb4f5d1 MD |
1852 | } |
1853 | ||
6011bdea GL |
1854 | /* Failure ignored */ |
1855 | priv->notifier.notifier_call = sh_mobile_lcdc_notify; | |
1856 | fb_register_client(&priv->notifier); | |
1857 | ||
cfb4f5d1 | 1858 | return 0; |
8bed9055 | 1859 | err1: |
cfb4f5d1 | 1860 | sh_mobile_lcdc_remove(pdev); |
8bed9055 | 1861 | |
cfb4f5d1 MD |
1862 | return error; |
1863 | } | |
1864 | ||
cfb4f5d1 MD |
1865 | static struct platform_driver sh_mobile_lcdc_driver = { |
1866 | .driver = { | |
1867 | .name = "sh_mobile_lcdc_fb", | |
1868 | .owner = THIS_MODULE, | |
2feb075a | 1869 | .pm = &sh_mobile_lcdc_dev_pm_ops, |
cfb4f5d1 MD |
1870 | }, |
1871 | .probe = sh_mobile_lcdc_probe, | |
1872 | .remove = sh_mobile_lcdc_remove, | |
1873 | }; | |
1874 | ||
4277f2c4 | 1875 | module_platform_driver(sh_mobile_lcdc_driver); |
cfb4f5d1 MD |
1876 | |
1877 | MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver"); | |
1878 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); | |
1879 | MODULE_LICENSE("GPL v2"); |