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Commit | Line | Data |
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cfb4f5d1 MD |
1 | /* |
2 | * SuperH Mobile LCDC Framebuffer | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
f1f60b5f LP |
11 | #include <linux/atomic.h> |
12 | #include <linux/backlight.h> | |
cfb4f5d1 | 13 | #include <linux/clk.h> |
f1f60b5f | 14 | #include <linux/console.h> |
cfb4f5d1 | 15 | #include <linux/dma-mapping.h> |
f1f60b5f LP |
16 | #include <linux/delay.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8564557a | 19 | #include <linux/interrupt.h> |
40331b21 | 20 | #include <linux/ioctl.h> |
f1f60b5f LP |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
355b200b | 23 | #include <linux/module.h> |
f1f60b5f LP |
24 | #include <linux/platform_device.h> |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <linux/vmalloc.h> | |
29 | ||
225c9a8d | 30 | #include <video/sh_mobile_lcdc.h> |
8a20974f | 31 | #include <video/sh_mobile_meram.h> |
cfb4f5d1 | 32 | |
6de9edd5 GL |
33 | #include "sh_mobile_lcdcfb.h" |
34 | ||
a6f15ade PE |
35 | #define SIDE_B_OFFSET 0x1000 |
36 | #define MIRROR_OFFSET 0x2000 | |
cfb4f5d1 | 37 | |
d2ecbab5 GL |
38 | #define MAX_XRES 1920 |
39 | #define MAX_YRES 1080 | |
cfb4f5d1 | 40 | |
f1f60b5f LP |
41 | struct sh_mobile_lcdc_priv { |
42 | void __iomem *base; | |
43 | int irq; | |
44 | atomic_t hw_usecnt; | |
45 | struct device *dev; | |
46 | struct clk *dot_clk; | |
47 | unsigned long lddckr; | |
48 | struct sh_mobile_lcdc_chan ch[2]; | |
49 | struct notifier_block notifier; | |
50 | int started; | |
51 | int forced_fourcc; /* 2 channel LCDC must share fourcc setting */ | |
52 | struct sh_mobile_meram_info *meram_dev; | |
53 | }; | |
54 | ||
55 | /* ----------------------------------------------------------------------------- | |
56 | * Registers access | |
57 | */ | |
58 | ||
0246c471 | 59 | static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
60 | [LDDCKPAT1R] = 0x400, |
61 | [LDDCKPAT2R] = 0x404, | |
62 | [LDMT1R] = 0x418, | |
63 | [LDMT2R] = 0x41c, | |
64 | [LDMT3R] = 0x420, | |
65 | [LDDFR] = 0x424, | |
66 | [LDSM1R] = 0x428, | |
8564557a | 67 | [LDSM2R] = 0x42c, |
cfb4f5d1 | 68 | [LDSA1R] = 0x430, |
53b50314 | 69 | [LDSA2R] = 0x434, |
cfb4f5d1 MD |
70 | [LDMLSR] = 0x438, |
71 | [LDHCNR] = 0x448, | |
72 | [LDHSYNR] = 0x44c, | |
73 | [LDVLNR] = 0x450, | |
74 | [LDVSYNR] = 0x454, | |
75 | [LDPMR] = 0x460, | |
6011bdea | 76 | [LDHAJR] = 0x4a0, |
cfb4f5d1 MD |
77 | }; |
78 | ||
0246c471 | 79 | static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
80 | [LDDCKPAT1R] = 0x408, |
81 | [LDDCKPAT2R] = 0x40c, | |
82 | [LDMT1R] = 0x600, | |
83 | [LDMT2R] = 0x604, | |
84 | [LDMT3R] = 0x608, | |
85 | [LDDFR] = 0x60c, | |
86 | [LDSM1R] = 0x610, | |
8564557a | 87 | [LDSM2R] = 0x614, |
cfb4f5d1 MD |
88 | [LDSA1R] = 0x618, |
89 | [LDMLSR] = 0x620, | |
90 | [LDHCNR] = 0x624, | |
91 | [LDHSYNR] = 0x628, | |
92 | [LDVLNR] = 0x62c, | |
93 | [LDVSYNR] = 0x630, | |
94 | [LDPMR] = 0x63c, | |
95 | }; | |
96 | ||
a6f15ade PE |
97 | static bool banked(int reg_nr) |
98 | { | |
99 | switch (reg_nr) { | |
100 | case LDMT1R: | |
101 | case LDMT2R: | |
102 | case LDMT3R: | |
103 | case LDDFR: | |
104 | case LDSM1R: | |
105 | case LDSA1R: | |
53b50314 | 106 | case LDSA2R: |
a6f15ade PE |
107 | case LDMLSR: |
108 | case LDHCNR: | |
109 | case LDHSYNR: | |
110 | case LDVLNR: | |
111 | case LDVSYNR: | |
112 | return true; | |
113 | } | |
114 | return false; | |
115 | } | |
116 | ||
f1f60b5f LP |
117 | static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan) |
118 | { | |
119 | return chan->cfg.chan == LCDC_CHAN_SUBLCD; | |
120 | } | |
121 | ||
cfb4f5d1 MD |
122 | static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan, |
123 | int reg_nr, unsigned long data) | |
124 | { | |
125 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); | |
a6f15ade PE |
126 | if (banked(reg_nr)) |
127 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
128 | SIDE_B_OFFSET); | |
129 | } | |
130 | ||
131 | static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan, | |
132 | int reg_nr, unsigned long data) | |
133 | { | |
134 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
135 | MIRROR_OFFSET); | |
cfb4f5d1 MD |
136 | } |
137 | ||
138 | static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan, | |
139 | int reg_nr) | |
140 | { | |
141 | return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); | |
142 | } | |
143 | ||
144 | static void lcdc_write(struct sh_mobile_lcdc_priv *priv, | |
145 | unsigned long reg_offs, unsigned long data) | |
146 | { | |
147 | iowrite32(data, priv->base + reg_offs); | |
148 | } | |
149 | ||
150 | static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv, | |
151 | unsigned long reg_offs) | |
152 | { | |
153 | return ioread32(priv->base + reg_offs); | |
154 | } | |
155 | ||
156 | static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv, | |
157 | unsigned long reg_offs, | |
158 | unsigned long mask, unsigned long until) | |
159 | { | |
160 | while ((lcdc_read(priv, reg_offs) & mask) != until) | |
161 | cpu_relax(); | |
162 | } | |
163 | ||
f1f60b5f LP |
164 | /* ----------------------------------------------------------------------------- |
165 | * Clock management | |
166 | */ | |
167 | ||
168 | static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) | |
cfb4f5d1 | 169 | { |
f1f60b5f LP |
170 | if (atomic_inc_and_test(&priv->hw_usecnt)) { |
171 | if (priv->dot_clk) | |
172 | clk_enable(priv->dot_clk); | |
173 | pm_runtime_get_sync(priv->dev); | |
174 | if (priv->meram_dev && priv->meram_dev->pdev) | |
175 | pm_runtime_get_sync(&priv->meram_dev->pdev->dev); | |
176 | } | |
cfb4f5d1 MD |
177 | } |
178 | ||
f1f60b5f LP |
179 | static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) |
180 | { | |
181 | if (atomic_sub_return(1, &priv->hw_usecnt) == -1) { | |
182 | if (priv->meram_dev && priv->meram_dev->pdev) | |
183 | pm_runtime_put_sync(&priv->meram_dev->pdev->dev); | |
184 | pm_runtime_put(priv->dev); | |
185 | if (priv->dot_clk) | |
186 | clk_disable(priv->dot_clk); | |
187 | } | |
188 | } | |
189 | ||
0a7f17aa LP |
190 | static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv, |
191 | int clock_source) | |
f1f60b5f | 192 | { |
4774c12a | 193 | struct clk *clk; |
f1f60b5f LP |
194 | char *str; |
195 | ||
196 | switch (clock_source) { | |
197 | case LCDC_CLK_BUS: | |
198 | str = "bus_clk"; | |
199 | priv->lddckr = LDDCKR_ICKSEL_BUS; | |
200 | break; | |
201 | case LCDC_CLK_PERIPHERAL: | |
202 | str = "peripheral_clk"; | |
203 | priv->lddckr = LDDCKR_ICKSEL_MIPI; | |
204 | break; | |
205 | case LCDC_CLK_EXTERNAL: | |
206 | str = NULL; | |
207 | priv->lddckr = LDDCKR_ICKSEL_HDMI; | |
208 | break; | |
209 | default: | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
4774c12a LP |
213 | if (str == NULL) |
214 | return 0; | |
215 | ||
0a7f17aa | 216 | clk = clk_get(priv->dev, str); |
4774c12a | 217 | if (IS_ERR(clk)) { |
0a7f17aa | 218 | dev_err(priv->dev, "cannot get dot clock %s\n", str); |
4774c12a | 219 | return PTR_ERR(clk); |
f1f60b5f LP |
220 | } |
221 | ||
4774c12a | 222 | priv->dot_clk = clk; |
f1f60b5f LP |
223 | return 0; |
224 | } | |
225 | ||
226 | /* ----------------------------------------------------------------------------- | |
37c5dcc2 | 227 | * Display, panel and deferred I/O |
f1f60b5f LP |
228 | */ |
229 | ||
cfb4f5d1 MD |
230 | static void lcdc_sys_write_index(void *handle, unsigned long data) |
231 | { | |
232 | struct sh_mobile_lcdc_chan *ch = handle; | |
233 | ||
ce1c0b08 LP |
234 | lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); |
235 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
236 | lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | | |
237 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
238 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
cfb4f5d1 MD |
239 | } |
240 | ||
241 | static void lcdc_sys_write_data(void *handle, unsigned long data) | |
242 | { | |
243 | struct sh_mobile_lcdc_chan *ch = handle; | |
244 | ||
ce1c0b08 LP |
245 | lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW); |
246 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
247 | lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | | |
248 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
249 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
cfb4f5d1 MD |
250 | } |
251 | ||
252 | static unsigned long lcdc_sys_read_data(void *handle) | |
253 | { | |
254 | struct sh_mobile_lcdc_chan *ch = handle; | |
255 | ||
ce1c0b08 LP |
256 | lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR); |
257 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); | |
258 | lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA | | |
259 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
cfb4f5d1 | 260 | udelay(1); |
ce1c0b08 | 261 | lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); |
cfb4f5d1 | 262 | |
ce1c0b08 | 263 | return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK; |
cfb4f5d1 MD |
264 | } |
265 | ||
266 | struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = { | |
267 | lcdc_sys_write_index, | |
268 | lcdc_sys_write_data, | |
269 | lcdc_sys_read_data, | |
270 | }; | |
271 | ||
1c6a307a PM |
272 | static int sh_mobile_lcdc_sginit(struct fb_info *info, |
273 | struct list_head *pagelist) | |
274 | { | |
275 | struct sh_mobile_lcdc_chan *ch = info->par; | |
276 | unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT; | |
277 | struct page *page; | |
278 | int nr_pages = 0; | |
279 | ||
280 | sg_init_table(ch->sglist, nr_pages_max); | |
281 | ||
282 | list_for_each_entry(page, pagelist, lru) | |
283 | sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0); | |
284 | ||
285 | return nr_pages; | |
286 | } | |
287 | ||
8564557a MD |
288 | static void sh_mobile_lcdc_deferred_io(struct fb_info *info, |
289 | struct list_head *pagelist) | |
290 | { | |
291 | struct sh_mobile_lcdc_chan *ch = info->par; | |
afaad83b | 292 | struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg; |
8564557a MD |
293 | |
294 | /* enable clocks before accessing hardware */ | |
295 | sh_mobile_lcdc_clk_on(ch->lcdc); | |
296 | ||
5c1a56b5 PM |
297 | /* |
298 | * It's possible to get here without anything on the pagelist via | |
299 | * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync() | |
300 | * invocation. In the former case, the acceleration routines are | |
301 | * stepped in to when using the framebuffer console causing the | |
302 | * workqueue to be scheduled without any dirty pages on the list. | |
303 | * | |
304 | * Despite this, a panel update is still needed given that the | |
305 | * acceleration routines have their own methods for writing in | |
306 | * that still need to be updated. | |
307 | * | |
308 | * The fsync() and empty pagelist case could be optimized for, | |
309 | * but we don't bother, as any application exhibiting such | |
310 | * behaviour is fundamentally broken anyways. | |
311 | */ | |
312 | if (!list_empty(pagelist)) { | |
313 | unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist); | |
314 | ||
315 | /* trigger panel update */ | |
316 | dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
afaad83b LP |
317 | if (panel->start_transfer) |
318 | panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops); | |
ce1c0b08 | 319 | lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG); |
5c1a56b5 | 320 | dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); |
ef61aae4 | 321 | } else { |
afaad83b LP |
322 | if (panel->start_transfer) |
323 | panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops); | |
ce1c0b08 | 324 | lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG); |
ef61aae4 | 325 | } |
8564557a MD |
326 | } |
327 | ||
328 | static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info) | |
329 | { | |
330 | struct fb_deferred_io *fbdefio = info->fbdefio; | |
331 | ||
332 | if (fbdefio) | |
333 | schedule_delayed_work(&info->deferred_work, fbdefio->delay); | |
334 | } | |
335 | ||
37c5dcc2 LP |
336 | static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch) |
337 | { | |
afaad83b | 338 | struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg; |
37c5dcc2 | 339 | |
9a2985e7 LP |
340 | if (ch->tx_dev) { |
341 | if (ch->tx_dev->ops->display_on(ch->tx_dev, ch->info) < 0) | |
342 | return; | |
343 | } | |
344 | ||
37c5dcc2 | 345 | /* HDMI must be enabled before LCDC configuration */ |
afaad83b LP |
346 | if (panel->display_on) |
347 | panel->display_on(); | |
37c5dcc2 LP |
348 | } |
349 | ||
350 | static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch) | |
351 | { | |
afaad83b | 352 | struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg.panel_cfg; |
37c5dcc2 | 353 | |
afaad83b LP |
354 | if (panel->display_off) |
355 | panel->display_off(); | |
9a2985e7 LP |
356 | |
357 | if (ch->tx_dev) | |
358 | ch->tx_dev->ops->display_off(ch->tx_dev); | |
37c5dcc2 LP |
359 | } |
360 | ||
f1f60b5f LP |
361 | /* ----------------------------------------------------------------------------- |
362 | * Format helpers | |
363 | */ | |
364 | ||
365 | static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var) | |
366 | { | |
367 | if (var->grayscale > 1) | |
368 | return var->grayscale; | |
369 | ||
370 | switch (var->bits_per_pixel) { | |
371 | case 16: | |
372 | return V4L2_PIX_FMT_RGB565; | |
373 | case 24: | |
374 | return V4L2_PIX_FMT_BGR24; | |
375 | case 32: | |
376 | return V4L2_PIX_FMT_BGR32; | |
377 | default: | |
378 | return 0; | |
379 | } | |
380 | } | |
381 | ||
382 | static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var) | |
383 | { | |
384 | return var->grayscale > 1; | |
385 | } | |
386 | ||
387 | static bool sh_mobile_format_is_yuv(const struct fb_var_screeninfo *var) | |
388 | { | |
389 | if (var->grayscale <= 1) | |
390 | return false; | |
391 | ||
392 | switch (var->grayscale) { | |
393 | case V4L2_PIX_FMT_NV12: | |
394 | case V4L2_PIX_FMT_NV21: | |
395 | case V4L2_PIX_FMT_NV16: | |
396 | case V4L2_PIX_FMT_NV61: | |
397 | case V4L2_PIX_FMT_NV24: | |
398 | case V4L2_PIX_FMT_NV42: | |
399 | return true; | |
400 | ||
401 | default: | |
402 | return false; | |
403 | } | |
404 | } | |
405 | ||
406 | /* ----------------------------------------------------------------------------- | |
407 | * Start, stop and IRQ | |
408 | */ | |
409 | ||
8564557a MD |
410 | static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data) |
411 | { | |
412 | struct sh_mobile_lcdc_priv *priv = data; | |
2feb075a | 413 | struct sh_mobile_lcdc_chan *ch; |
9dd38819 | 414 | unsigned long ldintr; |
2feb075a MD |
415 | int is_sub; |
416 | int k; | |
8564557a | 417 | |
dc48665f LP |
418 | /* Acknowledge interrupts and disable further VSYNC End IRQs. */ |
419 | ldintr = lcdc_read(priv, _LDINTR); | |
420 | lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE); | |
8564557a | 421 | |
2feb075a | 422 | /* figure out if this interrupt is for main or sub lcd */ |
ce1c0b08 | 423 | is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0; |
2feb075a | 424 | |
9dd38819 | 425 | /* wake up channel and disable clocks */ |
2feb075a MD |
426 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
427 | ch = &priv->ch[k]; | |
428 | ||
429 | if (!ch->enabled) | |
430 | continue; | |
431 | ||
dc48665f | 432 | /* Frame End */ |
9dd38819 PE |
433 | if (ldintr & LDINTR_FS) { |
434 | if (is_sub == lcdc_chan_is_sublcd(ch)) { | |
435 | ch->frame_end = 1; | |
436 | wake_up(&ch->frame_end_wait); | |
2feb075a | 437 | |
9dd38819 PE |
438 | sh_mobile_lcdc_clk_off(priv); |
439 | } | |
440 | } | |
441 | ||
442 | /* VSYNC End */ | |
40331b21 PE |
443 | if (ldintr & LDINTR_VES) |
444 | complete(&ch->vsync_completion); | |
2feb075a MD |
445 | } |
446 | ||
8564557a MD |
447 | return IRQ_HANDLED; |
448 | } | |
449 | ||
cfb4f5d1 MD |
450 | static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv, |
451 | int start) | |
452 | { | |
453 | unsigned long tmp = lcdc_read(priv, _LDCNT2R); | |
454 | int k; | |
455 | ||
456 | /* start or stop the lcdc */ | |
457 | if (start) | |
ce1c0b08 | 458 | lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO); |
cfb4f5d1 | 459 | else |
ce1c0b08 | 460 | lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO); |
cfb4f5d1 MD |
461 | |
462 | /* wait until power is applied/stopped on all channels */ | |
463 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
464 | if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled) | |
465 | while (1) { | |
ce1c0b08 LP |
466 | tmp = lcdc_read_chan(&priv->ch[k], LDPMR) |
467 | & LDPMR_LPS; | |
468 | if (start && tmp == LDPMR_LPS) | |
cfb4f5d1 MD |
469 | break; |
470 | if (!start && tmp == 0) | |
471 | break; | |
472 | cpu_relax(); | |
473 | } | |
474 | ||
475 | if (!start) | |
476 | lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */ | |
477 | } | |
478 | ||
6011bdea GL |
479 | static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch) |
480 | { | |
1c120deb GL |
481 | struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var; |
482 | unsigned long h_total, hsync_pos, display_h_total; | |
6011bdea GL |
483 | u32 tmp; |
484 | ||
485 | tmp = ch->ldmt1r_value; | |
ce1c0b08 LP |
486 | tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL; |
487 | tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL; | |
488 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0; | |
489 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0; | |
490 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0; | |
491 | tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0; | |
492 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0; | |
6011bdea GL |
493 | lcdc_write_chan(ch, LDMT1R, tmp); |
494 | ||
495 | /* setup SYS bus */ | |
496 | lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r); | |
497 | lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r); | |
498 | ||
499 | /* horizontal configuration */ | |
1c120deb GL |
500 | h_total = display_var->xres + display_var->hsync_len + |
501 | display_var->left_margin + display_var->right_margin; | |
6011bdea | 502 | tmp = h_total / 8; /* HTCN */ |
1c120deb | 503 | tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */ |
6011bdea GL |
504 | lcdc_write_chan(ch, LDHCNR, tmp); |
505 | ||
1c120deb | 506 | hsync_pos = display_var->xres + display_var->right_margin; |
6011bdea | 507 | tmp = hsync_pos / 8; /* HSYNP */ |
1c120deb | 508 | tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */ |
6011bdea GL |
509 | lcdc_write_chan(ch, LDHSYNR, tmp); |
510 | ||
511 | /* vertical configuration */ | |
1c120deb GL |
512 | tmp = display_var->yres + display_var->vsync_len + |
513 | display_var->upper_margin + display_var->lower_margin; /* VTLN */ | |
514 | tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */ | |
6011bdea GL |
515 | lcdc_write_chan(ch, LDVLNR, tmp); |
516 | ||
1c120deb GL |
517 | tmp = display_var->yres + display_var->lower_margin; /* VSYNP */ |
518 | tmp |= display_var->vsync_len << 16; /* VSYNW */ | |
6011bdea GL |
519 | lcdc_write_chan(ch, LDVSYNR, tmp); |
520 | ||
521 | /* Adjust horizontal synchronisation for HDMI */ | |
1c120deb GL |
522 | display_h_total = display_var->xres + display_var->hsync_len + |
523 | display_var->left_margin + display_var->right_margin; | |
524 | tmp = ((display_var->xres & 7) << 24) | | |
525 | ((display_h_total & 7) << 16) | | |
526 | ((display_var->hsync_len & 7) << 8) | | |
41e583c2 | 527 | (hsync_pos & 7); |
6011bdea GL |
528 | lcdc_write_chan(ch, LDHAJR, tmp); |
529 | } | |
530 | ||
9a217e34 LP |
531 | /* |
532 | * __sh_mobile_lcdc_start - Configure and tart the LCDC | |
533 | * @priv: LCDC device | |
534 | * | |
535 | * Configure all enabled channels and start the LCDC device. All external | |
536 | * devices (clocks, MERAM, panels, ...) are not touched by this function. | |
537 | */ | |
538 | static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) | |
cfb4f5d1 MD |
539 | { |
540 | struct sh_mobile_lcdc_chan *ch; | |
cfb4f5d1 | 541 | unsigned long tmp; |
9a217e34 | 542 | int k, m; |
8564557a | 543 | |
9a217e34 LP |
544 | /* Enable LCDC channels. Read data from external memory, avoid using the |
545 | * BEU for now. | |
546 | */ | |
547 | lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled); | |
cfb4f5d1 | 548 | |
9a217e34 | 549 | /* Stop the LCDC first and disable all interrupts. */ |
cfb4f5d1 | 550 | sh_mobile_lcdc_start_stop(priv, 0); |
9a217e34 | 551 | lcdc_write(priv, _LDINTR, 0); |
cfb4f5d1 | 552 | |
9a217e34 | 553 | /* Configure power supply, dot clocks and start them. */ |
cfb4f5d1 MD |
554 | tmp = priv->lddckr; |
555 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
556 | ch = &priv->ch[k]; | |
9a217e34 | 557 | if (!ch->enabled) |
cfb4f5d1 MD |
558 | continue; |
559 | ||
9a217e34 LP |
560 | /* Power supply */ |
561 | lcdc_write_chan(ch, LDPMR, 0); | |
562 | ||
cfb4f5d1 MD |
563 | m = ch->cfg.clock_divider; |
564 | if (!m) | |
565 | continue; | |
566 | ||
505c7de5 LP |
567 | /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider |
568 | * denominator. | |
569 | */ | |
570 | lcdc_write_chan(ch, LDDCKPAT1R, 0); | |
571 | lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1); | |
572 | ||
cfb4f5d1 | 573 | if (m == 1) |
ce1c0b08 | 574 | m = LDDCKR_MOSEL; |
cfb4f5d1 | 575 | tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0); |
cfb4f5d1 MD |
576 | } |
577 | ||
578 | lcdc_write(priv, _LDDCKR, tmp); | |
cfb4f5d1 MD |
579 | lcdc_write(priv, _LDDCKSTPR, 0); |
580 | lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0); | |
581 | ||
9a217e34 | 582 | /* Setup geometry, format, frame buffer memory and operation mode. */ |
cfb4f5d1 MD |
583 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
584 | ch = &priv->ch[k]; | |
cfb4f5d1 MD |
585 | if (!ch->enabled) |
586 | continue; | |
587 | ||
6011bdea | 588 | sh_mobile_lcdc_geometry(ch); |
cfb4f5d1 | 589 | |
edd153a3 LP |
590 | switch (sh_mobile_format_fourcc(&ch->info->var)) { |
591 | case V4L2_PIX_FMT_RGB565: | |
592 | tmp = LDDFR_PKF_RGB16; | |
593 | break; | |
594 | case V4L2_PIX_FMT_BGR24: | |
595 | tmp = LDDFR_PKF_RGB24; | |
596 | break; | |
597 | case V4L2_PIX_FMT_BGR32: | |
598 | tmp = LDDFR_PKF_ARGB32; | |
599 | break; | |
600 | case V4L2_PIX_FMT_NV12: | |
601 | case V4L2_PIX_FMT_NV21: | |
602 | tmp = LDDFR_CC | LDDFR_YF_420; | |
603 | break; | |
604 | case V4L2_PIX_FMT_NV16: | |
605 | case V4L2_PIX_FMT_NV61: | |
606 | tmp = LDDFR_CC | LDDFR_YF_422; | |
607 | break; | |
608 | case V4L2_PIX_FMT_NV24: | |
609 | case V4L2_PIX_FMT_NV42: | |
610 | tmp = LDDFR_CC | LDDFR_YF_444; | |
611 | break; | |
612 | } | |
613 | ||
614 | if (sh_mobile_format_is_yuv(&ch->info->var)) { | |
615 | switch (ch->info->var.colorspace) { | |
616 | case V4L2_COLORSPACE_REC709: | |
617 | tmp |= LDDFR_CF1; | |
53b50314 | 618 | break; |
edd153a3 LP |
619 | case V4L2_COLORSPACE_JPEG: |
620 | tmp |= LDDFR_CF0; | |
53b50314 DHG |
621 | break; |
622 | } | |
417d4827 | 623 | } |
7caa4342 | 624 | |
9a217e34 LP |
625 | lcdc_write_chan(ch, LDDFR, tmp); |
626 | lcdc_write_chan(ch, LDMLSR, ch->pitch); | |
627 | lcdc_write_chan(ch, LDSA1R, ch->base_addr_y); | |
edd153a3 | 628 | if (sh_mobile_format_is_yuv(&ch->info->var)) |
9a217e34 | 629 | lcdc_write_chan(ch, LDSA2R, ch->base_addr_c); |
7caa4342 | 630 | |
9a217e34 LP |
631 | /* When using deferred I/O mode, configure the LCDC for one-shot |
632 | * operation and enable the frame end interrupt. Otherwise use | |
633 | * continuous read mode. | |
634 | */ | |
635 | if (ch->ldmt1r_value & LDMT1R_IFM && | |
636 | ch->cfg.sys_bus_cfg.deferred_io_msec) { | |
637 | lcdc_write_chan(ch, LDSM1R, LDSM1R_OS); | |
638 | lcdc_write(priv, _LDINTR, LDINTR_FE); | |
639 | } else { | |
640 | lcdc_write_chan(ch, LDSM1R, 0); | |
641 | } | |
642 | } | |
7caa4342 | 643 | |
9a217e34 | 644 | /* Word and long word swap. */ |
edd153a3 LP |
645 | switch (sh_mobile_format_fourcc(&priv->ch[0].info->var)) { |
646 | case V4L2_PIX_FMT_RGB565: | |
647 | case V4L2_PIX_FMT_NV21: | |
648 | case V4L2_PIX_FMT_NV61: | |
649 | case V4L2_PIX_FMT_NV42: | |
650 | tmp = LDDDSR_LS | LDDDSR_WS; | |
651 | break; | |
652 | case V4L2_PIX_FMT_BGR24: | |
653 | case V4L2_PIX_FMT_NV12: | |
654 | case V4L2_PIX_FMT_NV16: | |
655 | case V4L2_PIX_FMT_NV24: | |
9a217e34 | 656 | tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS; |
edd153a3 LP |
657 | break; |
658 | case V4L2_PIX_FMT_BGR32: | |
659 | default: | |
660 | tmp = LDDDSR_LS; | |
661 | break; | |
9a217e34 LP |
662 | } |
663 | lcdc_write(priv, _LDDDSR, tmp); | |
7caa4342 | 664 | |
9a217e34 LP |
665 | /* Enable the display output. */ |
666 | lcdc_write(priv, _LDCNT1R, LDCNT1R_DE); | |
667 | sh_mobile_lcdc_start_stop(priv, 1); | |
668 | priv->started = 1; | |
669 | } | |
cfb4f5d1 | 670 | |
9a217e34 LP |
671 | static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) |
672 | { | |
673 | struct sh_mobile_meram_info *mdev = priv->meram_dev; | |
9a217e34 LP |
674 | struct sh_mobile_lcdc_chan *ch; |
675 | unsigned long tmp; | |
676 | int ret; | |
677 | int k; | |
cfb4f5d1 | 678 | |
9a217e34 LP |
679 | /* enable clocks before accessing the hardware */ |
680 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
681 | if (priv->ch[k].enabled) | |
682 | sh_mobile_lcdc_clk_on(priv); | |
683 | } | |
8564557a | 684 | |
9a217e34 LP |
685 | /* reset */ |
686 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR); | |
687 | lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0); | |
8564557a | 688 | |
9a217e34 | 689 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
afaad83b | 690 | struct sh_mobile_lcdc_panel_cfg *panel; |
8564557a | 691 | |
37c5dcc2 | 692 | ch = &priv->ch[k]; |
9a217e34 LP |
693 | if (!ch->enabled) |
694 | continue; | |
695 | ||
afaad83b LP |
696 | panel = &ch->cfg.panel_cfg; |
697 | if (panel->setup_sys) { | |
698 | ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops); | |
9a217e34 LP |
699 | if (ret) |
700 | return ret; | |
8564557a | 701 | } |
cfb4f5d1 MD |
702 | } |
703 | ||
9a217e34 LP |
704 | /* Compute frame buffer base address and pitch for each channel. */ |
705 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
706 | struct sh_mobile_meram_cfg *cfg; | |
707 | int pixelformat; | |
cfb4f5d1 | 708 | |
9a217e34 LP |
709 | ch = &priv->ch[k]; |
710 | if (!ch->enabled) | |
711 | continue; | |
cfb4f5d1 | 712 | |
9a217e34 LP |
713 | ch->base_addr_y = ch->info->fix.smem_start; |
714 | ch->base_addr_c = ch->base_addr_y | |
715 | + ch->info->var.xres | |
716 | * ch->info->var.yres_virtual; | |
717 | ch->pitch = ch->info->fix.line_length; | |
718 | ||
719 | /* Enable MERAM if possible. */ | |
720 | cfg = ch->cfg.meram_cfg; | |
721 | if (mdev == NULL || mdev->ops == NULL || cfg == NULL) | |
722 | continue; | |
723 | ||
724 | /* we need to de-init configured ICBs before we can | |
725 | * re-initialize them. | |
726 | */ | |
727 | if (ch->meram_enabled) { | |
728 | mdev->ops->meram_unregister(mdev, cfg); | |
729 | ch->meram_enabled = 0; | |
730 | } | |
731 | ||
edd153a3 LP |
732 | switch (sh_mobile_format_fourcc(&ch->info->var)) { |
733 | case V4L2_PIX_FMT_NV12: | |
734 | case V4L2_PIX_FMT_NV21: | |
735 | case V4L2_PIX_FMT_NV16: | |
736 | case V4L2_PIX_FMT_NV61: | |
9a217e34 | 737 | pixelformat = SH_MOBILE_MERAM_PF_NV; |
edd153a3 LP |
738 | break; |
739 | case V4L2_PIX_FMT_NV24: | |
740 | case V4L2_PIX_FMT_NV42: | |
741 | pixelformat = SH_MOBILE_MERAM_PF_NV24; | |
742 | break; | |
743 | case V4L2_PIX_FMT_RGB565: | |
744 | case V4L2_PIX_FMT_BGR24: | |
745 | case V4L2_PIX_FMT_BGR32: | |
746 | default: | |
747 | pixelformat = SH_MOBILE_MERAM_PF_RGB; | |
748 | break; | |
749 | } | |
9a217e34 LP |
750 | |
751 | ret = mdev->ops->meram_register(mdev, cfg, ch->pitch, | |
752 | ch->info->var.yres, pixelformat, | |
753 | ch->base_addr_y, ch->base_addr_c, | |
754 | &ch->base_addr_y, &ch->base_addr_c, | |
755 | &ch->pitch); | |
756 | if (!ret) | |
757 | ch->meram_enabled = 1; | |
758 | } | |
759 | ||
760 | /* Start the LCDC. */ | |
761 | __sh_mobile_lcdc_start(priv); | |
762 | ||
763 | /* Setup deferred I/O, tell the board code to enable the panels, and | |
764 | * turn backlight on. | |
765 | */ | |
cfb4f5d1 MD |
766 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
767 | ch = &priv->ch[k]; | |
21bc1f02 MD |
768 | if (!ch->enabled) |
769 | continue; | |
770 | ||
9a217e34 LP |
771 | tmp = ch->cfg.sys_bus_cfg.deferred_io_msec; |
772 | if (ch->ldmt1r_value & LDMT1R_IFM && tmp) { | |
773 | ch->defio.deferred_io = sh_mobile_lcdc_deferred_io; | |
774 | ch->defio.delay = msecs_to_jiffies(tmp); | |
775 | ch->info->fbdefio = &ch->defio; | |
776 | fb_deferred_io_init(ch->info); | |
777 | } | |
778 | ||
37c5dcc2 | 779 | sh_mobile_lcdc_display_on(ch); |
3b0fd9d7 AC |
780 | |
781 | if (ch->bl) { | |
782 | ch->bl->props.power = FB_BLANK_UNBLANK; | |
783 | backlight_update_status(ch->bl); | |
784 | } | |
cfb4f5d1 MD |
785 | } |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |
791 | { | |
792 | struct sh_mobile_lcdc_chan *ch; | |
cfb4f5d1 MD |
793 | int k; |
794 | ||
2feb075a | 795 | /* clean up deferred io and ask board code to disable panel */ |
cfb4f5d1 MD |
796 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
797 | ch = &priv->ch[k]; | |
21bc1f02 MD |
798 | if (!ch->enabled) |
799 | continue; | |
8564557a | 800 | |
2feb075a MD |
801 | /* deferred io mode: |
802 | * flush frame, and wait for frame end interrupt | |
803 | * clean up deferred io and enable clock | |
804 | */ | |
5ef6b505 | 805 | if (ch->info && ch->info->fbdefio) { |
2feb075a | 806 | ch->frame_end = 0; |
e33afddc | 807 | schedule_delayed_work(&ch->info->deferred_work, 0); |
2feb075a | 808 | wait_event(ch->frame_end_wait, ch->frame_end); |
e33afddc PM |
809 | fb_deferred_io_cleanup(ch->info); |
810 | ch->info->fbdefio = NULL; | |
2feb075a | 811 | sh_mobile_lcdc_clk_on(priv); |
8564557a | 812 | } |
2feb075a | 813 | |
3b0fd9d7 AC |
814 | if (ch->bl) { |
815 | ch->bl->props.power = FB_BLANK_POWERDOWN; | |
816 | backlight_update_status(ch->bl); | |
817 | } | |
818 | ||
37c5dcc2 | 819 | sh_mobile_lcdc_display_off(ch); |
7caa4342 DHG |
820 | |
821 | /* disable the meram */ | |
822 | if (ch->meram_enabled) { | |
823 | struct sh_mobile_meram_cfg *cfg; | |
824 | struct sh_mobile_meram_info *mdev; | |
825 | cfg = ch->cfg.meram_cfg; | |
826 | mdev = priv->meram_dev; | |
827 | mdev->ops->meram_unregister(mdev, cfg); | |
828 | ch->meram_enabled = 0; | |
829 | } | |
830 | ||
cfb4f5d1 MD |
831 | } |
832 | ||
833 | /* stop the lcdc */ | |
8e9bb19e MD |
834 | if (priv->started) { |
835 | sh_mobile_lcdc_start_stop(priv, 0); | |
836 | priv->started = 0; | |
837 | } | |
b51339ff | 838 | |
8564557a MD |
839 | /* stop clocks */ |
840 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
841 | if (priv->ch[k].enabled) | |
842 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
843 | } |
844 | ||
f1f60b5f LP |
845 | /* ----------------------------------------------------------------------------- |
846 | * Frame buffer operations | |
847 | */ | |
cfb4f5d1 MD |
848 | |
849 | static int sh_mobile_lcdc_setcolreg(u_int regno, | |
850 | u_int red, u_int green, u_int blue, | |
851 | u_int transp, struct fb_info *info) | |
852 | { | |
853 | u32 *palette = info->pseudo_palette; | |
854 | ||
855 | if (regno >= PALETTE_NR) | |
856 | return -EINVAL; | |
857 | ||
858 | /* only FB_VISUAL_TRUECOLOR supported */ | |
859 | ||
860 | red >>= 16 - info->var.red.length; | |
861 | green >>= 16 - info->var.green.length; | |
862 | blue >>= 16 - info->var.blue.length; | |
863 | transp >>= 16 - info->var.transp.length; | |
864 | ||
865 | palette[regno] = (red << info->var.red.offset) | | |
866 | (green << info->var.green.offset) | | |
867 | (blue << info->var.blue.offset) | | |
868 | (transp << info->var.transp.offset); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static struct fb_fix_screeninfo sh_mobile_lcdc_fix = { | |
874 | .id = "SH Mobile LCDC", | |
875 | .type = FB_TYPE_PACKED_PIXELS, | |
876 | .visual = FB_VISUAL_TRUECOLOR, | |
877 | .accel = FB_ACCEL_NONE, | |
9dd38819 PE |
878 | .xpanstep = 0, |
879 | .ypanstep = 1, | |
880 | .ywrapstep = 0, | |
edd153a3 | 881 | .capabilities = FB_CAP_FOURCC, |
cfb4f5d1 MD |
882 | }; |
883 | ||
8564557a MD |
884 | static void sh_mobile_lcdc_fillrect(struct fb_info *info, |
885 | const struct fb_fillrect *rect) | |
886 | { | |
887 | sys_fillrect(info, rect); | |
888 | sh_mobile_lcdc_deferred_io_touch(info); | |
889 | } | |
890 | ||
891 | static void sh_mobile_lcdc_copyarea(struct fb_info *info, | |
892 | const struct fb_copyarea *area) | |
893 | { | |
894 | sys_copyarea(info, area); | |
895 | sh_mobile_lcdc_deferred_io_touch(info); | |
896 | } | |
897 | ||
898 | static void sh_mobile_lcdc_imageblit(struct fb_info *info, | |
899 | const struct fb_image *image) | |
900 | { | |
901 | sys_imageblit(info, image); | |
902 | sh_mobile_lcdc_deferred_io_touch(info); | |
903 | } | |
904 | ||
9dd38819 PE |
905 | static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var, |
906 | struct fb_info *info) | |
907 | { | |
908 | struct sh_mobile_lcdc_chan *ch = info->par; | |
92e1f9a7 PE |
909 | struct sh_mobile_lcdc_priv *priv = ch->lcdc; |
910 | unsigned long ldrcntr; | |
911 | unsigned long new_pan_offset; | |
53b50314 DHG |
912 | unsigned long base_addr_y, base_addr_c; |
913 | unsigned long c_offset; | |
edd153a3 | 914 | bool yuv = sh_mobile_format_is_yuv(&info->var); |
92e1f9a7 | 915 | |
edd153a3 | 916 | if (!yuv) |
dc1d5ada LP |
917 | new_pan_offset = var->yoffset * info->fix.line_length |
918 | + var->xoffset * (info->var.bits_per_pixel / 8); | |
53b50314 | 919 | else |
dc1d5ada LP |
920 | new_pan_offset = var->yoffset * info->fix.line_length |
921 | + var->xoffset; | |
9dd38819 | 922 | |
92e1f9a7 | 923 | if (new_pan_offset == ch->pan_offset) |
9dd38819 PE |
924 | return 0; /* No change, do nothing */ |
925 | ||
92e1f9a7 | 926 | ldrcntr = lcdc_read(priv, _LDRCNTR); |
9dd38819 | 927 | |
92e1f9a7 | 928 | /* Set the source address for the next refresh */ |
53b50314 | 929 | base_addr_y = ch->dma_handle + new_pan_offset; |
edd153a3 | 930 | if (yuv) { |
53b50314 | 931 | /* Set y offset */ |
dc1d5ada LP |
932 | c_offset = var->yoffset * info->fix.line_length |
933 | * (info->var.bits_per_pixel - 8) / 8; | |
934 | base_addr_c = ch->dma_handle | |
935 | + info->var.xres * info->var.yres_virtual | |
936 | + c_offset; | |
53b50314 | 937 | /* Set x offset */ |
edd153a3 | 938 | if (sh_mobile_format_fourcc(&info->var) == V4L2_PIX_FMT_NV24) |
53b50314 DHG |
939 | base_addr_c += 2 * var->xoffset; |
940 | else | |
941 | base_addr_c += var->xoffset; | |
49d79ba2 | 942 | } |
53b50314 | 943 | |
49d79ba2 | 944 | if (ch->meram_enabled) { |
7caa4342 DHG |
945 | struct sh_mobile_meram_cfg *cfg; |
946 | struct sh_mobile_meram_info *mdev; | |
7caa4342 DHG |
947 | int ret; |
948 | ||
949 | cfg = ch->cfg.meram_cfg; | |
950 | mdev = priv->meram_dev; | |
951 | ret = mdev->ops->meram_update(mdev, cfg, | |
952 | base_addr_y, base_addr_c, | |
49d79ba2 | 953 | &base_addr_y, &base_addr_c); |
7caa4342 DHG |
954 | if (ret) |
955 | return ret; | |
49d79ba2 | 956 | } |
7caa4342 | 957 | |
49d79ba2 LP |
958 | ch->base_addr_y = base_addr_y; |
959 | ch->base_addr_c = base_addr_c; | |
7caa4342 | 960 | |
49d79ba2 | 961 | lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y); |
edd153a3 | 962 | if (yuv) |
49d79ba2 | 963 | lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c); |
53b50314 | 964 | |
92e1f9a7 PE |
965 | if (lcdc_chan_is_sublcd(ch)) |
966 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); | |
967 | else | |
968 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS); | |
969 | ||
970 | ch->pan_offset = new_pan_offset; | |
971 | ||
972 | sh_mobile_lcdc_deferred_io_touch(info); | |
9dd38819 PE |
973 | |
974 | return 0; | |
975 | } | |
976 | ||
40331b21 PE |
977 | static int sh_mobile_wait_for_vsync(struct fb_info *info) |
978 | { | |
979 | struct sh_mobile_lcdc_chan *ch = info->par; | |
980 | unsigned long ldintr; | |
981 | int ret; | |
982 | ||
dc48665f LP |
983 | /* Enable VSync End interrupt and be careful not to acknowledge any |
984 | * pending interrupt. | |
985 | */ | |
40331b21 | 986 | ldintr = lcdc_read(ch->lcdc, _LDINTR); |
dc48665f | 987 | ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK; |
40331b21 PE |
988 | lcdc_write(ch->lcdc, _LDINTR, ldintr); |
989 | ||
990 | ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion, | |
991 | msecs_to_jiffies(100)); | |
992 | if (!ret) | |
993 | return -ETIMEDOUT; | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd, | |
999 | unsigned long arg) | |
1000 | { | |
1001 | int retval; | |
1002 | ||
1003 | switch (cmd) { | |
1004 | case FBIO_WAITFORVSYNC: | |
1005 | retval = sh_mobile_wait_for_vsync(info); | |
1006 | break; | |
1007 | ||
1008 | default: | |
1009 | retval = -ENOIOCTLCMD; | |
1010 | break; | |
1011 | } | |
1012 | return retval; | |
1013 | } | |
1014 | ||
dd210503 GL |
1015 | static void sh_mobile_fb_reconfig(struct fb_info *info) |
1016 | { | |
1017 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1018 | struct fb_videomode mode1, mode2; | |
1019 | struct fb_event event; | |
1020 | int evnt = FB_EVENT_MODE_CHANGE_ALL; | |
1021 | ||
1022 | if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par)) | |
1023 | /* More framebuffer users are active */ | |
1024 | return; | |
1025 | ||
1026 | fb_var_to_videomode(&mode1, &ch->display_var); | |
1027 | fb_var_to_videomode(&mode2, &info->var); | |
1028 | ||
1029 | if (fb_mode_is_equal(&mode1, &mode2)) | |
1030 | return; | |
1031 | ||
1032 | /* Display has been re-plugged, framebuffer is free now, reconfigure */ | |
1033 | if (fb_set_var(info, &ch->display_var) < 0) | |
1034 | /* Couldn't reconfigure, hopefully, can continue as before */ | |
1035 | return; | |
1036 | ||
dd210503 GL |
1037 | /* |
1038 | * fb_set_var() calls the notifier change internally, only if | |
1039 | * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a | |
1040 | * user event, we have to call the chain ourselves. | |
1041 | */ | |
1042 | event.info = info; | |
cc267ec5 | 1043 | event.data = &mode1; |
dd210503 GL |
1044 | fb_notifier_call_chain(evnt, &event); |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | * Locking: both .fb_release() and .fb_open() are called with info->lock held if | |
1049 | * user == 1, or with console sem held, if user == 0. | |
1050 | */ | |
1051 | static int sh_mobile_release(struct fb_info *info, int user) | |
1052 | { | |
1053 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1054 | ||
1055 | mutex_lock(&ch->open_lock); | |
1056 | dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count); | |
1057 | ||
1058 | ch->use_count--; | |
1059 | ||
1060 | /* Nothing to reconfigure, when called from fbcon */ | |
1061 | if (user) { | |
ac751efa | 1062 | console_lock(); |
dd210503 | 1063 | sh_mobile_fb_reconfig(info); |
ac751efa | 1064 | console_unlock(); |
dd210503 GL |
1065 | } |
1066 | ||
1067 | mutex_unlock(&ch->open_lock); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int sh_mobile_open(struct fb_info *info, int user) | |
1073 | { | |
1074 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1075 | ||
1076 | mutex_lock(&ch->open_lock); | |
1077 | ch->use_count++; | |
1078 | ||
1079 | dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count); | |
1080 | mutex_unlock(&ch->open_lock); | |
1081 | ||
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
1086 | { | |
1087 | struct sh_mobile_lcdc_chan *ch = info->par; | |
417d4827 | 1088 | struct sh_mobile_lcdc_priv *p = ch->lcdc; |
03862194 LP |
1089 | unsigned int best_dist = (unsigned int)-1; |
1090 | unsigned int best_xres = 0; | |
1091 | unsigned int best_yres = 0; | |
1092 | unsigned int i; | |
dd210503 | 1093 | |
03862194 | 1094 | if (var->xres > MAX_XRES || var->yres > MAX_YRES) |
dd210503 | 1095 | return -EINVAL; |
03862194 LP |
1096 | |
1097 | /* If board code provides us with a list of available modes, make sure | |
1098 | * we use one of them. Find the mode closest to the requested one. The | |
1099 | * distance between two modes is defined as the size of the | |
1100 | * non-overlapping parts of the two rectangles. | |
1101 | */ | |
1102 | for (i = 0; i < ch->cfg.num_cfg; ++i) { | |
1103 | const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i]; | |
1104 | unsigned int dist; | |
1105 | ||
1106 | /* We can only round up. */ | |
1107 | if (var->xres > mode->xres || var->yres > mode->yres) | |
1108 | continue; | |
1109 | ||
1110 | dist = var->xres * var->yres + mode->xres * mode->yres | |
1111 | - 2 * min(var->xres, mode->xres) | |
1112 | * min(var->yres, mode->yres); | |
1113 | ||
1114 | if (dist < best_dist) { | |
1115 | best_xres = mode->xres; | |
1116 | best_yres = mode->yres; | |
1117 | best_dist = dist; | |
1118 | } | |
dd210503 | 1119 | } |
417d4827 | 1120 | |
03862194 LP |
1121 | /* If no available mode can be used, return an error. */ |
1122 | if (ch->cfg.num_cfg != 0) { | |
1123 | if (best_dist == (unsigned int)-1) | |
1124 | return -EINVAL; | |
1125 | ||
1126 | var->xres = best_xres; | |
1127 | var->yres = best_yres; | |
1128 | } | |
1129 | ||
1130 | /* Make sure the virtual resolution is at least as big as the visible | |
1131 | * resolution. | |
1132 | */ | |
1133 | if (var->xres_virtual < var->xres) | |
1134 | var->xres_virtual = var->xres; | |
1135 | if (var->yres_virtual < var->yres) | |
1136 | var->yres_virtual = var->yres; | |
1137 | ||
edd153a3 LP |
1138 | if (sh_mobile_format_is_fourcc(var)) { |
1139 | switch (var->grayscale) { | |
1140 | case V4L2_PIX_FMT_NV12: | |
1141 | case V4L2_PIX_FMT_NV21: | |
1142 | var->bits_per_pixel = 12; | |
1143 | break; | |
1144 | case V4L2_PIX_FMT_RGB565: | |
1145 | case V4L2_PIX_FMT_NV16: | |
1146 | case V4L2_PIX_FMT_NV61: | |
1147 | var->bits_per_pixel = 16; | |
1148 | break; | |
1149 | case V4L2_PIX_FMT_BGR24: | |
1150 | case V4L2_PIX_FMT_NV24: | |
1151 | case V4L2_PIX_FMT_NV42: | |
1152 | var->bits_per_pixel = 24; | |
1153 | break; | |
1154 | case V4L2_PIX_FMT_BGR32: | |
1155 | var->bits_per_pixel = 32; | |
1156 | break; | |
1157 | default: | |
1158 | return -EINVAL; | |
1159 | } | |
1160 | ||
1161 | /* Default to RGB and JPEG color-spaces for RGB and YUV formats | |
1162 | * respectively. | |
1163 | */ | |
1164 | if (!sh_mobile_format_is_yuv(var)) | |
1165 | var->colorspace = V4L2_COLORSPACE_SRGB; | |
1166 | else if (var->colorspace != V4L2_COLORSPACE_REC709) | |
1167 | var->colorspace = V4L2_COLORSPACE_JPEG; | |
1168 | } else { | |
1169 | if (var->bits_per_pixel <= 16) { /* RGB 565 */ | |
1170 | var->bits_per_pixel = 16; | |
1171 | var->red.offset = 11; | |
1172 | var->red.length = 5; | |
1173 | var->green.offset = 5; | |
1174 | var->green.length = 6; | |
1175 | var->blue.offset = 0; | |
1176 | var->blue.length = 5; | |
1177 | var->transp.offset = 0; | |
1178 | var->transp.length = 0; | |
1179 | } else if (var->bits_per_pixel <= 24) { /* RGB 888 */ | |
1180 | var->bits_per_pixel = 24; | |
1181 | var->red.offset = 16; | |
1182 | var->red.length = 8; | |
1183 | var->green.offset = 8; | |
1184 | var->green.length = 8; | |
1185 | var->blue.offset = 0; | |
1186 | var->blue.length = 8; | |
1187 | var->transp.offset = 0; | |
1188 | var->transp.length = 0; | |
1189 | } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */ | |
1190 | var->bits_per_pixel = 32; | |
1191 | var->red.offset = 16; | |
1192 | var->red.length = 8; | |
1193 | var->green.offset = 8; | |
1194 | var->green.length = 8; | |
1195 | var->blue.offset = 0; | |
1196 | var->blue.length = 8; | |
1197 | var->transp.offset = 24; | |
1198 | var->transp.length = 8; | |
1199 | } else | |
1200 | return -EINVAL; | |
417d4827 | 1201 | |
edd153a3 LP |
1202 | var->red.msb_right = 0; |
1203 | var->green.msb_right = 0; | |
1204 | var->blue.msb_right = 0; | |
1205 | var->transp.msb_right = 0; | |
1206 | } | |
03862194 LP |
1207 | |
1208 | /* Make sure we don't exceed our allocated memory. */ | |
1209 | if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 > | |
1210 | info->fix.smem_len) | |
1211 | return -EINVAL; | |
1212 | ||
edd153a3 LP |
1213 | /* only accept the forced_fourcc for dual channel configurations */ |
1214 | if (p->forced_fourcc && | |
1215 | p->forced_fourcc != sh_mobile_format_fourcc(var)) | |
417d4827 | 1216 | return -EINVAL; |
417d4827 | 1217 | |
dd210503 GL |
1218 | return 0; |
1219 | } | |
40331b21 | 1220 | |
ed5bebf2 LP |
1221 | static int sh_mobile_set_par(struct fb_info *info) |
1222 | { | |
1223 | struct sh_mobile_lcdc_chan *ch = info->par; | |
91fba48d | 1224 | u32 line_length = info->fix.line_length; |
ed5bebf2 LP |
1225 | int ret; |
1226 | ||
1227 | sh_mobile_lcdc_stop(ch->lcdc); | |
91fba48d | 1228 | |
edd153a3 | 1229 | if (sh_mobile_format_is_yuv(&info->var)) |
91fba48d LP |
1230 | info->fix.line_length = info->var.xres; |
1231 | else | |
1232 | info->fix.line_length = info->var.xres | |
1233 | * info->var.bits_per_pixel / 8; | |
1234 | ||
ed5bebf2 | 1235 | ret = sh_mobile_lcdc_start(ch->lcdc); |
91fba48d | 1236 | if (ret < 0) { |
ed5bebf2 | 1237 | dev_err(info->dev, "%s: unable to restart LCDC\n", __func__); |
91fba48d LP |
1238 | info->fix.line_length = line_length; |
1239 | } | |
ed5bebf2 | 1240 | |
edd153a3 LP |
1241 | if (sh_mobile_format_is_fourcc(&info->var)) { |
1242 | info->fix.type = FB_TYPE_FOURCC; | |
1243 | info->fix.visual = FB_VISUAL_FOURCC; | |
1244 | } else { | |
1245 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
1246 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
1247 | } | |
1248 | ||
ed5bebf2 LP |
1249 | return ret; |
1250 | } | |
1251 | ||
8857b9aa AC |
1252 | /* |
1253 | * Screen blanking. Behavior is as follows: | |
1254 | * FB_BLANK_UNBLANK: screen unblanked, clocks enabled | |
1255 | * FB_BLANK_NORMAL: screen blanked, clocks enabled | |
1256 | * FB_BLANK_VSYNC, | |
1257 | * FB_BLANK_HSYNC, | |
1258 | * FB_BLANK_POWEROFF: screen blanked, clocks disabled | |
1259 | */ | |
1260 | static int sh_mobile_lcdc_blank(int blank, struct fb_info *info) | |
1261 | { | |
1262 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1263 | struct sh_mobile_lcdc_priv *p = ch->lcdc; | |
1264 | ||
1265 | /* blank the screen? */ | |
1266 | if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) { | |
1267 | struct fb_fillrect rect = { | |
1268 | .width = info->var.xres, | |
1269 | .height = info->var.yres, | |
1270 | }; | |
1271 | sh_mobile_lcdc_fillrect(info, &rect); | |
1272 | } | |
1273 | /* turn clocks on? */ | |
1274 | if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) { | |
1275 | sh_mobile_lcdc_clk_on(p); | |
1276 | } | |
1277 | /* turn clocks off? */ | |
1278 | if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) { | |
1279 | /* make sure the screen is updated with the black fill before | |
1280 | * switching the clocks off. one vsync is not enough since | |
1281 | * blanking may occur in the middle of a refresh. deferred io | |
1282 | * mode will reenable the clocks and update the screen in time, | |
1283 | * so it does not need this. */ | |
1284 | if (!info->fbdefio) { | |
1285 | sh_mobile_wait_for_vsync(info); | |
1286 | sh_mobile_wait_for_vsync(info); | |
1287 | } | |
1288 | sh_mobile_lcdc_clk_off(p); | |
1289 | } | |
1290 | ||
1291 | ch->blank_status = blank; | |
1292 | return 0; | |
1293 | } | |
1294 | ||
cfb4f5d1 | 1295 | static struct fb_ops sh_mobile_lcdc_ops = { |
9dd38819 | 1296 | .owner = THIS_MODULE, |
cfb4f5d1 | 1297 | .fb_setcolreg = sh_mobile_lcdc_setcolreg, |
2540c111 MD |
1298 | .fb_read = fb_sys_read, |
1299 | .fb_write = fb_sys_write, | |
8564557a MD |
1300 | .fb_fillrect = sh_mobile_lcdc_fillrect, |
1301 | .fb_copyarea = sh_mobile_lcdc_copyarea, | |
1302 | .fb_imageblit = sh_mobile_lcdc_imageblit, | |
8857b9aa | 1303 | .fb_blank = sh_mobile_lcdc_blank, |
9dd38819 | 1304 | .fb_pan_display = sh_mobile_fb_pan_display, |
40331b21 | 1305 | .fb_ioctl = sh_mobile_ioctl, |
dd210503 GL |
1306 | .fb_open = sh_mobile_open, |
1307 | .fb_release = sh_mobile_release, | |
1308 | .fb_check_var = sh_mobile_check_var, | |
ed5bebf2 | 1309 | .fb_set_par = sh_mobile_set_par, |
cfb4f5d1 MD |
1310 | }; |
1311 | ||
f1f60b5f LP |
1312 | /* ----------------------------------------------------------------------------- |
1313 | * Backlight | |
1314 | */ | |
1315 | ||
3b0fd9d7 AC |
1316 | static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev) |
1317 | { | |
1318 | struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev); | |
3b0fd9d7 AC |
1319 | int brightness = bdev->props.brightness; |
1320 | ||
1321 | if (bdev->props.power != FB_BLANK_UNBLANK || | |
1322 | bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) | |
1323 | brightness = 0; | |
1324 | ||
43059b0f | 1325 | return ch->cfg.bl_info.set_brightness(brightness); |
3b0fd9d7 AC |
1326 | } |
1327 | ||
1328 | static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev) | |
1329 | { | |
1330 | struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev); | |
3b0fd9d7 | 1331 | |
43059b0f | 1332 | return ch->cfg.bl_info.get_brightness(); |
3b0fd9d7 AC |
1333 | } |
1334 | ||
1335 | static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev, | |
1336 | struct fb_info *info) | |
1337 | { | |
1338 | return (info->bl_dev == bdev); | |
1339 | } | |
1340 | ||
1341 | static struct backlight_ops sh_mobile_lcdc_bl_ops = { | |
1342 | .options = BL_CORE_SUSPENDRESUME, | |
1343 | .update_status = sh_mobile_lcdc_update_bl, | |
1344 | .get_brightness = sh_mobile_lcdc_get_brightness, | |
1345 | .check_fb = sh_mobile_lcdc_check_fb, | |
1346 | }; | |
1347 | ||
1348 | static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent, | |
1349 | struct sh_mobile_lcdc_chan *ch) | |
1350 | { | |
1351 | struct backlight_device *bl; | |
1352 | ||
1353 | bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch, | |
1354 | &sh_mobile_lcdc_bl_ops, NULL); | |
beee1f20 DC |
1355 | if (IS_ERR(bl)) { |
1356 | dev_err(parent, "unable to register backlight device: %ld\n", | |
1357 | PTR_ERR(bl)); | |
3b0fd9d7 AC |
1358 | return NULL; |
1359 | } | |
1360 | ||
1361 | bl->props.max_brightness = ch->cfg.bl_info.max_brightness; | |
1362 | bl->props.brightness = bl->props.max_brightness; | |
1363 | backlight_update_status(bl); | |
1364 | ||
1365 | return bl; | |
1366 | } | |
1367 | ||
1368 | static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev) | |
1369 | { | |
1370 | backlight_device_unregister(bdev); | |
1371 | } | |
1372 | ||
f1f60b5f LP |
1373 | /* ----------------------------------------------------------------------------- |
1374 | * Power management | |
1375 | */ | |
1376 | ||
2feb075a MD |
1377 | static int sh_mobile_lcdc_suspend(struct device *dev) |
1378 | { | |
1379 | struct platform_device *pdev = to_platform_device(dev); | |
1380 | ||
1381 | sh_mobile_lcdc_stop(platform_get_drvdata(pdev)); | |
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | static int sh_mobile_lcdc_resume(struct device *dev) | |
1386 | { | |
1387 | struct platform_device *pdev = to_platform_device(dev); | |
1388 | ||
1389 | return sh_mobile_lcdc_start(platform_get_drvdata(pdev)); | |
1390 | } | |
1391 | ||
0246c471 MD |
1392 | static int sh_mobile_lcdc_runtime_suspend(struct device *dev) |
1393 | { | |
1394 | struct platform_device *pdev = to_platform_device(dev); | |
2427bb24 | 1395 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); |
0246c471 MD |
1396 | |
1397 | /* turn off LCDC hardware */ | |
2427bb24 LP |
1398 | lcdc_write(priv, _LDCNT1R, 0); |
1399 | ||
0246c471 MD |
1400 | return 0; |
1401 | } | |
1402 | ||
1403 | static int sh_mobile_lcdc_runtime_resume(struct device *dev) | |
1404 | { | |
1405 | struct platform_device *pdev = to_platform_device(dev); | |
2427bb24 | 1406 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); |
0246c471 | 1407 | |
2427bb24 | 1408 | __sh_mobile_lcdc_start(priv); |
0246c471 MD |
1409 | |
1410 | return 0; | |
1411 | } | |
1412 | ||
47145210 | 1413 | static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { |
2feb075a MD |
1414 | .suspend = sh_mobile_lcdc_suspend, |
1415 | .resume = sh_mobile_lcdc_resume, | |
0246c471 MD |
1416 | .runtime_suspend = sh_mobile_lcdc_runtime_suspend, |
1417 | .runtime_resume = sh_mobile_lcdc_runtime_resume, | |
2feb075a MD |
1418 | }; |
1419 | ||
f1f60b5f LP |
1420 | /* ----------------------------------------------------------------------------- |
1421 | * Framebuffer notifier | |
1422 | */ | |
1423 | ||
6de9edd5 | 1424 | /* locking: called with info->lock held */ |
6011bdea GL |
1425 | static int sh_mobile_lcdc_notify(struct notifier_block *nb, |
1426 | unsigned long action, void *data) | |
1427 | { | |
1428 | struct fb_event *event = data; | |
1429 | struct fb_info *info = event->info; | |
1430 | struct sh_mobile_lcdc_chan *ch = info->par; | |
6011bdea GL |
1431 | |
1432 | if (&ch->lcdc->notifier != nb) | |
baf16374 | 1433 | return NOTIFY_DONE; |
6011bdea GL |
1434 | |
1435 | dev_dbg(info->dev, "%s(): action = %lu, data = %p\n", | |
1436 | __func__, action, event->data); | |
1437 | ||
1438 | switch(action) { | |
1439 | case FB_EVENT_SUSPEND: | |
37c5dcc2 | 1440 | sh_mobile_lcdc_display_off(ch); |
afe417c0 | 1441 | sh_mobile_lcdc_stop(ch->lcdc); |
6011bdea GL |
1442 | break; |
1443 | case FB_EVENT_RESUME: | |
dd210503 GL |
1444 | mutex_lock(&ch->open_lock); |
1445 | sh_mobile_fb_reconfig(info); | |
1446 | mutex_unlock(&ch->open_lock); | |
6011bdea | 1447 | |
37c5dcc2 | 1448 | sh_mobile_lcdc_display_on(ch); |
ebe5e12d | 1449 | sh_mobile_lcdc_start(ch->lcdc); |
6011bdea GL |
1450 | } |
1451 | ||
baf16374 | 1452 | return NOTIFY_OK; |
6011bdea GL |
1453 | } |
1454 | ||
f1f60b5f LP |
1455 | /* ----------------------------------------------------------------------------- |
1456 | * Probe/remove and driver init/exit | |
1457 | */ | |
1458 | ||
217e9c43 | 1459 | static const struct fb_videomode default_720p __devinitconst = { |
f1f60b5f LP |
1460 | .name = "HDMI 720p", |
1461 | .xres = 1280, | |
1462 | .yres = 720, | |
1463 | ||
1464 | .left_margin = 220, | |
1465 | .right_margin = 110, | |
1466 | .hsync_len = 40, | |
1467 | ||
1468 | .upper_margin = 20, | |
1469 | .lower_margin = 5, | |
1470 | .vsync_len = 5, | |
1471 | ||
1472 | .pixclock = 13468, | |
1473 | .refresh = 60, | |
1474 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, | |
1475 | }; | |
1476 | ||
b4bee692 LP |
1477 | static int sh_mobile_lcdc_remove(struct platform_device *pdev) |
1478 | { | |
1479 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); | |
1480 | struct fb_info *info; | |
1481 | int i; | |
1482 | ||
1483 | fb_unregister_client(&priv->notifier); | |
1484 | ||
1485 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) | |
1486 | if (priv->ch[i].info && priv->ch[i].info->dev) | |
1487 | unregister_framebuffer(priv->ch[i].info); | |
1488 | ||
1489 | sh_mobile_lcdc_stop(priv); | |
1490 | ||
1491 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
9a2985e7 | 1492 | struct sh_mobile_lcdc_chan *ch = &priv->ch[i]; |
b4bee692 | 1493 | |
9a2985e7 | 1494 | info = ch->info; |
b4bee692 LP |
1495 | if (!info || !info->device) |
1496 | continue; | |
1497 | ||
9a2985e7 LP |
1498 | if (ch->tx_dev) |
1499 | module_put(ch->cfg.tx_dev->dev.driver->owner); | |
1500 | ||
1501 | if (ch->sglist) | |
1502 | vfree(ch->sglist); | |
b4bee692 LP |
1503 | |
1504 | if (info->screen_base) | |
1505 | dma_free_coherent(&pdev->dev, info->fix.smem_len, | |
9a2985e7 | 1506 | info->screen_base, ch->dma_handle); |
b4bee692 LP |
1507 | fb_dealloc_cmap(&info->cmap); |
1508 | framebuffer_release(info); | |
1509 | } | |
1510 | ||
1511 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
1512 | if (priv->ch[i].bl) | |
1513 | sh_mobile_lcdc_bl_remove(priv->ch[i].bl); | |
1514 | } | |
1515 | ||
4774c12a LP |
1516 | if (priv->dot_clk) { |
1517 | pm_runtime_disable(&pdev->dev); | |
b4bee692 | 1518 | clk_put(priv->dot_clk); |
4774c12a | 1519 | } |
b4bee692 LP |
1520 | |
1521 | if (priv->base) | |
1522 | iounmap(priv->base); | |
1523 | ||
1524 | if (priv->irq) | |
1525 | free_irq(priv->irq, priv); | |
1526 | kfree(priv); | |
1527 | return 0; | |
1528 | } | |
cfb4f5d1 | 1529 | |
217e9c43 | 1530 | static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch) |
f1f60b5f LP |
1531 | { |
1532 | int interface_type = ch->cfg.interface_type; | |
1533 | ||
1534 | switch (interface_type) { | |
1535 | case RGB8: | |
1536 | case RGB9: | |
1537 | case RGB12A: | |
1538 | case RGB12B: | |
1539 | case RGB16: | |
1540 | case RGB18: | |
1541 | case RGB24: | |
1542 | case SYS8A: | |
1543 | case SYS8B: | |
1544 | case SYS8C: | |
1545 | case SYS8D: | |
1546 | case SYS9: | |
1547 | case SYS12: | |
1548 | case SYS16A: | |
1549 | case SYS16B: | |
1550 | case SYS16C: | |
1551 | case SYS18: | |
1552 | case SYS24: | |
1553 | break; | |
1554 | default: | |
1555 | return -EINVAL; | |
1556 | } | |
1557 | ||
1558 | /* SUBLCD only supports SYS interface */ | |
1559 | if (lcdc_chan_is_sublcd(ch)) { | |
1560 | if (!(interface_type & LDMT1R_IFM)) | |
1561 | return -EINVAL; | |
1562 | ||
1563 | interface_type &= ~LDMT1R_IFM; | |
1564 | } | |
1565 | ||
1566 | ch->ldmt1r_value = interface_type; | |
1567 | return 0; | |
1568 | } | |
1569 | ||
0a7f17aa LP |
1570 | static int __devinit |
1571 | sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_priv *priv, | |
1572 | struct sh_mobile_lcdc_chan *ch) | |
cfb4f5d1 | 1573 | { |
3ce05599 LP |
1574 | struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg; |
1575 | const struct fb_videomode *max_mode; | |
1576 | const struct fb_videomode *mode; | |
1577 | struct fb_var_screeninfo *var; | |
cfb4f5d1 | 1578 | struct fb_info *info; |
3ce05599 LP |
1579 | unsigned int max_size; |
1580 | int num_cfg; | |
1581 | void *buf; | |
1582 | int ret; | |
1583 | int i; | |
1584 | ||
a67472ad LP |
1585 | mutex_init(&ch->open_lock); |
1586 | ||
1587 | /* Allocate the frame buffer device. */ | |
0a7f17aa | 1588 | ch->info = framebuffer_alloc(0, priv->dev); |
3ce05599 | 1589 | if (!ch->info) { |
0a7f17aa | 1590 | dev_err(priv->dev, "unable to allocate fb_info\n"); |
3ce05599 LP |
1591 | return -ENOMEM; |
1592 | } | |
1593 | ||
1594 | info = ch->info; | |
3ce05599 LP |
1595 | info->fbops = &sh_mobile_lcdc_ops; |
1596 | info->par = ch; | |
a67472ad LP |
1597 | info->pseudo_palette = &ch->pseudo_palette; |
1598 | info->flags = FBINFO_FLAG_DEFAULT; | |
3ce05599 | 1599 | |
9a2985e7 LP |
1600 | if (cfg->tx_dev) { |
1601 | if (!cfg->tx_dev->dev.driver || | |
1602 | !try_module_get(cfg->tx_dev->dev.driver->owner)) { | |
1603 | dev_warn(priv->dev, | |
1604 | "unable to get transmitter device\n"); | |
1605 | return -EINVAL; | |
1606 | } | |
1607 | ch->tx_dev = platform_get_drvdata(cfg->tx_dev); | |
1608 | } | |
1609 | ||
3ce05599 LP |
1610 | /* Iterate through the modes to validate them and find the highest |
1611 | * resolution. | |
1612 | */ | |
1613 | max_mode = NULL; | |
1614 | max_size = 0; | |
1615 | ||
1616 | for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) { | |
1617 | unsigned int size = mode->yres * mode->xres; | |
1618 | ||
edd153a3 LP |
1619 | /* NV12/NV21 buffers must have even number of lines */ |
1620 | if ((cfg->fourcc == V4L2_PIX_FMT_NV12 || | |
1621 | cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) { | |
0a7f17aa LP |
1622 | dev_err(priv->dev, "yres must be multiple of 2 for " |
1623 | "YCbCr420 mode.\n"); | |
3ce05599 LP |
1624 | return -EINVAL; |
1625 | } | |
1626 | ||
1627 | if (size > max_size) { | |
1628 | max_mode = mode; | |
1629 | max_size = size; | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | if (!max_size) | |
1634 | max_size = MAX_XRES * MAX_YRES; | |
1635 | else | |
0a7f17aa | 1636 | dev_dbg(priv->dev, "Found largest videomode %ux%u\n", |
3ce05599 LP |
1637 | max_mode->xres, max_mode->yres); |
1638 | ||
a67472ad | 1639 | /* Create the mode list. */ |
3ce05599 LP |
1640 | if (cfg->lcd_cfg == NULL) { |
1641 | mode = &default_720p; | |
1642 | num_cfg = 1; | |
1643 | } else { | |
1644 | mode = cfg->lcd_cfg; | |
1645 | num_cfg = cfg->num_cfg; | |
1646 | } | |
1647 | ||
1648 | fb_videomode_to_modelist(mode, num_cfg, &info->modelist); | |
1649 | ||
a67472ad LP |
1650 | /* Initialize variable screen information using the first mode as |
1651 | * default. The default Y virtual resolution is twice the panel size to | |
1652 | * allow for double-buffering. | |
1653 | */ | |
1654 | var = &info->var; | |
3ce05599 | 1655 | fb_videomode_to_var(var, mode); |
afaad83b LP |
1656 | var->width = cfg->panel_cfg.width; |
1657 | var->height = cfg->panel_cfg.height; | |
3ce05599 LP |
1658 | var->yres_virtual = var->yres * 2; |
1659 | var->activate = FB_ACTIVATE_NOW; | |
1660 | ||
edd153a3 LP |
1661 | switch (cfg->fourcc) { |
1662 | case V4L2_PIX_FMT_RGB565: | |
1663 | var->bits_per_pixel = 16; | |
1664 | break; | |
1665 | case V4L2_PIX_FMT_BGR24: | |
1666 | var->bits_per_pixel = 24; | |
1667 | break; | |
1668 | case V4L2_PIX_FMT_BGR32: | |
1669 | var->bits_per_pixel = 32; | |
1670 | break; | |
1671 | default: | |
1672 | var->grayscale = cfg->fourcc; | |
1673 | break; | |
1674 | } | |
1675 | ||
1676 | /* Make sure the memory size check won't fail. smem_len is initialized | |
1677 | * later based on var. | |
1678 | */ | |
1679 | info->fix.smem_len = UINT_MAX; | |
a67472ad | 1680 | ret = sh_mobile_check_var(var, info); |
3ce05599 LP |
1681 | if (ret) |
1682 | return ret; | |
1683 | ||
edd153a3 LP |
1684 | max_size = max_size * var->bits_per_pixel / 8 * 2; |
1685 | ||
a67472ad | 1686 | /* Allocate frame buffer memory and color map. */ |
0a7f17aa LP |
1687 | buf = dma_alloc_coherent(priv->dev, max_size, &ch->dma_handle, |
1688 | GFP_KERNEL); | |
3ce05599 | 1689 | if (!buf) { |
0a7f17aa | 1690 | dev_err(priv->dev, "unable to allocate buffer\n"); |
3ce05599 LP |
1691 | return -ENOMEM; |
1692 | } | |
1693 | ||
3ce05599 LP |
1694 | ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0); |
1695 | if (ret < 0) { | |
0a7f17aa LP |
1696 | dev_err(priv->dev, "unable to allocate cmap\n"); |
1697 | dma_free_coherent(priv->dev, max_size, buf, ch->dma_handle); | |
3ce05599 LP |
1698 | return ret; |
1699 | } | |
1700 | ||
edd153a3 LP |
1701 | /* Initialize fixed screen information. Restrict pan to 2 lines steps |
1702 | * for NV12 and NV21. | |
1703 | */ | |
1704 | info->fix = sh_mobile_lcdc_fix; | |
3ce05599 | 1705 | info->fix.smem_start = ch->dma_handle; |
edd153a3 LP |
1706 | info->fix.smem_len = max_size; |
1707 | if (cfg->fourcc == V4L2_PIX_FMT_NV12 || | |
1708 | cfg->fourcc == V4L2_PIX_FMT_NV21) | |
1709 | info->fix.ypanstep = 2; | |
1710 | ||
1711 | if (sh_mobile_format_is_yuv(var)) { | |
3ce05599 | 1712 | info->fix.line_length = var->xres; |
edd153a3 LP |
1713 | info->fix.visual = FB_VISUAL_FOURCC; |
1714 | } else { | |
1715 | info->fix.line_length = var->xres * var->bits_per_pixel / 8; | |
1716 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
1717 | } | |
3ce05599 LP |
1718 | |
1719 | info->screen_base = buf; | |
0a7f17aa | 1720 | info->device = priv->dev; |
3ce05599 LP |
1721 | ch->display_var = *var; |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
1726 | static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev) | |
1727 | { | |
01ac25b5 | 1728 | struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data; |
3ce05599 | 1729 | struct sh_mobile_lcdc_priv *priv; |
cfb4f5d1 | 1730 | struct resource *res; |
3ce05599 | 1731 | int num_channels; |
cfb4f5d1 | 1732 | int error; |
3ce05599 | 1733 | int i; |
cfb4f5d1 | 1734 | |
01ac25b5 | 1735 | if (!pdata) { |
cfb4f5d1 | 1736 | dev_err(&pdev->dev, "no platform data defined\n"); |
8bed9055 | 1737 | return -EINVAL; |
cfb4f5d1 MD |
1738 | } |
1739 | ||
1740 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8564557a MD |
1741 | i = platform_get_irq(pdev, 0); |
1742 | if (!res || i < 0) { | |
1743 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
8bed9055 | 1744 | return -ENOENT; |
cfb4f5d1 MD |
1745 | } |
1746 | ||
1747 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1748 | if (!priv) { | |
1749 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
8bed9055 | 1750 | return -ENOMEM; |
cfb4f5d1 MD |
1751 | } |
1752 | ||
4774c12a LP |
1753 | priv->dev = &pdev->dev; |
1754 | priv->meram_dev = pdata->meram_dev; | |
8bed9055 GL |
1755 | platform_set_drvdata(pdev, priv); |
1756 | ||
f8798ccb | 1757 | error = request_irq(i, sh_mobile_lcdc_irq, 0, |
7ad33e74 | 1758 | dev_name(&pdev->dev), priv); |
8564557a MD |
1759 | if (error) { |
1760 | dev_err(&pdev->dev, "unable to request irq\n"); | |
1761 | goto err1; | |
1762 | } | |
1763 | ||
1764 | priv->irq = i; | |
5ef6b505 | 1765 | atomic_set(&priv->hw_usecnt, -1); |
cfb4f5d1 | 1766 | |
3ce05599 LP |
1767 | for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) { |
1768 | struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels; | |
cfb4f5d1 | 1769 | |
01ac25b5 GL |
1770 | ch->lcdc = priv; |
1771 | memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i])); | |
cfb4f5d1 | 1772 | |
01ac25b5 | 1773 | error = sh_mobile_lcdc_check_interface(ch); |
cfb4f5d1 MD |
1774 | if (error) { |
1775 | dev_err(&pdev->dev, "unsupported interface type\n"); | |
1776 | goto err1; | |
1777 | } | |
01ac25b5 GL |
1778 | init_waitqueue_head(&ch->frame_end_wait); |
1779 | init_completion(&ch->vsync_completion); | |
1780 | ch->pan_offset = 0; | |
cfb4f5d1 | 1781 | |
3b0fd9d7 AC |
1782 | /* probe the backlight is there is one defined */ |
1783 | if (ch->cfg.bl_info.max_brightness) | |
1784 | ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch); | |
1785 | ||
cfb4f5d1 MD |
1786 | switch (pdata->ch[i].chan) { |
1787 | case LCDC_CHAN_MAINLCD: | |
ce1c0b08 | 1788 | ch->enabled = LDCNT2R_ME; |
01ac25b5 | 1789 | ch->reg_offs = lcdc_offs_mainlcd; |
3ce05599 | 1790 | num_channels++; |
cfb4f5d1 MD |
1791 | break; |
1792 | case LCDC_CHAN_SUBLCD: | |
ce1c0b08 | 1793 | ch->enabled = LDCNT2R_SE; |
01ac25b5 | 1794 | ch->reg_offs = lcdc_offs_sublcd; |
3ce05599 | 1795 | num_channels++; |
cfb4f5d1 MD |
1796 | break; |
1797 | } | |
1798 | } | |
1799 | ||
3ce05599 | 1800 | if (!num_channels) { |
cfb4f5d1 MD |
1801 | dev_err(&pdev->dev, "no channels defined\n"); |
1802 | error = -EINVAL; | |
1803 | goto err1; | |
1804 | } | |
1805 | ||
edd153a3 | 1806 | /* for dual channel LCDC (MAIN + SUB) force shared format setting */ |
3ce05599 | 1807 | if (num_channels == 2) |
edd153a3 | 1808 | priv->forced_fourcc = pdata->ch[0].fourcc; |
417d4827 | 1809 | |
dba6f385 GL |
1810 | priv->base = ioremap_nocache(res->start, resource_size(res)); |
1811 | if (!priv->base) | |
1812 | goto err1; | |
1813 | ||
0a7f17aa | 1814 | error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source); |
cfb4f5d1 MD |
1815 | if (error) { |
1816 | dev_err(&pdev->dev, "unable to setup clocks\n"); | |
1817 | goto err1; | |
1818 | } | |
1819 | ||
4774c12a LP |
1820 | /* Enable runtime PM. */ |
1821 | pm_runtime_enable(&pdev->dev); | |
7caa4342 | 1822 | |
3ce05599 | 1823 | for (i = 0; i < num_channels; i++) { |
01ac25b5 | 1824 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
c44f9f76 | 1825 | |
0a7f17aa | 1826 | error = sh_mobile_lcdc_channel_init(priv, ch); |
cfb4f5d1 | 1827 | if (error) |
3ce05599 | 1828 | goto err1; |
cfb4f5d1 MD |
1829 | } |
1830 | ||
cfb4f5d1 MD |
1831 | error = sh_mobile_lcdc_start(priv); |
1832 | if (error) { | |
1833 | dev_err(&pdev->dev, "unable to start hardware\n"); | |
1834 | goto err1; | |
1835 | } | |
1836 | ||
3ce05599 | 1837 | for (i = 0; i < num_channels; i++) { |
1c6a307a | 1838 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
3ce05599 | 1839 | struct fb_info *info = ch->info; |
1c6a307a PM |
1840 | |
1841 | if (info->fbdefio) { | |
8bed9055 | 1842 | ch->sglist = vmalloc(sizeof(struct scatterlist) * |
1c6a307a | 1843 | info->fix.smem_len >> PAGE_SHIFT); |
8bed9055 | 1844 | if (!ch->sglist) { |
1c6a307a PM |
1845 | dev_err(&pdev->dev, "cannot allocate sglist\n"); |
1846 | goto err1; | |
1847 | } | |
1848 | } | |
1849 | ||
3b0fd9d7 AC |
1850 | info->bl_dev = ch->bl; |
1851 | ||
1c6a307a | 1852 | error = register_framebuffer(info); |
cfb4f5d1 MD |
1853 | if (error < 0) |
1854 | goto err1; | |
cfb4f5d1 | 1855 | |
0a7f17aa | 1856 | dev_info(&pdev->dev, "registered %s/%s as %dx%d %dbpp.\n", |
edd153a3 LP |
1857 | pdev->name, (ch->cfg.chan == LCDC_CHAN_MAINLCD) ? |
1858 | "mainlcd" : "sublcd", info->var.xres, info->var.yres, | |
1859 | info->var.bits_per_pixel); | |
8564557a MD |
1860 | |
1861 | /* deferred io mode: disable clock to save power */ | |
6011bdea | 1862 | if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED) |
8564557a | 1863 | sh_mobile_lcdc_clk_off(priv); |
cfb4f5d1 MD |
1864 | } |
1865 | ||
6011bdea GL |
1866 | /* Failure ignored */ |
1867 | priv->notifier.notifier_call = sh_mobile_lcdc_notify; | |
1868 | fb_register_client(&priv->notifier); | |
1869 | ||
cfb4f5d1 | 1870 | return 0; |
8bed9055 | 1871 | err1: |
cfb4f5d1 | 1872 | sh_mobile_lcdc_remove(pdev); |
8bed9055 | 1873 | |
cfb4f5d1 MD |
1874 | return error; |
1875 | } | |
1876 | ||
cfb4f5d1 MD |
1877 | static struct platform_driver sh_mobile_lcdc_driver = { |
1878 | .driver = { | |
1879 | .name = "sh_mobile_lcdc_fb", | |
1880 | .owner = THIS_MODULE, | |
2feb075a | 1881 | .pm = &sh_mobile_lcdc_dev_pm_ops, |
cfb4f5d1 MD |
1882 | }, |
1883 | .probe = sh_mobile_lcdc_probe, | |
1884 | .remove = sh_mobile_lcdc_remove, | |
1885 | }; | |
1886 | ||
4277f2c4 | 1887 | module_platform_driver(sh_mobile_lcdc_driver); |
cfb4f5d1 MD |
1888 | |
1889 | MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver"); | |
1890 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); | |
1891 | MODULE_LICENSE("GPL v2"); |