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CommitLineData
cfb4f5d1
MD
1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
3b0fd9d7
AC
24#include <linux/backlight.h>
25#include <linux/gpio.h>
225c9a8d 26#include <video/sh_mobile_lcdc.h>
8564557a 27#include <asm/atomic.h>
cfb4f5d1 28
6de9edd5
GL
29#include "sh_mobile_lcdcfb.h"
30
a6f15ade
PE
31#define SIDE_B_OFFSET 0x1000
32#define MIRROR_OFFSET 0x2000
cfb4f5d1 33
cfb4f5d1
MD
34/* shared registers */
35#define _LDDCKR 0x410
36#define _LDDCKSTPR 0x414
37#define _LDINTR 0x468
38#define _LDSR 0x46c
39#define _LDCNT1R 0x470
40#define _LDCNT2R 0x474
9dd38819 41#define _LDRCNTR 0x478
cfb4f5d1
MD
42#define _LDDDSR 0x47c
43#define _LDDWD0R 0x800
44#define _LDDRDR 0x840
45#define _LDDWAR 0x900
46#define _LDDRAR 0x904
47
0246c471
MD
48/* shared registers and their order for context save/restore */
49static int lcdc_shared_regs[] = {
50 _LDDCKR,
51 _LDDCKSTPR,
52 _LDINTR,
53 _LDDDSR,
54 _LDCNT1R,
55 _LDCNT2R,
56};
57#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
58
d2ecbab5
GL
59#define MAX_XRES 1920
60#define MAX_YRES 1080
cfb4f5d1 61
0246c471 62static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD
63 [LDDCKPAT1R] = 0x400,
64 [LDDCKPAT2R] = 0x404,
65 [LDMT1R] = 0x418,
66 [LDMT2R] = 0x41c,
67 [LDMT3R] = 0x420,
68 [LDDFR] = 0x424,
69 [LDSM1R] = 0x428,
8564557a 70 [LDSM2R] = 0x42c,
cfb4f5d1
MD
71 [LDSA1R] = 0x430,
72 [LDMLSR] = 0x438,
73 [LDHCNR] = 0x448,
74 [LDHSYNR] = 0x44c,
75 [LDVLNR] = 0x450,
76 [LDVSYNR] = 0x454,
77 [LDPMR] = 0x460,
6011bdea 78 [LDHAJR] = 0x4a0,
cfb4f5d1
MD
79};
80
0246c471 81static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD
82 [LDDCKPAT1R] = 0x408,
83 [LDDCKPAT2R] = 0x40c,
84 [LDMT1R] = 0x600,
85 [LDMT2R] = 0x604,
86 [LDMT3R] = 0x608,
87 [LDDFR] = 0x60c,
88 [LDSM1R] = 0x610,
8564557a 89 [LDSM2R] = 0x614,
cfb4f5d1
MD
90 [LDSA1R] = 0x618,
91 [LDMLSR] = 0x620,
92 [LDHCNR] = 0x624,
93 [LDHSYNR] = 0x628,
94 [LDVLNR] = 0x62c,
95 [LDVSYNR] = 0x630,
96 [LDPMR] = 0x63c,
97};
98
99#define START_LCDC 0x00000001
100#define LCDC_RESET 0x00000100
101#define DISPLAY_BEU 0x00000008
102#define LCDC_ENABLE 0x00000001
8564557a 103#define LDINTR_FE 0x00000400
9dd38819
PE
104#define LDINTR_VSE 0x00000200
105#define LDINTR_VEE 0x00000100
8564557a 106#define LDINTR_FS 0x00000004
9dd38819
PE
107#define LDINTR_VSS 0x00000002
108#define LDINTR_VES 0x00000001
a6f15ade
PE
109#define LDRCNTR_SRS 0x00020000
110#define LDRCNTR_SRC 0x00010000
111#define LDRCNTR_MRS 0x00000002
112#define LDRCNTR_MRC 0x00000001
40331b21 113#define LDSR_MRS 0x00000100
cfb4f5d1 114
c44f9f76
GL
115static const struct fb_videomode default_720p = {
116 .name = "HDMI 720p",
117 .xres = 1280,
118 .yres = 720,
119
5ae0cf82
GL
120 .left_margin = 220,
121 .right_margin = 110,
122 .hsync_len = 40,
c44f9f76
GL
123
124 .upper_margin = 20,
125 .lower_margin = 5,
126 .vsync_len = 5,
127
128 .pixclock = 13468,
5ae0cf82 129 .refresh = 60,
c44f9f76 130 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD
131};
132
133struct sh_mobile_lcdc_priv {
134 void __iomem *base;
135 int irq;
136 atomic_t hw_usecnt;
137 struct device *dev;
138 struct clk *dot_clk;
139 unsigned long lddckr;
140 struct sh_mobile_lcdc_chan ch[2];
6011bdea 141 struct notifier_block notifier;
0246c471
MD
142 unsigned long saved_shared_regs[NR_SHARED_REGS];
143 int started;
417d4827 144 int forced_bpp; /* 2 channel LCDC must share bpp setting */
0246c471
MD
145};
146
a6f15ade
PE
147static bool banked(int reg_nr)
148{
149 switch (reg_nr) {
150 case LDMT1R:
151 case LDMT2R:
152 case LDMT3R:
153 case LDDFR:
154 case LDSM1R:
155 case LDSA1R:
156 case LDMLSR:
157 case LDHCNR:
158 case LDHSYNR:
159 case LDVLNR:
160 case LDVSYNR:
161 return true;
162 }
163 return false;
164}
165
cfb4f5d1
MD
166static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
167 int reg_nr, unsigned long data)
168{
169 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE
170 if (banked(reg_nr))
171 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
172 SIDE_B_OFFSET);
173}
174
175static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
176 int reg_nr, unsigned long data)
177{
178 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
179 MIRROR_OFFSET);
cfb4f5d1
MD
180}
181
182static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
183 int reg_nr)
184{
185 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
186}
187
188static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
189 unsigned long reg_offs, unsigned long data)
190{
191 iowrite32(data, priv->base + reg_offs);
192}
193
194static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
195 unsigned long reg_offs)
196{
197 return ioread32(priv->base + reg_offs);
198}
199
200static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
201 unsigned long reg_offs,
202 unsigned long mask, unsigned long until)
203{
204 while ((lcdc_read(priv, reg_offs) & mask) != until)
205 cpu_relax();
206}
207
208static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
209{
210 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
211}
212
213static void lcdc_sys_write_index(void *handle, unsigned long data)
214{
215 struct sh_mobile_lcdc_chan *ch = handle;
216
217 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
218 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
219 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 220 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD
221}
222
223static void lcdc_sys_write_data(void *handle, unsigned long data)
224{
225 struct sh_mobile_lcdc_chan *ch = handle;
226
227 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
228 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
229 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 230 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD
231}
232
233static unsigned long lcdc_sys_read_data(void *handle)
234{
235 struct sh_mobile_lcdc_chan *ch = handle;
236
237 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
238 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
239 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
240 udelay(1);
909f10de 241 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 242
ec56b66f 243 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD
244}
245
246struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
247 lcdc_sys_write_index,
248 lcdc_sys_write_data,
249 lcdc_sys_read_data,
250};
251
8564557a
MD
252static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
253{
0246c471
MD
254 if (atomic_inc_and_test(&priv->hw_usecnt)) {
255 pm_runtime_get_sync(priv->dev);
8564557a
MD
256 if (priv->dot_clk)
257 clk_enable(priv->dot_clk);
258 }
259}
260
261static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
262{
0246c471 263 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD
264 if (priv->dot_clk)
265 clk_disable(priv->dot_clk);
0246c471 266 pm_runtime_put(priv->dev);
8564557a
MD
267 }
268}
8564557a 269
1c6a307a
PM
270static int sh_mobile_lcdc_sginit(struct fb_info *info,
271 struct list_head *pagelist)
272{
273 struct sh_mobile_lcdc_chan *ch = info->par;
274 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
275 struct page *page;
276 int nr_pages = 0;
277
278 sg_init_table(ch->sglist, nr_pages_max);
279
280 list_for_each_entry(page, pagelist, lru)
281 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
282
283 return nr_pages;
284}
285
8564557a
MD
286static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
287 struct list_head *pagelist)
288{
289 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 290 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD
291
292 /* enable clocks before accessing hardware */
293 sh_mobile_lcdc_clk_on(ch->lcdc);
294
5c1a56b5
PM
295 /*
296 * It's possible to get here without anything on the pagelist via
297 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
298 * invocation. In the former case, the acceleration routines are
299 * stepped in to when using the framebuffer console causing the
300 * workqueue to be scheduled without any dirty pages on the list.
301 *
302 * Despite this, a panel update is still needed given that the
303 * acceleration routines have their own methods for writing in
304 * that still need to be updated.
305 *
306 * The fsync() and empty pagelist case could be optimized for,
307 * but we don't bother, as any application exhibiting such
308 * behaviour is fundamentally broken anyways.
309 */
310 if (!list_empty(pagelist)) {
311 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
312
313 /* trigger panel update */
314 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD
315 if (bcfg->start_transfer)
316 bcfg->start_transfer(bcfg->board_data, ch,
317 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM
318 lcdc_write_chan(ch, LDSM2R, 1);
319 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD
320 } else {
321 if (bcfg->start_transfer)
322 bcfg->start_transfer(bcfg->board_data, ch,
323 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 324 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 325 }
8564557a
MD
326}
327
328static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
329{
330 struct fb_deferred_io *fbdefio = info->fbdefio;
331
332 if (fbdefio)
333 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
334}
335
336static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
337{
338 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 339 struct sh_mobile_lcdc_chan *ch;
8564557a 340 unsigned long tmp;
9dd38819 341 unsigned long ldintr;
2feb075a
MD
342 int is_sub;
343 int k;
8564557a
MD
344
345 /* acknowledge interrupt */
9dd38819
PE
346 ldintr = tmp = lcdc_read(priv, _LDINTR);
347 /*
348 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
349 * write 0 to bits 0-6 to ack all triggered IRQs.
350 */
351 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD
352 lcdc_write(priv, _LDINTR, tmp);
353
2feb075a
MD
354 /* figure out if this interrupt is for main or sub lcd */
355 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
356
9dd38819 357 /* wake up channel and disable clocks */
2feb075a
MD
358 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
359 ch = &priv->ch[k];
360
361 if (!ch->enabled)
362 continue;
363
9dd38819
PE
364 /* Frame Start */
365 if (ldintr & LDINTR_FS) {
366 if (is_sub == lcdc_chan_is_sublcd(ch)) {
367 ch->frame_end = 1;
368 wake_up(&ch->frame_end_wait);
2feb075a 369
9dd38819
PE
370 sh_mobile_lcdc_clk_off(priv);
371 }
372 }
373
374 /* VSYNC End */
40331b21
PE
375 if (ldintr & LDINTR_VES)
376 complete(&ch->vsync_completion);
2feb075a
MD
377 }
378
8564557a
MD
379 return IRQ_HANDLED;
380}
381
cfb4f5d1
MD
382static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
383 int start)
384{
385 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
386 int k;
387
388 /* start or stop the lcdc */
389 if (start)
390 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
391 else
392 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
393
394 /* wait until power is applied/stopped on all channels */
395 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
396 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
397 while (1) {
398 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
399 if (start && tmp == 3)
400 break;
401 if (!start && tmp == 0)
402 break;
403 cpu_relax();
404 }
405
406 if (!start)
407 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
408}
409
6011bdea
GL
410static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
411{
1c120deb
GL
412 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
413 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL
414 u32 tmp;
415
416 tmp = ch->ldmt1r_value;
417 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
418 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
419 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
420 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
421 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
422 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
423 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
424 lcdc_write_chan(ch, LDMT1R, tmp);
425
426 /* setup SYS bus */
427 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
428 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
429
430 /* horizontal configuration */
1c120deb
GL
431 h_total = display_var->xres + display_var->hsync_len +
432 display_var->left_margin + display_var->right_margin;
6011bdea 433 tmp = h_total / 8; /* HTCN */
1c120deb 434 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL
435 lcdc_write_chan(ch, LDHCNR, tmp);
436
1c120deb 437 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 438 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 439 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL
440 lcdc_write_chan(ch, LDHSYNR, tmp);
441
442 /* vertical configuration */
1c120deb
GL
443 tmp = display_var->yres + display_var->vsync_len +
444 display_var->upper_margin + display_var->lower_margin; /* VTLN */
445 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL
446 lcdc_write_chan(ch, LDVLNR, tmp);
447
1c120deb
GL
448 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
449 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL
450 lcdc_write_chan(ch, LDVSYNR, tmp);
451
452 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL
453 display_h_total = display_var->xres + display_var->hsync_len +
454 display_var->left_margin + display_var->right_margin;
455 tmp = ((display_var->xres & 7) << 24) |
456 ((display_h_total & 7) << 16) |
457 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL
458 hsync_pos;
459 lcdc_write_chan(ch, LDHAJR, tmp);
460}
461
cfb4f5d1
MD
462static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
463{
464 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD
465 struct sh_mobile_lcdc_board_cfg *board_cfg;
466 unsigned long tmp;
417d4827 467 int bpp = 0;
cfb4f5d1
MD
468 int k, m;
469 int ret = 0;
470
8564557a 471 /* enable clocks before accessing the hardware */
417d4827
MD
472 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
473 if (priv->ch[k].enabled) {
8564557a 474 sh_mobile_lcdc_clk_on(priv);
417d4827
MD
475 if (!bpp)
476 bpp = priv->ch[k].info->var.bits_per_pixel;
477 }
478 }
8564557a 479
cfb4f5d1
MD
480 /* reset */
481 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
482 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
483
484 /* enable LCDC channels */
485 tmp = lcdc_read(priv, _LDCNT2R);
486 tmp |= priv->ch[0].enabled;
487 tmp |= priv->ch[1].enabled;
488 lcdc_write(priv, _LDCNT2R, tmp);
489
490 /* read data from external memory, avoid using the BEU for now */
491 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
492
493 /* stop the lcdc first */
494 sh_mobile_lcdc_start_stop(priv, 0);
495
496 /* configure clocks */
497 tmp = priv->lddckr;
498 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
499 ch = &priv->ch[k];
500
501 if (!priv->ch[k].enabled)
502 continue;
503
504 m = ch->cfg.clock_divider;
505 if (!m)
506 continue;
507
508 if (m == 1)
509 m = 1 << 6;
510 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
511
dd210503 512 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
1c120deb 513 lcdc_write_chan(ch, LDDCKPAT1R, 0);
cfb4f5d1
MD
514 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
515 }
516
517 lcdc_write(priv, _LDDCKR, tmp);
518
519 /* start dotclock again */
520 lcdc_write(priv, _LDDCKSTPR, 0);
521 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
522
8564557a 523 /* interrupts are disabled to begin with */
cfb4f5d1
MD
524 lcdc_write(priv, _LDINTR, 0);
525
526 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
527 ch = &priv->ch[k];
cfb4f5d1
MD
528
529 if (!ch->enabled)
530 continue;
531
6011bdea 532 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD
533
534 /* power supply */
535 lcdc_write_chan(ch, LDPMR, 0);
536
cfb4f5d1
MD
537 board_cfg = &ch->cfg.board_cfg;
538 if (board_cfg->setup_sys)
539 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
540 &sh_mobile_lcdc_sys_bus_ops);
541 if (ret)
542 return ret;
543 }
544
cfb4f5d1 545 /* word and long word swap */
417d4827
MD
546 switch (bpp) {
547 case 16:
548 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
549 break;
550 case 24:
551 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 7);
552 break;
553 case 32:
554 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 4);
555 break;
556 }
cfb4f5d1
MD
557
558 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
559 ch = &priv->ch[k];
560
561 if (!priv->ch[k].enabled)
562 continue;
563
564 /* set bpp format in PKF[4:0] */
565 tmp = lcdc_read_chan(ch, LDDFR);
1c120deb 566 tmp &= ~0x0001001f;
417d4827
MD
567 switch (ch->info->var.bits_per_pixel) {
568 case 16:
569 tmp |= 0x03;
570 break;
571 case 24:
572 tmp |= 0x0b;
573 break;
574 case 32:
575 break;
576 }
cfb4f5d1
MD
577 lcdc_write_chan(ch, LDDFR, tmp);
578
579 /* point out our frame buffer */
e33afddc 580 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD
581
582 /* set line size */
e33afddc 583 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 584
8564557a
MD
585 /* setup deferred io if SYS bus */
586 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
587 if (ch->ldmt1r_value & (1 << 12) && tmp) {
588 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
589 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM
590 ch->info->fbdefio = &ch->defio;
591 fb_deferred_io_init(ch->info);
8564557a
MD
592
593 /* one-shot mode */
594 lcdc_write_chan(ch, LDSM1R, 1);
595
596 /* enable "Frame End Interrupt Enable" bit */
597 lcdc_write(priv, _LDINTR, LDINTR_FE);
598
599 } else {
600 /* continuous read mode */
601 lcdc_write_chan(ch, LDSM1R, 0);
602 }
cfb4f5d1
MD
603 }
604
605 /* display output */
606 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
607
608 /* start the lcdc */
609 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 610 priv->started = 1;
cfb4f5d1
MD
611
612 /* tell the board code to enable the panel */
613 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
614 ch = &priv->ch[k];
21bc1f02
MD
615 if (!ch->enabled)
616 continue;
617
cfb4f5d1 618 board_cfg = &ch->cfg.board_cfg;
6de9edd5 619 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
c2439398 620 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL
621 module_put(board_cfg->owner);
622 }
3b0fd9d7
AC
623
624 if (ch->bl) {
625 ch->bl->props.power = FB_BLANK_UNBLANK;
626 backlight_update_status(ch->bl);
627 }
cfb4f5d1
MD
628 }
629
630 return 0;
631}
632
633static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
634{
635 struct sh_mobile_lcdc_chan *ch;
636 struct sh_mobile_lcdc_board_cfg *board_cfg;
637 int k;
638
2feb075a 639 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD
640 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
641 ch = &priv->ch[k];
21bc1f02
MD
642 if (!ch->enabled)
643 continue;
8564557a 644
2feb075a
MD
645 /* deferred io mode:
646 * flush frame, and wait for frame end interrupt
647 * clean up deferred io and enable clock
648 */
5ef6b505 649 if (ch->info && ch->info->fbdefio) {
2feb075a 650 ch->frame_end = 0;
e33afddc 651 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 652 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM
653 fb_deferred_io_cleanup(ch->info);
654 ch->info->fbdefio = NULL;
2feb075a 655 sh_mobile_lcdc_clk_on(priv);
8564557a 656 }
2feb075a 657
3b0fd9d7
AC
658 if (ch->bl) {
659 ch->bl->props.power = FB_BLANK_POWERDOWN;
660 backlight_update_status(ch->bl);
661 }
662
2feb075a 663 board_cfg = &ch->cfg.board_cfg;
6de9edd5 664 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
2feb075a 665 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL
666 module_put(board_cfg->owner);
667 }
cfb4f5d1
MD
668 }
669
670 /* stop the lcdc */
8e9bb19e
MD
671 if (priv->started) {
672 sh_mobile_lcdc_start_stop(priv, 0);
673 priv->started = 0;
674 }
b51339ff 675
8564557a
MD
676 /* stop clocks */
677 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
678 if (priv->ch[k].enabled)
679 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD
680}
681
682static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
683{
684 int ifm, miftyp;
685
686 switch (ch->cfg.interface_type) {
687 case RGB8: ifm = 0; miftyp = 0; break;
688 case RGB9: ifm = 0; miftyp = 4; break;
689 case RGB12A: ifm = 0; miftyp = 5; break;
690 case RGB12B: ifm = 0; miftyp = 6; break;
691 case RGB16: ifm = 0; miftyp = 7; break;
692 case RGB18: ifm = 0; miftyp = 10; break;
693 case RGB24: ifm = 0; miftyp = 11; break;
694 case SYS8A: ifm = 1; miftyp = 0; break;
695 case SYS8B: ifm = 1; miftyp = 1; break;
696 case SYS8C: ifm = 1; miftyp = 2; break;
697 case SYS8D: ifm = 1; miftyp = 3; break;
698 case SYS9: ifm = 1; miftyp = 4; break;
699 case SYS12: ifm = 1; miftyp = 5; break;
700 case SYS16A: ifm = 1; miftyp = 7; break;
701 case SYS16B: ifm = 1; miftyp = 8; break;
702 case SYS16C: ifm = 1; miftyp = 9; break;
703 case SYS18: ifm = 1; miftyp = 10; break;
704 case SYS24: ifm = 1; miftyp = 11; break;
705 default: goto bad;
706 }
707
708 /* SUBLCD only supports SYS interface */
709 if (lcdc_chan_is_sublcd(ch)) {
710 if (ifm == 0)
711 goto bad;
712 else
713 ifm = 0;
714 }
715
716 ch->ldmt1r_value = (ifm << 12) | miftyp;
717 return 0;
718 bad:
719 return -EINVAL;
720}
721
b51339ff
MD
722static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
723 int clock_source,
cfb4f5d1
MD
724 struct sh_mobile_lcdc_priv *priv)
725{
726 char *str;
727 int icksel;
728
729 switch (clock_source) {
730 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
731 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
732 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
733 default:
734 return -EINVAL;
735 }
736
737 priv->lddckr = icksel << 16;
738
739 if (str) {
b51339ff
MD
740 priv->dot_clk = clk_get(&pdev->dev, str);
741 if (IS_ERR(priv->dot_clk)) {
742 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 743 return PTR_ERR(priv->dot_clk);
cfb4f5d1 744 }
cfb4f5d1 745 }
0246c471
MD
746
747 /* Runtime PM support involves two step for this driver:
748 * 1) Enable Runtime PM
749 * 2) Force Runtime PM Resume since hardware is accessed from probe()
750 */
8bed9055 751 priv->dev = &pdev->dev;
0246c471
MD
752 pm_runtime_enable(priv->dev);
753 pm_runtime_resume(priv->dev);
cfb4f5d1
MD
754 return 0;
755}
756
757static int sh_mobile_lcdc_setcolreg(u_int regno,
758 u_int red, u_int green, u_int blue,
759 u_int transp, struct fb_info *info)
760{
761 u32 *palette = info->pseudo_palette;
762
763 if (regno >= PALETTE_NR)
764 return -EINVAL;
765
766 /* only FB_VISUAL_TRUECOLOR supported */
767
768 red >>= 16 - info->var.red.length;
769 green >>= 16 - info->var.green.length;
770 blue >>= 16 - info->var.blue.length;
771 transp >>= 16 - info->var.transp.length;
772
773 palette[regno] = (red << info->var.red.offset) |
774 (green << info->var.green.offset) |
775 (blue << info->var.blue.offset) |
776 (transp << info->var.transp.offset);
777
778 return 0;
779}
780
781static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
782 .id = "SH Mobile LCDC",
783 .type = FB_TYPE_PACKED_PIXELS,
784 .visual = FB_VISUAL_TRUECOLOR,
785 .accel = FB_ACCEL_NONE,
9dd38819
PE
786 .xpanstep = 0,
787 .ypanstep = 1,
788 .ywrapstep = 0,
cfb4f5d1
MD
789};
790
8564557a
MD
791static void sh_mobile_lcdc_fillrect(struct fb_info *info,
792 const struct fb_fillrect *rect)
793{
794 sys_fillrect(info, rect);
795 sh_mobile_lcdc_deferred_io_touch(info);
796}
797
798static void sh_mobile_lcdc_copyarea(struct fb_info *info,
799 const struct fb_copyarea *area)
800{
801 sys_copyarea(info, area);
802 sh_mobile_lcdc_deferred_io_touch(info);
803}
804
805static void sh_mobile_lcdc_imageblit(struct fb_info *info,
806 const struct fb_image *image)
807{
808 sys_imageblit(info, image);
809 sh_mobile_lcdc_deferred_io_touch(info);
810}
811
9dd38819
PE
812static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
813 struct fb_info *info)
814{
815 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE
816 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
817 unsigned long ldrcntr;
818 unsigned long new_pan_offset;
819
820 new_pan_offset = (var->yoffset * info->fix.line_length) +
821 (var->xoffset * (info->var.bits_per_pixel / 8));
9dd38819 822
92e1f9a7 823 if (new_pan_offset == ch->pan_offset)
9dd38819
PE
824 return 0; /* No change, do nothing */
825
92e1f9a7 826 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 827
92e1f9a7
PE
828 /* Set the source address for the next refresh */
829 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
830 if (lcdc_chan_is_sublcd(ch))
831 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
832 else
833 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
834
835 ch->pan_offset = new_pan_offset;
836
837 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE
838
839 return 0;
840}
841
40331b21
PE
842static int sh_mobile_wait_for_vsync(struct fb_info *info)
843{
844 struct sh_mobile_lcdc_chan *ch = info->par;
845 unsigned long ldintr;
846 int ret;
847
848 /* Enable VSync End interrupt */
849 ldintr = lcdc_read(ch->lcdc, _LDINTR);
850 ldintr |= LDINTR_VEE;
851 lcdc_write(ch->lcdc, _LDINTR, ldintr);
852
853 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
854 msecs_to_jiffies(100));
855 if (!ret)
856 return -ETIMEDOUT;
857
858 return 0;
859}
860
861static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
862 unsigned long arg)
863{
864 int retval;
865
866 switch (cmd) {
867 case FBIO_WAITFORVSYNC:
868 retval = sh_mobile_wait_for_vsync(info);
869 break;
870
871 default:
872 retval = -ENOIOCTLCMD;
873 break;
874 }
875 return retval;
876}
877
dd210503
GL
878static void sh_mobile_fb_reconfig(struct fb_info *info)
879{
880 struct sh_mobile_lcdc_chan *ch = info->par;
881 struct fb_videomode mode1, mode2;
882 struct fb_event event;
883 int evnt = FB_EVENT_MODE_CHANGE_ALL;
884
885 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
886 /* More framebuffer users are active */
887 return;
888
889 fb_var_to_videomode(&mode1, &ch->display_var);
890 fb_var_to_videomode(&mode2, &info->var);
891
892 if (fb_mode_is_equal(&mode1, &mode2))
893 return;
894
895 /* Display has been re-plugged, framebuffer is free now, reconfigure */
896 if (fb_set_var(info, &ch->display_var) < 0)
897 /* Couldn't reconfigure, hopefully, can continue as before */
898 return;
899
cc267ec5 900 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
dd210503
GL
901
902 /*
903 * fb_set_var() calls the notifier change internally, only if
904 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
905 * user event, we have to call the chain ourselves.
906 */
907 event.info = info;
cc267ec5 908 event.data = &mode1;
dd210503
GL
909 fb_notifier_call_chain(evnt, &event);
910}
911
912/*
913 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
914 * user == 1, or with console sem held, if user == 0.
915 */
916static int sh_mobile_release(struct fb_info *info, int user)
917{
918 struct sh_mobile_lcdc_chan *ch = info->par;
919
920 mutex_lock(&ch->open_lock);
921 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
922
923 ch->use_count--;
924
925 /* Nothing to reconfigure, when called from fbcon */
926 if (user) {
ac751efa 927 console_lock();
dd210503 928 sh_mobile_fb_reconfig(info);
ac751efa 929 console_unlock();
dd210503
GL
930 }
931
932 mutex_unlock(&ch->open_lock);
933
934 return 0;
935}
936
937static int sh_mobile_open(struct fb_info *info, int user)
938{
939 struct sh_mobile_lcdc_chan *ch = info->par;
940
941 mutex_lock(&ch->open_lock);
942 ch->use_count++;
943
944 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
945 mutex_unlock(&ch->open_lock);
946
947 return 0;
948}
949
950static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
951{
952 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 953 struct sh_mobile_lcdc_priv *p = ch->lcdc;
dd210503 954
d2ecbab5 955 if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
dd210503 956 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
830539d1 957 dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
d2ecbab5
GL
958 var->left_margin, var->xres, var->right_margin, var->hsync_len,
959 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
960 PICOS2KHZ(var->pixclock));
dd210503
GL
961 return -EINVAL;
962 }
417d4827
MD
963
964 /* only accept the forced_bpp for dual channel configurations */
965 if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
966 return -EINVAL;
967
968 switch (var->bits_per_pixel) {
969 case 16: /* PKF[4:0] = 00011 - RGB 565 */
970 case 24: /* PKF[4:0] = 01011 - RGB 888 */
971 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
972 break;
973 default:
974 return -EINVAL;
975 }
976
dd210503
GL
977 return 0;
978}
40331b21 979
cfb4f5d1 980static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 981 .owner = THIS_MODULE,
cfb4f5d1 982 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD
983 .fb_read = fb_sys_read,
984 .fb_write = fb_sys_write,
8564557a
MD
985 .fb_fillrect = sh_mobile_lcdc_fillrect,
986 .fb_copyarea = sh_mobile_lcdc_copyarea,
987 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 988 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 989 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL
990 .fb_open = sh_mobile_open,
991 .fb_release = sh_mobile_release,
992 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD
993};
994
3b0fd9d7
AC
995static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
996{
997 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
998 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
999 int brightness = bdev->props.brightness;
1000
1001 if (bdev->props.power != FB_BLANK_UNBLANK ||
1002 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1003 brightness = 0;
1004
1005 return cfg->set_brightness(cfg->board_data, brightness);
1006}
1007
1008static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1009{
1010 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1011 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1012
1013 return cfg->get_brightness(cfg->board_data);
1014}
1015
1016static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1017 struct fb_info *info)
1018{
1019 return (info->bl_dev == bdev);
1020}
1021
1022static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1023 .options = BL_CORE_SUSPENDRESUME,
1024 .update_status = sh_mobile_lcdc_update_bl,
1025 .get_brightness = sh_mobile_lcdc_get_brightness,
1026 .check_fb = sh_mobile_lcdc_check_fb,
1027};
1028
1029static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1030 struct sh_mobile_lcdc_chan *ch)
1031{
1032 struct backlight_device *bl;
1033
1034 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1035 &sh_mobile_lcdc_bl_ops, NULL);
1036 if (!bl) {
1037 dev_err(parent, "unable to register backlight device\n");
1038 return NULL;
1039 }
1040
1041 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1042 bl->props.brightness = bl->props.max_brightness;
1043 backlight_update_status(bl);
1044
1045 return bl;
1046}
1047
1048static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1049{
1050 backlight_device_unregister(bdev);
1051}
1052
cfb4f5d1
MD
1053static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
1054{
1055 switch (bpp) {
1056 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1057 var->red.offset = 11;
1058 var->red.length = 5;
1059 var->green.offset = 5;
1060 var->green.length = 6;
1061 var->blue.offset = 0;
1062 var->blue.length = 5;
1063 var->transp.offset = 0;
1064 var->transp.length = 0;
1065 break;
1066
417d4827
MD
1067 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1068 var->red.offset = 16;
cfb4f5d1 1069 var->red.length = 8;
417d4827 1070 var->green.offset = 8;
cfb4f5d1 1071 var->green.length = 8;
417d4827 1072 var->blue.offset = 0;
cfb4f5d1
MD
1073 var->blue.length = 8;
1074 var->transp.offset = 0;
1075 var->transp.length = 0;
1076 break;
417d4827
MD
1077
1078 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1079 var->red.offset = 16;
1080 var->red.length = 8;
1081 var->green.offset = 8;
1082 var->green.length = 8;
1083 var->blue.offset = 0;
1084 var->blue.length = 8;
1085 var->transp.offset = 24;
1086 var->transp.length = 8;
1087 break;
cfb4f5d1
MD
1088 default:
1089 return -EINVAL;
1090 }
1091 var->bits_per_pixel = bpp;
1092 var->red.msb_right = 0;
1093 var->green.msb_right = 0;
1094 var->blue.msb_right = 0;
1095 var->transp.msb_right = 0;
1096 return 0;
1097}
1098
2feb075a
MD
1099static int sh_mobile_lcdc_suspend(struct device *dev)
1100{
1101 struct platform_device *pdev = to_platform_device(dev);
1102
1103 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1104 return 0;
1105}
1106
1107static int sh_mobile_lcdc_resume(struct device *dev)
1108{
1109 struct platform_device *pdev = to_platform_device(dev);
1110
1111 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1112}
1113
0246c471
MD
1114static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1115{
1116 struct platform_device *pdev = to_platform_device(dev);
1117 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1118 struct sh_mobile_lcdc_chan *ch;
1119 int k, n;
1120
1121 /* save per-channel registers */
1122 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1123 ch = &p->ch[k];
1124 if (!ch->enabled)
1125 continue;
1126 for (n = 0; n < NR_CH_REGS; n++)
1127 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1128 }
1129
1130 /* save shared registers */
1131 for (n = 0; n < NR_SHARED_REGS; n++)
1132 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1133
1134 /* turn off LCDC hardware */
1135 lcdc_write(p, _LDCNT1R, 0);
1136 return 0;
1137}
1138
1139static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1140{
1141 struct platform_device *pdev = to_platform_device(dev);
1142 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1143 struct sh_mobile_lcdc_chan *ch;
1144 int k, n;
1145
1146 /* restore per-channel registers */
1147 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1148 ch = &p->ch[k];
1149 if (!ch->enabled)
1150 continue;
1151 for (n = 0; n < NR_CH_REGS; n++)
1152 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1153 }
1154
1155 /* restore shared registers */
1156 for (n = 0; n < NR_SHARED_REGS; n++)
1157 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1158
1159 return 0;
1160}
1161
47145210 1162static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD
1163 .suspend = sh_mobile_lcdc_suspend,
1164 .resume = sh_mobile_lcdc_resume,
0246c471
MD
1165 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1166 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD
1167};
1168
6de9edd5 1169/* locking: called with info->lock held */
6011bdea
GL
1170static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1171 unsigned long action, void *data)
1172{
1173 struct fb_event *event = data;
1174 struct fb_info *info = event->info;
1175 struct sh_mobile_lcdc_chan *ch = info->par;
1176 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
afe417c0 1177 int ret;
6011bdea
GL
1178
1179 if (&ch->lcdc->notifier != nb)
baf16374 1180 return NOTIFY_DONE;
6011bdea
GL
1181
1182 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1183 __func__, action, event->data);
1184
1185 switch(action) {
1186 case FB_EVENT_SUSPEND:
6de9edd5 1187 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
6011bdea 1188 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL
1189 module_put(board_cfg->owner);
1190 }
6011bdea 1191 pm_runtime_put(info->device);
afe417c0 1192 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL
1193 break;
1194 case FB_EVENT_RESUME:
dd210503
GL
1195 mutex_lock(&ch->open_lock);
1196 sh_mobile_fb_reconfig(info);
1197 mutex_unlock(&ch->open_lock);
6011bdea
GL
1198
1199 /* HDMI must be enabled before LCDC configuration */
6de9edd5 1200 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
dd210503 1201 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1202 module_put(board_cfg->owner);
6011bdea
GL
1203 }
1204
afe417c0
GL
1205 ret = sh_mobile_lcdc_start(ch->lcdc);
1206 if (!ret)
1207 pm_runtime_get_sync(info->device);
6011bdea
GL
1208 }
1209
baf16374 1210 return NOTIFY_OK;
6011bdea
GL
1211}
1212
cfb4f5d1
MD
1213static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1214
c2e13037 1215static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD
1216{
1217 struct fb_info *info;
1218 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1219 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD
1220 struct resource *res;
1221 int error;
1222 void *buf;
1223 int i, j;
1224
01ac25b5 1225 if (!pdata) {
cfb4f5d1 1226 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1227 return -EINVAL;
cfb4f5d1
MD
1228 }
1229
1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD
1231 i = platform_get_irq(pdev, 0);
1232 if (!res || i < 0) {
1233 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1234 return -ENOENT;
cfb4f5d1
MD
1235 }
1236
1237 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1238 if (!priv) {
1239 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1240 return -ENOMEM;
cfb4f5d1
MD
1241 }
1242
8bed9055
GL
1243 platform_set_drvdata(pdev, priv);
1244
8564557a 1245 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1246 dev_name(&pdev->dev), priv);
8564557a
MD
1247 if (error) {
1248 dev_err(&pdev->dev, "unable to request irq\n");
1249 goto err1;
1250 }
1251
1252 priv->irq = i;
5ef6b505 1253 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD
1254
1255 j = 0;
1256 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1257 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1258
01ac25b5
GL
1259 ch->lcdc = priv;
1260 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1261
01ac25b5 1262 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD
1263 if (error) {
1264 dev_err(&pdev->dev, "unsupported interface type\n");
1265 goto err1;
1266 }
01ac25b5
GL
1267 init_waitqueue_head(&ch->frame_end_wait);
1268 init_completion(&ch->vsync_completion);
1269 ch->pan_offset = 0;
cfb4f5d1 1270
3b0fd9d7
AC
1271 /* probe the backlight is there is one defined */
1272 if (ch->cfg.bl_info.max_brightness)
1273 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1274
cfb4f5d1
MD
1275 switch (pdata->ch[i].chan) {
1276 case LCDC_CHAN_MAINLCD:
01ac25b5
GL
1277 ch->enabled = 1 << 1;
1278 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD
1279 j++;
1280 break;
1281 case LCDC_CHAN_SUBLCD:
01ac25b5
GL
1282 ch->enabled = 1 << 2;
1283 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD
1284 j++;
1285 break;
1286 }
1287 }
1288
1289 if (!j) {
1290 dev_err(&pdev->dev, "no channels defined\n");
1291 error = -EINVAL;
1292 goto err1;
1293 }
1294
417d4827
MD
1295 /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
1296 if (j == 2)
1297 priv->forced_bpp = pdata->ch[0].bpp;
1298
dba6f385
GL
1299 priv->base = ioremap_nocache(res->start, resource_size(res));
1300 if (!priv->base)
1301 goto err1;
1302
b51339ff 1303 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD
1304 if (error) {
1305 dev_err(&pdev->dev, "unable to setup clocks\n");
1306 goto err1;
1307 }
1308
cfb4f5d1 1309 for (i = 0; i < j; i++) {
6011bdea 1310 struct fb_var_screeninfo *var;
71d3b0fc 1311 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1312 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL
1313 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1314 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL
1315 unsigned long max_size = 0;
1316 int k;
5fd284e6 1317 int num_cfg;
cfb4f5d1 1318
01ac25b5
GL
1319 ch->info = framebuffer_alloc(0, &pdev->dev);
1320 if (!ch->info) {
e33afddc
PM
1321 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1322 error = -ENOMEM;
1323 break;
1324 }
1325
01ac25b5 1326 info = ch->info;
6011bdea 1327 var = &info->var;
cfb4f5d1 1328 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1329 info->par = ch;
dd210503
GL
1330
1331 mutex_init(&ch->open_lock);
1332
c44f9f76
GL
1333 for (k = 0, lcd_cfg = mode;
1334 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL
1335 k++, lcd_cfg++) {
1336 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
1337
1338 if (size > max_size) {
1339 max_cfg = lcd_cfg;
1340 max_size = size;
1341 }
1342 }
1343
c44f9f76 1344 if (!mode)
d2ecbab5 1345 max_size = MAX_XRES * MAX_YRES;
c44f9f76
GL
1346 else if (max_cfg)
1347 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1348 max_cfg->xres, max_cfg->yres);
71d3b0fc 1349
cfb4f5d1 1350 info->fix = sh_mobile_lcdc_fix;
71d3b0fc 1351 info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
cfb4f5d1 1352
5fd284e6 1353 if (!mode) {
c44f9f76 1354 mode = &default_720p;
5fd284e6
GL
1355 num_cfg = 1;
1356 } else {
e0b9fb26 1357 num_cfg = cfg->num_cfg;
5fd284e6
GL
1358 }
1359
1360 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
c44f9f76
GL
1361
1362 fb_videomode_to_var(var, mode);
e0b9fb26
GL
1363 var->width = cfg->lcd_size_cfg.width;
1364 var->height = cfg->lcd_size_cfg.height;
9dd38819 1365 /* Default Y virtual resolution is 2x panel size */
6011bdea 1366 var->yres_virtual = var->yres * 2;
6011bdea 1367 var->activate = FB_ACTIVATE_NOW;
6011bdea
GL
1368
1369 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
cfb4f5d1
MD
1370 if (error)
1371 break;
1372
cfb4f5d1 1373 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1374 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD
1375 if (!buf) {
1376 dev_err(&pdev->dev, "unable to allocate buffer\n");
1377 error = -ENOMEM;
1378 break;
1379 }
1380
01ac25b5 1381 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD
1382 info->flags = FBINFO_FLAG_DEFAULT;
1383
1384 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1385 if (error < 0) {
1386 dev_err(&pdev->dev, "unable to allocate cmap\n");
1387 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1388 buf, ch->dma_handle);
cfb4f5d1
MD
1389 break;
1390 }
1391
01ac25b5 1392 info->fix.smem_start = ch->dma_handle;
c44f9f76 1393 info->fix.line_length = var->xres * (cfg->bpp / 8);
cfb4f5d1
MD
1394 info->screen_base = buf;
1395 info->device = &pdev->dev;
1c120deb 1396 ch->display_var = *var;
cfb4f5d1
MD
1397 }
1398
1399 if (error)
1400 goto err1;
1401
1402 error = sh_mobile_lcdc_start(priv);
1403 if (error) {
1404 dev_err(&pdev->dev, "unable to start hardware\n");
1405 goto err1;
1406 }
1407
1408 for (i = 0; i < j; i++) {
1c6a307a
PM
1409 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1410
e33afddc 1411 info = ch->info;
1c6a307a
PM
1412
1413 if (info->fbdefio) {
8bed9055 1414 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1415 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1416 if (!ch->sglist) {
1c6a307a
PM
1417 dev_err(&pdev->dev, "cannot allocate sglist\n");
1418 goto err1;
1419 }
1420 }
1421
3b0fd9d7
AC
1422 info->bl_dev = ch->bl;
1423
1c6a307a 1424 error = register_framebuffer(info);
cfb4f5d1
MD
1425 if (error < 0)
1426 goto err1;
cfb4f5d1 1427
cfb4f5d1
MD
1428 dev_info(info->dev,
1429 "registered %s/%s as %dx%d %dbpp.\n",
1430 pdev->name,
1c6a307a 1431 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1432 "mainlcd" : "sublcd",
c44f9f76 1433 info->var.xres, info->var.yres,
1c6a307a 1434 ch->cfg.bpp);
8564557a
MD
1435
1436 /* deferred io mode: disable clock to save power */
6011bdea 1437 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1438 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD
1439 }
1440
6011bdea
GL
1441 /* Failure ignored */
1442 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1443 fb_register_client(&priv->notifier);
1444
cfb4f5d1 1445 return 0;
8bed9055 1446err1:
cfb4f5d1 1447 sh_mobile_lcdc_remove(pdev);
8bed9055 1448
cfb4f5d1
MD
1449 return error;
1450}
1451
1452static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1453{
1454 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1455 struct fb_info *info;
1456 int i;
1457
6011bdea
GL
1458 fb_unregister_client(&priv->notifier);
1459
cfb4f5d1 1460 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1461 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1462 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD
1463
1464 sh_mobile_lcdc_stop(priv);
1465
1466 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1467 info = priv->ch[i].info;
cfb4f5d1 1468
e33afddc 1469 if (!info || !info->device)
cfb4f5d1
MD
1470 continue;
1471
1c6a307a
PM
1472 if (priv->ch[i].sglist)
1473 vfree(priv->ch[i].sglist);
1474
1ffbb037
MD
1475 if (info->screen_base)
1476 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1477 info->screen_base,
1478 priv->ch[i].dma_handle);
cfb4f5d1 1479 fb_dealloc_cmap(&info->cmap);
e33afddc 1480 framebuffer_release(info);
cfb4f5d1
MD
1481 }
1482
3b0fd9d7
AC
1483 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1484 if (priv->ch[i].bl)
1485 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1486 }
1487
b51339ff
MD
1488 if (priv->dot_clk)
1489 clk_put(priv->dot_clk);
0246c471 1490
8bed9055
GL
1491 if (priv->dev)
1492 pm_runtime_disable(priv->dev);
cfb4f5d1
MD
1493
1494 if (priv->base)
1495 iounmap(priv->base);
1496
8564557a
MD
1497 if (priv->irq)
1498 free_irq(priv->irq, priv);
cfb4f5d1
MD
1499 kfree(priv);
1500 return 0;
1501}
1502
1503static struct platform_driver sh_mobile_lcdc_driver = {
1504 .driver = {
1505 .name = "sh_mobile_lcdc_fb",
1506 .owner = THIS_MODULE,
2feb075a 1507 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD
1508 },
1509 .probe = sh_mobile_lcdc_probe,
1510 .remove = sh_mobile_lcdc_remove,
1511};
1512
1513static int __init sh_mobile_lcdc_init(void)
1514{
1515 return platform_driver_register(&sh_mobile_lcdc_driver);
1516}
1517
1518static void __exit sh_mobile_lcdc_exit(void)
1519{
1520 platform_driver_unregister(&sh_mobile_lcdc_driver);
1521}
1522
1523module_init(sh_mobile_lcdc_init);
1524module_exit(sh_mobile_lcdc_exit);
1525
1526MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1527MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1528MODULE_LICENSE("GPL v2");