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fbdev: sh_mobile_lcdc: use dma_mmap_coherent
[mirror_ubuntu-zesty-kernel.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
c5deac3c 15#include <linux/ctype.h>
cfb4f5d1 16#include <linux/dma-mapping.h>
f1f60b5f
LP		 17#include <linux/delay.h>
18#include <linux/gpio.h>
19#include <linux/init.h>
8564557a 20#include <linux/interrupt.h>
40331b21 21#include <linux/ioctl.h>
f1f60b5f
LP		 22#include <linux/kernel.h>
23#include <linux/mm.h>
355b200b 24#include <linux/module.h>
f1f60b5f
LP		 25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/videodev2.h>
29#include <linux/vmalloc.h>
30
225c9a8d 31#include <video/sh_mobile_lcdc.h>
8a20974f 32#include <video/sh_mobile_meram.h>
cfb4f5d1 33
6de9edd5
GL		 34#include "sh_mobile_lcdcfb.h"
35
c5deac3c
LP		 36/* ----------------------------------------------------------------------------
37 * Overlay register definitions
38 */
39
40#define LDBCR 0xb00
41#define LDBCR_UPC(n) (1 << ((n) + 16))
42#define LDBCR_UPF(n) (1 << ((n) + 8))
43#define LDBCR_UPD(n) (1 << ((n) + 0))
44#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
45#define LDBBSIFR_EN (1 << 31)
46#define LDBBSIFR_VS (1 << 29)
47#define LDBBSIFR_BRSEL (1 << 28)
48#define LDBBSIFR_MX (1 << 27)
49#define LDBBSIFR_MY (1 << 26)
50#define LDBBSIFR_CV3 (3 << 24)
51#define LDBBSIFR_CV2 (2 << 24)
52#define LDBBSIFR_CV1 (1 << 24)
53#define LDBBSIFR_CV0 (0 << 24)
54#define LDBBSIFR_CV_MASK (3 << 24)
55#define LDBBSIFR_LAY_MASK (0xff << 16)
56#define LDBBSIFR_LAY_SHIFT 16
57#define LDBBSIFR_ROP3_MASK (0xff << 16)
58#define LDBBSIFR_ROP3_SHIFT 16
59#define LDBBSIFR_AL_PL8 (3 << 14)
60#define LDBBSIFR_AL_PL1 (2 << 14)
61#define LDBBSIFR_AL_PK (1 << 14)
62#define LDBBSIFR_AL_1 (0 << 14)
63#define LDBBSIFR_AL_MASK (3 << 14)
64#define LDBBSIFR_SWPL (1 << 10)
65#define LDBBSIFR_SWPW (1 << 9)
66#define LDBBSIFR_SWPB (1 << 8)
67#define LDBBSIFR_RY (1 << 7)
68#define LDBBSIFR_CHRR_420 (2 << 0)
69#define LDBBSIFR_CHRR_422 (1 << 0)
70#define LDBBSIFR_CHRR_444 (0 << 0)
71#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
72#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
73#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
74#define LDBBSIFR_RPKF_MASK (0x1f << 0)
75#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
76#define LDBBSSZR_BVSS_MASK (0xfff << 16)
77#define LDBBSSZR_BVSS_SHIFT 16
78#define LDBBSSZR_BHSS_MASK (0xfff << 0)
79#define LDBBSSZR_BHSS_SHIFT 0
80#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
81#define LDBBLOCR_CVLC_MASK (0xfff << 16)
82#define LDBBLOCR_CVLC_SHIFT 16
83#define LDBBLOCR_CHLC_MASK (0xfff << 0)
84#define LDBBLOCR_CHLC_SHIFT 0
85#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
86#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
87#define LDBBSMWR_BSMWA_SHIFT 16
88#define LDBBSMWR_BSMW_MASK (0xffff << 0)
89#define LDBBSMWR_BSMW_SHIFT 0
90#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
91#define LDBBSAYR_FG1A_MASK (0xff << 24)
92#define LDBBSAYR_FG1A_SHIFT 24
93#define LDBBSAYR_FG1R_MASK (0xff << 16)
94#define LDBBSAYR_FG1R_SHIFT 16
95#define LDBBSAYR_FG1G_MASK (0xff << 8)
96#define LDBBSAYR_FG1G_SHIFT 8
97#define LDBBSAYR_FG1B_MASK (0xff << 0)
98#define LDBBSAYR_FG1B_SHIFT 0
99#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
100#define LDBBSACR_FG2A_MASK (0xff << 24)
101#define LDBBSACR_FG2A_SHIFT 24
102#define LDBBSACR_FG2R_MASK (0xff << 16)
103#define LDBBSACR_FG2R_SHIFT 16
104#define LDBBSACR_FG2G_MASK (0xff << 8)
105#define LDBBSACR_FG2G_SHIFT 8
106#define LDBBSACR_FG2B_MASK (0xff << 0)
107#define LDBBSACR_FG2B_SHIFT 0
108#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
109#define LDBBSAAR_AP_MASK (0xff << 24)
110#define LDBBSAAR_AP_SHIFT 24
111#define LDBBSAAR_R_MASK (0xff << 16)
112#define LDBBSAAR_R_SHIFT 16
113#define LDBBSAAR_GY_MASK (0xff << 8)
114#define LDBBSAAR_GY_SHIFT 8
115#define LDBBSAAR_B_MASK (0xff << 0)
116#define LDBBSAAR_B_SHIFT 0
117#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
118#define LDBBPPCR_AP_MASK (0xff << 24)
119#define LDBBPPCR_AP_SHIFT 24
120#define LDBBPPCR_R_MASK (0xff << 16)
121#define LDBBPPCR_R_SHIFT 16
122#define LDBBPPCR_GY_MASK (0xff << 8)
123#define LDBBPPCR_GY_SHIFT 8
124#define LDBBPPCR_B_MASK (0xff << 0)
125#define LDBBPPCR_B_SHIFT 0
126#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
127#define LDBBBGCL_BGA_MASK (0xff << 24)
128#define LDBBBGCL_BGA_SHIFT 24
129#define LDBBBGCL_BGR_MASK (0xff << 16)
130#define LDBBBGCL_BGR_SHIFT 16
131#define LDBBBGCL_BGG_MASK (0xff << 8)
132#define LDBBBGCL_BGG_SHIFT 8
133#define LDBBBGCL_BGB_MASK (0xff << 0)
134#define LDBBBGCL_BGB_SHIFT 0
135
a6f15ade
PE		 136#define SIDE_B_OFFSET 0x1000
137#define MIRROR_OFFSET 0x2000
cfb4f5d1 138
d2ecbab5
GL		 139#define MAX_XRES 1920
140#define MAX_YRES 1080
cfb4f5d1 141
c5deac3c
LP		 142enum sh_mobile_lcdc_overlay_mode {
143 LCDC_OVERLAY_BLEND,
144 LCDC_OVERLAY_ROP3,
145};
146
147/*
148 * struct sh_mobile_lcdc_overlay - LCDC display overlay
149 *
150 * @channel: LCDC channel this overlay belongs to
151 * @cfg: Overlay configuration
152 * @info: Frame buffer device
153 * @index: Overlay index (0-3)
154 * @base: Overlay registers base address
155 * @enabled: True if the overlay is enabled
156 * @mode: Overlay blending mode (alpha blend or ROP3)
157 * @alpha: Global alpha blending value (0-255, for alpha blending mode)
158 * @rop3: Raster operation (for ROP3 mode)
159 * @fb_mem: Frame buffer virtual memory address
160 * @fb_size: Frame buffer size in bytes
161 * @dma_handle: Frame buffer DMA address
162 * @base_addr_y: Overlay base address (RGB or luma component)
163 * @base_addr_c: Overlay base address (chroma component)
a4aa25f6 164 * @pan_y_offset: Panning linear offset in bytes (luma component)
c5deac3c
LP		 165 * @format: Current pixelf format
166 * @xres: Horizontal visible resolution
167 * @xres_virtual: Horizontal total resolution
168 * @yres: Vertical visible resolution
169 * @yres_virtual: Vertical total resolution
170 * @pitch: Overlay line pitch
171 * @pos_x: Horizontal overlay position
172 * @pos_y: Vertical overlay position
173 */
174struct sh_mobile_lcdc_overlay {
175 struct sh_mobile_lcdc_chan *channel;
176
177 const struct sh_mobile_lcdc_overlay_cfg *cfg;
178 struct fb_info *info;
179
180 unsigned int index;
181 unsigned long base;
182
183 bool enabled;
184 enum sh_mobile_lcdc_overlay_mode mode;
185 unsigned int alpha;
186 unsigned int rop3;
187
188 void *fb_mem;
189 unsigned long fb_size;
190
191 dma_addr_t dma_handle;
192 unsigned long base_addr_y;
193 unsigned long base_addr_c;
a4aa25f6 194 unsigned long pan_y_offset;
c5deac3c
LP		 195
196 const struct sh_mobile_lcdc_format_info *format;
197 unsigned int xres;
198 unsigned int xres_virtual;
199 unsigned int yres;
200 unsigned int yres_virtual;
201 unsigned int pitch;
202 int pos_x;
203 int pos_y;
204};
205
f1f60b5f
LP		 206struct sh_mobile_lcdc_priv {
207 void __iomem *base;
208 int irq;
209 atomic_t hw_usecnt;
210 struct device *dev;
211 struct clk *dot_clk;
212 unsigned long lddckr;
c5deac3c 213
f1f60b5f 214 struct sh_mobile_lcdc_chan ch[2];
c5deac3c
LP		 215 struct sh_mobile_lcdc_overlay overlays[4];
216
f1f60b5f
LP		 217 struct notifier_block notifier;
218 int started;
219 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
220 struct sh_mobile_meram_info *meram_dev;
221};
222
223/* -----------------------------------------------------------------------------
224 * Registers access
225 */
226
0246c471 227static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 228 [LDDCKPAT1R] = 0x400,
229 [LDDCKPAT2R] = 0x404,
230 [LDMT1R] = 0x418,
231 [LDMT2R] = 0x41c,
232 [LDMT3R] = 0x420,
233 [LDDFR] = 0x424,
234 [LDSM1R] = 0x428,
8564557a 235 [LDSM2R] = 0x42c,
cfb4f5d1 236 [LDSA1R] = 0x430,
53b50314 237 [LDSA2R] = 0x434,
cfb4f5d1
MD		 238 [LDMLSR] = 0x438,
239 [LDHCNR] = 0x448,
240 [LDHSYNR] = 0x44c,
241 [LDVLNR] = 0x450,
242 [LDVSYNR] = 0x454,
243 [LDPMR] = 0x460,
6011bdea 244 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 245};
246
0246c471 247static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 248 [LDDCKPAT1R] = 0x408,
249 [LDDCKPAT2R] = 0x40c,
250 [LDMT1R] = 0x600,
251 [LDMT2R] = 0x604,
252 [LDMT3R] = 0x608,
253 [LDDFR] = 0x60c,
254 [LDSM1R] = 0x610,
8564557a 255 [LDSM2R] = 0x614,
cfb4f5d1
MD		 256 [LDSA1R] = 0x618,
257 [LDMLSR] = 0x620,
258 [LDHCNR] = 0x624,
259 [LDHSYNR] = 0x628,
260 [LDVLNR] = 0x62c,
261 [LDVSYNR] = 0x630,
262 [LDPMR] = 0x63c,
263};
264
a6f15ade
PE		 265static bool banked(int reg_nr)
266{
267 switch (reg_nr) {
268 case LDMT1R:
269 case LDMT2R:
270 case LDMT3R:
271 case LDDFR:
272 case LDSM1R:
273 case LDSA1R:
53b50314 274 case LDSA2R:
a6f15ade
PE		 275 case LDMLSR:
276 case LDHCNR:
277 case LDHSYNR:
278 case LDVLNR:
279 case LDVSYNR:
280 return true;
281 }
282 return false;
283}
284
f1f60b5f
LP		 285static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
286{
b5ef967d 287 return chan->cfg->chan == LCDC_CHAN_SUBLCD;
f1f60b5f
LP		 288}
289
cfb4f5d1
MD		 290static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
291 int reg_nr, unsigned long data)
292{
293 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 294 if (banked(reg_nr))
295 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
296 SIDE_B_OFFSET);
297}
298
299static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
300 int reg_nr, unsigned long data)
301{
302 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
303 MIRROR_OFFSET);
cfb4f5d1
MD		 304}
305
306static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
307 int reg_nr)
308{
309 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
310}
311
c5deac3c
LP		 312static void lcdc_write_overlay(struct sh_mobile_lcdc_overlay *ovl,
313 int reg, unsigned long data)
314{
315 iowrite32(data, ovl->channel->lcdc->base + reg);
316 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET);
317}
318
cfb4f5d1
MD		 319static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
320 unsigned long reg_offs, unsigned long data)
321{
322 iowrite32(data, priv->base + reg_offs);
323}
324
325static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
326 unsigned long reg_offs)
327{
328 return ioread32(priv->base + reg_offs);
329}
330
331static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
332 unsigned long reg_offs,
333 unsigned long mask, unsigned long until)
334{
335 while ((lcdc_read(priv, reg_offs) & mask) != until)
336 cpu_relax();
337}
338
f1f60b5f
LP		 339/* -----------------------------------------------------------------------------
340 * Clock management
341 */
342
343static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 344{
f1f60b5f
LP		 345 if (atomic_inc_and_test(&priv->hw_usecnt)) {
346 if (priv->dot_clk)
347 clk_enable(priv->dot_clk);
348 pm_runtime_get_sync(priv->dev);
349 if (priv->meram_dev && priv->meram_dev->pdev)
350 pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
351 }
cfb4f5d1
MD		 352}
353
f1f60b5f
LP		 354static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
355{
356 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
357 if (priv->meram_dev && priv->meram_dev->pdev)
358 pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
359 pm_runtime_put(priv->dev);
360 if (priv->dot_clk)
361 clk_disable(priv->dot_clk);
362 }
363}
364
0a7f17aa
LP		 365static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
366 int clock_source)
f1f60b5f 367{
4774c12a 368 struct clk *clk;
f1f60b5f
LP		 369 char *str;
370
371 switch (clock_source) {
372 case LCDC_CLK_BUS:
373 str = "bus_clk";
374 priv->lddckr = LDDCKR_ICKSEL_BUS;
375 break;
376 case LCDC_CLK_PERIPHERAL:
377 str = "peripheral_clk";
378 priv->lddckr = LDDCKR_ICKSEL_MIPI;
379 break;
380 case LCDC_CLK_EXTERNAL:
381 str = NULL;
382 priv->lddckr = LDDCKR_ICKSEL_HDMI;
383 break;
384 default:
385 return -EINVAL;
386 }
387
4774c12a
LP		 388 if (str == NULL)
389 return 0;
390
0a7f17aa 391 clk = clk_get(priv->dev, str);
4774c12a 392 if (IS_ERR(clk)) {
0a7f17aa 393 dev_err(priv->dev, "cannot get dot clock %s\n", str);
4774c12a 394 return PTR_ERR(clk);
f1f60b5f
LP		 395 }
396
4774c12a 397 priv->dot_clk = clk;
f1f60b5f
LP		 398 return 0;
399}
400
401/* -----------------------------------------------------------------------------
37c5dcc2 402 * Display, panel and deferred I/O
f1f60b5f
LP		 403 */
404
cfb4f5d1
MD		 405static void lcdc_sys_write_index(void *handle, unsigned long data)
406{
407 struct sh_mobile_lcdc_chan *ch = handle;
408
ce1c0b08
LP		 409 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
410 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
411 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
412 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
413 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 414}
415
416static void lcdc_sys_write_data(void *handle, unsigned long data)
417{
418 struct sh_mobile_lcdc_chan *ch = handle;
419
ce1c0b08
LP		 420 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
421 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
422 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
423 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
424 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 425}
426
427static unsigned long lcdc_sys_read_data(void *handle)
428{
429 struct sh_mobile_lcdc_chan *ch = handle;
430
ce1c0b08
LP		 431 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
432 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
433 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
434 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 435 udelay(1);
ce1c0b08 436 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 437
ce1c0b08 438 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 439}
440
441struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
442 lcdc_sys_write_index,
443 lcdc_sys_write_data,
444 lcdc_sys_read_data,
445};
446
1c6a307a
PM		 447static int sh_mobile_lcdc_sginit(struct fb_info *info,
448 struct list_head *pagelist)
449{
450 struct sh_mobile_lcdc_chan *ch = info->par;
58f03d99 451 unsigned int nr_pages_max = ch->fb_size >> PAGE_SHIFT;
1c6a307a
PM		 452 struct page *page;
453 int nr_pages = 0;
454
455 sg_init_table(ch->sglist, nr_pages_max);
456
457 list_for_each_entry(page, pagelist, lru)
458 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
459
460 return nr_pages;
461}
462
8564557a
MD		 463static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
464 struct list_head *pagelist)
465{
466 struct sh_mobile_lcdc_chan *ch = info->par;
b5ef967d 467 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
8564557a
MD		 468
469 /* enable clocks before accessing hardware */
470 sh_mobile_lcdc_clk_on(ch->lcdc);
471
5c1a56b5
PM		 472 /*
473 * It's possible to get here without anything on the pagelist via
474 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
475 * invocation. In the former case, the acceleration routines are
476 * stepped in to when using the framebuffer console causing the
477 * workqueue to be scheduled without any dirty pages on the list.
478 *
479 * Despite this, a panel update is still needed given that the
480 * acceleration routines have their own methods for writing in
481 * that still need to be updated.
482 *
483 * The fsync() and empty pagelist case could be optimized for,
484 * but we don't bother, as any application exhibiting such
485 * behaviour is fundamentally broken anyways.
486 */
487 if (!list_empty(pagelist)) {
488 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
489
490 /* trigger panel update */
e8363140 491 dma_map_sg(ch->lcdc->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
afaad83b
LP		 492 if (panel->start_transfer)
493 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 494 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
e8363140
LP		 495 dma_unmap_sg(ch->lcdc->dev, ch->sglist, nr_pages,
496 DMA_TO_DEVICE);
ef61aae4 497 } else {
afaad83b
LP		 498 if (panel->start_transfer)
499 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 500 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 501 }
8564557a
MD		 502}
503
504static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
505{
506 struct fb_deferred_io *fbdefio = info->fbdefio;
507
508 if (fbdefio)
509 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
510}
511
37c5dcc2
LP		 512static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
513{
b5ef967d 514 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 515
9a2985e7 516 if (ch->tx_dev) {
458981c3
LP		 517 int ret;
518
519 ret = ch->tx_dev->ops->display_on(ch->tx_dev);
520 if (ret < 0)
9a2985e7 521 return;
458981c3
LP		 522
523 if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
524 ch->info->state = FBINFO_STATE_SUSPENDED;
9a2985e7
LP		 525 }
526
37c5dcc2 527 /* HDMI must be enabled before LCDC configuration */
afaad83b
LP		 528 if (panel->display_on)
529 panel->display_on();
37c5dcc2
LP		 530}
531
532static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
533{
b5ef967d 534 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 535
afaad83b
LP		 536 if (panel->display_off)
537 panel->display_off();
9a2985e7
LP		 538
539 if (ch->tx_dev)
540 ch->tx_dev->ops->display_off(ch->tx_dev);
37c5dcc2
LP		 541}
542
ecd29947
LP		 543static bool
544sh_mobile_lcdc_must_reconfigure(struct sh_mobile_lcdc_chan *ch,
e0c8601a 545 const struct fb_videomode *new_mode)
ecd29947 546{
ecd29947 547 dev_dbg(ch->info->dev, "Old %ux%u, new %ux%u\n",
2d04559d
LP		 548 ch->display.mode.xres, ch->display.mode.yres,
549 new_mode->xres, new_mode->yres);
ecd29947 550
e0c8601a 551 /* It can be a different monitor with an equal video-mode */
2d04559d 552 if (fb_mode_is_equal(&ch->display.mode, new_mode))
ecd29947 553 return false;
ecd29947
LP		 554
555 dev_dbg(ch->info->dev, "Switching %u -> %u lines\n",
2d04559d
LP		 556 ch->display.mode.yres, new_mode->yres);
557 ch->display.mode = *new_mode;
ecd29947
LP		 558
559 return true;
560}
561
d7ad3342
LP		 562static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
563 struct fb_info *info);
ecd29947
LP		 564
565static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch,
566 enum sh_mobile_lcdc_entity_event event,
e0c8601a
LP		 567 const struct fb_videomode *mode,
568 const struct fb_monspecs *monspec)
ecd29947
LP		 569{
570 struct fb_info *info = ch->info;
e0c8601a 571 struct fb_var_screeninfo var;
ecd29947
LP		 572 int ret = 0;
573
574 switch (event) {
575 case SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT:
576 /* HDMI plug in */
577 if (lock_fb_info(info)) {
578 console_lock();
579
2d04559d
LP		 580 ch->display.width = monspec->max_x * 10;
581 ch->display.height = monspec->max_y * 10;
e0c8601a
LP		 582
583 if (!sh_mobile_lcdc_must_reconfigure(ch, mode) &&
ecd29947
LP		 584 info->state == FBINFO_STATE_RUNNING) {
585 /* First activation with the default monitor.
586 * Just turn on, if we run a resume here, the
587 * logo disappears.
588 */
e0c8601a
LP		 589 info->var.width = monspec->max_x * 10;
590 info->var.height = monspec->max_y * 10;
ecd29947
LP		 591 sh_mobile_lcdc_display_on(ch);
592 } else {
593 /* New monitor or have to wake up */
594 fb_set_suspend(info, 0);
595 }
596
597 console_unlock();
598 unlock_fb_info(info);
599 }
600 break;
601
602 case SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT:
603 /* HDMI disconnect */
604 if (lock_fb_info(info)) {
605 console_lock();
606 fb_set_suspend(info, 1);
607 console_unlock();
608 unlock_fb_info(info);
609 }
610 break;
611
612 case SH_MOBILE_LCDC_EVENT_DISPLAY_MODE:
613 /* Validate a proposed new mode */
e0c8601a
LP		 614 fb_videomode_to_var(&var, mode);
615 var.bits_per_pixel = info->var.bits_per_pixel;
616 var.grayscale = info->var.grayscale;
d7ad3342 617 ret = sh_mobile_lcdc_check_var(&var, info);
ecd29947
LP		 618 break;
619 }
620
621 return ret;
622}
623
f1f60b5f
LP		 624/* -----------------------------------------------------------------------------
625 * Format helpers
626 */
627
105784bb
LP		 628struct sh_mobile_lcdc_format_info {
629 u32 fourcc;
630 unsigned int bpp;
631 bool yuv;
632 u32 lddfr;
633};
634
635static const struct sh_mobile_lcdc_format_info sh_mobile_format_infos[] = {
636 {
637 .fourcc = V4L2_PIX_FMT_RGB565,
638 .bpp = 16,
639 .yuv = false,
640 .lddfr = LDDFR_PKF_RGB16,
641 }, {
642 .fourcc = V4L2_PIX_FMT_BGR24,
643 .bpp = 24,
644 .yuv = false,
645 .lddfr = LDDFR_PKF_RGB24,
646 }, {
647 .fourcc = V4L2_PIX_FMT_BGR32,
648 .bpp = 32,
649 .yuv = false,
650 .lddfr = LDDFR_PKF_ARGB32,
651 }, {
652 .fourcc = V4L2_PIX_FMT_NV12,
653 .bpp = 12,
654 .yuv = true,
655 .lddfr = LDDFR_CC | LDDFR_YF_420,
656 }, {
657 .fourcc = V4L2_PIX_FMT_NV21,
658 .bpp = 12,
659 .yuv = true,
660 .lddfr = LDDFR_CC | LDDFR_YF_420,
661 }, {
662 .fourcc = V4L2_PIX_FMT_NV16,
663 .bpp = 16,
664 .yuv = true,
665 .lddfr = LDDFR_CC | LDDFR_YF_422,
666 }, {
667 .fourcc = V4L2_PIX_FMT_NV61,
668 .bpp = 16,
669 .yuv = true,
670 .lddfr = LDDFR_CC | LDDFR_YF_422,
671 }, {
672 .fourcc = V4L2_PIX_FMT_NV24,
673 .bpp = 24,
674 .yuv = true,
675 .lddfr = LDDFR_CC | LDDFR_YF_444,
676 }, {
677 .fourcc = V4L2_PIX_FMT_NV42,
678 .bpp = 24,
679 .yuv = true,
680 .lddfr = LDDFR_CC | LDDFR_YF_444,
681 },
682};
683
684static const struct sh_mobile_lcdc_format_info *
685sh_mobile_format_info(u32 fourcc)
686{
687 unsigned int i;
688
689 for (i = 0; i < ARRAY_SIZE(sh_mobile_format_infos); ++i) {
690 if (sh_mobile_format_infos[i].fourcc == fourcc)
691 return &sh_mobile_format_infos[i];
692 }
693
694 return NULL;
695}
696
f1f60b5f
LP		 697static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
698{
699 if (var->grayscale > 1)
700 return var->grayscale;
701
702 switch (var->bits_per_pixel) {
703 case 16:
704 return V4L2_PIX_FMT_RGB565;
705 case 24:
706 return V4L2_PIX_FMT_BGR24;
707 case 32:
708 return V4L2_PIX_FMT_BGR32;
709 default:
710 return 0;
711 }
712}
713
714static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
715{
716 return var->grayscale > 1;
717}
718
f1f60b5f
LP		 719/* -----------------------------------------------------------------------------
720 * Start, stop and IRQ
721 */
722
8564557a
MD		 723static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
724{
725 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 726 struct sh_mobile_lcdc_chan *ch;
9dd38819 727 unsigned long ldintr;
2feb075a
MD		 728 int is_sub;
729 int k;
8564557a 730
dc48665f
LP		 731 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
732 ldintr = lcdc_read(priv, _LDINTR);
733 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 734
2feb075a 735 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 736 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 737
9dd38819 738 /* wake up channel and disable clocks */
2feb075a
MD		 739 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
740 ch = &priv->ch[k];
741
742 if (!ch->enabled)
743 continue;
744
dc48665f 745 /* Frame End */
9dd38819
PE		 746 if (ldintr & LDINTR_FS) {
747 if (is_sub == lcdc_chan_is_sublcd(ch)) {
748 ch->frame_end = 1;
749 wake_up(&ch->frame_end_wait);
2feb075a 750
9dd38819
PE		 751 sh_mobile_lcdc_clk_off(priv);
752 }
753 }
754
755 /* VSYNC End */
40331b21
PE		 756 if (ldintr & LDINTR_VES)
757 complete(&ch->vsync_completion);
2feb075a
MD		 758 }
759
8564557a
MD		 760 return IRQ_HANDLED;
761}
762
d7ad3342 763static int sh_mobile_lcdc_wait_for_vsync(struct sh_mobile_lcdc_chan *ch)
4976677f
LP		 764{
765 unsigned long ldintr;
766 int ret;
767
768 /* Enable VSync End interrupt and be careful not to acknowledge any
769 * pending interrupt.
770 */
771 ldintr = lcdc_read(ch->lcdc, _LDINTR);
772 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
773 lcdc_write(ch->lcdc, _LDINTR, ldintr);
774
775 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
776 msecs_to_jiffies(100));
777 if (!ret)
778 return -ETIMEDOUT;
779
780 return 0;
781}
782
cfb4f5d1
MD		 783static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
784 int start)
785{
786 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
787 int k;
788
789 /* start or stop the lcdc */
790 if (start)
ce1c0b08 791 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 792 else
ce1c0b08 793 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 794
795 /* wait until power is applied/stopped on all channels */
796 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
797 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
798 while (1) {
ce1c0b08
LP		 799 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
800 & LDPMR_LPS;
801 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 802 break;
803 if (!start && tmp == 0)
804 break;
805 cpu_relax();
806 }
807
808 if (!start)
809 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
810}
811
6011bdea
GL		 812static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
813{
2d04559d
LP		 814 const struct fb_var_screeninfo *var = &ch->info->var;
815 const struct fb_videomode *mode = &ch->display.mode;
1c120deb 816 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 817 u32 tmp;
818
819 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 820 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
821 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
b5ef967d
LP		 822 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
823 tmp |= (ch->cfg->flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
824 tmp |= (ch->cfg->flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
825 tmp |= (ch->cfg->flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
826 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 827 lcdc_write_chan(ch, LDMT1R, tmp);
828
829 /* setup SYS bus */
b5ef967d
LP		 830 lcdc_write_chan(ch, LDMT2R, ch->cfg->sys_bus_cfg.ldmt2r);
831 lcdc_write_chan(ch, LDMT3R, ch->cfg->sys_bus_cfg.ldmt3r);
6011bdea
GL		 832
833 /* horizontal configuration */
2d04559d
LP		 834 h_total = mode->xres + mode->hsync_len + mode->left_margin
835 + mode->right_margin;
6011bdea 836 tmp = h_total / 8; /* HTCN */
58f03d99 837 tmp |= (min(mode->xres, ch->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 838 lcdc_write_chan(ch, LDHCNR, tmp);
839
2d04559d 840 hsync_pos = mode->xres + mode->right_margin;
6011bdea 841 tmp = hsync_pos / 8; /* HSYNP */
2d04559d 842 tmp |= (mode->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 843 lcdc_write_chan(ch, LDHSYNR, tmp);
844
845 /* vertical configuration */
2d04559d
LP		 846 tmp = mode->yres + mode->vsync_len + mode->upper_margin
847 + mode->lower_margin; /* VTLN */
58f03d99 848 tmp |= min(mode->yres, ch->yres) << 16; /* VDLN */
6011bdea
GL		 849 lcdc_write_chan(ch, LDVLNR, tmp);
850
2d04559d
LP		 851 tmp = mode->yres + mode->lower_margin; /* VSYNP */
852 tmp |= mode->vsync_len << 16; /* VSYNW */
6011bdea
GL		 853 lcdc_write_chan(ch, LDVSYNR, tmp);
854
855 /* Adjust horizontal synchronisation for HDMI */
2d04559d
LP		 856 display_h_total = mode->xres + mode->hsync_len + mode->left_margin
857 + mode->right_margin;
858 tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
859 | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
6011bdea
GL		 860 lcdc_write_chan(ch, LDHAJR, tmp);
861}
862
c5deac3c
LP		 863static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
864{
865 u32 format = 0;
866
867 if (!ovl->enabled) {
868 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
869 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), 0);
870 lcdc_write(ovl->channel->lcdc, LDBCR,
871 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
872 return;
873 }
874
875 ovl->base_addr_y = ovl->dma_handle;
a4aa25f6
LP		 876 ovl->base_addr_c = ovl->dma_handle
877 + ovl->xres_virtual * ovl->yres_virtual;
c5deac3c
LP		 878
879 switch (ovl->mode) {
880 case LCDC_OVERLAY_BLEND:
881 format = LDBBSIFR_EN | (ovl->alpha << LDBBSIFR_LAY_SHIFT);
882 break;
883
884 case LCDC_OVERLAY_ROP3:
885 format = LDBBSIFR_EN | LDBBSIFR_BRSEL
886 | (ovl->rop3 << LDBBSIFR_ROP3_SHIFT);
887 break;
888 }
889
890 switch (ovl->format->fourcc) {
891 case V4L2_PIX_FMT_RGB565:
892 case V4L2_PIX_FMT_NV21:
893 case V4L2_PIX_FMT_NV61:
894 case V4L2_PIX_FMT_NV42:
895 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW;
896 break;
897 case V4L2_PIX_FMT_BGR24:
898 case V4L2_PIX_FMT_NV12:
899 case V4L2_PIX_FMT_NV16:
900 case V4L2_PIX_FMT_NV24:
901 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW | LDBBSIFR_SWPB;
902 break;
903 case V4L2_PIX_FMT_BGR32:
904 default:
905 format |= LDBBSIFR_SWPL;
906 break;
907 }
908
909 switch (ovl->format->fourcc) {
910 case V4L2_PIX_FMT_RGB565:
911 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB16;
912 break;
913 case V4L2_PIX_FMT_BGR24:
914 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB24;
915 break;
916 case V4L2_PIX_FMT_BGR32:
917 format |= LDBBSIFR_AL_PK | LDBBSIFR_RY | LDDFR_PKF_ARGB32;
918 break;
919 case V4L2_PIX_FMT_NV12:
920 case V4L2_PIX_FMT_NV21:
921 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_420;
922 break;
923 case V4L2_PIX_FMT_NV16:
924 case V4L2_PIX_FMT_NV61:
925 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_422;
926 break;
927 case V4L2_PIX_FMT_NV24:
928 case V4L2_PIX_FMT_NV42:
929 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_444;
930 break;
931 }
932
933 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
934
935 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), format);
936
937 lcdc_write_overlay(ovl, LDBnBSSZR(ovl->index),
938 (ovl->yres << LDBBSSZR_BVSS_SHIFT) |
939 (ovl->xres << LDBBSSZR_BHSS_SHIFT));
940 lcdc_write_overlay(ovl, LDBnBLOCR(ovl->index),
941 (ovl->pos_y << LDBBLOCR_CVLC_SHIFT) |
942 (ovl->pos_x << LDBBLOCR_CHLC_SHIFT));
943 lcdc_write_overlay(ovl, LDBnBSMWR(ovl->index),
944 ovl->pitch << LDBBSMWR_BSMW_SHIFT);
945
946 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
947 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
948
949 lcdc_write(ovl->channel->lcdc, LDBCR,
950 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
951}
952
9a217e34 953/*
d7ad3342 954 * __sh_mobile_lcdc_start - Configure and start the LCDC
9a217e34
LP		 955 * @priv: LCDC device
956 *
957 * Configure all enabled channels and start the LCDC device. All external
958 * devices (clocks, MERAM, panels, ...) are not touched by this function.
959 */
960static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 961{
962 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 963 unsigned long tmp;
9a217e34 964 int k, m;
8564557a 965
9a217e34
LP		 966 /* Enable LCDC channels. Read data from external memory, avoid using the
967 * BEU for now.
968 */
969 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 970
9a217e34 971 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 972 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 973 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 974
9a217e34 975 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 976 tmp = priv->lddckr;
977 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
978 ch = &priv->ch[k];
9a217e34 979 if (!ch->enabled)
cfb4f5d1
MD		 980 continue;
981
9a217e34
LP		 982 /* Power supply */
983 lcdc_write_chan(ch, LDPMR, 0);
984
b5ef967d 985 m = ch->cfg->clock_divider;
cfb4f5d1
MD		 986 if (!m)
987 continue;
988
505c7de5
LP		 989 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
990 * denominator.
991 */
992 lcdc_write_chan(ch, LDDCKPAT1R, 0);
993 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
994
cfb4f5d1 995 if (m == 1)
ce1c0b08 996 m = LDDCKR_MOSEL;
cfb4f5d1 997 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 998 }
999
1000 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 1001 lcdc_write(priv, _LDDCKSTPR, 0);
1002 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
1003
9a217e34 1004 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 1005 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1006 ch = &priv->ch[k];
cfb4f5d1
MD		 1007 if (!ch->enabled)
1008 continue;
1009
6011bdea 1010 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 1011
fc9e78e6 1012 tmp = ch->format->lddfr;
edd153a3 1013
fc9e78e6 1014 if (ch->format->yuv) {
58f03d99 1015 switch (ch->colorspace) {
edd153a3
LP		 1016 case V4L2_COLORSPACE_REC709:
1017 tmp |= LDDFR_CF1;
53b50314 1018 break;
edd153a3
LP		 1019 case V4L2_COLORSPACE_JPEG:
1020 tmp |= LDDFR_CF0;
53b50314
DHG		 1021 break;
1022 }
417d4827 1023 }
7caa4342 1024
9a217e34 1025 lcdc_write_chan(ch, LDDFR, tmp);
72c04af9 1026 lcdc_write_chan(ch, LDMLSR, ch->line_size);
9a217e34 1027 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
fc9e78e6 1028 if (ch->format->yuv)
9a217e34 1029 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 1030
9a217e34
LP		 1031 /* When using deferred I/O mode, configure the LCDC for one-shot
1032 * operation and enable the frame end interrupt. Otherwise use
1033 * continuous read mode.
1034 */
1035 if (ch->ldmt1r_value & LDMT1R_IFM &&
b5ef967d 1036 ch->cfg->sys_bus_cfg.deferred_io_msec) {
9a217e34
LP		 1037 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
1038 lcdc_write(priv, _LDINTR, LDINTR_FE);
1039 } else {
1040 lcdc_write_chan(ch, LDSM1R, 0);
1041 }
1042 }
7caa4342 1043
9a217e34 1044 /* Word and long word swap. */
fc9e78e6 1045 switch (priv->ch[0].format->fourcc) {
edd153a3
LP		 1046 case V4L2_PIX_FMT_RGB565:
1047 case V4L2_PIX_FMT_NV21:
1048 case V4L2_PIX_FMT_NV61:
1049 case V4L2_PIX_FMT_NV42:
1050 tmp = LDDDSR_LS | LDDDSR_WS;
1051 break;
1052 case V4L2_PIX_FMT_BGR24:
1053 case V4L2_PIX_FMT_NV12:
1054 case V4L2_PIX_FMT_NV16:
1055 case V4L2_PIX_FMT_NV24:
9a217e34 1056 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 1057 break;
1058 case V4L2_PIX_FMT_BGR32:
1059 default:
1060 tmp = LDDDSR_LS;
1061 break;
9a217e34
LP		 1062 }
1063 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 1064
9a217e34
LP		 1065 /* Enable the display output. */
1066 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
1067 sh_mobile_lcdc_start_stop(priv, 1);
1068 priv->started = 1;
1069}
cfb4f5d1 1070
9a217e34
LP		 1071static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
1072{
1073 struct sh_mobile_meram_info *mdev = priv->meram_dev;
9a217e34
LP		 1074 struct sh_mobile_lcdc_chan *ch;
1075 unsigned long tmp;
1076 int ret;
1077 int k;
cfb4f5d1 1078
9a217e34
LP		 1079 /* enable clocks before accessing the hardware */
1080 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1081 if (priv->ch[k].enabled)
1082 sh_mobile_lcdc_clk_on(priv);
1083 }
8564557a 1084
9a217e34
LP		 1085 /* reset */
1086 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
1087 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 1088
9a217e34 1089 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
b5ef967d 1090 const struct sh_mobile_lcdc_panel_cfg *panel;
8564557a 1091
37c5dcc2 1092 ch = &priv->ch[k];
9a217e34
LP		 1093 if (!ch->enabled)
1094 continue;
1095
b5ef967d 1096 panel = &ch->cfg->panel_cfg;
afaad83b
LP		 1097 if (panel->setup_sys) {
1098 ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
9a217e34
LP		 1099 if (ret)
1100 return ret;
8564557a 1101 }
cfb4f5d1
MD		 1102 }
1103
9a217e34
LP		 1104 /* Compute frame buffer base address and pitch for each channel. */
1105 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
9a217e34 1106 int pixelformat;
4a237177 1107 void *cache;
cfb4f5d1 1108
9a217e34
LP		 1109 ch = &priv->ch[k];
1110 if (!ch->enabled)
1111 continue;
cfb4f5d1 1112
58f03d99 1113 ch->base_addr_y = ch->dma_handle;
a4aa25f6
LP		 1114 ch->base_addr_c = ch->dma_handle
1115 + ch->xres_virtual * ch->yres_virtual;
72c04af9 1116 ch->line_size = ch->pitch;
9a217e34
LP		 1117
1118 /* Enable MERAM if possible. */
6e729b41 1119 if (mdev == NULL || ch->cfg->meram_cfg == NULL)
9a217e34
LP		 1120 continue;
1121
4a237177
LP		 1122 /* Free the allocated MERAM cache. */
1123 if (ch->cache) {
6e729b41 1124 sh_mobile_meram_cache_free(mdev, ch->cache);
4a237177 1125 ch->cache = NULL;
9a217e34
LP		 1126 }
1127
fc9e78e6 1128 switch (ch->format->fourcc) {
edd153a3
LP		 1129 case V4L2_PIX_FMT_NV12:
1130 case V4L2_PIX_FMT_NV21:
1131 case V4L2_PIX_FMT_NV16:
1132 case V4L2_PIX_FMT_NV61:
9a217e34 1133 pixelformat = SH_MOBILE_MERAM_PF_NV;
edd153a3
LP		 1134 break;
1135 case V4L2_PIX_FMT_NV24:
1136 case V4L2_PIX_FMT_NV42:
1137 pixelformat = SH_MOBILE_MERAM_PF_NV24;
1138 break;
1139 case V4L2_PIX_FMT_RGB565:
1140 case V4L2_PIX_FMT_BGR24:
1141 case V4L2_PIX_FMT_BGR32:
1142 default:
1143 pixelformat = SH_MOBILE_MERAM_PF_RGB;
1144 break;
1145 }
9a217e34 1146
6e729b41 1147 cache = sh_mobile_meram_cache_alloc(mdev, ch->cfg->meram_cfg,
b5ef967d 1148 ch->pitch, ch->yres, pixelformat,
72c04af9 1149 &ch->line_size);
4a237177 1150 if (!IS_ERR(cache)) {
6e729b41 1151 sh_mobile_meram_cache_update(mdev, cache,
97d16fe6
LP		 1152 ch->base_addr_y, ch->base_addr_c,
1153 &ch->base_addr_y, &ch->base_addr_c);
4a237177 1154 ch->cache = cache;
97d16fe6 1155 }
9a217e34
LP		 1156 }
1157
c5deac3c
LP		 1158 for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
1159 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k];
1160 sh_mobile_lcdc_overlay_setup(ovl);
1161 }
1162
9a217e34
LP		 1163 /* Start the LCDC. */
1164 __sh_mobile_lcdc_start(priv);
1165
1166 /* Setup deferred I/O, tell the board code to enable the panels, and
1167 * turn backlight on.
1168 */
cfb4f5d1
MD		 1169 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1170 ch = &priv->ch[k];
21bc1f02
MD		 1171 if (!ch->enabled)
1172 continue;
1173
b5ef967d 1174 tmp = ch->cfg->sys_bus_cfg.deferred_io_msec;
9a217e34
LP		 1175 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
1176 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
1177 ch->defio.delay = msecs_to_jiffies(tmp);
1178 ch->info->fbdefio = &ch->defio;
1179 fb_deferred_io_init(ch->info);
1180 }
1181
37c5dcc2 1182 sh_mobile_lcdc_display_on(ch);
3b0fd9d7
AC		 1183
1184 if (ch->bl) {
1185 ch->bl->props.power = FB_BLANK_UNBLANK;
1186 backlight_update_status(ch->bl);
1187 }
cfb4f5d1
MD		 1188 }
1189
1190 return 0;
1191}
1192
1193static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
1194{
1195 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 1196 int k;
1197
2feb075a 1198 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 1199 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1200 ch = &priv->ch[k];
21bc1f02
MD		 1201 if (!ch->enabled)
1202 continue;
8564557a 1203
2feb075a
MD		 1204 /* deferred io mode:
1205 * flush frame, and wait for frame end interrupt
1206 * clean up deferred io and enable clock
1207 */
5ef6b505 1208 if (ch->info && ch->info->fbdefio) {
2feb075a 1209 ch->frame_end = 0;
e33afddc 1210 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 1211 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 1212 fb_deferred_io_cleanup(ch->info);
1213 ch->info->fbdefio = NULL;
2feb075a 1214 sh_mobile_lcdc_clk_on(priv);
8564557a 1215 }
2feb075a 1216
3b0fd9d7
AC		 1217 if (ch->bl) {
1218 ch->bl->props.power = FB_BLANK_POWERDOWN;
1219 backlight_update_status(ch->bl);
1220 }
1221
37c5dcc2 1222 sh_mobile_lcdc_display_off(ch);
7caa4342 1223
4a237177
LP		 1224 /* Free the MERAM cache. */
1225 if (ch->cache) {
6e729b41 1226 sh_mobile_meram_cache_free(priv->meram_dev, ch->cache);
4a237177 1227 ch->cache = 0;
7caa4342
DHG		 1228 }
1229
cfb4f5d1
MD		 1230 }
1231
1232 /* stop the lcdc */
8e9bb19e
MD		 1233 if (priv->started) {
1234 sh_mobile_lcdc_start_stop(priv, 0);
1235 priv->started = 0;
1236 }
b51339ff 1237
8564557a
MD		 1238 /* stop clocks */
1239 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
1240 if (priv->ch[k].enabled)
1241 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1242}
1243
c5deac3c
LP		 1244static int __sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1245 struct fb_info *info)
1246{
1247 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
1248 return -EINVAL;
1249
1250 /* Make sure the virtual resolution is at least as big as the visible
1251 * resolution.
1252 */
1253 if (var->xres_virtual < var->xres)
1254 var->xres_virtual = var->xres;
1255 if (var->yres_virtual < var->yres)
1256 var->yres_virtual = var->yres;
1257
1258 if (sh_mobile_format_is_fourcc(var)) {
1259 const struct sh_mobile_lcdc_format_info *format;
1260
1261 format = sh_mobile_format_info(var->grayscale);
1262 if (format == NULL)
1263 return -EINVAL;
1264 var->bits_per_pixel = format->bpp;
1265
1266 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1267 * respectively.
1268 */
1269 if (!format->yuv)
1270 var->colorspace = V4L2_COLORSPACE_SRGB;
1271 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1272 var->colorspace = V4L2_COLORSPACE_JPEG;
1273 } else {
1274 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1275 var->bits_per_pixel = 16;
1276 var->red.offset = 11;
1277 var->red.length = 5;
1278 var->green.offset = 5;
1279 var->green.length = 6;
1280 var->blue.offset = 0;
1281 var->blue.length = 5;
1282 var->transp.offset = 0;
1283 var->transp.length = 0;
1284 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1285 var->bits_per_pixel = 24;
1286 var->red.offset = 16;
1287 var->red.length = 8;
1288 var->green.offset = 8;
1289 var->green.length = 8;
1290 var->blue.offset = 0;
1291 var->blue.length = 8;
1292 var->transp.offset = 0;
1293 var->transp.length = 0;
1294 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1295 var->bits_per_pixel = 32;
1296 var->red.offset = 16;
1297 var->red.length = 8;
1298 var->green.offset = 8;
1299 var->green.length = 8;
1300 var->blue.offset = 0;
1301 var->blue.length = 8;
1302 var->transp.offset = 24;
1303 var->transp.length = 8;
1304 } else
1305 return -EINVAL;
1306
1307 var->red.msb_right = 0;
1308 var->green.msb_right = 0;
1309 var->blue.msb_right = 0;
1310 var->transp.msb_right = 0;
1311 }
1312
1313 /* Make sure we don't exceed our allocated memory. */
1314 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1315 info->fix.smem_len)
1316 return -EINVAL;
1317
1318 return 0;
1319}
1320
1321/* -----------------------------------------------------------------------------
1322 * Frame buffer operations - Overlays
1323 */
1324
1325static ssize_t
1326overlay_alpha_show(struct device *dev, struct device_attribute *attr, char *buf)
1327{
1328 struct fb_info *info = dev_get_drvdata(dev);
1329 struct sh_mobile_lcdc_overlay *ovl = info->par;
1330
1331 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->alpha);
1332}
1333
1334static ssize_t
1335overlay_alpha_store(struct device *dev, struct device_attribute *attr,
1336 const char *buf, size_t count)
1337{
1338 struct fb_info *info = dev_get_drvdata(dev);
1339 struct sh_mobile_lcdc_overlay *ovl = info->par;
1340 unsigned int alpha;
1341 char *endp;
1342
1343 alpha = simple_strtoul(buf, &endp, 10);
1344 if (isspace(*endp))
1345 endp++;
1346
1347 if (endp - buf != count)
1348 return -EINVAL;
1349
1350 if (alpha > 255)
1351 return -EINVAL;
1352
1353 if (ovl->alpha != alpha) {
1354 ovl->alpha = alpha;
1355
1356 if (ovl->mode == LCDC_OVERLAY_BLEND && ovl->enabled)
1357 sh_mobile_lcdc_overlay_setup(ovl);
1358 }
1359
1360 return count;
1361}
1362
1363static ssize_t
1364overlay_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1365{
1366 struct fb_info *info = dev_get_drvdata(dev);
1367 struct sh_mobile_lcdc_overlay *ovl = info->par;
1368
1369 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->mode);
1370}
1371
1372static ssize_t
1373overlay_mode_store(struct device *dev, struct device_attribute *attr,
1374 const char *buf, size_t count)
1375{
1376 struct fb_info *info = dev_get_drvdata(dev);
1377 struct sh_mobile_lcdc_overlay *ovl = info->par;
1378 unsigned int mode;
1379 char *endp;
1380
1381 mode = simple_strtoul(buf, &endp, 10);
1382 if (isspace(*endp))
1383 endp++;
1384
1385 if (endp - buf != count)
1386 return -EINVAL;
1387
1388 if (mode != LCDC_OVERLAY_BLEND && mode != LCDC_OVERLAY_ROP3)
1389 return -EINVAL;
1390
1391 if (ovl->mode != mode) {
1392 ovl->mode = mode;
1393
1394 if (ovl->enabled)
1395 sh_mobile_lcdc_overlay_setup(ovl);
1396 }
1397
1398 return count;
1399}
1400
1401static ssize_t
1402overlay_position_show(struct device *dev, struct device_attribute *attr,
1403 char *buf)
1404{
1405 struct fb_info *info = dev_get_drvdata(dev);
1406 struct sh_mobile_lcdc_overlay *ovl = info->par;
1407
1408 return scnprintf(buf, PAGE_SIZE, "%d,%d\n", ovl->pos_x, ovl->pos_y);
1409}
1410
1411static ssize_t
1412overlay_position_store(struct device *dev, struct device_attribute *attr,
1413 const char *buf, size_t count)
1414{
1415 struct fb_info *info = dev_get_drvdata(dev);
1416 struct sh_mobile_lcdc_overlay *ovl = info->par;
1417 char *endp;
1418 int pos_x;
1419 int pos_y;
1420
1421 pos_x = simple_strtol(buf, &endp, 10);
1422 if (*endp != ',')
1423 return -EINVAL;
1424
1425 pos_y = simple_strtol(endp + 1, &endp, 10);
1426 if (isspace(*endp))
1427 endp++;
1428
1429 if (endp - buf != count)
1430 return -EINVAL;
1431
1432 if (ovl->pos_x != pos_x || ovl->pos_y != pos_y) {
1433 ovl->pos_x = pos_x;
1434 ovl->pos_y = pos_y;
1435
1436 if (ovl->enabled)
1437 sh_mobile_lcdc_overlay_setup(ovl);
1438 }
1439
1440 return count;
1441}
1442
1443static ssize_t
1444overlay_rop3_show(struct device *dev, struct device_attribute *attr, char *buf)
1445{
1446 struct fb_info *info = dev_get_drvdata(dev);
1447 struct sh_mobile_lcdc_overlay *ovl = info->par;
1448
1449 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->rop3);
1450}
1451
1452static ssize_t
1453overlay_rop3_store(struct device *dev, struct device_attribute *attr,
1454 const char *buf, size_t count)
1455{
1456 struct fb_info *info = dev_get_drvdata(dev);
1457 struct sh_mobile_lcdc_overlay *ovl = info->par;
1458 unsigned int rop3;
1459 char *endp;
1460
1461 rop3 = !!simple_strtoul(buf, &endp, 10);
1462 if (isspace(*endp))
1463 endp++;
1464
1465 if (endp - buf != count)
1466 return -EINVAL;
1467
1468 if (rop3 > 255)
1469 return -EINVAL;
1470
1471 if (ovl->rop3 != rop3) {
1472 ovl->rop3 = rop3;
1473
1474 if (ovl->mode == LCDC_OVERLAY_ROP3 && ovl->enabled)
1475 sh_mobile_lcdc_overlay_setup(ovl);
1476 }
1477
1478 return count;
1479}
1480
1481static const struct device_attribute overlay_sysfs_attrs[] = {
1482 __ATTR(ovl_alpha, S_IRUGO|S_IWUSR,
1483 overlay_alpha_show, overlay_alpha_store),
1484 __ATTR(ovl_mode, S_IRUGO|S_IWUSR,
1485 overlay_mode_show, overlay_mode_store),
1486 __ATTR(ovl_position, S_IRUGO|S_IWUSR,
1487 overlay_position_show, overlay_position_store),
1488 __ATTR(ovl_rop3, S_IRUGO|S_IWUSR,
1489 overlay_rop3_show, overlay_rop3_store),
1490};
1491
1492static const struct fb_fix_screeninfo sh_mobile_lcdc_overlay_fix = {
1493 .id = "SH Mobile LCDC",
1494 .type = FB_TYPE_PACKED_PIXELS,
1495 .visual = FB_VISUAL_TRUECOLOR,
1496 .accel = FB_ACCEL_NONE,
15dede88 1497 .xpanstep = 1,
c5deac3c
LP		 1498 .ypanstep = 1,
1499 .ywrapstep = 0,
1500 .capabilities = FB_CAP_FOURCC,
1501};
1502
1503static int sh_mobile_lcdc_overlay_pan(struct fb_var_screeninfo *var,
1504 struct fb_info *info)
1505{
1506 struct sh_mobile_lcdc_overlay *ovl = info->par;
1507 unsigned long base_addr_y;
1508 unsigned long base_addr_c;
a4aa25f6 1509 unsigned long y_offset;
c5deac3c
LP		 1510 unsigned long c_offset;
1511
a4aa25f6
LP		 1512 if (!ovl->format->yuv) {
1513 y_offset = (var->yoffset * ovl->xres_virtual + var->xoffset)
1514 * ovl->format->bpp / 8;
1515 c_offset = 0;
1516 } else {
1517 unsigned int xsub = ovl->format->bpp < 24 ? 2 : 1;
1518 unsigned int ysub = ovl->format->bpp < 16 ? 2 : 1;
1519
1520 y_offset = var->yoffset * ovl->xres_virtual + var->xoffset;
1521 c_offset = var->yoffset / ysub * ovl->xres_virtual * 2 / xsub
1522 + var->xoffset * 2 / xsub;
1523 }
c5deac3c 1524
a4aa25f6
LP		 1525 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1526 * nothing to do in that case.
1527 */
1528 if (y_offset == ovl->pan_y_offset)
1529 return 0;
c5deac3c
LP		 1530
1531 /* Set the source address for the next refresh */
a4aa25f6
LP		 1532 base_addr_y = ovl->dma_handle + y_offset;
1533 base_addr_c = ovl->dma_handle + ovl->xres_virtual * ovl->yres_virtual
1534 + c_offset;
c5deac3c
LP		 1535
1536 ovl->base_addr_y = base_addr_y;
a4aa25f6
LP		 1537 ovl->base_addr_c = base_addr_c;
1538 ovl->pan_y_offset = y_offset;
c5deac3c 1539
8be7c669
LP		 1540 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
1541
c5deac3c
LP		 1542 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
1543 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
1544
8be7c669
LP		 1545 lcdc_write(ovl->channel->lcdc, LDBCR,
1546 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
1547
c5deac3c
LP		 1548 return 0;
1549}
1550
1551static int sh_mobile_lcdc_overlay_ioctl(struct fb_info *info, unsigned int cmd,
1552 unsigned long arg)
1553{
1554 struct sh_mobile_lcdc_overlay *ovl = info->par;
1555
1556 switch (cmd) {
1557 case FBIO_WAITFORVSYNC:
1558 return sh_mobile_lcdc_wait_for_vsync(ovl->channel);
1559
1560 default:
1561 return -ENOIOCTLCMD;
1562 }
1563}
1564
1565static int sh_mobile_lcdc_overlay_check_var(struct fb_var_screeninfo *var,
1566 struct fb_info *info)
1567{
1568 return __sh_mobile_lcdc_check_var(var, info);
1569}
1570
1571static int sh_mobile_lcdc_overlay_set_par(struct fb_info *info)
1572{
1573 struct sh_mobile_lcdc_overlay *ovl = info->par;
1574
1575 ovl->format =
1576 sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
1577
1578 ovl->xres = info->var.xres;
1579 ovl->xres_virtual = info->var.xres_virtual;
1580 ovl->yres = info->var.yres;
1581 ovl->yres_virtual = info->var.yres_virtual;
1582
1583 if (ovl->format->yuv)
16ca21c9 1584 ovl->pitch = info->var.xres_virtual;
c5deac3c 1585 else
16ca21c9 1586 ovl->pitch = info->var.xres_virtual * ovl->format->bpp / 8;
c5deac3c
LP		 1587
1588 sh_mobile_lcdc_overlay_setup(ovl);
1589
1590 info->fix.line_length = ovl->pitch;
1591
1592 if (sh_mobile_format_is_fourcc(&info->var)) {
1593 info->fix.type = FB_TYPE_FOURCC;
1594 info->fix.visual = FB_VISUAL_FOURCC;
1595 } else {
1596 info->fix.type = FB_TYPE_PACKED_PIXELS;
1597 info->fix.visual = FB_VISUAL_TRUECOLOR;
1598 }
1599
1600 return 0;
1601}
1602
1603/* Overlay blanking. Disable the overlay when blanked. */
1604static int sh_mobile_lcdc_overlay_blank(int blank, struct fb_info *info)
1605{
1606 struct sh_mobile_lcdc_overlay *ovl = info->par;
1607
1608 ovl->enabled = !blank;
1609 sh_mobile_lcdc_overlay_setup(ovl);
1610
1611 /* Prevent the backlight from receiving a blanking event by returning
1612 * a non-zero value.
1613 */
1614 return 1;
1615}
1616
bf10a537
HE		 1617static int
1618sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct *vma)
1619{
1620 struct sh_mobile_lcdc_overlay *ovl = info->par;
1621
1622 return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
1623 ovl->dma_handle, ovl->fb_size);
1624}
1625
c5deac3c
LP		 1626static struct fb_ops sh_mobile_lcdc_overlay_ops = {
1627 .owner = THIS_MODULE,
1628 .fb_read = fb_sys_read,
1629 .fb_write = fb_sys_write,
1630 .fb_fillrect = sys_fillrect,
1631 .fb_copyarea = sys_copyarea,
1632 .fb_imageblit = sys_imageblit,
1633 .fb_blank = sh_mobile_lcdc_overlay_blank,
1634 .fb_pan_display = sh_mobile_lcdc_overlay_pan,
1635 .fb_ioctl = sh_mobile_lcdc_overlay_ioctl,
1636 .fb_check_var = sh_mobile_lcdc_overlay_check_var,
1637 .fb_set_par = sh_mobile_lcdc_overlay_set_par,
bf10a537 1638 .fb_mmap = sh_mobile_lcdc_overlay_mmap,
c5deac3c
LP		 1639};
1640
1641static void
1642sh_mobile_lcdc_overlay_fb_unregister(struct sh_mobile_lcdc_overlay *ovl)
1643{
1644 struct fb_info *info = ovl->info;
1645
1646 if (info == NULL || info->dev == NULL)
1647 return;
1648
1649 unregister_framebuffer(ovl->info);
1650}
1651
1652static int __devinit
1653sh_mobile_lcdc_overlay_fb_register(struct sh_mobile_lcdc_overlay *ovl)
1654{
1655 struct sh_mobile_lcdc_priv *lcdc = ovl->channel->lcdc;
1656 struct fb_info *info = ovl->info;
1657 unsigned int i;
1658 int ret;
1659
1660 if (info == NULL)
1661 return 0;
1662
1663 ret = register_framebuffer(info);
1664 if (ret < 0)
1665 return ret;
1666
1667 dev_info(lcdc->dev, "registered %s/overlay %u as %dx%d %dbpp.\n",
1668 dev_name(lcdc->dev), ovl->index, info->var.xres,
1669 info->var.yres, info->var.bits_per_pixel);
1670
1671 for (i = 0; i < ARRAY_SIZE(overlay_sysfs_attrs); ++i) {
1672 ret = device_create_file(info->dev, &overlay_sysfs_attrs[i]);
1673 if (ret < 0)
1674 return ret;
1675 }
1676
1677 return 0;
1678}
1679
1680static void
1681sh_mobile_lcdc_overlay_fb_cleanup(struct sh_mobile_lcdc_overlay *ovl)
1682{
1683 struct fb_info *info = ovl->info;
1684
1685 if (info == NULL || info->device == NULL)
1686 return;
1687
1688 framebuffer_release(info);
1689}
1690
1691static int __devinit
1692sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
1693{
1694 struct sh_mobile_lcdc_priv *priv = ovl->channel->lcdc;
1695 struct fb_var_screeninfo *var;
1696 struct fb_info *info;
1697
1698 /* Allocate and initialize the frame buffer device. */
1699 info = framebuffer_alloc(0, priv->dev);
1700 if (info == NULL) {
1701 dev_err(priv->dev, "unable to allocate fb_info\n");
1702 return -ENOMEM;
1703 }
1704
1705 ovl->info = info;
1706
1707 info->flags = FBINFO_FLAG_DEFAULT;
1708 info->fbops = &sh_mobile_lcdc_overlay_ops;
1709 info->device = priv->dev;
1710 info->screen_base = ovl->fb_mem;
1711 info->par = ovl;
1712
1713 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1714 * for NV12 and NV21.
1715 */
1716 info->fix = sh_mobile_lcdc_overlay_fix;
1717 snprintf(info->fix.id, sizeof(info->fix.id),
1718 "SH Mobile LCDC Overlay %u", ovl->index);
1719 info->fix.smem_start = ovl->dma_handle;
1720 info->fix.smem_len = ovl->fb_size;
1721 info->fix.line_length = ovl->pitch;
1722
1723 if (ovl->format->yuv)
1724 info->fix.visual = FB_VISUAL_FOURCC;
1725 else
1726 info->fix.visual = FB_VISUAL_TRUECOLOR;
1727
15dede88 1728 switch (ovl->format->fourcc) {
15dede88
LP		 1729 case V4L2_PIX_FMT_NV12:
1730 case V4L2_PIX_FMT_NV21:
ac33a207
LP		 1731 info->fix.ypanstep = 2;
1732 case V4L2_PIX_FMT_NV16:
1733 case V4L2_PIX_FMT_NV61:
15dede88
LP		 1734 info->fix.xpanstep = 2;
1735 }
c5deac3c
LP		 1736
1737 /* Initialize variable screen information. */
1738 var = &info->var;
1739 memset(var, 0, sizeof(*var));
1740 var->xres = ovl->xres;
1741 var->yres = ovl->yres;
1742 var->xres_virtual = ovl->xres_virtual;
1743 var->yres_virtual = ovl->yres_virtual;
1744 var->activate = FB_ACTIVATE_NOW;
1745
1746 /* Use the legacy API by default for RGB formats, and the FOURCC API
1747 * for YUV formats.
1748 */
1749 if (!ovl->format->yuv)
1750 var->bits_per_pixel = ovl->format->bpp;
1751 else
1752 var->grayscale = ovl->format->fourcc;
1753
1754 return sh_mobile_lcdc_overlay_check_var(var, info);
1755}
1756
f1f60b5f 1757/* -----------------------------------------------------------------------------
c5deac3c 1758 * Frame buffer operations - main frame buffer
f1f60b5f 1759 */
cfb4f5d1
MD		 1760
1761static int sh_mobile_lcdc_setcolreg(u_int regno,
1762 u_int red, u_int green, u_int blue,
1763 u_int transp, struct fb_info *info)
1764{
1765 u32 *palette = info->pseudo_palette;
1766
1767 if (regno >= PALETTE_NR)
1768 return -EINVAL;
1769
1770 /* only FB_VISUAL_TRUECOLOR supported */
1771
1772 red >>= 16 - info->var.red.length;
1773 green >>= 16 - info->var.green.length;
1774 blue >>= 16 - info->var.blue.length;
1775 transp >>= 16 - info->var.transp.length;
1776
1777 palette[regno] = (red << info->var.red.offset) |
1778 (green << info->var.green.offset) |
1779 (blue << info->var.blue.offset) |
1780 (transp << info->var.transp.offset);
1781
1782 return 0;
1783}
1784
3281e54c 1785static const struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
cfb4f5d1
MD		 1786 .id = "SH Mobile LCDC",
1787 .type = FB_TYPE_PACKED_PIXELS,
1788 .visual = FB_VISUAL_TRUECOLOR,
1789 .accel = FB_ACCEL_NONE,
15dede88 1790 .xpanstep = 1,
9dd38819
PE		 1791 .ypanstep = 1,
1792 .ywrapstep = 0,
edd153a3 1793 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 1794};
1795
8564557a
MD		 1796static void sh_mobile_lcdc_fillrect(struct fb_info *info,
1797 const struct fb_fillrect *rect)
1798{
1799 sys_fillrect(info, rect);
1800 sh_mobile_lcdc_deferred_io_touch(info);
1801}
1802
1803static void sh_mobile_lcdc_copyarea(struct fb_info *info,
1804 const struct fb_copyarea *area)
1805{
1806 sys_copyarea(info, area);
1807 sh_mobile_lcdc_deferred_io_touch(info);
1808}
1809
1810static void sh_mobile_lcdc_imageblit(struct fb_info *info,
1811 const struct fb_image *image)
1812{
1813 sys_imageblit(info, image);
1814 sh_mobile_lcdc_deferred_io_touch(info);
1815}
1816
d7ad3342
LP		 1817static int sh_mobile_lcdc_pan(struct fb_var_screeninfo *var,
1818 struct fb_info *info)
9dd38819
PE		 1819{
1820 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 1821 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
1822 unsigned long ldrcntr;
a4aa25f6
LP		 1823 unsigned long base_addr_y, base_addr_c;
1824 unsigned long y_offset;
53b50314 1825 unsigned long c_offset;
92e1f9a7 1826
a4aa25f6
LP		 1827 if (!ch->format->yuv) {
1828 y_offset = (var->yoffset * ch->xres_virtual + var->xoffset)
1829 * ch->format->bpp / 8;
1830 c_offset = 0;
1831 } else {
1832 unsigned int xsub = ch->format->bpp < 24 ? 2 : 1;
1833 unsigned int ysub = ch->format->bpp < 16 ? 2 : 1;
9dd38819 1834
a4aa25f6
LP		 1835 y_offset = var->yoffset * ch->xres_virtual + var->xoffset;
1836 c_offset = var->yoffset / ysub * ch->xres_virtual * 2 / xsub
1837 + var->xoffset * 2 / xsub;
1838 }
9dd38819 1839
a4aa25f6
LP		 1840 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1841 * nothing to do in that case.
1842 */
1843 if (y_offset == ch->pan_y_offset)
1844 return 0;
9dd38819 1845
92e1f9a7 1846 /* Set the source address for the next refresh */
a4aa25f6
LP		 1847 base_addr_y = ch->dma_handle + y_offset;
1848 base_addr_c = ch->dma_handle + ch->xres_virtual * ch->yres_virtual
1849 + c_offset;
53b50314 1850
6e729b41
LP		 1851 if (ch->cache)
1852 sh_mobile_meram_cache_update(priv->meram_dev, ch->cache,
1853 base_addr_y, base_addr_c,
1854 &base_addr_y, &base_addr_c);
7caa4342 1855
49d79ba2
LP		 1856 ch->base_addr_y = base_addr_y;
1857 ch->base_addr_c = base_addr_c;
a4aa25f6 1858 ch->pan_y_offset = y_offset;
7caa4342 1859
49d79ba2 1860 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
58f03d99 1861 if (ch->format->yuv)
49d79ba2 1862 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 1863
a4aa25f6 1864 ldrcntr = lcdc_read(priv, _LDRCNTR);
92e1f9a7
PE		 1865 if (lcdc_chan_is_sublcd(ch))
1866 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
1867 else
1868 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
1869
92e1f9a7
PE		 1870
1871 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 1872
1873 return 0;
1874}
1875
d7ad3342
LP		 1876static int sh_mobile_lcdc_ioctl(struct fb_info *info, unsigned int cmd,
1877 unsigned long arg)
40331b21 1878{
d7ad3342 1879 struct sh_mobile_lcdc_chan *ch = info->par;
40331b21
PE		 1880 int retval;
1881
1882 switch (cmd) {
1883 case FBIO_WAITFORVSYNC:
d7ad3342 1884 retval = sh_mobile_lcdc_wait_for_vsync(ch);
40331b21
PE		 1885 break;
1886
1887 default:
1888 retval = -ENOIOCTLCMD;
1889 break;
1890 }
1891 return retval;
1892}
1893
dd210503
GL		 1894static void sh_mobile_fb_reconfig(struct fb_info *info)
1895{
1896 struct sh_mobile_lcdc_chan *ch = info->par;
2d04559d
LP		 1897 struct fb_var_screeninfo var;
1898 struct fb_videomode mode;
dd210503
GL		 1899 struct fb_event event;
1900 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1901
1902 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1903 /* More framebuffer users are active */
1904 return;
1905
2d04559d 1906 fb_var_to_videomode(&mode, &info->var);
dd210503 1907
2d04559d 1908 if (fb_mode_is_equal(&ch->display.mode, &mode))
dd210503
GL		 1909 return;
1910
1911 /* Display has been re-plugged, framebuffer is free now, reconfigure */
2d04559d
LP		 1912 var = info->var;
1913 fb_videomode_to_var(&var, &ch->display.mode);
1914 var.width = ch->display.width;
1915 var.height = ch->display.height;
1916 var.activate = FB_ACTIVATE_NOW;
1917
1918 if (fb_set_var(info, &var) < 0)
dd210503
GL		 1919 /* Couldn't reconfigure, hopefully, can continue as before */
1920 return;
1921
dd210503
GL		 1922 /*
1923 * fb_set_var() calls the notifier change internally, only if
1924 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1925 * user event, we have to call the chain ourselves.
1926 */
1927 event.info = info;
2d04559d 1928 event.data = &ch->display.mode;
dd210503
GL		 1929 fb_notifier_call_chain(evnt, &event);
1930}
1931
1932/*
1933 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1934 * user == 1, or with console sem held, if user == 0.
1935 */
d7ad3342 1936static int sh_mobile_lcdc_release(struct fb_info *info, int user)
dd210503
GL		 1937{
1938 struct sh_mobile_lcdc_chan *ch = info->par;
1939
1940 mutex_lock(&ch->open_lock);
1941 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1942
1943 ch->use_count--;
1944
1945 /* Nothing to reconfigure, when called from fbcon */
1946 if (user) {
ac751efa 1947 console_lock();
dd210503 1948 sh_mobile_fb_reconfig(info);
ac751efa 1949 console_unlock();
dd210503
GL		 1950 }
1951
1952 mutex_unlock(&ch->open_lock);
1953
1954 return 0;
1955}
1956
d7ad3342 1957static int sh_mobile_lcdc_open(struct fb_info *info, int user)
dd210503
GL		 1958{
1959 struct sh_mobile_lcdc_chan *ch = info->par;
1960
1961 mutex_lock(&ch->open_lock);
1962 ch->use_count++;
1963
1964 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1965 mutex_unlock(&ch->open_lock);
1966
1967 return 0;
1968}
1969
d7ad3342
LP		 1970static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1971 struct fb_info *info)
dd210503
GL		 1972{
1973 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1974 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1975 unsigned int best_dist = (unsigned int)-1;
1976 unsigned int best_xres = 0;
1977 unsigned int best_yres = 0;
1978 unsigned int i;
c5deac3c 1979 int ret;
03862194
LP		 1980
1981 /* If board code provides us with a list of available modes, make sure
1982 * we use one of them. Find the mode closest to the requested one. The
1983 * distance between two modes is defined as the size of the
1984 * non-overlapping parts of the two rectangles.
1985 */
b5ef967d
LP		 1986 for (i = 0; i < ch->cfg->num_modes; ++i) {
1987 const struct fb_videomode *mode = &ch->cfg->lcd_modes[i];
03862194
LP		 1988 unsigned int dist;
1989
1990 /* We can only round up. */
1991 if (var->xres > mode->xres || var->yres > mode->yres)
1992 continue;
1993
1994 dist = var->xres * var->yres + mode->xres * mode->yres
1995 - 2 * min(var->xres, mode->xres)
1996 * min(var->yres, mode->yres);
1997
1998 if (dist < best_dist) {
1999 best_xres = mode->xres;
2000 best_yres = mode->yres;
2001 best_dist = dist;
2002 }
dd210503 2003 }
417d4827 2004
03862194 2005 /* If no available mode can be used, return an error. */
b5ef967d 2006 if (ch->cfg->num_modes != 0) {
03862194
LP		 2007 if (best_dist == (unsigned int)-1)
2008 return -EINVAL;
2009
2010 var->xres = best_xres;
2011 var->yres = best_yres;
2012 }
2013
c5deac3c
LP		 2014 ret = __sh_mobile_lcdc_check_var(var, info);
2015 if (ret < 0)
2016 return ret;
03862194 2017
edd153a3
LP		 2018 /* only accept the forced_fourcc for dual channel configurations */
2019 if (p->forced_fourcc &&
2020 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 2021 return -EINVAL;
417d4827 2022
dd210503
GL		 2023 return 0;
2024}
40331b21 2025
d7ad3342 2026static int sh_mobile_lcdc_set_par(struct fb_info *info)
ed5bebf2
LP		 2027{
2028 struct sh_mobile_lcdc_chan *ch = info->par;
2029 int ret;
2030
2031 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 2032
fc9e78e6 2033 ch->format = sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
58f03d99
LP		 2034 ch->colorspace = info->var.colorspace;
2035
2036 ch->xres = info->var.xres;
2037 ch->xres_virtual = info->var.xres_virtual;
2038 ch->yres = info->var.yres;
2039 ch->yres_virtual = info->var.yres_virtual;
2040
2041 if (ch->format->yuv)
16ca21c9 2042 ch->pitch = info->var.xres_virtual;
58f03d99 2043 else
16ca21c9 2044 ch->pitch = info->var.xres_virtual * ch->format->bpp / 8;
fc9e78e6 2045
ed5bebf2 2046 ret = sh_mobile_lcdc_start(ch->lcdc);
58f03d99 2047 if (ret < 0)
ed5bebf2 2048 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
58f03d99
LP		 2049
2050 info->fix.line_length = ch->pitch;
ed5bebf2 2051
edd153a3
LP		 2052 if (sh_mobile_format_is_fourcc(&info->var)) {
2053 info->fix.type = FB_TYPE_FOURCC;
2054 info->fix.visual = FB_VISUAL_FOURCC;
2055 } else {
2056 info->fix.type = FB_TYPE_PACKED_PIXELS;
2057 info->fix.visual = FB_VISUAL_TRUECOLOR;
2058 }
2059
ed5bebf2
LP		 2060 return ret;
2061}
2062
8857b9aa
AC		 2063/*
2064 * Screen blanking. Behavior is as follows:
2065 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
2066 * FB_BLANK_NORMAL: screen blanked, clocks enabled
2067 * FB_BLANK_VSYNC,
2068 * FB_BLANK_HSYNC,
2069 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
2070 */
2071static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
2072{
2073 struct sh_mobile_lcdc_chan *ch = info->par;
2074 struct sh_mobile_lcdc_priv *p = ch->lcdc;
2075
2076 /* blank the screen? */
2077 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
2078 struct fb_fillrect rect = {
58f03d99
LP		 2079 .width = ch->xres,
2080 .height = ch->yres,
8857b9aa
AC		 2081 };
2082 sh_mobile_lcdc_fillrect(info, &rect);
2083 }
2084 /* turn clocks on? */
2085 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
2086 sh_mobile_lcdc_clk_on(p);
2087 }
2088 /* turn clocks off? */
2089 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
2090 /* make sure the screen is updated with the black fill before
2091 * switching the clocks off. one vsync is not enough since
2092 * blanking may occur in the middle of a refresh. deferred io
2093 * mode will reenable the clocks and update the screen in time,
2094 * so it does not need this. */
2095 if (!info->fbdefio) {
d7ad3342
LP		 2096 sh_mobile_lcdc_wait_for_vsync(ch);
2097 sh_mobile_lcdc_wait_for_vsync(ch);
8857b9aa
AC		 2098 }
2099 sh_mobile_lcdc_clk_off(p);
2100 }
2101
2102 ch->blank_status = blank;
2103 return 0;
2104}
2105
bf10a537
HE		 2106static int
2107sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
2108{
2109 struct sh_mobile_lcdc_chan *ch = info->par;
2110
2111 return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
2112 ch->dma_handle, ch->fb_size);
2113}
2114
cfb4f5d1 2115static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 2116 .owner = THIS_MODULE,
cfb4f5d1 2117 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 2118 .fb_read = fb_sys_read,
2119 .fb_write = fb_sys_write,
8564557a
MD		 2120 .fb_fillrect = sh_mobile_lcdc_fillrect,
2121 .fb_copyarea = sh_mobile_lcdc_copyarea,
2122 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 2123 .fb_blank = sh_mobile_lcdc_blank,
d7ad3342
LP		 2124 .fb_pan_display = sh_mobile_lcdc_pan,
2125 .fb_ioctl = sh_mobile_lcdc_ioctl,
2126 .fb_open = sh_mobile_lcdc_open,
2127 .fb_release = sh_mobile_lcdc_release,
2128 .fb_check_var = sh_mobile_lcdc_check_var,
2129 .fb_set_par = sh_mobile_lcdc_set_par,
bf10a537 2130 .fb_mmap = sh_mobile_lcdc_mmap,
cfb4f5d1
MD		 2131};
2132
a67f379d
LP		 2133static void
2134sh_mobile_lcdc_channel_fb_unregister(struct sh_mobile_lcdc_chan *ch)
2135{
2136 if (ch->info && ch->info->dev)
2137 unregister_framebuffer(ch->info);
2138}
2139
2140static int __devinit
2141sh_mobile_lcdc_channel_fb_register(struct sh_mobile_lcdc_chan *ch)
2142{
2143 struct fb_info *info = ch->info;
2144 int ret;
2145
2146 if (info->fbdefio) {
2147 ch->sglist = vmalloc(sizeof(struct scatterlist) *
2148 ch->fb_size >> PAGE_SHIFT);
2149 if (!ch->sglist) {
2150 dev_err(ch->lcdc->dev, "cannot allocate sglist\n");
2151 return -ENOMEM;
2152 }
2153 }
2154
2155 info->bl_dev = ch->bl;
2156
2157 ret = register_framebuffer(info);
2158 if (ret < 0)
2159 return ret;
2160
2161 dev_info(ch->lcdc->dev, "registered %s/%s as %dx%d %dbpp.\n",
b5ef967d 2162 dev_name(ch->lcdc->dev), (ch->cfg->chan == LCDC_CHAN_MAINLCD) ?
a67f379d
LP		 2163 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
2164 info->var.bits_per_pixel);
2165
2166 /* deferred io mode: disable clock to save power */
2167 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
2168 sh_mobile_lcdc_clk_off(ch->lcdc);
2169
2170 return ret;
2171}
2172
2173static void
2174sh_mobile_lcdc_channel_fb_cleanup(struct sh_mobile_lcdc_chan *ch)
2175{
2176 struct fb_info *info = ch->info;
2177
2178 if (!info || !info->device)
2179 return;
2180
2181 if (ch->sglist)
2182 vfree(ch->sglist);
2183
2184 fb_dealloc_cmap(&info->cmap);
2185 framebuffer_release(info);
2186}
2187
2188static int __devinit
2189sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
2190 const struct fb_videomode *mode,
2191 unsigned int num_modes)
2192{
2193 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
2194 struct fb_var_screeninfo *var;
2195 struct fb_info *info;
2196 int ret;
2197
2198 /* Allocate and initialize the frame buffer device. Create the modes
2199 * list and allocate the color map.
2200 */
2201 info = framebuffer_alloc(0, priv->dev);
2202 if (info == NULL) {
2203 dev_err(priv->dev, "unable to allocate fb_info\n");
2204 return -ENOMEM;
2205 }
2206
2207 ch->info = info;
2208
2209 info->flags = FBINFO_FLAG_DEFAULT;
2210 info->fbops = &sh_mobile_lcdc_ops;
2211 info->device = priv->dev;
2212 info->screen_base = ch->fb_mem;
2213 info->pseudo_palette = &ch->pseudo_palette;
2214 info->par = ch;
2215
2216 fb_videomode_to_modelist(mode, num_modes, &info->modelist);
2217
2218 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
2219 if (ret < 0) {
2220 dev_err(priv->dev, "unable to allocate cmap\n");
2221 return ret;
2222 }
2223
2224 /* Initialize fixed screen information. Restrict pan to 2 lines steps
2225 * for NV12 and NV21.
2226 */
2227 info->fix = sh_mobile_lcdc_fix;
2228 info->fix.smem_start = ch->dma_handle;
2229 info->fix.smem_len = ch->fb_size;
58f03d99
LP		 2230 info->fix.line_length = ch->pitch;
2231
2232 if (ch->format->yuv)
2233 info->fix.visual = FB_VISUAL_FOURCC;
2234 else
2235 info->fix.visual = FB_VISUAL_TRUECOLOR;
2236
15dede88 2237 switch (ch->format->fourcc) {
15dede88
LP		 2238 case V4L2_PIX_FMT_NV12:
2239 case V4L2_PIX_FMT_NV21:
ac33a207
LP		 2240 info->fix.ypanstep = 2;
2241 case V4L2_PIX_FMT_NV16:
2242 case V4L2_PIX_FMT_NV61:
15dede88
LP		 2243 info->fix.xpanstep = 2;
2244 }
a67f379d
LP		 2245
2246 /* Initialize variable screen information using the first mode as
bd5f2c69 2247 * default.
a67f379d
LP		 2248 */
2249 var = &info->var;
2250 fb_videomode_to_var(var, mode);
b5ef967d
LP		 2251 var->width = ch->cfg->panel_cfg.width;
2252 var->height = ch->cfg->panel_cfg.height;
bd5f2c69
LP		 2253 var->xres_virtual = ch->xres_virtual;
2254 var->yres_virtual = ch->yres_virtual;
a67f379d
LP		 2255 var->activate = FB_ACTIVATE_NOW;
2256
2257 /* Use the legacy API by default for RGB formats, and the FOURCC API
2258 * for YUV formats.
2259 */
2260 if (!ch->format->yuv)
2261 var->bits_per_pixel = ch->format->bpp;
2262 else
2263 var->grayscale = ch->format->fourcc;
2264
d7ad3342 2265 ret = sh_mobile_lcdc_check_var(var, info);
a67f379d
LP		 2266 if (ret)
2267 return ret;
2268
a67f379d
LP		 2269 return 0;
2270}
2271
f1f60b5f
LP		 2272/* -----------------------------------------------------------------------------
2273 * Backlight
2274 */
2275
3b0fd9d7
AC		 2276static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
2277{
2278 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7
AC		 2279 int brightness = bdev->props.brightness;
2280
2281 if (bdev->props.power != FB_BLANK_UNBLANK ||
2282 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
2283 brightness = 0;
2284
b5ef967d 2285 return ch->cfg->bl_info.set_brightness(brightness);
3b0fd9d7
AC		 2286}
2287
2288static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
2289{
2290 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7 2291
b5ef967d 2292 return ch->cfg->bl_info.get_brightness();
3b0fd9d7
AC		 2293}
2294
2295static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
2296 struct fb_info *info)
2297{
2298 return (info->bl_dev == bdev);
2299}
2300
2301static struct backlight_ops sh_mobile_lcdc_bl_ops = {
2302 .options = BL_CORE_SUSPENDRESUME,
2303 .update_status = sh_mobile_lcdc_update_bl,
2304 .get_brightness = sh_mobile_lcdc_get_brightness,
2305 .check_fb = sh_mobile_lcdc_check_fb,
2306};
2307
2308static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
2309 struct sh_mobile_lcdc_chan *ch)
2310{
2311 struct backlight_device *bl;
2312
b5ef967d 2313 bl = backlight_device_register(ch->cfg->bl_info.name, parent, ch,
3b0fd9d7 2314 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 2315 if (IS_ERR(bl)) {
2316 dev_err(parent, "unable to register backlight device: %ld\n",
2317 PTR_ERR(bl));
3b0fd9d7
AC		 2318 return NULL;
2319 }
2320
b5ef967d 2321 bl->props.max_brightness = ch->cfg->bl_info.max_brightness;
3b0fd9d7
AC		 2322 bl->props.brightness = bl->props.max_brightness;
2323 backlight_update_status(bl);
2324
2325 return bl;
2326}
2327
2328static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
2329{
2330 backlight_device_unregister(bdev);
2331}
2332
f1f60b5f
LP		 2333/* -----------------------------------------------------------------------------
2334 * Power management
2335 */
2336
2feb075a
MD		 2337static int sh_mobile_lcdc_suspend(struct device *dev)
2338{
2339 struct platform_device *pdev = to_platform_device(dev);
2340
2341 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
2342 return 0;
2343}
2344
2345static int sh_mobile_lcdc_resume(struct device *dev)
2346{
2347 struct platform_device *pdev = to_platform_device(dev);
2348
2349 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
2350}
2351
0246c471
MD		 2352static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
2353{
2354 struct platform_device *pdev = to_platform_device(dev);
2427bb24 2355 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471
MD		 2356
2357 /* turn off LCDC hardware */
2427bb24
LP		 2358 lcdc_write(priv, _LDCNT1R, 0);
2359
0246c471
MD		 2360 return 0;
2361}
2362
2363static int sh_mobile_lcdc_runtime_resume(struct device *dev)
2364{
2365 struct platform_device *pdev = to_platform_device(dev);
2427bb24 2366 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
0246c471 2367
2427bb24 2368 __sh_mobile_lcdc_start(priv);
0246c471
MD		 2369
2370 return 0;
2371}
2372
47145210 2373static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 2374 .suspend = sh_mobile_lcdc_suspend,
2375 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 2376 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
2377 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 2378};
2379
f1f60b5f
LP		 2380/* -----------------------------------------------------------------------------
2381 * Framebuffer notifier
2382 */
2383
6de9edd5 2384/* locking: called with info->lock held */
6011bdea
GL		 2385static int sh_mobile_lcdc_notify(struct notifier_block *nb,
2386 unsigned long action, void *data)
2387{
2388 struct fb_event *event = data;
2389 struct fb_info *info = event->info;
2390 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea
GL		 2391
2392 if (&ch->lcdc->notifier != nb)
baf16374 2393 return NOTIFY_DONE;
6011bdea
GL		 2394
2395 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
2396 __func__, action, event->data);
2397
2398 switch(action) {
2399 case FB_EVENT_SUSPEND:
37c5dcc2 2400 sh_mobile_lcdc_display_off(ch);
afe417c0 2401 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 2402 break;
2403 case FB_EVENT_RESUME:
dd210503
GL		 2404 mutex_lock(&ch->open_lock);
2405 sh_mobile_fb_reconfig(info);
2406 mutex_unlock(&ch->open_lock);
6011bdea 2407
37c5dcc2 2408 sh_mobile_lcdc_display_on(ch);
ebe5e12d 2409 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 2410 }
2411
baf16374 2412 return NOTIFY_OK;
6011bdea
GL		 2413}
2414
f1f60b5f
LP		 2415/* -----------------------------------------------------------------------------
2416 * Probe/remove and driver init/exit
2417 */
2418
217e9c43 2419static const struct fb_videomode default_720p __devinitconst = {
f1f60b5f
LP		 2420 .name = "HDMI 720p",
2421 .xres = 1280,
2422 .yres = 720,
2423
2424 .left_margin = 220,
2425 .right_margin = 110,
2426 .hsync_len = 40,
2427
2428 .upper_margin = 20,
2429 .lower_margin = 5,
2430 .vsync_len = 5,
2431
2432 .pixclock = 13468,
2433 .refresh = 60,
2434 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
2435};
2436
b4bee692
LP		 2437static int sh_mobile_lcdc_remove(struct platform_device *pdev)
2438{
2439 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
c5deac3c 2440 unsigned int i;
b4bee692
LP		 2441
2442 fb_unregister_client(&priv->notifier);
2443
c5deac3c
LP		 2444 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++)
2445 sh_mobile_lcdc_overlay_fb_unregister(&priv->overlays[i]);
b4bee692 2446 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
a67f379d 2447 sh_mobile_lcdc_channel_fb_unregister(&priv->ch[i]);
b4bee692
LP		 2448
2449 sh_mobile_lcdc_stop(priv);
2450
c5deac3c
LP		 2451 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++) {
2452 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2453
2454 sh_mobile_lcdc_overlay_fb_cleanup(ovl);
2455
2456 if (ovl->fb_mem)
2457 dma_free_coherent(&pdev->dev, ovl->fb_size,
2458 ovl->fb_mem, ovl->dma_handle);
2459 }
2460
b4bee692 2461 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
9a2985e7 2462 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
b4bee692 2463
e34d0bbb
LP		 2464 if (ch->tx_dev) {
2465 ch->tx_dev->lcdc = NULL;
b5ef967d 2466 module_put(ch->cfg->tx_dev->dev.driver->owner);
e34d0bbb 2467 }
9a2985e7 2468
a67f379d 2469 sh_mobile_lcdc_channel_fb_cleanup(ch);
b4bee692 2470
a67f379d
LP		 2471 if (ch->fb_mem)
2472 dma_free_coherent(&pdev->dev, ch->fb_size,
2473 ch->fb_mem, ch->dma_handle);
b4bee692
LP		 2474 }
2475
2476 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
0c75c4e0
LP		 2477 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
2478
2479 if (ch->bl)
2480 sh_mobile_lcdc_bl_remove(ch->bl);
2481 mutex_destroy(&ch->open_lock);
b4bee692
LP		 2482 }
2483
4774c12a
LP		 2484 if (priv->dot_clk) {
2485 pm_runtime_disable(&pdev->dev);
b4bee692 2486 clk_put(priv->dot_clk);
4774c12a 2487 }
b4bee692
LP		 2488
2489 if (priv->base)
2490 iounmap(priv->base);
2491
2492 if (priv->irq)
2493 free_irq(priv->irq, priv);
2494 kfree(priv);
2495 return 0;
2496}
cfb4f5d1 2497
217e9c43 2498static int __devinit sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f 2499{
b5ef967d 2500 int interface_type = ch->cfg->interface_type;
f1f60b5f
LP		 2501
2502 switch (interface_type) {
2503 case RGB8:
2504 case RGB9:
2505 case RGB12A:
2506 case RGB12B:
2507 case RGB16:
2508 case RGB18:
2509 case RGB24:
2510 case SYS8A:
2511 case SYS8B:
2512 case SYS8C:
2513 case SYS8D:
2514 case SYS9:
2515 case SYS12:
2516 case SYS16A:
2517 case SYS16B:
2518 case SYS16C:
2519 case SYS18:
2520 case SYS24:
2521 break;
2522 default:
2523 return -EINVAL;
2524 }
2525
2526 /* SUBLCD only supports SYS interface */
2527 if (lcdc_chan_is_sublcd(ch)) {
2528 if (!(interface_type & LDMT1R_IFM))
2529 return -EINVAL;
2530
2531 interface_type &= ~LDMT1R_IFM;
2532 }
2533
2534 ch->ldmt1r_value = interface_type;
2535 return 0;
2536}
2537
c5deac3c
LP		 2538static int __devinit
2539sh_mobile_lcdc_overlay_init(struct sh_mobile_lcdc_priv *priv,
2540 struct sh_mobile_lcdc_overlay *ovl)
2541{
2542 const struct sh_mobile_lcdc_format_info *format;
2543 int ret;
2544
2545 if (ovl->cfg->fourcc == 0)
2546 return 0;
2547
2548 /* Validate the format. */
2549 format = sh_mobile_format_info(ovl->cfg->fourcc);
2550 if (format == NULL) {
2551 dev_err(priv->dev, "Invalid FOURCC %08x\n", ovl->cfg->fourcc);
2552 return -EINVAL;
2553 }
2554
2555 ovl->enabled = false;
2556 ovl->mode = LCDC_OVERLAY_BLEND;
2557 ovl->alpha = 255;
2558 ovl->rop3 = 0;
2559 ovl->pos_x = 0;
2560 ovl->pos_y = 0;
2561
2562 /* The default Y virtual resolution is twice the panel size to allow for
2563 * double-buffering.
2564 */
2565 ovl->format = format;
2566 ovl->xres = ovl->cfg->max_xres;
2567 ovl->xres_virtual = ovl->xres;
2568 ovl->yres = ovl->cfg->max_yres;
2569 ovl->yres_virtual = ovl->yres * 2;
2570
2571 if (!format->yuv)
16ca21c9 2572 ovl->pitch = ovl->xres_virtual * format->bpp / 8;
c5deac3c 2573 else
16ca21c9 2574 ovl->pitch = ovl->xres_virtual;
c5deac3c
LP		 2575
2576 /* Allocate frame buffer memory. */
2577 ovl->fb_size = ovl->cfg->max_xres * ovl->cfg->max_yres
2578 * format->bpp / 8 * 2;
2579 ovl->fb_mem = dma_alloc_coherent(priv->dev, ovl->fb_size,
2580 &ovl->dma_handle, GFP_KERNEL);
2581 if (!ovl->fb_mem) {
2582 dev_err(priv->dev, "unable to allocate buffer\n");
2583 return -ENOMEM;
2584 }
2585
2586 ret = sh_mobile_lcdc_overlay_fb_init(ovl);
2587 if (ret < 0)
2588 return ret;
2589
2590 return 0;
2591}
2592
0a7f17aa
LP		 2593static int __devinit
2594sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_priv *priv,
2595 struct sh_mobile_lcdc_chan *ch)
cfb4f5d1 2596{
105784bb 2597 const struct sh_mobile_lcdc_format_info *format;
b5ef967d 2598 const struct sh_mobile_lcdc_chan_cfg *cfg = ch->cfg;
3ce05599
LP		 2599 const struct fb_videomode *max_mode;
2600 const struct fb_videomode *mode;
a67f379d 2601 unsigned int num_modes;
3ce05599 2602 unsigned int max_size;
a67f379d 2603 unsigned int i;
3ce05599 2604
a67472ad 2605 mutex_init(&ch->open_lock);
ecd29947 2606 ch->notify = sh_mobile_lcdc_display_notify;
a67472ad 2607
105784bb
LP		 2608 /* Validate the format. */
2609 format = sh_mobile_format_info(cfg->fourcc);
2610 if (format == NULL) {
2611 dev_err(priv->dev, "Invalid FOURCC %08x.\n", cfg->fourcc);
2612 return -EINVAL;
2613 }
2614
3ce05599
LP		 2615 /* Iterate through the modes to validate them and find the highest
2616 * resolution.
2617 */
2618 max_mode = NULL;
2619 max_size = 0;
2620
93ff2598 2621 for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
3ce05599
LP		 2622 unsigned int size = mode->yres * mode->xres;
2623
edd153a3
LP		 2624 /* NV12/NV21 buffers must have even number of lines */
2625 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
2626 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
0a7f17aa
LP		 2627 dev_err(priv->dev, "yres must be multiple of 2 for "
2628 "YCbCr420 mode.\n");
3ce05599
LP		 2629 return -EINVAL;
2630 }
2631
2632 if (size > max_size) {
2633 max_mode = mode;
2634 max_size = size;
2635 }
2636 }
2637
2638 if (!max_size)
2639 max_size = MAX_XRES * MAX_YRES;
2640 else
0a7f17aa 2641 dev_dbg(priv->dev, "Found largest videomode %ux%u\n",
3ce05599
LP		 2642 max_mode->xres, max_mode->yres);
2643
93ff2598 2644 if (cfg->lcd_modes == NULL) {
3ce05599 2645 mode = &default_720p;
93ff2598 2646 num_modes = 1;
3ce05599 2647 } else {
93ff2598
LP		 2648 mode = cfg->lcd_modes;
2649 num_modes = cfg->num_modes;
3ce05599
LP		 2650 }
2651
bd5f2c69
LP		 2652 /* Use the first mode as default. The default Y virtual resolution is
2653 * twice the panel size to allow for double-buffering.
2654 */
58f03d99
LP		 2655 ch->format = format;
2656 ch->xres = mode->xres;
2657 ch->xres_virtual = mode->xres;
2658 ch->yres = mode->yres;
2659 ch->yres_virtual = mode->yres * 2;
2660
2661 if (!format->yuv) {
2662 ch->colorspace = V4L2_COLORSPACE_SRGB;
16ca21c9 2663 ch->pitch = ch->xres_virtual * format->bpp / 8;
58f03d99
LP		 2664 } else {
2665 ch->colorspace = V4L2_COLORSPACE_REC709;
16ca21c9 2666 ch->pitch = ch->xres_virtual;
58f03d99
LP		 2667 }
2668
a67f379d
LP		 2669 ch->display.width = cfg->panel_cfg.width;
2670 ch->display.height = cfg->panel_cfg.height;
2671 ch->display.mode = *mode;
2672
2673 /* Allocate frame buffer memory. */
2674 ch->fb_size = max_size * format->bpp / 8 * 2;
2675 ch->fb_mem = dma_alloc_coherent(priv->dev, ch->fb_size, &ch->dma_handle,
2676 GFP_KERNEL);
2677 if (ch->fb_mem == NULL) {
2678 dev_err(priv->dev, "unable to allocate buffer\n");
2679 return -ENOMEM;
2680 }
3ce05599 2681
13f80eea
LP		 2682 /* Initialize the transmitter device if present. */
2683 if (cfg->tx_dev) {
2684 if (!cfg->tx_dev->dev.driver ||
2685 !try_module_get(cfg->tx_dev->dev.driver->owner)) {
2686 dev_warn(priv->dev,
2687 "unable to get transmitter device\n");
2688 return -EINVAL;
2689 }
2690 ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
2691 ch->tx_dev->lcdc = ch;
2692 ch->tx_dev->def_mode = *mode;
2693 }
2694
a67f379d 2695 return sh_mobile_lcdc_channel_fb_init(ch, mode, num_modes);
3ce05599
LP		 2696}
2697
2698static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
2699{
01ac25b5 2700 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 2701 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 2702 struct resource *res;
3ce05599 2703 int num_channels;
cfb4f5d1 2704 int error;
3ce05599 2705 int i;
cfb4f5d1 2706
01ac25b5 2707 if (!pdata) {
cfb4f5d1 2708 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 2709 return -EINVAL;
cfb4f5d1
MD		 2710 }
2711
2712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 2713 i = platform_get_irq(pdev, 0);
2714 if (!res || i < 0) {
2715 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 2716 return -ENOENT;
cfb4f5d1
MD		 2717 }
2718
2719 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2720 if (!priv) {
2721 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 2722 return -ENOMEM;
cfb4f5d1
MD		 2723 }
2724
4774c12a
LP		 2725 priv->dev = &pdev->dev;
2726 priv->meram_dev = pdata->meram_dev;
8bed9055
GL		 2727 platform_set_drvdata(pdev, priv);
2728
f8798ccb 2729 error = request_irq(i, sh_mobile_lcdc_irq, 0,
7ad33e74 2730 dev_name(&pdev->dev), priv);
8564557a
MD		 2731 if (error) {
2732 dev_err(&pdev->dev, "unable to request irq\n");
2733 goto err1;
2734 }
2735
2736 priv->irq = i;
5ef6b505 2737 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 2738
3ce05599
LP		 2739 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
2740 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 2741
01ac25b5 2742 ch->lcdc = priv;
b5ef967d 2743 ch->cfg = &pdata->ch[i];
cfb4f5d1 2744
01ac25b5 2745 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 2746 if (error) {
2747 dev_err(&pdev->dev, "unsupported interface type\n");
2748 goto err1;
2749 }
01ac25b5
GL		 2750 init_waitqueue_head(&ch->frame_end_wait);
2751 init_completion(&ch->vsync_completion);
cfb4f5d1 2752
3b0fd9d7 2753 /* probe the backlight is there is one defined */
b5ef967d 2754 if (ch->cfg->bl_info.max_brightness)
3b0fd9d7
AC		 2755 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
2756
cfb4f5d1
MD		 2757 switch (pdata->ch[i].chan) {
2758 case LCDC_CHAN_MAINLCD:
ce1c0b08 2759 ch->enabled = LDCNT2R_ME;
01ac25b5 2760 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 2761 num_channels++;
cfb4f5d1
MD		 2762 break;
2763 case LCDC_CHAN_SUBLCD:
ce1c0b08 2764 ch->enabled = LDCNT2R_SE;
01ac25b5 2765 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 2766 num_channels++;
cfb4f5d1
MD		 2767 break;
2768 }
2769 }
2770
3ce05599 2771 if (!num_channels) {
cfb4f5d1
MD		 2772 dev_err(&pdev->dev, "no channels defined\n");
2773 error = -EINVAL;
2774 goto err1;
2775 }
2776
edd153a3 2777 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 2778 if (num_channels == 2)
edd153a3 2779 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 2780
dba6f385
GL		 2781 priv->base = ioremap_nocache(res->start, resource_size(res));
2782 if (!priv->base)
2783 goto err1;
2784
0a7f17aa 2785 error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
cfb4f5d1
MD		 2786 if (error) {
2787 dev_err(&pdev->dev, "unable to setup clocks\n");
2788 goto err1;
2789 }
2790
4774c12a
LP		 2791 /* Enable runtime PM. */
2792 pm_runtime_enable(&pdev->dev);
7caa4342 2793
3ce05599 2794 for (i = 0; i < num_channels; i++) {
01ac25b5 2795 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76 2796
0a7f17aa 2797 error = sh_mobile_lcdc_channel_init(priv, ch);
cfb4f5d1 2798 if (error)
3ce05599 2799 goto err1;
cfb4f5d1
MD		 2800 }
2801
c5deac3c
LP		 2802 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2803 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2804
2805 ovl->cfg = &pdata->overlays[i];
2806 ovl->channel = &priv->ch[0];
2807
2808 error = sh_mobile_lcdc_overlay_init(priv, ovl);
2809 if (error)
2810 goto err1;
2811 }
2812
cfb4f5d1
MD		 2813 error = sh_mobile_lcdc_start(priv);
2814 if (error) {
2815 dev_err(&pdev->dev, "unable to start hardware\n");
2816 goto err1;
2817 }
2818
3ce05599 2819 for (i = 0; i < num_channels; i++) {
1c6a307a 2820 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1c6a307a 2821
a67f379d
LP		 2822 error = sh_mobile_lcdc_channel_fb_register(ch);
2823 if (error)
cfb4f5d1 2824 goto err1;
cfb4f5d1
MD		 2825 }
2826
c5deac3c
LP		 2827 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2828 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2829
2830 error = sh_mobile_lcdc_overlay_fb_register(ovl);
2831 if (error)
2832 goto err1;
2833 }
2834
6011bdea
GL		 2835 /* Failure ignored */
2836 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
2837 fb_register_client(&priv->notifier);
2838
cfb4f5d1 2839 return 0;
8bed9055 2840err1:
cfb4f5d1 2841 sh_mobile_lcdc_remove(pdev);
8bed9055 2842
cfb4f5d1
MD		 2843 return error;
2844}
2845
cfb4f5d1
MD		 2846static struct platform_driver sh_mobile_lcdc_driver = {
2847 .driver = {
2848 .name = "sh_mobile_lcdc_fb",
2849 .owner = THIS_MODULE,
2feb075a 2850 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 2851 },
2852 .probe = sh_mobile_lcdc_probe,
2853 .remove = sh_mobile_lcdc_remove,
2854};
2855
4277f2c4 2856module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 2857
2858MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
2859MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
2860MODULE_LICENSE("GPL v2");
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