]>
Commit | Line | Data |
---|---|---|
cfb4f5d1 MD |
1 | /* |
2 | * SuperH Mobile LCDC Framebuffer | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/fb.h> | |
16 | #include <linux/clk.h> | |
0246c471 | 17 | #include <linux/pm_runtime.h> |
cfb4f5d1 MD |
18 | #include <linux/platform_device.h> |
19 | #include <linux/dma-mapping.h> | |
8564557a | 20 | #include <linux/interrupt.h> |
1c6a307a | 21 | #include <linux/vmalloc.h> |
225c9a8d | 22 | #include <video/sh_mobile_lcdc.h> |
8564557a | 23 | #include <asm/atomic.h> |
cfb4f5d1 MD |
24 | |
25 | #define PALETTE_NR 16 | |
26 | ||
cfb4f5d1 MD |
27 | /* shared registers */ |
28 | #define _LDDCKR 0x410 | |
29 | #define _LDDCKSTPR 0x414 | |
30 | #define _LDINTR 0x468 | |
31 | #define _LDSR 0x46c | |
32 | #define _LDCNT1R 0x470 | |
33 | #define _LDCNT2R 0x474 | |
34 | #define _LDDDSR 0x47c | |
35 | #define _LDDWD0R 0x800 | |
36 | #define _LDDRDR 0x840 | |
37 | #define _LDDWAR 0x900 | |
38 | #define _LDDRAR 0x904 | |
39 | ||
0246c471 MD |
40 | /* shared registers and their order for context save/restore */ |
41 | static int lcdc_shared_regs[] = { | |
42 | _LDDCKR, | |
43 | _LDDCKSTPR, | |
44 | _LDINTR, | |
45 | _LDDDSR, | |
46 | _LDCNT1R, | |
47 | _LDCNT2R, | |
48 | }; | |
49 | #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs) | |
50 | ||
cfb4f5d1 MD |
51 | /* per-channel registers */ |
52 | enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R, | |
0246c471 MD |
53 | LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR, |
54 | NR_CH_REGS }; | |
cfb4f5d1 | 55 | |
0246c471 | 56 | static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
57 | [LDDCKPAT1R] = 0x400, |
58 | [LDDCKPAT2R] = 0x404, | |
59 | [LDMT1R] = 0x418, | |
60 | [LDMT2R] = 0x41c, | |
61 | [LDMT3R] = 0x420, | |
62 | [LDDFR] = 0x424, | |
63 | [LDSM1R] = 0x428, | |
8564557a | 64 | [LDSM2R] = 0x42c, |
cfb4f5d1 MD |
65 | [LDSA1R] = 0x430, |
66 | [LDMLSR] = 0x438, | |
67 | [LDHCNR] = 0x448, | |
68 | [LDHSYNR] = 0x44c, | |
69 | [LDVLNR] = 0x450, | |
70 | [LDVSYNR] = 0x454, | |
71 | [LDPMR] = 0x460, | |
72 | }; | |
73 | ||
0246c471 | 74 | static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
75 | [LDDCKPAT1R] = 0x408, |
76 | [LDDCKPAT2R] = 0x40c, | |
77 | [LDMT1R] = 0x600, | |
78 | [LDMT2R] = 0x604, | |
79 | [LDMT3R] = 0x608, | |
80 | [LDDFR] = 0x60c, | |
81 | [LDSM1R] = 0x610, | |
8564557a | 82 | [LDSM2R] = 0x614, |
cfb4f5d1 MD |
83 | [LDSA1R] = 0x618, |
84 | [LDMLSR] = 0x620, | |
85 | [LDHCNR] = 0x624, | |
86 | [LDHSYNR] = 0x628, | |
87 | [LDVLNR] = 0x62c, | |
88 | [LDVSYNR] = 0x630, | |
89 | [LDPMR] = 0x63c, | |
90 | }; | |
91 | ||
92 | #define START_LCDC 0x00000001 | |
93 | #define LCDC_RESET 0x00000100 | |
94 | #define DISPLAY_BEU 0x00000008 | |
95 | #define LCDC_ENABLE 0x00000001 | |
8564557a MD |
96 | #define LDINTR_FE 0x00000400 |
97 | #define LDINTR_FS 0x00000004 | |
cfb4f5d1 | 98 | |
0246c471 MD |
99 | struct sh_mobile_lcdc_priv; |
100 | struct sh_mobile_lcdc_chan { | |
101 | struct sh_mobile_lcdc_priv *lcdc; | |
102 | unsigned long *reg_offs; | |
103 | unsigned long ldmt1r_value; | |
104 | unsigned long enabled; /* ME and SE in LDCNT2R */ | |
105 | struct sh_mobile_lcdc_chan_cfg cfg; | |
106 | u32 pseudo_palette[PALETTE_NR]; | |
107 | unsigned long saved_ch_regs[NR_CH_REGS]; | |
108 | struct fb_info *info; | |
109 | dma_addr_t dma_handle; | |
110 | struct fb_deferred_io defio; | |
111 | struct scatterlist *sglist; | |
112 | unsigned long frame_end; | |
113 | wait_queue_head_t frame_end_wait; | |
114 | }; | |
115 | ||
116 | struct sh_mobile_lcdc_priv { | |
117 | void __iomem *base; | |
118 | int irq; | |
119 | atomic_t hw_usecnt; | |
120 | struct device *dev; | |
121 | struct clk *dot_clk; | |
122 | unsigned long lddckr; | |
123 | struct sh_mobile_lcdc_chan ch[2]; | |
124 | unsigned long saved_shared_regs[NR_SHARED_REGS]; | |
125 | int started; | |
126 | }; | |
127 | ||
cfb4f5d1 MD |
128 | static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan, |
129 | int reg_nr, unsigned long data) | |
130 | { | |
131 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); | |
132 | } | |
133 | ||
134 | static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan, | |
135 | int reg_nr) | |
136 | { | |
137 | return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); | |
138 | } | |
139 | ||
140 | static void lcdc_write(struct sh_mobile_lcdc_priv *priv, | |
141 | unsigned long reg_offs, unsigned long data) | |
142 | { | |
143 | iowrite32(data, priv->base + reg_offs); | |
144 | } | |
145 | ||
146 | static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv, | |
147 | unsigned long reg_offs) | |
148 | { | |
149 | return ioread32(priv->base + reg_offs); | |
150 | } | |
151 | ||
152 | static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv, | |
153 | unsigned long reg_offs, | |
154 | unsigned long mask, unsigned long until) | |
155 | { | |
156 | while ((lcdc_read(priv, reg_offs) & mask) != until) | |
157 | cpu_relax(); | |
158 | } | |
159 | ||
160 | static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan) | |
161 | { | |
162 | return chan->cfg.chan == LCDC_CHAN_SUBLCD; | |
163 | } | |
164 | ||
165 | static void lcdc_sys_write_index(void *handle, unsigned long data) | |
166 | { | |
167 | struct sh_mobile_lcdc_chan *ch = handle; | |
168 | ||
169 | lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000); | |
170 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
171 | lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
909f10de | 172 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 MD |
173 | } |
174 | ||
175 | static void lcdc_sys_write_data(void *handle, unsigned long data) | |
176 | { | |
177 | struct sh_mobile_lcdc_chan *ch = handle; | |
178 | ||
179 | lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000); | |
180 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
181 | lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
909f10de | 182 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 MD |
183 | } |
184 | ||
185 | static unsigned long lcdc_sys_read_data(void *handle) | |
186 | { | |
187 | struct sh_mobile_lcdc_chan *ch = handle; | |
188 | ||
189 | lcdc_write(ch->lcdc, _LDDRDR, 0x01000000); | |
190 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
191 | lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
192 | udelay(1); | |
909f10de | 193 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 | 194 | |
ec56b66f | 195 | return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff; |
cfb4f5d1 MD |
196 | } |
197 | ||
198 | struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = { | |
199 | lcdc_sys_write_index, | |
200 | lcdc_sys_write_data, | |
201 | lcdc_sys_read_data, | |
202 | }; | |
203 | ||
8564557a MD |
204 | static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) |
205 | { | |
0246c471 MD |
206 | if (atomic_inc_and_test(&priv->hw_usecnt)) { |
207 | pm_runtime_get_sync(priv->dev); | |
8564557a MD |
208 | if (priv->dot_clk) |
209 | clk_enable(priv->dot_clk); | |
210 | } | |
211 | } | |
212 | ||
213 | static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) | |
214 | { | |
0246c471 | 215 | if (atomic_sub_return(1, &priv->hw_usecnt) == -1) { |
8564557a MD |
216 | if (priv->dot_clk) |
217 | clk_disable(priv->dot_clk); | |
0246c471 | 218 | pm_runtime_put(priv->dev); |
8564557a MD |
219 | } |
220 | } | |
8564557a | 221 | |
1c6a307a PM |
222 | static int sh_mobile_lcdc_sginit(struct fb_info *info, |
223 | struct list_head *pagelist) | |
224 | { | |
225 | struct sh_mobile_lcdc_chan *ch = info->par; | |
226 | unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT; | |
227 | struct page *page; | |
228 | int nr_pages = 0; | |
229 | ||
230 | sg_init_table(ch->sglist, nr_pages_max); | |
231 | ||
232 | list_for_each_entry(page, pagelist, lru) | |
233 | sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0); | |
234 | ||
235 | return nr_pages; | |
236 | } | |
237 | ||
8564557a MD |
238 | static void sh_mobile_lcdc_deferred_io(struct fb_info *info, |
239 | struct list_head *pagelist) | |
240 | { | |
241 | struct sh_mobile_lcdc_chan *ch = info->par; | |
1c6a307a | 242 | unsigned int nr_pages; |
8564557a MD |
243 | |
244 | /* enable clocks before accessing hardware */ | |
245 | sh_mobile_lcdc_clk_on(ch->lcdc); | |
246 | ||
1c6a307a PM |
247 | nr_pages = sh_mobile_lcdc_sginit(info, pagelist); |
248 | dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
249 | ||
8564557a MD |
250 | /* trigger panel update */ |
251 | lcdc_write_chan(ch, LDSM2R, 1); | |
1c6a307a PM |
252 | |
253 | dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
8564557a MD |
254 | } |
255 | ||
256 | static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info) | |
257 | { | |
258 | struct fb_deferred_io *fbdefio = info->fbdefio; | |
259 | ||
260 | if (fbdefio) | |
261 | schedule_delayed_work(&info->deferred_work, fbdefio->delay); | |
262 | } | |
263 | ||
264 | static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data) | |
265 | { | |
266 | struct sh_mobile_lcdc_priv *priv = data; | |
2feb075a | 267 | struct sh_mobile_lcdc_chan *ch; |
8564557a | 268 | unsigned long tmp; |
2feb075a MD |
269 | int is_sub; |
270 | int k; | |
8564557a MD |
271 | |
272 | /* acknowledge interrupt */ | |
273 | tmp = lcdc_read(priv, _LDINTR); | |
274 | tmp &= 0xffffff00; /* mask in high 24 bits */ | |
275 | tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */ | |
276 | lcdc_write(priv, _LDINTR, tmp); | |
277 | ||
2feb075a MD |
278 | /* figure out if this interrupt is for main or sub lcd */ |
279 | is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0; | |
280 | ||
281 | /* wake up channel and disable clocks*/ | |
282 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
283 | ch = &priv->ch[k]; | |
284 | ||
285 | if (!ch->enabled) | |
286 | continue; | |
287 | ||
288 | if (is_sub == lcdc_chan_is_sublcd(ch)) { | |
289 | ch->frame_end = 1; | |
290 | wake_up(&ch->frame_end_wait); | |
291 | ||
292 | sh_mobile_lcdc_clk_off(priv); | |
293 | } | |
294 | } | |
295 | ||
8564557a MD |
296 | return IRQ_HANDLED; |
297 | } | |
298 | ||
cfb4f5d1 MD |
299 | static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv, |
300 | int start) | |
301 | { | |
302 | unsigned long tmp = lcdc_read(priv, _LDCNT2R); | |
303 | int k; | |
304 | ||
305 | /* start or stop the lcdc */ | |
306 | if (start) | |
307 | lcdc_write(priv, _LDCNT2R, tmp | START_LCDC); | |
308 | else | |
309 | lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC); | |
310 | ||
311 | /* wait until power is applied/stopped on all channels */ | |
312 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
313 | if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled) | |
314 | while (1) { | |
315 | tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3; | |
316 | if (start && tmp == 3) | |
317 | break; | |
318 | if (!start && tmp == 0) | |
319 | break; | |
320 | cpu_relax(); | |
321 | } | |
322 | ||
323 | if (!start) | |
324 | lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */ | |
325 | } | |
326 | ||
327 | static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) | |
328 | { | |
329 | struct sh_mobile_lcdc_chan *ch; | |
330 | struct fb_videomode *lcd_cfg; | |
331 | struct sh_mobile_lcdc_board_cfg *board_cfg; | |
332 | unsigned long tmp; | |
333 | int k, m; | |
334 | int ret = 0; | |
335 | ||
8564557a MD |
336 | /* enable clocks before accessing the hardware */ |
337 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
338 | if (priv->ch[k].enabled) | |
339 | sh_mobile_lcdc_clk_on(priv); | |
340 | ||
cfb4f5d1 MD |
341 | /* reset */ |
342 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET); | |
343 | lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0); | |
344 | ||
345 | /* enable LCDC channels */ | |
346 | tmp = lcdc_read(priv, _LDCNT2R); | |
347 | tmp |= priv->ch[0].enabled; | |
348 | tmp |= priv->ch[1].enabled; | |
349 | lcdc_write(priv, _LDCNT2R, tmp); | |
350 | ||
351 | /* read data from external memory, avoid using the BEU for now */ | |
352 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU); | |
353 | ||
354 | /* stop the lcdc first */ | |
355 | sh_mobile_lcdc_start_stop(priv, 0); | |
356 | ||
357 | /* configure clocks */ | |
358 | tmp = priv->lddckr; | |
359 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
360 | ch = &priv->ch[k]; | |
361 | ||
362 | if (!priv->ch[k].enabled) | |
363 | continue; | |
364 | ||
365 | m = ch->cfg.clock_divider; | |
366 | if (!m) | |
367 | continue; | |
368 | ||
369 | if (m == 1) | |
370 | m = 1 << 6; | |
371 | tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0); | |
372 | ||
373 | lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000); | |
374 | lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1); | |
375 | } | |
376 | ||
377 | lcdc_write(priv, _LDDCKR, tmp); | |
378 | ||
379 | /* start dotclock again */ | |
380 | lcdc_write(priv, _LDDCKSTPR, 0); | |
381 | lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0); | |
382 | ||
8564557a | 383 | /* interrupts are disabled to begin with */ |
cfb4f5d1 MD |
384 | lcdc_write(priv, _LDINTR, 0); |
385 | ||
386 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
387 | ch = &priv->ch[k]; | |
388 | lcd_cfg = &ch->cfg.lcd_cfg; | |
389 | ||
390 | if (!ch->enabled) | |
391 | continue; | |
392 | ||
393 | tmp = ch->ldmt1r_value; | |
394 | tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28; | |
395 | tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27; | |
f400f510 MD |
396 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0; |
397 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0; | |
398 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0; | |
399 | tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0; | |
400 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0; | |
cfb4f5d1 MD |
401 | lcdc_write_chan(ch, LDMT1R, tmp); |
402 | ||
403 | /* setup SYS bus */ | |
404 | lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r); | |
405 | lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r); | |
406 | ||
407 | /* horizontal configuration */ | |
408 | tmp = lcd_cfg->xres + lcd_cfg->hsync_len; | |
409 | tmp += lcd_cfg->left_margin; | |
410 | tmp += lcd_cfg->right_margin; | |
411 | tmp /= 8; /* HTCN */ | |
412 | tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */ | |
413 | lcdc_write_chan(ch, LDHCNR, tmp); | |
414 | ||
415 | tmp = lcd_cfg->xres; | |
416 | tmp += lcd_cfg->right_margin; | |
417 | tmp /= 8; /* HSYNP */ | |
418 | tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */ | |
419 | lcdc_write_chan(ch, LDHSYNR, tmp); | |
420 | ||
421 | /* power supply */ | |
422 | lcdc_write_chan(ch, LDPMR, 0); | |
423 | ||
424 | /* vertical configuration */ | |
425 | tmp = lcd_cfg->yres + lcd_cfg->vsync_len; | |
426 | tmp += lcd_cfg->upper_margin; | |
427 | tmp += lcd_cfg->lower_margin; /* VTLN */ | |
428 | tmp |= lcd_cfg->yres << 16; /* VDLN */ | |
429 | lcdc_write_chan(ch, LDVLNR, tmp); | |
430 | ||
431 | tmp = lcd_cfg->yres; | |
432 | tmp += lcd_cfg->lower_margin; /* VSYNP */ | |
433 | tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */ | |
434 | lcdc_write_chan(ch, LDVSYNR, tmp); | |
435 | ||
436 | board_cfg = &ch->cfg.board_cfg; | |
437 | if (board_cfg->setup_sys) | |
438 | ret = board_cfg->setup_sys(board_cfg->board_data, ch, | |
439 | &sh_mobile_lcdc_sys_bus_ops); | |
440 | if (ret) | |
441 | return ret; | |
442 | } | |
443 | ||
cfb4f5d1 MD |
444 | /* word and long word swap */ |
445 | lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6); | |
446 | ||
447 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
448 | ch = &priv->ch[k]; | |
449 | ||
450 | if (!priv->ch[k].enabled) | |
451 | continue; | |
452 | ||
453 | /* set bpp format in PKF[4:0] */ | |
454 | tmp = lcdc_read_chan(ch, LDDFR); | |
455 | tmp &= ~(0x0001001f); | |
e33afddc | 456 | tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0; |
cfb4f5d1 MD |
457 | lcdc_write_chan(ch, LDDFR, tmp); |
458 | ||
459 | /* point out our frame buffer */ | |
e33afddc | 460 | lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start); |
cfb4f5d1 MD |
461 | |
462 | /* set line size */ | |
e33afddc | 463 | lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length); |
cfb4f5d1 | 464 | |
8564557a MD |
465 | /* setup deferred io if SYS bus */ |
466 | tmp = ch->cfg.sys_bus_cfg.deferred_io_msec; | |
467 | if (ch->ldmt1r_value & (1 << 12) && tmp) { | |
468 | ch->defio.deferred_io = sh_mobile_lcdc_deferred_io; | |
469 | ch->defio.delay = msecs_to_jiffies(tmp); | |
e33afddc PM |
470 | ch->info->fbdefio = &ch->defio; |
471 | fb_deferred_io_init(ch->info); | |
8564557a MD |
472 | |
473 | /* one-shot mode */ | |
474 | lcdc_write_chan(ch, LDSM1R, 1); | |
475 | ||
476 | /* enable "Frame End Interrupt Enable" bit */ | |
477 | lcdc_write(priv, _LDINTR, LDINTR_FE); | |
478 | ||
479 | } else { | |
480 | /* continuous read mode */ | |
481 | lcdc_write_chan(ch, LDSM1R, 0); | |
482 | } | |
cfb4f5d1 MD |
483 | } |
484 | ||
485 | /* display output */ | |
486 | lcdc_write(priv, _LDCNT1R, LCDC_ENABLE); | |
487 | ||
488 | /* start the lcdc */ | |
489 | sh_mobile_lcdc_start_stop(priv, 1); | |
8e9bb19e | 490 | priv->started = 1; |
cfb4f5d1 MD |
491 | |
492 | /* tell the board code to enable the panel */ | |
493 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
494 | ch = &priv->ch[k]; | |
21bc1f02 MD |
495 | if (!ch->enabled) |
496 | continue; | |
497 | ||
cfb4f5d1 MD |
498 | board_cfg = &ch->cfg.board_cfg; |
499 | if (board_cfg->display_on) | |
500 | board_cfg->display_on(board_cfg->board_data); | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |
507 | { | |
508 | struct sh_mobile_lcdc_chan *ch; | |
509 | struct sh_mobile_lcdc_board_cfg *board_cfg; | |
510 | int k; | |
511 | ||
2feb075a | 512 | /* clean up deferred io and ask board code to disable panel */ |
cfb4f5d1 MD |
513 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
514 | ch = &priv->ch[k]; | |
21bc1f02 MD |
515 | if (!ch->enabled) |
516 | continue; | |
8564557a | 517 | |
2feb075a MD |
518 | /* deferred io mode: |
519 | * flush frame, and wait for frame end interrupt | |
520 | * clean up deferred io and enable clock | |
521 | */ | |
e33afddc | 522 | if (ch->info->fbdefio) { |
2feb075a | 523 | ch->frame_end = 0; |
e33afddc | 524 | schedule_delayed_work(&ch->info->deferred_work, 0); |
2feb075a | 525 | wait_event(ch->frame_end_wait, ch->frame_end); |
e33afddc PM |
526 | fb_deferred_io_cleanup(ch->info); |
527 | ch->info->fbdefio = NULL; | |
2feb075a | 528 | sh_mobile_lcdc_clk_on(priv); |
8564557a | 529 | } |
2feb075a MD |
530 | |
531 | board_cfg = &ch->cfg.board_cfg; | |
532 | if (board_cfg->display_off) | |
533 | board_cfg->display_off(board_cfg->board_data); | |
cfb4f5d1 MD |
534 | } |
535 | ||
536 | /* stop the lcdc */ | |
8e9bb19e MD |
537 | if (priv->started) { |
538 | sh_mobile_lcdc_start_stop(priv, 0); | |
539 | priv->started = 0; | |
540 | } | |
b51339ff | 541 | |
8564557a MD |
542 | /* stop clocks */ |
543 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
544 | if (priv->ch[k].enabled) | |
545 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
546 | } |
547 | ||
548 | static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch) | |
549 | { | |
550 | int ifm, miftyp; | |
551 | ||
552 | switch (ch->cfg.interface_type) { | |
553 | case RGB8: ifm = 0; miftyp = 0; break; | |
554 | case RGB9: ifm = 0; miftyp = 4; break; | |
555 | case RGB12A: ifm = 0; miftyp = 5; break; | |
556 | case RGB12B: ifm = 0; miftyp = 6; break; | |
557 | case RGB16: ifm = 0; miftyp = 7; break; | |
558 | case RGB18: ifm = 0; miftyp = 10; break; | |
559 | case RGB24: ifm = 0; miftyp = 11; break; | |
560 | case SYS8A: ifm = 1; miftyp = 0; break; | |
561 | case SYS8B: ifm = 1; miftyp = 1; break; | |
562 | case SYS8C: ifm = 1; miftyp = 2; break; | |
563 | case SYS8D: ifm = 1; miftyp = 3; break; | |
564 | case SYS9: ifm = 1; miftyp = 4; break; | |
565 | case SYS12: ifm = 1; miftyp = 5; break; | |
566 | case SYS16A: ifm = 1; miftyp = 7; break; | |
567 | case SYS16B: ifm = 1; miftyp = 8; break; | |
568 | case SYS16C: ifm = 1; miftyp = 9; break; | |
569 | case SYS18: ifm = 1; miftyp = 10; break; | |
570 | case SYS24: ifm = 1; miftyp = 11; break; | |
571 | default: goto bad; | |
572 | } | |
573 | ||
574 | /* SUBLCD only supports SYS interface */ | |
575 | if (lcdc_chan_is_sublcd(ch)) { | |
576 | if (ifm == 0) | |
577 | goto bad; | |
578 | else | |
579 | ifm = 0; | |
580 | } | |
581 | ||
582 | ch->ldmt1r_value = (ifm << 12) | miftyp; | |
583 | return 0; | |
584 | bad: | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
b51339ff MD |
588 | static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev, |
589 | int clock_source, | |
cfb4f5d1 MD |
590 | struct sh_mobile_lcdc_priv *priv) |
591 | { | |
592 | char *str; | |
593 | int icksel; | |
594 | ||
595 | switch (clock_source) { | |
596 | case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break; | |
597 | case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break; | |
598 | case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break; | |
599 | default: | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
603 | priv->lddckr = icksel << 16; | |
604 | ||
605 | if (str) { | |
b51339ff MD |
606 | priv->dot_clk = clk_get(&pdev->dev, str); |
607 | if (IS_ERR(priv->dot_clk)) { | |
608 | dev_err(&pdev->dev, "cannot get dot clock %s\n", str); | |
b51339ff | 609 | return PTR_ERR(priv->dot_clk); |
cfb4f5d1 | 610 | } |
cfb4f5d1 | 611 | } |
0246c471 MD |
612 | atomic_set(&priv->hw_usecnt, -1); |
613 | ||
614 | /* Runtime PM support involves two step for this driver: | |
615 | * 1) Enable Runtime PM | |
616 | * 2) Force Runtime PM Resume since hardware is accessed from probe() | |
617 | */ | |
618 | pm_runtime_enable(priv->dev); | |
619 | pm_runtime_resume(priv->dev); | |
cfb4f5d1 MD |
620 | return 0; |
621 | } | |
622 | ||
623 | static int sh_mobile_lcdc_setcolreg(u_int regno, | |
624 | u_int red, u_int green, u_int blue, | |
625 | u_int transp, struct fb_info *info) | |
626 | { | |
627 | u32 *palette = info->pseudo_palette; | |
628 | ||
629 | if (regno >= PALETTE_NR) | |
630 | return -EINVAL; | |
631 | ||
632 | /* only FB_VISUAL_TRUECOLOR supported */ | |
633 | ||
634 | red >>= 16 - info->var.red.length; | |
635 | green >>= 16 - info->var.green.length; | |
636 | blue >>= 16 - info->var.blue.length; | |
637 | transp >>= 16 - info->var.transp.length; | |
638 | ||
639 | palette[regno] = (red << info->var.red.offset) | | |
640 | (green << info->var.green.offset) | | |
641 | (blue << info->var.blue.offset) | | |
642 | (transp << info->var.transp.offset); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
647 | static struct fb_fix_screeninfo sh_mobile_lcdc_fix = { | |
648 | .id = "SH Mobile LCDC", | |
649 | .type = FB_TYPE_PACKED_PIXELS, | |
650 | .visual = FB_VISUAL_TRUECOLOR, | |
651 | .accel = FB_ACCEL_NONE, | |
652 | }; | |
653 | ||
8564557a MD |
654 | static void sh_mobile_lcdc_fillrect(struct fb_info *info, |
655 | const struct fb_fillrect *rect) | |
656 | { | |
657 | sys_fillrect(info, rect); | |
658 | sh_mobile_lcdc_deferred_io_touch(info); | |
659 | } | |
660 | ||
661 | static void sh_mobile_lcdc_copyarea(struct fb_info *info, | |
662 | const struct fb_copyarea *area) | |
663 | { | |
664 | sys_copyarea(info, area); | |
665 | sh_mobile_lcdc_deferred_io_touch(info); | |
666 | } | |
667 | ||
668 | static void sh_mobile_lcdc_imageblit(struct fb_info *info, | |
669 | const struct fb_image *image) | |
670 | { | |
671 | sys_imageblit(info, image); | |
672 | sh_mobile_lcdc_deferred_io_touch(info); | |
673 | } | |
674 | ||
cfb4f5d1 MD |
675 | static struct fb_ops sh_mobile_lcdc_ops = { |
676 | .fb_setcolreg = sh_mobile_lcdc_setcolreg, | |
2540c111 MD |
677 | .fb_read = fb_sys_read, |
678 | .fb_write = fb_sys_write, | |
8564557a MD |
679 | .fb_fillrect = sh_mobile_lcdc_fillrect, |
680 | .fb_copyarea = sh_mobile_lcdc_copyarea, | |
681 | .fb_imageblit = sh_mobile_lcdc_imageblit, | |
cfb4f5d1 MD |
682 | }; |
683 | ||
684 | static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp) | |
685 | { | |
686 | switch (bpp) { | |
687 | case 16: /* PKF[4:0] = 00011 - RGB 565 */ | |
688 | var->red.offset = 11; | |
689 | var->red.length = 5; | |
690 | var->green.offset = 5; | |
691 | var->green.length = 6; | |
692 | var->blue.offset = 0; | |
693 | var->blue.length = 5; | |
694 | var->transp.offset = 0; | |
695 | var->transp.length = 0; | |
696 | break; | |
697 | ||
698 | case 32: /* PKF[4:0] = 00000 - RGB 888 | |
699 | * sh7722 pdf says 00RRGGBB but reality is GGBB00RR | |
700 | * this may be because LDDDSR has word swap enabled.. | |
701 | */ | |
702 | var->red.offset = 0; | |
703 | var->red.length = 8; | |
704 | var->green.offset = 24; | |
705 | var->green.length = 8; | |
706 | var->blue.offset = 16; | |
707 | var->blue.length = 8; | |
708 | var->transp.offset = 0; | |
709 | var->transp.length = 0; | |
710 | break; | |
711 | default: | |
712 | return -EINVAL; | |
713 | } | |
714 | var->bits_per_pixel = bpp; | |
715 | var->red.msb_right = 0; | |
716 | var->green.msb_right = 0; | |
717 | var->blue.msb_right = 0; | |
718 | var->transp.msb_right = 0; | |
719 | return 0; | |
720 | } | |
721 | ||
2feb075a MD |
722 | static int sh_mobile_lcdc_suspend(struct device *dev) |
723 | { | |
724 | struct platform_device *pdev = to_platform_device(dev); | |
725 | ||
726 | sh_mobile_lcdc_stop(platform_get_drvdata(pdev)); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static int sh_mobile_lcdc_resume(struct device *dev) | |
731 | { | |
732 | struct platform_device *pdev = to_platform_device(dev); | |
733 | ||
734 | return sh_mobile_lcdc_start(platform_get_drvdata(pdev)); | |
735 | } | |
736 | ||
0246c471 MD |
737 | static int sh_mobile_lcdc_runtime_suspend(struct device *dev) |
738 | { | |
739 | struct platform_device *pdev = to_platform_device(dev); | |
740 | struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev); | |
741 | struct sh_mobile_lcdc_chan *ch; | |
742 | int k, n; | |
743 | ||
744 | /* save per-channel registers */ | |
745 | for (k = 0; k < ARRAY_SIZE(p->ch); k++) { | |
746 | ch = &p->ch[k]; | |
747 | if (!ch->enabled) | |
748 | continue; | |
749 | for (n = 0; n < NR_CH_REGS; n++) | |
750 | ch->saved_ch_regs[n] = lcdc_read_chan(ch, n); | |
751 | } | |
752 | ||
753 | /* save shared registers */ | |
754 | for (n = 0; n < NR_SHARED_REGS; n++) | |
755 | p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]); | |
756 | ||
757 | /* turn off LCDC hardware */ | |
758 | lcdc_write(p, _LDCNT1R, 0); | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static int sh_mobile_lcdc_runtime_resume(struct device *dev) | |
763 | { | |
764 | struct platform_device *pdev = to_platform_device(dev); | |
765 | struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev); | |
766 | struct sh_mobile_lcdc_chan *ch; | |
767 | int k, n; | |
768 | ||
769 | /* restore per-channel registers */ | |
770 | for (k = 0; k < ARRAY_SIZE(p->ch); k++) { | |
771 | ch = &p->ch[k]; | |
772 | if (!ch->enabled) | |
773 | continue; | |
774 | for (n = 0; n < NR_CH_REGS; n++) | |
775 | lcdc_write_chan(ch, n, ch->saved_ch_regs[n]); | |
776 | } | |
777 | ||
778 | /* restore shared registers */ | |
779 | for (n = 0; n < NR_SHARED_REGS; n++) | |
780 | lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
2feb075a MD |
785 | static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { |
786 | .suspend = sh_mobile_lcdc_suspend, | |
787 | .resume = sh_mobile_lcdc_resume, | |
0246c471 MD |
788 | .runtime_suspend = sh_mobile_lcdc_runtime_suspend, |
789 | .runtime_resume = sh_mobile_lcdc_runtime_resume, | |
2feb075a MD |
790 | }; |
791 | ||
cfb4f5d1 MD |
792 | static int sh_mobile_lcdc_remove(struct platform_device *pdev); |
793 | ||
794 | static int __init sh_mobile_lcdc_probe(struct platform_device *pdev) | |
795 | { | |
796 | struct fb_info *info; | |
797 | struct sh_mobile_lcdc_priv *priv; | |
798 | struct sh_mobile_lcdc_info *pdata; | |
799 | struct sh_mobile_lcdc_chan_cfg *cfg; | |
800 | struct resource *res; | |
801 | int error; | |
802 | void *buf; | |
803 | int i, j; | |
804 | ||
805 | if (!pdev->dev.platform_data) { | |
806 | dev_err(&pdev->dev, "no platform data defined\n"); | |
807 | error = -EINVAL; | |
808 | goto err0; | |
809 | } | |
810 | ||
811 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8564557a MD |
812 | i = platform_get_irq(pdev, 0); |
813 | if (!res || i < 0) { | |
814 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
cfb4f5d1 MD |
815 | error = -ENOENT; |
816 | goto err0; | |
817 | } | |
818 | ||
819 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
820 | if (!priv) { | |
821 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
822 | error = -ENOMEM; | |
823 | goto err0; | |
824 | } | |
825 | ||
8564557a | 826 | error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED, |
7ad33e74 | 827 | dev_name(&pdev->dev), priv); |
8564557a MD |
828 | if (error) { |
829 | dev_err(&pdev->dev, "unable to request irq\n"); | |
830 | goto err1; | |
831 | } | |
832 | ||
833 | priv->irq = i; | |
0246c471 | 834 | priv->dev = &pdev->dev; |
cfb4f5d1 MD |
835 | platform_set_drvdata(pdev, priv); |
836 | pdata = pdev->dev.platform_data; | |
837 | ||
838 | j = 0; | |
839 | for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) { | |
840 | priv->ch[j].lcdc = priv; | |
841 | memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i])); | |
842 | ||
843 | error = sh_mobile_lcdc_check_interface(&priv->ch[i]); | |
844 | if (error) { | |
845 | dev_err(&pdev->dev, "unsupported interface type\n"); | |
846 | goto err1; | |
847 | } | |
2feb075a | 848 | init_waitqueue_head(&priv->ch[i].frame_end_wait); |
cfb4f5d1 MD |
849 | |
850 | switch (pdata->ch[i].chan) { | |
851 | case LCDC_CHAN_MAINLCD: | |
852 | priv->ch[j].enabled = 1 << 1; | |
853 | priv->ch[j].reg_offs = lcdc_offs_mainlcd; | |
854 | j++; | |
855 | break; | |
856 | case LCDC_CHAN_SUBLCD: | |
857 | priv->ch[j].enabled = 1 << 2; | |
858 | priv->ch[j].reg_offs = lcdc_offs_sublcd; | |
859 | j++; | |
860 | break; | |
861 | } | |
862 | } | |
863 | ||
864 | if (!j) { | |
865 | dev_err(&pdev->dev, "no channels defined\n"); | |
866 | error = -EINVAL; | |
867 | goto err1; | |
868 | } | |
869 | ||
b51339ff | 870 | error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv); |
cfb4f5d1 MD |
871 | if (error) { |
872 | dev_err(&pdev->dev, "unable to setup clocks\n"); | |
873 | goto err1; | |
874 | } | |
875 | ||
cfb4f5d1 MD |
876 | priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1); |
877 | ||
878 | for (i = 0; i < j; i++) { | |
cfb4f5d1 MD |
879 | cfg = &priv->ch[i].cfg; |
880 | ||
e33afddc PM |
881 | priv->ch[i].info = framebuffer_alloc(0, &pdev->dev); |
882 | if (!priv->ch[i].info) { | |
883 | dev_err(&pdev->dev, "unable to allocate fb_info\n"); | |
884 | error = -ENOMEM; | |
885 | break; | |
886 | } | |
887 | ||
888 | info = priv->ch[i].info; | |
cfb4f5d1 MD |
889 | info->fbops = &sh_mobile_lcdc_ops; |
890 | info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres; | |
891 | info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres; | |
ce9c008c MD |
892 | info->var.width = cfg->lcd_size_cfg.width; |
893 | info->var.height = cfg->lcd_size_cfg.height; | |
cfb4f5d1 MD |
894 | info->var.activate = FB_ACTIVATE_NOW; |
895 | error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp); | |
896 | if (error) | |
897 | break; | |
898 | ||
899 | info->fix = sh_mobile_lcdc_fix; | |
900 | info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8); | |
901 | info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres; | |
902 | ||
903 | buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len, | |
904 | &priv->ch[i].dma_handle, GFP_KERNEL); | |
905 | if (!buf) { | |
906 | dev_err(&pdev->dev, "unable to allocate buffer\n"); | |
907 | error = -ENOMEM; | |
908 | break; | |
909 | } | |
910 | ||
911 | info->pseudo_palette = &priv->ch[i].pseudo_palette; | |
912 | info->flags = FBINFO_FLAG_DEFAULT; | |
913 | ||
914 | error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0); | |
915 | if (error < 0) { | |
916 | dev_err(&pdev->dev, "unable to allocate cmap\n"); | |
917 | dma_free_coherent(&pdev->dev, info->fix.smem_len, | |
918 | buf, priv->ch[i].dma_handle); | |
919 | break; | |
920 | } | |
921 | ||
922 | memset(buf, 0, info->fix.smem_len); | |
923 | info->fix.smem_start = priv->ch[i].dma_handle; | |
924 | info->screen_base = buf; | |
925 | info->device = &pdev->dev; | |
8564557a | 926 | info->par = &priv->ch[i]; |
cfb4f5d1 MD |
927 | } |
928 | ||
929 | if (error) | |
930 | goto err1; | |
931 | ||
932 | error = sh_mobile_lcdc_start(priv); | |
933 | if (error) { | |
934 | dev_err(&pdev->dev, "unable to start hardware\n"); | |
935 | goto err1; | |
936 | } | |
937 | ||
938 | for (i = 0; i < j; i++) { | |
1c6a307a PM |
939 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
940 | ||
e33afddc | 941 | info = ch->info; |
1c6a307a PM |
942 | |
943 | if (info->fbdefio) { | |
944 | priv->ch->sglist = vmalloc(sizeof(struct scatterlist) * | |
945 | info->fix.smem_len >> PAGE_SHIFT); | |
946 | if (!priv->ch->sglist) { | |
947 | dev_err(&pdev->dev, "cannot allocate sglist\n"); | |
948 | goto err1; | |
949 | } | |
950 | } | |
951 | ||
952 | error = register_framebuffer(info); | |
cfb4f5d1 MD |
953 | if (error < 0) |
954 | goto err1; | |
cfb4f5d1 | 955 | |
cfb4f5d1 MD |
956 | dev_info(info->dev, |
957 | "registered %s/%s as %dx%d %dbpp.\n", | |
958 | pdev->name, | |
1c6a307a | 959 | (ch->cfg.chan == LCDC_CHAN_MAINLCD) ? |
cfb4f5d1 | 960 | "mainlcd" : "sublcd", |
1c6a307a PM |
961 | (int) ch->cfg.lcd_cfg.xres, |
962 | (int) ch->cfg.lcd_cfg.yres, | |
963 | ch->cfg.bpp); | |
8564557a MD |
964 | |
965 | /* deferred io mode: disable clock to save power */ | |
966 | if (info->fbdefio) | |
967 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
968 | } |
969 | ||
970 | return 0; | |
971 | err1: | |
972 | sh_mobile_lcdc_remove(pdev); | |
973 | err0: | |
974 | return error; | |
975 | } | |
976 | ||
977 | static int sh_mobile_lcdc_remove(struct platform_device *pdev) | |
978 | { | |
979 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); | |
980 | struct fb_info *info; | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) | |
e33afddc PM |
984 | if (priv->ch[i].info->dev) |
985 | unregister_framebuffer(priv->ch[i].info); | |
cfb4f5d1 MD |
986 | |
987 | sh_mobile_lcdc_stop(priv); | |
988 | ||
989 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
e33afddc | 990 | info = priv->ch[i].info; |
cfb4f5d1 | 991 | |
e33afddc | 992 | if (!info || !info->device) |
cfb4f5d1 MD |
993 | continue; |
994 | ||
1c6a307a PM |
995 | if (priv->ch[i].sglist) |
996 | vfree(priv->ch[i].sglist); | |
997 | ||
cfb4f5d1 MD |
998 | dma_free_coherent(&pdev->dev, info->fix.smem_len, |
999 | info->screen_base, priv->ch[i].dma_handle); | |
1000 | fb_dealloc_cmap(&info->cmap); | |
e33afddc | 1001 | framebuffer_release(info); |
cfb4f5d1 MD |
1002 | } |
1003 | ||
b51339ff MD |
1004 | if (priv->dot_clk) |
1005 | clk_put(priv->dot_clk); | |
0246c471 MD |
1006 | |
1007 | pm_runtime_disable(priv->dev); | |
cfb4f5d1 MD |
1008 | |
1009 | if (priv->base) | |
1010 | iounmap(priv->base); | |
1011 | ||
8564557a MD |
1012 | if (priv->irq) |
1013 | free_irq(priv->irq, priv); | |
cfb4f5d1 MD |
1014 | kfree(priv); |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static struct platform_driver sh_mobile_lcdc_driver = { | |
1019 | .driver = { | |
1020 | .name = "sh_mobile_lcdc_fb", | |
1021 | .owner = THIS_MODULE, | |
2feb075a | 1022 | .pm = &sh_mobile_lcdc_dev_pm_ops, |
cfb4f5d1 MD |
1023 | }, |
1024 | .probe = sh_mobile_lcdc_probe, | |
1025 | .remove = sh_mobile_lcdc_remove, | |
1026 | }; | |
1027 | ||
1028 | static int __init sh_mobile_lcdc_init(void) | |
1029 | { | |
1030 | return platform_driver_register(&sh_mobile_lcdc_driver); | |
1031 | } | |
1032 | ||
1033 | static void __exit sh_mobile_lcdc_exit(void) | |
1034 | { | |
1035 | platform_driver_unregister(&sh_mobile_lcdc_driver); | |
1036 | } | |
1037 | ||
1038 | module_init(sh_mobile_lcdc_init); | |
1039 | module_exit(sh_mobile_lcdc_exit); | |
1040 | ||
1041 | MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver"); | |
1042 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); | |
1043 | MODULE_LICENSE("GPL v2"); |