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Commit | Line | Data |
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cfb4f5d1 MD |
1 | /* |
2 | * SuperH Mobile LCDC Framebuffer | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/fb.h> | |
16 | #include <linux/clk.h> | |
0246c471 | 17 | #include <linux/pm_runtime.h> |
cfb4f5d1 MD |
18 | #include <linux/platform_device.h> |
19 | #include <linux/dma-mapping.h> | |
8564557a | 20 | #include <linux/interrupt.h> |
1c6a307a | 21 | #include <linux/vmalloc.h> |
40331b21 | 22 | #include <linux/ioctl.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
225c9a8d | 24 | #include <video/sh_mobile_lcdc.h> |
8564557a | 25 | #include <asm/atomic.h> |
cfb4f5d1 MD |
26 | |
27 | #define PALETTE_NR 16 | |
a6f15ade PE |
28 | #define SIDE_B_OFFSET 0x1000 |
29 | #define MIRROR_OFFSET 0x2000 | |
cfb4f5d1 | 30 | |
cfb4f5d1 MD |
31 | /* shared registers */ |
32 | #define _LDDCKR 0x410 | |
33 | #define _LDDCKSTPR 0x414 | |
34 | #define _LDINTR 0x468 | |
35 | #define _LDSR 0x46c | |
36 | #define _LDCNT1R 0x470 | |
37 | #define _LDCNT2R 0x474 | |
9dd38819 | 38 | #define _LDRCNTR 0x478 |
cfb4f5d1 MD |
39 | #define _LDDDSR 0x47c |
40 | #define _LDDWD0R 0x800 | |
41 | #define _LDDRDR 0x840 | |
42 | #define _LDDWAR 0x900 | |
43 | #define _LDDRAR 0x904 | |
44 | ||
0246c471 MD |
45 | /* shared registers and their order for context save/restore */ |
46 | static int lcdc_shared_regs[] = { | |
47 | _LDDCKR, | |
48 | _LDDCKSTPR, | |
49 | _LDINTR, | |
50 | _LDDDSR, | |
51 | _LDCNT1R, | |
52 | _LDCNT2R, | |
53 | }; | |
54 | #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs) | |
55 | ||
cfb4f5d1 MD |
56 | /* per-channel registers */ |
57 | enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R, | |
0246c471 MD |
58 | LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR, |
59 | NR_CH_REGS }; | |
cfb4f5d1 | 60 | |
0246c471 | 61 | static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
62 | [LDDCKPAT1R] = 0x400, |
63 | [LDDCKPAT2R] = 0x404, | |
64 | [LDMT1R] = 0x418, | |
65 | [LDMT2R] = 0x41c, | |
66 | [LDMT3R] = 0x420, | |
67 | [LDDFR] = 0x424, | |
68 | [LDSM1R] = 0x428, | |
8564557a | 69 | [LDSM2R] = 0x42c, |
cfb4f5d1 MD |
70 | [LDSA1R] = 0x430, |
71 | [LDMLSR] = 0x438, | |
72 | [LDHCNR] = 0x448, | |
73 | [LDHSYNR] = 0x44c, | |
74 | [LDVLNR] = 0x450, | |
75 | [LDVSYNR] = 0x454, | |
76 | [LDPMR] = 0x460, | |
77 | }; | |
78 | ||
0246c471 | 79 | static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = { |
cfb4f5d1 MD |
80 | [LDDCKPAT1R] = 0x408, |
81 | [LDDCKPAT2R] = 0x40c, | |
82 | [LDMT1R] = 0x600, | |
83 | [LDMT2R] = 0x604, | |
84 | [LDMT3R] = 0x608, | |
85 | [LDDFR] = 0x60c, | |
86 | [LDSM1R] = 0x610, | |
8564557a | 87 | [LDSM2R] = 0x614, |
cfb4f5d1 MD |
88 | [LDSA1R] = 0x618, |
89 | [LDMLSR] = 0x620, | |
90 | [LDHCNR] = 0x624, | |
91 | [LDHSYNR] = 0x628, | |
92 | [LDVLNR] = 0x62c, | |
93 | [LDVSYNR] = 0x630, | |
94 | [LDPMR] = 0x63c, | |
95 | }; | |
96 | ||
97 | #define START_LCDC 0x00000001 | |
98 | #define LCDC_RESET 0x00000100 | |
99 | #define DISPLAY_BEU 0x00000008 | |
100 | #define LCDC_ENABLE 0x00000001 | |
8564557a | 101 | #define LDINTR_FE 0x00000400 |
9dd38819 PE |
102 | #define LDINTR_VSE 0x00000200 |
103 | #define LDINTR_VEE 0x00000100 | |
8564557a | 104 | #define LDINTR_FS 0x00000004 |
9dd38819 PE |
105 | #define LDINTR_VSS 0x00000002 |
106 | #define LDINTR_VES 0x00000001 | |
a6f15ade PE |
107 | #define LDRCNTR_SRS 0x00020000 |
108 | #define LDRCNTR_SRC 0x00010000 | |
109 | #define LDRCNTR_MRS 0x00000002 | |
110 | #define LDRCNTR_MRC 0x00000001 | |
40331b21 | 111 | #define LDSR_MRS 0x00000100 |
cfb4f5d1 | 112 | |
0246c471 MD |
113 | struct sh_mobile_lcdc_priv; |
114 | struct sh_mobile_lcdc_chan { | |
115 | struct sh_mobile_lcdc_priv *lcdc; | |
116 | unsigned long *reg_offs; | |
117 | unsigned long ldmt1r_value; | |
118 | unsigned long enabled; /* ME and SE in LDCNT2R */ | |
119 | struct sh_mobile_lcdc_chan_cfg cfg; | |
120 | u32 pseudo_palette[PALETTE_NR]; | |
121 | unsigned long saved_ch_regs[NR_CH_REGS]; | |
122 | struct fb_info *info; | |
123 | dma_addr_t dma_handle; | |
124 | struct fb_deferred_io defio; | |
125 | struct scatterlist *sglist; | |
126 | unsigned long frame_end; | |
9dd38819 | 127 | unsigned long pan_offset; |
0246c471 | 128 | wait_queue_head_t frame_end_wait; |
40331b21 | 129 | struct completion vsync_completion; |
0246c471 MD |
130 | }; |
131 | ||
132 | struct sh_mobile_lcdc_priv { | |
133 | void __iomem *base; | |
134 | int irq; | |
135 | atomic_t hw_usecnt; | |
136 | struct device *dev; | |
137 | struct clk *dot_clk; | |
138 | unsigned long lddckr; | |
139 | struct sh_mobile_lcdc_chan ch[2]; | |
140 | unsigned long saved_shared_regs[NR_SHARED_REGS]; | |
141 | int started; | |
142 | }; | |
143 | ||
a6f15ade PE |
144 | static bool banked(int reg_nr) |
145 | { | |
146 | switch (reg_nr) { | |
147 | case LDMT1R: | |
148 | case LDMT2R: | |
149 | case LDMT3R: | |
150 | case LDDFR: | |
151 | case LDSM1R: | |
152 | case LDSA1R: | |
153 | case LDMLSR: | |
154 | case LDHCNR: | |
155 | case LDHSYNR: | |
156 | case LDVLNR: | |
157 | case LDVSYNR: | |
158 | return true; | |
159 | } | |
160 | return false; | |
161 | } | |
162 | ||
cfb4f5d1 MD |
163 | static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan, |
164 | int reg_nr, unsigned long data) | |
165 | { | |
166 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); | |
a6f15ade PE |
167 | if (banked(reg_nr)) |
168 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
169 | SIDE_B_OFFSET); | |
170 | } | |
171 | ||
172 | static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan, | |
173 | int reg_nr, unsigned long data) | |
174 | { | |
175 | iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + | |
176 | MIRROR_OFFSET); | |
cfb4f5d1 MD |
177 | } |
178 | ||
179 | static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan, | |
180 | int reg_nr) | |
181 | { | |
182 | return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); | |
183 | } | |
184 | ||
185 | static void lcdc_write(struct sh_mobile_lcdc_priv *priv, | |
186 | unsigned long reg_offs, unsigned long data) | |
187 | { | |
188 | iowrite32(data, priv->base + reg_offs); | |
189 | } | |
190 | ||
191 | static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv, | |
192 | unsigned long reg_offs) | |
193 | { | |
194 | return ioread32(priv->base + reg_offs); | |
195 | } | |
196 | ||
197 | static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv, | |
198 | unsigned long reg_offs, | |
199 | unsigned long mask, unsigned long until) | |
200 | { | |
201 | while ((lcdc_read(priv, reg_offs) & mask) != until) | |
202 | cpu_relax(); | |
203 | } | |
204 | ||
205 | static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan) | |
206 | { | |
207 | return chan->cfg.chan == LCDC_CHAN_SUBLCD; | |
208 | } | |
209 | ||
210 | static void lcdc_sys_write_index(void *handle, unsigned long data) | |
211 | { | |
212 | struct sh_mobile_lcdc_chan *ch = handle; | |
213 | ||
214 | lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000); | |
215 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
216 | lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
909f10de | 217 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 MD |
218 | } |
219 | ||
220 | static void lcdc_sys_write_data(void *handle, unsigned long data) | |
221 | { | |
222 | struct sh_mobile_lcdc_chan *ch = handle; | |
223 | ||
224 | lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000); | |
225 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
226 | lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
909f10de | 227 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 MD |
228 | } |
229 | ||
230 | static unsigned long lcdc_sys_read_data(void *handle) | |
231 | { | |
232 | struct sh_mobile_lcdc_chan *ch = handle; | |
233 | ||
234 | lcdc_write(ch->lcdc, _LDDRDR, 0x01000000); | |
235 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); | |
236 | lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0)); | |
237 | udelay(1); | |
909f10de | 238 | lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0); |
cfb4f5d1 | 239 | |
ec56b66f | 240 | return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff; |
cfb4f5d1 MD |
241 | } |
242 | ||
243 | struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = { | |
244 | lcdc_sys_write_index, | |
245 | lcdc_sys_write_data, | |
246 | lcdc_sys_read_data, | |
247 | }; | |
248 | ||
8564557a MD |
249 | static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) |
250 | { | |
0246c471 MD |
251 | if (atomic_inc_and_test(&priv->hw_usecnt)) { |
252 | pm_runtime_get_sync(priv->dev); | |
8564557a MD |
253 | if (priv->dot_clk) |
254 | clk_enable(priv->dot_clk); | |
255 | } | |
256 | } | |
257 | ||
258 | static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) | |
259 | { | |
0246c471 | 260 | if (atomic_sub_return(1, &priv->hw_usecnt) == -1) { |
8564557a MD |
261 | if (priv->dot_clk) |
262 | clk_disable(priv->dot_clk); | |
0246c471 | 263 | pm_runtime_put(priv->dev); |
8564557a MD |
264 | } |
265 | } | |
8564557a | 266 | |
1c6a307a PM |
267 | static int sh_mobile_lcdc_sginit(struct fb_info *info, |
268 | struct list_head *pagelist) | |
269 | { | |
270 | struct sh_mobile_lcdc_chan *ch = info->par; | |
271 | unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT; | |
272 | struct page *page; | |
273 | int nr_pages = 0; | |
274 | ||
275 | sg_init_table(ch->sglist, nr_pages_max); | |
276 | ||
277 | list_for_each_entry(page, pagelist, lru) | |
278 | sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0); | |
279 | ||
280 | return nr_pages; | |
281 | } | |
282 | ||
8564557a MD |
283 | static void sh_mobile_lcdc_deferred_io(struct fb_info *info, |
284 | struct list_head *pagelist) | |
285 | { | |
286 | struct sh_mobile_lcdc_chan *ch = info->par; | |
ef61aae4 | 287 | struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg; |
8564557a MD |
288 | |
289 | /* enable clocks before accessing hardware */ | |
290 | sh_mobile_lcdc_clk_on(ch->lcdc); | |
291 | ||
5c1a56b5 PM |
292 | /* |
293 | * It's possible to get here without anything on the pagelist via | |
294 | * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync() | |
295 | * invocation. In the former case, the acceleration routines are | |
296 | * stepped in to when using the framebuffer console causing the | |
297 | * workqueue to be scheduled without any dirty pages on the list. | |
298 | * | |
299 | * Despite this, a panel update is still needed given that the | |
300 | * acceleration routines have their own methods for writing in | |
301 | * that still need to be updated. | |
302 | * | |
303 | * The fsync() and empty pagelist case could be optimized for, | |
304 | * but we don't bother, as any application exhibiting such | |
305 | * behaviour is fundamentally broken anyways. | |
306 | */ | |
307 | if (!list_empty(pagelist)) { | |
308 | unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist); | |
309 | ||
310 | /* trigger panel update */ | |
311 | dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
ef61aae4 MD |
312 | if (bcfg->start_transfer) |
313 | bcfg->start_transfer(bcfg->board_data, ch, | |
314 | &sh_mobile_lcdc_sys_bus_ops); | |
5c1a56b5 PM |
315 | lcdc_write_chan(ch, LDSM2R, 1); |
316 | dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); | |
ef61aae4 MD |
317 | } else { |
318 | if (bcfg->start_transfer) | |
319 | bcfg->start_transfer(bcfg->board_data, ch, | |
320 | &sh_mobile_lcdc_sys_bus_ops); | |
5c1a56b5 | 321 | lcdc_write_chan(ch, LDSM2R, 1); |
ef61aae4 | 322 | } |
8564557a MD |
323 | } |
324 | ||
325 | static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info) | |
326 | { | |
327 | struct fb_deferred_io *fbdefio = info->fbdefio; | |
328 | ||
329 | if (fbdefio) | |
330 | schedule_delayed_work(&info->deferred_work, fbdefio->delay); | |
331 | } | |
332 | ||
333 | static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data) | |
334 | { | |
335 | struct sh_mobile_lcdc_priv *priv = data; | |
2feb075a | 336 | struct sh_mobile_lcdc_chan *ch; |
8564557a | 337 | unsigned long tmp; |
9dd38819 | 338 | unsigned long ldintr; |
2feb075a MD |
339 | int is_sub; |
340 | int k; | |
8564557a MD |
341 | |
342 | /* acknowledge interrupt */ | |
9dd38819 PE |
343 | ldintr = tmp = lcdc_read(priv, _LDINTR); |
344 | /* | |
345 | * disable further VSYNC End IRQs, preserve all other enabled IRQs, | |
346 | * write 0 to bits 0-6 to ack all triggered IRQs. | |
347 | */ | |
348 | tmp &= 0xffffff00 & ~LDINTR_VEE; | |
8564557a MD |
349 | lcdc_write(priv, _LDINTR, tmp); |
350 | ||
2feb075a MD |
351 | /* figure out if this interrupt is for main or sub lcd */ |
352 | is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0; | |
353 | ||
9dd38819 | 354 | /* wake up channel and disable clocks */ |
2feb075a MD |
355 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
356 | ch = &priv->ch[k]; | |
357 | ||
358 | if (!ch->enabled) | |
359 | continue; | |
360 | ||
9dd38819 PE |
361 | /* Frame Start */ |
362 | if (ldintr & LDINTR_FS) { | |
363 | if (is_sub == lcdc_chan_is_sublcd(ch)) { | |
364 | ch->frame_end = 1; | |
365 | wake_up(&ch->frame_end_wait); | |
2feb075a | 366 | |
9dd38819 PE |
367 | sh_mobile_lcdc_clk_off(priv); |
368 | } | |
369 | } | |
370 | ||
371 | /* VSYNC End */ | |
40331b21 PE |
372 | if (ldintr & LDINTR_VES) |
373 | complete(&ch->vsync_completion); | |
2feb075a MD |
374 | } |
375 | ||
8564557a MD |
376 | return IRQ_HANDLED; |
377 | } | |
378 | ||
cfb4f5d1 MD |
379 | static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv, |
380 | int start) | |
381 | { | |
382 | unsigned long tmp = lcdc_read(priv, _LDCNT2R); | |
383 | int k; | |
384 | ||
385 | /* start or stop the lcdc */ | |
386 | if (start) | |
387 | lcdc_write(priv, _LDCNT2R, tmp | START_LCDC); | |
388 | else | |
389 | lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC); | |
390 | ||
391 | /* wait until power is applied/stopped on all channels */ | |
392 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
393 | if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled) | |
394 | while (1) { | |
395 | tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3; | |
396 | if (start && tmp == 3) | |
397 | break; | |
398 | if (!start && tmp == 0) | |
399 | break; | |
400 | cpu_relax(); | |
401 | } | |
402 | ||
403 | if (!start) | |
404 | lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */ | |
405 | } | |
406 | ||
407 | static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv) | |
408 | { | |
409 | struct sh_mobile_lcdc_chan *ch; | |
410 | struct fb_videomode *lcd_cfg; | |
411 | struct sh_mobile_lcdc_board_cfg *board_cfg; | |
412 | unsigned long tmp; | |
413 | int k, m; | |
414 | int ret = 0; | |
415 | ||
8564557a MD |
416 | /* enable clocks before accessing the hardware */ |
417 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
418 | if (priv->ch[k].enabled) | |
419 | sh_mobile_lcdc_clk_on(priv); | |
420 | ||
cfb4f5d1 MD |
421 | /* reset */ |
422 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET); | |
423 | lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0); | |
424 | ||
425 | /* enable LCDC channels */ | |
426 | tmp = lcdc_read(priv, _LDCNT2R); | |
427 | tmp |= priv->ch[0].enabled; | |
428 | tmp |= priv->ch[1].enabled; | |
429 | lcdc_write(priv, _LDCNT2R, tmp); | |
430 | ||
431 | /* read data from external memory, avoid using the BEU for now */ | |
432 | lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU); | |
433 | ||
434 | /* stop the lcdc first */ | |
435 | sh_mobile_lcdc_start_stop(priv, 0); | |
436 | ||
437 | /* configure clocks */ | |
438 | tmp = priv->lddckr; | |
439 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
440 | ch = &priv->ch[k]; | |
441 | ||
442 | if (!priv->ch[k].enabled) | |
443 | continue; | |
444 | ||
445 | m = ch->cfg.clock_divider; | |
446 | if (!m) | |
447 | continue; | |
448 | ||
449 | if (m == 1) | |
450 | m = 1 << 6; | |
451 | tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0); | |
452 | ||
453 | lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000); | |
454 | lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1); | |
455 | } | |
456 | ||
457 | lcdc_write(priv, _LDDCKR, tmp); | |
458 | ||
459 | /* start dotclock again */ | |
460 | lcdc_write(priv, _LDDCKSTPR, 0); | |
461 | lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0); | |
462 | ||
8564557a | 463 | /* interrupts are disabled to begin with */ |
cfb4f5d1 MD |
464 | lcdc_write(priv, _LDINTR, 0); |
465 | ||
466 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
467 | ch = &priv->ch[k]; | |
468 | lcd_cfg = &ch->cfg.lcd_cfg; | |
469 | ||
470 | if (!ch->enabled) | |
471 | continue; | |
472 | ||
473 | tmp = ch->ldmt1r_value; | |
474 | tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28; | |
475 | tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27; | |
f400f510 MD |
476 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0; |
477 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0; | |
478 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0; | |
479 | tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0; | |
480 | tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0; | |
cfb4f5d1 MD |
481 | lcdc_write_chan(ch, LDMT1R, tmp); |
482 | ||
483 | /* setup SYS bus */ | |
484 | lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r); | |
485 | lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r); | |
486 | ||
487 | /* horizontal configuration */ | |
488 | tmp = lcd_cfg->xres + lcd_cfg->hsync_len; | |
489 | tmp += lcd_cfg->left_margin; | |
490 | tmp += lcd_cfg->right_margin; | |
491 | tmp /= 8; /* HTCN */ | |
492 | tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */ | |
493 | lcdc_write_chan(ch, LDHCNR, tmp); | |
494 | ||
495 | tmp = lcd_cfg->xres; | |
496 | tmp += lcd_cfg->right_margin; | |
497 | tmp /= 8; /* HSYNP */ | |
498 | tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */ | |
499 | lcdc_write_chan(ch, LDHSYNR, tmp); | |
500 | ||
501 | /* power supply */ | |
502 | lcdc_write_chan(ch, LDPMR, 0); | |
503 | ||
504 | /* vertical configuration */ | |
505 | tmp = lcd_cfg->yres + lcd_cfg->vsync_len; | |
506 | tmp += lcd_cfg->upper_margin; | |
507 | tmp += lcd_cfg->lower_margin; /* VTLN */ | |
508 | tmp |= lcd_cfg->yres << 16; /* VDLN */ | |
509 | lcdc_write_chan(ch, LDVLNR, tmp); | |
510 | ||
511 | tmp = lcd_cfg->yres; | |
512 | tmp += lcd_cfg->lower_margin; /* VSYNP */ | |
513 | tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */ | |
514 | lcdc_write_chan(ch, LDVSYNR, tmp); | |
515 | ||
516 | board_cfg = &ch->cfg.board_cfg; | |
517 | if (board_cfg->setup_sys) | |
518 | ret = board_cfg->setup_sys(board_cfg->board_data, ch, | |
519 | &sh_mobile_lcdc_sys_bus_ops); | |
520 | if (ret) | |
521 | return ret; | |
522 | } | |
523 | ||
cfb4f5d1 MD |
524 | /* word and long word swap */ |
525 | lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6); | |
526 | ||
527 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
528 | ch = &priv->ch[k]; | |
529 | ||
530 | if (!priv->ch[k].enabled) | |
531 | continue; | |
532 | ||
533 | /* set bpp format in PKF[4:0] */ | |
534 | tmp = lcdc_read_chan(ch, LDDFR); | |
535 | tmp &= ~(0x0001001f); | |
e33afddc | 536 | tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0; |
cfb4f5d1 MD |
537 | lcdc_write_chan(ch, LDDFR, tmp); |
538 | ||
539 | /* point out our frame buffer */ | |
e33afddc | 540 | lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start); |
cfb4f5d1 MD |
541 | |
542 | /* set line size */ | |
e33afddc | 543 | lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length); |
cfb4f5d1 | 544 | |
8564557a MD |
545 | /* setup deferred io if SYS bus */ |
546 | tmp = ch->cfg.sys_bus_cfg.deferred_io_msec; | |
547 | if (ch->ldmt1r_value & (1 << 12) && tmp) { | |
548 | ch->defio.deferred_io = sh_mobile_lcdc_deferred_io; | |
549 | ch->defio.delay = msecs_to_jiffies(tmp); | |
e33afddc PM |
550 | ch->info->fbdefio = &ch->defio; |
551 | fb_deferred_io_init(ch->info); | |
8564557a MD |
552 | |
553 | /* one-shot mode */ | |
554 | lcdc_write_chan(ch, LDSM1R, 1); | |
555 | ||
556 | /* enable "Frame End Interrupt Enable" bit */ | |
557 | lcdc_write(priv, _LDINTR, LDINTR_FE); | |
558 | ||
559 | } else { | |
560 | /* continuous read mode */ | |
561 | lcdc_write_chan(ch, LDSM1R, 0); | |
562 | } | |
cfb4f5d1 MD |
563 | } |
564 | ||
565 | /* display output */ | |
566 | lcdc_write(priv, _LDCNT1R, LCDC_ENABLE); | |
567 | ||
568 | /* start the lcdc */ | |
569 | sh_mobile_lcdc_start_stop(priv, 1); | |
8e9bb19e | 570 | priv->started = 1; |
cfb4f5d1 MD |
571 | |
572 | /* tell the board code to enable the panel */ | |
573 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { | |
574 | ch = &priv->ch[k]; | |
21bc1f02 MD |
575 | if (!ch->enabled) |
576 | continue; | |
577 | ||
cfb4f5d1 MD |
578 | board_cfg = &ch->cfg.board_cfg; |
579 | if (board_cfg->display_on) | |
580 | board_cfg->display_on(board_cfg->board_data); | |
581 | } | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |
587 | { | |
588 | struct sh_mobile_lcdc_chan *ch; | |
589 | struct sh_mobile_lcdc_board_cfg *board_cfg; | |
590 | int k; | |
591 | ||
2feb075a | 592 | /* clean up deferred io and ask board code to disable panel */ |
cfb4f5d1 MD |
593 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { |
594 | ch = &priv->ch[k]; | |
21bc1f02 MD |
595 | if (!ch->enabled) |
596 | continue; | |
8564557a | 597 | |
2feb075a MD |
598 | /* deferred io mode: |
599 | * flush frame, and wait for frame end interrupt | |
600 | * clean up deferred io and enable clock | |
601 | */ | |
e33afddc | 602 | if (ch->info->fbdefio) { |
2feb075a | 603 | ch->frame_end = 0; |
e33afddc | 604 | schedule_delayed_work(&ch->info->deferred_work, 0); |
2feb075a | 605 | wait_event(ch->frame_end_wait, ch->frame_end); |
e33afddc PM |
606 | fb_deferred_io_cleanup(ch->info); |
607 | ch->info->fbdefio = NULL; | |
2feb075a | 608 | sh_mobile_lcdc_clk_on(priv); |
8564557a | 609 | } |
2feb075a MD |
610 | |
611 | board_cfg = &ch->cfg.board_cfg; | |
612 | if (board_cfg->display_off) | |
613 | board_cfg->display_off(board_cfg->board_data); | |
cfb4f5d1 MD |
614 | } |
615 | ||
616 | /* stop the lcdc */ | |
8e9bb19e MD |
617 | if (priv->started) { |
618 | sh_mobile_lcdc_start_stop(priv, 0); | |
619 | priv->started = 0; | |
620 | } | |
b51339ff | 621 | |
8564557a MD |
622 | /* stop clocks */ |
623 | for (k = 0; k < ARRAY_SIZE(priv->ch); k++) | |
624 | if (priv->ch[k].enabled) | |
625 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
626 | } |
627 | ||
628 | static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch) | |
629 | { | |
630 | int ifm, miftyp; | |
631 | ||
632 | switch (ch->cfg.interface_type) { | |
633 | case RGB8: ifm = 0; miftyp = 0; break; | |
634 | case RGB9: ifm = 0; miftyp = 4; break; | |
635 | case RGB12A: ifm = 0; miftyp = 5; break; | |
636 | case RGB12B: ifm = 0; miftyp = 6; break; | |
637 | case RGB16: ifm = 0; miftyp = 7; break; | |
638 | case RGB18: ifm = 0; miftyp = 10; break; | |
639 | case RGB24: ifm = 0; miftyp = 11; break; | |
640 | case SYS8A: ifm = 1; miftyp = 0; break; | |
641 | case SYS8B: ifm = 1; miftyp = 1; break; | |
642 | case SYS8C: ifm = 1; miftyp = 2; break; | |
643 | case SYS8D: ifm = 1; miftyp = 3; break; | |
644 | case SYS9: ifm = 1; miftyp = 4; break; | |
645 | case SYS12: ifm = 1; miftyp = 5; break; | |
646 | case SYS16A: ifm = 1; miftyp = 7; break; | |
647 | case SYS16B: ifm = 1; miftyp = 8; break; | |
648 | case SYS16C: ifm = 1; miftyp = 9; break; | |
649 | case SYS18: ifm = 1; miftyp = 10; break; | |
650 | case SYS24: ifm = 1; miftyp = 11; break; | |
651 | default: goto bad; | |
652 | } | |
653 | ||
654 | /* SUBLCD only supports SYS interface */ | |
655 | if (lcdc_chan_is_sublcd(ch)) { | |
656 | if (ifm == 0) | |
657 | goto bad; | |
658 | else | |
659 | ifm = 0; | |
660 | } | |
661 | ||
662 | ch->ldmt1r_value = (ifm << 12) | miftyp; | |
663 | return 0; | |
664 | bad: | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
b51339ff MD |
668 | static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev, |
669 | int clock_source, | |
cfb4f5d1 MD |
670 | struct sh_mobile_lcdc_priv *priv) |
671 | { | |
672 | char *str; | |
673 | int icksel; | |
674 | ||
675 | switch (clock_source) { | |
676 | case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break; | |
677 | case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break; | |
678 | case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break; | |
679 | default: | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | priv->lddckr = icksel << 16; | |
684 | ||
685 | if (str) { | |
b51339ff MD |
686 | priv->dot_clk = clk_get(&pdev->dev, str); |
687 | if (IS_ERR(priv->dot_clk)) { | |
688 | dev_err(&pdev->dev, "cannot get dot clock %s\n", str); | |
b51339ff | 689 | return PTR_ERR(priv->dot_clk); |
cfb4f5d1 | 690 | } |
cfb4f5d1 | 691 | } |
0246c471 MD |
692 | atomic_set(&priv->hw_usecnt, -1); |
693 | ||
694 | /* Runtime PM support involves two step for this driver: | |
695 | * 1) Enable Runtime PM | |
696 | * 2) Force Runtime PM Resume since hardware is accessed from probe() | |
697 | */ | |
698 | pm_runtime_enable(priv->dev); | |
699 | pm_runtime_resume(priv->dev); | |
cfb4f5d1 MD |
700 | return 0; |
701 | } | |
702 | ||
703 | static int sh_mobile_lcdc_setcolreg(u_int regno, | |
704 | u_int red, u_int green, u_int blue, | |
705 | u_int transp, struct fb_info *info) | |
706 | { | |
707 | u32 *palette = info->pseudo_palette; | |
708 | ||
709 | if (regno >= PALETTE_NR) | |
710 | return -EINVAL; | |
711 | ||
712 | /* only FB_VISUAL_TRUECOLOR supported */ | |
713 | ||
714 | red >>= 16 - info->var.red.length; | |
715 | green >>= 16 - info->var.green.length; | |
716 | blue >>= 16 - info->var.blue.length; | |
717 | transp >>= 16 - info->var.transp.length; | |
718 | ||
719 | palette[regno] = (red << info->var.red.offset) | | |
720 | (green << info->var.green.offset) | | |
721 | (blue << info->var.blue.offset) | | |
722 | (transp << info->var.transp.offset); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static struct fb_fix_screeninfo sh_mobile_lcdc_fix = { | |
728 | .id = "SH Mobile LCDC", | |
729 | .type = FB_TYPE_PACKED_PIXELS, | |
730 | .visual = FB_VISUAL_TRUECOLOR, | |
731 | .accel = FB_ACCEL_NONE, | |
9dd38819 PE |
732 | .xpanstep = 0, |
733 | .ypanstep = 1, | |
734 | .ywrapstep = 0, | |
cfb4f5d1 MD |
735 | }; |
736 | ||
8564557a MD |
737 | static void sh_mobile_lcdc_fillrect(struct fb_info *info, |
738 | const struct fb_fillrect *rect) | |
739 | { | |
740 | sys_fillrect(info, rect); | |
741 | sh_mobile_lcdc_deferred_io_touch(info); | |
742 | } | |
743 | ||
744 | static void sh_mobile_lcdc_copyarea(struct fb_info *info, | |
745 | const struct fb_copyarea *area) | |
746 | { | |
747 | sys_copyarea(info, area); | |
748 | sh_mobile_lcdc_deferred_io_touch(info); | |
749 | } | |
750 | ||
751 | static void sh_mobile_lcdc_imageblit(struct fb_info *info, | |
752 | const struct fb_image *image) | |
753 | { | |
754 | sys_imageblit(info, image); | |
755 | sh_mobile_lcdc_deferred_io_touch(info); | |
756 | } | |
757 | ||
9dd38819 PE |
758 | static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var, |
759 | struct fb_info *info) | |
760 | { | |
761 | struct sh_mobile_lcdc_chan *ch = info->par; | |
92e1f9a7 PE |
762 | struct sh_mobile_lcdc_priv *priv = ch->lcdc; |
763 | unsigned long ldrcntr; | |
764 | unsigned long new_pan_offset; | |
765 | ||
766 | new_pan_offset = (var->yoffset * info->fix.line_length) + | |
767 | (var->xoffset * (info->var.bits_per_pixel / 8)); | |
9dd38819 | 768 | |
92e1f9a7 | 769 | if (new_pan_offset == ch->pan_offset) |
9dd38819 PE |
770 | return 0; /* No change, do nothing */ |
771 | ||
92e1f9a7 | 772 | ldrcntr = lcdc_read(priv, _LDRCNTR); |
9dd38819 | 773 | |
92e1f9a7 PE |
774 | /* Set the source address for the next refresh */ |
775 | lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset); | |
776 | if (lcdc_chan_is_sublcd(ch)) | |
777 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); | |
778 | else | |
779 | lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS); | |
780 | ||
781 | ch->pan_offset = new_pan_offset; | |
782 | ||
783 | sh_mobile_lcdc_deferred_io_touch(info); | |
9dd38819 PE |
784 | |
785 | return 0; | |
786 | } | |
787 | ||
40331b21 PE |
788 | static int sh_mobile_wait_for_vsync(struct fb_info *info) |
789 | { | |
790 | struct sh_mobile_lcdc_chan *ch = info->par; | |
791 | unsigned long ldintr; | |
792 | int ret; | |
793 | ||
794 | /* Enable VSync End interrupt */ | |
795 | ldintr = lcdc_read(ch->lcdc, _LDINTR); | |
796 | ldintr |= LDINTR_VEE; | |
797 | lcdc_write(ch->lcdc, _LDINTR, ldintr); | |
798 | ||
799 | ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion, | |
800 | msecs_to_jiffies(100)); | |
801 | if (!ret) | |
802 | return -ETIMEDOUT; | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd, | |
808 | unsigned long arg) | |
809 | { | |
810 | int retval; | |
811 | ||
812 | switch (cmd) { | |
813 | case FBIO_WAITFORVSYNC: | |
814 | retval = sh_mobile_wait_for_vsync(info); | |
815 | break; | |
816 | ||
817 | default: | |
818 | retval = -ENOIOCTLCMD; | |
819 | break; | |
820 | } | |
821 | return retval; | |
822 | } | |
823 | ||
824 | ||
cfb4f5d1 | 825 | static struct fb_ops sh_mobile_lcdc_ops = { |
9dd38819 | 826 | .owner = THIS_MODULE, |
cfb4f5d1 | 827 | .fb_setcolreg = sh_mobile_lcdc_setcolreg, |
2540c111 MD |
828 | .fb_read = fb_sys_read, |
829 | .fb_write = fb_sys_write, | |
8564557a MD |
830 | .fb_fillrect = sh_mobile_lcdc_fillrect, |
831 | .fb_copyarea = sh_mobile_lcdc_copyarea, | |
832 | .fb_imageblit = sh_mobile_lcdc_imageblit, | |
9dd38819 | 833 | .fb_pan_display = sh_mobile_fb_pan_display, |
40331b21 | 834 | .fb_ioctl = sh_mobile_ioctl, |
cfb4f5d1 MD |
835 | }; |
836 | ||
837 | static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp) | |
838 | { | |
839 | switch (bpp) { | |
840 | case 16: /* PKF[4:0] = 00011 - RGB 565 */ | |
841 | var->red.offset = 11; | |
842 | var->red.length = 5; | |
843 | var->green.offset = 5; | |
844 | var->green.length = 6; | |
845 | var->blue.offset = 0; | |
846 | var->blue.length = 5; | |
847 | var->transp.offset = 0; | |
848 | var->transp.length = 0; | |
849 | break; | |
850 | ||
851 | case 32: /* PKF[4:0] = 00000 - RGB 888 | |
852 | * sh7722 pdf says 00RRGGBB but reality is GGBB00RR | |
853 | * this may be because LDDDSR has word swap enabled.. | |
854 | */ | |
855 | var->red.offset = 0; | |
856 | var->red.length = 8; | |
857 | var->green.offset = 24; | |
858 | var->green.length = 8; | |
859 | var->blue.offset = 16; | |
860 | var->blue.length = 8; | |
861 | var->transp.offset = 0; | |
862 | var->transp.length = 0; | |
863 | break; | |
864 | default: | |
865 | return -EINVAL; | |
866 | } | |
867 | var->bits_per_pixel = bpp; | |
868 | var->red.msb_right = 0; | |
869 | var->green.msb_right = 0; | |
870 | var->blue.msb_right = 0; | |
871 | var->transp.msb_right = 0; | |
872 | return 0; | |
873 | } | |
874 | ||
2feb075a MD |
875 | static int sh_mobile_lcdc_suspend(struct device *dev) |
876 | { | |
877 | struct platform_device *pdev = to_platform_device(dev); | |
878 | ||
879 | sh_mobile_lcdc_stop(platform_get_drvdata(pdev)); | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static int sh_mobile_lcdc_resume(struct device *dev) | |
884 | { | |
885 | struct platform_device *pdev = to_platform_device(dev); | |
886 | ||
887 | return sh_mobile_lcdc_start(platform_get_drvdata(pdev)); | |
888 | } | |
889 | ||
0246c471 MD |
890 | static int sh_mobile_lcdc_runtime_suspend(struct device *dev) |
891 | { | |
892 | struct platform_device *pdev = to_platform_device(dev); | |
893 | struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev); | |
894 | struct sh_mobile_lcdc_chan *ch; | |
895 | int k, n; | |
896 | ||
897 | /* save per-channel registers */ | |
898 | for (k = 0; k < ARRAY_SIZE(p->ch); k++) { | |
899 | ch = &p->ch[k]; | |
900 | if (!ch->enabled) | |
901 | continue; | |
902 | for (n = 0; n < NR_CH_REGS; n++) | |
903 | ch->saved_ch_regs[n] = lcdc_read_chan(ch, n); | |
904 | } | |
905 | ||
906 | /* save shared registers */ | |
907 | for (n = 0; n < NR_SHARED_REGS; n++) | |
908 | p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]); | |
909 | ||
910 | /* turn off LCDC hardware */ | |
911 | lcdc_write(p, _LDCNT1R, 0); | |
912 | return 0; | |
913 | } | |
914 | ||
915 | static int sh_mobile_lcdc_runtime_resume(struct device *dev) | |
916 | { | |
917 | struct platform_device *pdev = to_platform_device(dev); | |
918 | struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev); | |
919 | struct sh_mobile_lcdc_chan *ch; | |
920 | int k, n; | |
921 | ||
922 | /* restore per-channel registers */ | |
923 | for (k = 0; k < ARRAY_SIZE(p->ch); k++) { | |
924 | ch = &p->ch[k]; | |
925 | if (!ch->enabled) | |
926 | continue; | |
927 | for (n = 0; n < NR_CH_REGS; n++) | |
928 | lcdc_write_chan(ch, n, ch->saved_ch_regs[n]); | |
929 | } | |
930 | ||
931 | /* restore shared registers */ | |
932 | for (n = 0; n < NR_SHARED_REGS; n++) | |
933 | lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
47145210 | 938 | static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { |
2feb075a MD |
939 | .suspend = sh_mobile_lcdc_suspend, |
940 | .resume = sh_mobile_lcdc_resume, | |
0246c471 MD |
941 | .runtime_suspend = sh_mobile_lcdc_runtime_suspend, |
942 | .runtime_resume = sh_mobile_lcdc_runtime_resume, | |
2feb075a MD |
943 | }; |
944 | ||
cfb4f5d1 MD |
945 | static int sh_mobile_lcdc_remove(struct platform_device *pdev); |
946 | ||
c2e13037 | 947 | static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev) |
cfb4f5d1 MD |
948 | { |
949 | struct fb_info *info; | |
950 | struct sh_mobile_lcdc_priv *priv; | |
951 | struct sh_mobile_lcdc_info *pdata; | |
952 | struct sh_mobile_lcdc_chan_cfg *cfg; | |
953 | struct resource *res; | |
954 | int error; | |
955 | void *buf; | |
956 | int i, j; | |
957 | ||
958 | if (!pdev->dev.platform_data) { | |
959 | dev_err(&pdev->dev, "no platform data defined\n"); | |
960 | error = -EINVAL; | |
961 | goto err0; | |
962 | } | |
963 | ||
964 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8564557a MD |
965 | i = platform_get_irq(pdev, 0); |
966 | if (!res || i < 0) { | |
967 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
cfb4f5d1 MD |
968 | error = -ENOENT; |
969 | goto err0; | |
970 | } | |
971 | ||
972 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
973 | if (!priv) { | |
974 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
975 | error = -ENOMEM; | |
976 | goto err0; | |
977 | } | |
978 | ||
8564557a | 979 | error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED, |
7ad33e74 | 980 | dev_name(&pdev->dev), priv); |
8564557a MD |
981 | if (error) { |
982 | dev_err(&pdev->dev, "unable to request irq\n"); | |
983 | goto err1; | |
984 | } | |
985 | ||
986 | priv->irq = i; | |
0246c471 | 987 | priv->dev = &pdev->dev; |
cfb4f5d1 MD |
988 | platform_set_drvdata(pdev, priv); |
989 | pdata = pdev->dev.platform_data; | |
990 | ||
991 | j = 0; | |
992 | for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) { | |
993 | priv->ch[j].lcdc = priv; | |
994 | memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i])); | |
995 | ||
996 | error = sh_mobile_lcdc_check_interface(&priv->ch[i]); | |
997 | if (error) { | |
998 | dev_err(&pdev->dev, "unsupported interface type\n"); | |
999 | goto err1; | |
1000 | } | |
2feb075a | 1001 | init_waitqueue_head(&priv->ch[i].frame_end_wait); |
40331b21 | 1002 | init_completion(&priv->ch[i].vsync_completion); |
9dd38819 | 1003 | priv->ch[j].pan_offset = 0; |
cfb4f5d1 MD |
1004 | |
1005 | switch (pdata->ch[i].chan) { | |
1006 | case LCDC_CHAN_MAINLCD: | |
1007 | priv->ch[j].enabled = 1 << 1; | |
1008 | priv->ch[j].reg_offs = lcdc_offs_mainlcd; | |
1009 | j++; | |
1010 | break; | |
1011 | case LCDC_CHAN_SUBLCD: | |
1012 | priv->ch[j].enabled = 1 << 2; | |
1013 | priv->ch[j].reg_offs = lcdc_offs_sublcd; | |
1014 | j++; | |
1015 | break; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | if (!j) { | |
1020 | dev_err(&pdev->dev, "no channels defined\n"); | |
1021 | error = -EINVAL; | |
1022 | goto err1; | |
1023 | } | |
1024 | ||
b51339ff | 1025 | error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv); |
cfb4f5d1 MD |
1026 | if (error) { |
1027 | dev_err(&pdev->dev, "unable to setup clocks\n"); | |
1028 | goto err1; | |
1029 | } | |
1030 | ||
cfb4f5d1 MD |
1031 | priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1); |
1032 | ||
1033 | for (i = 0; i < j; i++) { | |
cfb4f5d1 MD |
1034 | cfg = &priv->ch[i].cfg; |
1035 | ||
e33afddc PM |
1036 | priv->ch[i].info = framebuffer_alloc(0, &pdev->dev); |
1037 | if (!priv->ch[i].info) { | |
1038 | dev_err(&pdev->dev, "unable to allocate fb_info\n"); | |
1039 | error = -ENOMEM; | |
1040 | break; | |
1041 | } | |
1042 | ||
1043 | info = priv->ch[i].info; | |
cfb4f5d1 MD |
1044 | info->fbops = &sh_mobile_lcdc_ops; |
1045 | info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres; | |
9dd38819 PE |
1046 | info->var.yres = cfg->lcd_cfg.yres; |
1047 | /* Default Y virtual resolution is 2x panel size */ | |
1048 | info->var.yres_virtual = info->var.yres * 2; | |
ce9c008c MD |
1049 | info->var.width = cfg->lcd_size_cfg.width; |
1050 | info->var.height = cfg->lcd_size_cfg.height; | |
cfb4f5d1 MD |
1051 | info->var.activate = FB_ACTIVATE_NOW; |
1052 | error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp); | |
1053 | if (error) | |
1054 | break; | |
1055 | ||
1056 | info->fix = sh_mobile_lcdc_fix; | |
1057 | info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8); | |
9dd38819 PE |
1058 | info->fix.smem_len = info->fix.line_length * |
1059 | info->var.yres_virtual; | |
cfb4f5d1 MD |
1060 | |
1061 | buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len, | |
1062 | &priv->ch[i].dma_handle, GFP_KERNEL); | |
1063 | if (!buf) { | |
1064 | dev_err(&pdev->dev, "unable to allocate buffer\n"); | |
1065 | error = -ENOMEM; | |
1066 | break; | |
1067 | } | |
1068 | ||
1069 | info->pseudo_palette = &priv->ch[i].pseudo_palette; | |
1070 | info->flags = FBINFO_FLAG_DEFAULT; | |
1071 | ||
1072 | error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0); | |
1073 | if (error < 0) { | |
1074 | dev_err(&pdev->dev, "unable to allocate cmap\n"); | |
1075 | dma_free_coherent(&pdev->dev, info->fix.smem_len, | |
1076 | buf, priv->ch[i].dma_handle); | |
1077 | break; | |
1078 | } | |
1079 | ||
1080 | memset(buf, 0, info->fix.smem_len); | |
1081 | info->fix.smem_start = priv->ch[i].dma_handle; | |
1082 | info->screen_base = buf; | |
1083 | info->device = &pdev->dev; | |
8564557a | 1084 | info->par = &priv->ch[i]; |
cfb4f5d1 MD |
1085 | } |
1086 | ||
1087 | if (error) | |
1088 | goto err1; | |
1089 | ||
1090 | error = sh_mobile_lcdc_start(priv); | |
1091 | if (error) { | |
1092 | dev_err(&pdev->dev, "unable to start hardware\n"); | |
1093 | goto err1; | |
1094 | } | |
1095 | ||
1096 | for (i = 0; i < j; i++) { | |
1c6a307a PM |
1097 | struct sh_mobile_lcdc_chan *ch = priv->ch + i; |
1098 | ||
e33afddc | 1099 | info = ch->info; |
1c6a307a PM |
1100 | |
1101 | if (info->fbdefio) { | |
1102 | priv->ch->sglist = vmalloc(sizeof(struct scatterlist) * | |
1103 | info->fix.smem_len >> PAGE_SHIFT); | |
1104 | if (!priv->ch->sglist) { | |
1105 | dev_err(&pdev->dev, "cannot allocate sglist\n"); | |
1106 | goto err1; | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | error = register_framebuffer(info); | |
cfb4f5d1 MD |
1111 | if (error < 0) |
1112 | goto err1; | |
cfb4f5d1 | 1113 | |
cfb4f5d1 MD |
1114 | dev_info(info->dev, |
1115 | "registered %s/%s as %dx%d %dbpp.\n", | |
1116 | pdev->name, | |
1c6a307a | 1117 | (ch->cfg.chan == LCDC_CHAN_MAINLCD) ? |
cfb4f5d1 | 1118 | "mainlcd" : "sublcd", |
1c6a307a PM |
1119 | (int) ch->cfg.lcd_cfg.xres, |
1120 | (int) ch->cfg.lcd_cfg.yres, | |
1121 | ch->cfg.bpp); | |
8564557a MD |
1122 | |
1123 | /* deferred io mode: disable clock to save power */ | |
1124 | if (info->fbdefio) | |
1125 | sh_mobile_lcdc_clk_off(priv); | |
cfb4f5d1 MD |
1126 | } |
1127 | ||
1128 | return 0; | |
1129 | err1: | |
1130 | sh_mobile_lcdc_remove(pdev); | |
1131 | err0: | |
1132 | return error; | |
1133 | } | |
1134 | ||
1135 | static int sh_mobile_lcdc_remove(struct platform_device *pdev) | |
1136 | { | |
1137 | struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev); | |
1138 | struct fb_info *info; | |
1139 | int i; | |
1140 | ||
1141 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) | |
e33afddc PM |
1142 | if (priv->ch[i].info->dev) |
1143 | unregister_framebuffer(priv->ch[i].info); | |
cfb4f5d1 MD |
1144 | |
1145 | sh_mobile_lcdc_stop(priv); | |
1146 | ||
1147 | for (i = 0; i < ARRAY_SIZE(priv->ch); i++) { | |
e33afddc | 1148 | info = priv->ch[i].info; |
cfb4f5d1 | 1149 | |
e33afddc | 1150 | if (!info || !info->device) |
cfb4f5d1 MD |
1151 | continue; |
1152 | ||
1c6a307a PM |
1153 | if (priv->ch[i].sglist) |
1154 | vfree(priv->ch[i].sglist); | |
1155 | ||
cfb4f5d1 MD |
1156 | dma_free_coherent(&pdev->dev, info->fix.smem_len, |
1157 | info->screen_base, priv->ch[i].dma_handle); | |
1158 | fb_dealloc_cmap(&info->cmap); | |
e33afddc | 1159 | framebuffer_release(info); |
cfb4f5d1 MD |
1160 | } |
1161 | ||
b51339ff MD |
1162 | if (priv->dot_clk) |
1163 | clk_put(priv->dot_clk); | |
0246c471 MD |
1164 | |
1165 | pm_runtime_disable(priv->dev); | |
cfb4f5d1 MD |
1166 | |
1167 | if (priv->base) | |
1168 | iounmap(priv->base); | |
1169 | ||
8564557a MD |
1170 | if (priv->irq) |
1171 | free_irq(priv->irq, priv); | |
cfb4f5d1 MD |
1172 | kfree(priv); |
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | static struct platform_driver sh_mobile_lcdc_driver = { | |
1177 | .driver = { | |
1178 | .name = "sh_mobile_lcdc_fb", | |
1179 | .owner = THIS_MODULE, | |
2feb075a | 1180 | .pm = &sh_mobile_lcdc_dev_pm_ops, |
cfb4f5d1 MD |
1181 | }, |
1182 | .probe = sh_mobile_lcdc_probe, | |
1183 | .remove = sh_mobile_lcdc_remove, | |
1184 | }; | |
1185 | ||
1186 | static int __init sh_mobile_lcdc_init(void) | |
1187 | { | |
1188 | return platform_driver_register(&sh_mobile_lcdc_driver); | |
1189 | } | |
1190 | ||
1191 | static void __exit sh_mobile_lcdc_exit(void) | |
1192 | { | |
1193 | platform_driver_unregister(&sh_mobile_lcdc_driver); | |
1194 | } | |
1195 | ||
1196 | module_init(sh_mobile_lcdc_init); | |
1197 | module_exit(sh_mobile_lcdc_exit); | |
1198 | ||
1199 | MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver"); | |
1200 | MODULE_AUTHOR("Magnus Damm <damm@opensource.se>"); | |
1201 | MODULE_LICENSE("GPL v2"); |