[mirror_ubuntu-zesty-kernel.git] / drivers / video / sunxvr500.c

/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
 *
 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/of_device.h>

#include <asm/io.h>

/* XXX This device has a 'dev-comm' property which apparently is
 * XXX a pointer into the openfirmware's address space which is
 * XXX a shared area the kernel driver can use to keep OBP
 * XXX informed about the current resolution setting.  The idea
 * XXX is that the kernel can change resolutions, and as long
 * XXX as the values in the 'dev-comm' area are accurate then
 * XXX OBP can still render text properly to the console.
 * XXX
 * XXX I'm still working out the layout of this and whether there
 * XXX are any signatures we need to look for etc.
 */
struct e3d_info {
	struct fb_info		*info;
	struct pci_dev		*pdev;

	spinlock_t		lock;

	char __iomem		*fb_base;
	unsigned long		fb_base_phys;

	unsigned long		fb8_buf_diff;
	unsigned long		regs_base_phys;

	void __iomem		*ramdac;

	struct device_node	*of_node;

	unsigned int		width;
	unsigned int		height;
	unsigned int		depth;
	unsigned int		fb_size;

	u32			fb_base_reg;
	u32			fb8_0_off;
	u32			fb8_1_off;

	u32			pseudo_palette[16];
};

static int e3d_get_props(struct e3d_info *ep)
{
	ep->width = of_getintprop_default(ep->of_node, "width", 0);
	ep->height = of_getintprop_default(ep->of_node, "height", 0);
	ep->depth = of_getintprop_default(ep->of_node, "depth", 8);

	if (!ep->width || !ep->height) {
		printk(KERN_ERR "e3d: Critical properties missing for %s\n",
		       pci_name(ep->pdev));
		return -EINVAL;
	}

	return 0;
}

/* My XVR-500 comes up, at 1280x768 and a FB base register value of
 * 0x04000000, the following video layout register values:
 *
 * RAMDAC_VID_WH	0x03ff04ff
 * RAMDAC_VID_CFG	0x1a0b0088
 * RAMDAC_VID_32FB_0	0x04000000
 * RAMDAC_VID_32FB_1	0x04800000
 * RAMDAC_VID_8FB_0	0x05000000
 * RAMDAC_VID_8FB_1	0x05200000
 * RAMDAC_VID_XXXFB	0x05400000
 * RAMDAC_VID_YYYFB	0x05c00000
 * RAMDAC_VID_ZZZFB	0x05e00000
 */
/* Video layout registers */
#define RAMDAC_VID_WH		0x00000070UL /* (height-1)<<16 | (width-1) */
#define RAMDAC_VID_CFG		0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
#define RAMDAC_VID_32FB_0	0x00000078UL /* PCI base 32bpp FB buffer 0 */
#define RAMDAC_VID_32FB_1	0x0000007cUL /* PCI base 32bpp FB buffer 1 */
#define RAMDAC_VID_8FB_0	0x00000080UL /* PCI base 8bpp FB buffer 0 */
#define RAMDAC_VID_8FB_1	0x00000084UL /* PCI base 8bpp FB buffer 1 */
#define RAMDAC_VID_XXXFB	0x00000088UL /* PCI base of XXX FB */
#define RAMDAC_VID_YYYFB	0x0000008cUL /* PCI base of YYY FB */
#define RAMDAC_VID_ZZZFB	0x00000090UL /* PCI base of ZZZ FB */

/* CLUT registers */
#define RAMDAC_INDEX		0x000000bcUL
#define RAMDAC_DATA		0x000000c0UL

static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
{
	void __iomem *ramdac = ep->ramdac;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);

	writel(index, ramdac + RAMDAC_INDEX);
	writel(val, ramdac + RAMDAC_DATA);

	spin_unlock_irqrestore(&ep->lock, flags);
}

static int e3d_setcolreg(unsigned regno,
			 unsigned red, unsigned green, unsigned blue,
			 unsigned transp, struct fb_info *info)
{
	struct e3d_info *ep = info->par;
	u32 red_8, green_8, blue_8;
	u32 red_10, green_10, blue_10;
	u32 value;

	if (regno >= 256)
		return 1;

	red_8 = red >> 8;
	green_8 = green >> 8;
	blue_8 = blue >> 8;

	value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);

	if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
		((u32 *)info->pseudo_palette)[regno] = value;


	red_10 = red >> 6;
	green_10 = green >> 6;
	blue_10 = blue >> 6;

	value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
	e3d_clut_write(ep, regno, value);

	return 0;
}

/* XXX This is a bit of a hack.  I can't figure out exactly how the
 * XXX two 8bpp areas of the framebuffer work.  I imagine there is
 * XXX a WID attribute somewhere else in the framebuffer which tells
 * XXX the ramdac which of the two 8bpp framebuffer regions to take
 * XXX the pixel from.  So, for now, render into both regions to make
 * XXX sure the pixel shows up.
 */
static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_imageblit(info, image);
	info->screen_base += ep->fb8_buf_diff;
	cfb_imageblit(info, image);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_fillrect(info, rect);
	info->screen_base += ep->fb8_buf_diff;
	cfb_fillrect(info, rect);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
	struct e3d_info *ep = info->par;
	unsigned long flags;

	spin_lock_irqsave(&ep->lock, flags);
	cfb_copyarea(info, area);
	info->screen_base += ep->fb8_buf_diff;
	cfb_copyarea(info, area);
	info->screen_base -= ep->fb8_buf_diff;
	spin_unlock_irqrestore(&ep->lock, flags);
}

static struct fb_ops e3d_ops = {
	.owner			= THIS_MODULE,
	.fb_setcolreg		= e3d_setcolreg,
	.fb_fillrect		= e3d_fillrect,
	.fb_copyarea		= e3d_copyarea,
	.fb_imageblit		= e3d_imageblit,
};

static int e3d_set_fbinfo(struct e3d_info *ep)
{
	struct fb_info *info = ep->info;
	struct fb_var_screeninfo *var = &info->var;

	info->flags = FBINFO_DEFAULT;
	info->fbops = &e3d_ops;
	info->screen_base = ep->fb_base;
	info->screen_size = ep->fb_size;

	info->pseudo_palette = ep->pseudo_palette;

	/* Fill fix common fields */
	strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
        info->fix.smem_start = ep->fb_base_phys;
        info->fix.smem_len = ep->fb_size;
        info->fix.type = FB_TYPE_PACKED_PIXELS;
	if (ep->depth == 32 || ep->depth == 24)
		info->fix.visual = FB_VISUAL_TRUECOLOR;
	else
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	var->xres = ep->width;
	var->yres = ep->height;
	var->xres_virtual = var->xres;
	var->yres_virtual = var->yres;
	var->bits_per_pixel = ep->depth;

	var->red.offset = 8;
	var->red.length = 8;
	var->green.offset = 16;
	var->green.length = 8;
	var->blue.offset = 24;
	var->blue.length = 8;
	var->transp.offset = 0;
	var->transp.length = 0;

	if (fb_alloc_cmap(&info->cmap, 256, 0)) {
		printk(KERN_ERR "e3d: Cannot allocate color map.\n");
		return -ENOMEM;
	}

        return 0;
}

static int e3d_pci_register(struct pci_dev *pdev,
			    const struct pci_device_id *ent)
{
	struct device_node *of_node;
	const char *device_type;
	struct fb_info *info;
	struct e3d_info *ep;
	unsigned int line_length;
	int err;

	of_node = pci_device_to_OF_node(pdev);
	if (!of_node) {
		printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
		       pci_name(pdev));
		return -ENODEV;
	}

	device_type = of_get_property(of_node, "device_type", NULL);
	if (!device_type) {
		printk(KERN_INFO "e3d: Ignoring secondary output device "
		       "at %s\n", pci_name(pdev));
		return -ENODEV;
	}

	err = pci_enable_device(pdev);
	if (err < 0) {
		printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
		       pci_name(pdev));
		goto err_out;
	}

	info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
	if (!info) {
		printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
		err = -ENOMEM;
		goto err_disable;
	}

	ep = info->par;
	ep->info = info;
	ep->pdev = pdev;
	spin_lock_init(&ep->lock);
	ep->of_node = of_node;

	/* Read the PCI base register of the frame buffer, which we
	 * need in order to interpret the RAMDAC_VID_*FB* values in
	 * the ramdac correctly.
	 */
	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
			      &ep->fb_base_reg);
	ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;

	ep->regs_base_phys = pci_resource_start (pdev, 1);
	err = pci_request_region(pdev, 1, "e3d regs");
	if (err < 0) {
		printk("e3d: Cannot request region 1 for %s\n",
		       pci_name(pdev));
		goto err_release_fb;
	}
	ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
	if (!ep->ramdac) {
		err = -ENOMEM;
		goto err_release_pci1;
	}

	ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
	ep->fb8_0_off -= ep->fb_base_reg;

	ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
	ep->fb8_1_off -= ep->fb_base_reg;

	ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;

	ep->fb_base_phys = pci_resource_start (pdev, 0);
	ep->fb_base_phys += ep->fb8_0_off;

	err = pci_request_region(pdev, 0, "e3d framebuffer");
	if (err < 0) {
		printk("e3d: Cannot request region 0 for %s\n",
		       pci_name(pdev));
		goto err_unmap_ramdac;
	}

	err = e3d_get_props(ep);
	if (err)
		goto err_release_pci0;

	line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
	line_length = 1 << line_length;

	switch (ep->depth) {
	case 8:
		info->fix.line_length = line_length;
		break;
	case 16:
		info->fix.line_length = line_length * 2;
		break;
	case 24:
		info->fix.line_length = line_length * 3;
		break;
	case 32:
		info->fix.line_length = line_length * 4;
		break;
	}
	ep->fb_size = info->fix.line_length * ep->height;

	ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
	if (!ep->fb_base) {
		err = -ENOMEM;
		goto err_release_pci0;
	}

	err = e3d_set_fbinfo(ep);
	if (err)
		goto err_unmap_fb;

	pci_set_drvdata(pdev, info);

	printk("e3d: Found device at %s\n", pci_name(pdev));

	err = register_framebuffer(info);
	if (err < 0) {
		printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
		       pci_name(pdev));
		goto err_free_cmap;
	}

	return 0;

err_free_cmap:
	fb_dealloc_cmap(&info->cmap);

err_unmap_fb:
	iounmap(ep->fb_base);

err_release_pci0:
	pci_release_region(pdev, 0);

err_unmap_ramdac:
	iounmap(ep->ramdac);

err_release_pci1:
	pci_release_region(pdev, 1);

err_release_fb:
        framebuffer_release(info);

err_disable:
	pci_disable_device(pdev);

err_out:
	return err;
}

static void e3d_pci_unregister(struct pci_dev *pdev)
{
	struct fb_info *info = pci_get_drvdata(pdev);
	struct e3d_info *ep = info->par;

	unregister_framebuffer(info);

	iounmap(ep->ramdac);
	iounmap(ep->fb_base);

	pci_release_region(pdev, 0);
	pci_release_region(pdev, 1);

	fb_dealloc_cmap(&info->cmap);
        framebuffer_release(info);

	pci_disable_device(pdev);
}

static struct pci_device_id e3d_pci_table[] = {
	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0),	},
	{	PCI_DEVICE(0x1091, 0x7a0),			},
	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2),	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x0108,
	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x0140,
	},
	{	.vendor = PCI_VENDOR_ID_3DLABS,
		.device = PCI_ANY_ID,
		.subvendor = PCI_VENDOR_ID_3DLABS,
		.subdevice = 0x1024,
	},
	{ 0, }
};

static struct pci_driver e3d_driver = {
	.name		= "e3d",
	.id_table	= e3d_pci_table,
	.probe		= e3d_pci_register,
	.remove		= e3d_pci_unregister,
};

static int __init e3d_init(void)
{
	if (fb_get_options("e3d", NULL))
		return -ENODEV;

	return pci_register_driver(&e3d_driver);
}

static void __exit e3d_exit(void)
{
	pci_unregister_driver(&e3d_driver);
}

module_init(e3d_init);
module_exit(e3d_exit);

MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
453e93b3 DM	1	/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
	2	*
	3	* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
	4	*/
	5
	6	#include <linux/module.h>
	7	#include <linux/kernel.h>
453e93b3 DM	8	#include <linux/fb.h>
	9	#include <linux/pci.h>
	10	#include <linux/init.h>
6cd5a86b	11	#include <linux/of_device.h>
453e93b3 DM	12
453e93b3 DM	13	#include <asm/io.h>
453e93b3	14
ff0c2642	15	/* XXX This device has a 'dev-comm' property which apparently is
453e93b3 DM	16	* XXX a pointer into the openfirmware's address space which is
	17	* XXX a shared area the kernel driver can use to keep OBP
	18	* XXX informed about the current resolution setting. The idea
	19	* XXX is that the kernel can change resolutions, and as long
	20	* XXX as the values in the 'dev-comm' area are accurate then
	21	* XXX OBP can still render text properly to the console.
	22	* XXX
	23	* XXX I'm still working out the layout of this and whether there
	24	* XXX are any signatures we need to look for etc.
	25	*/
	26	struct e3d_info {
	27	struct fb_info *info;
	28	struct pci_dev *pdev;
	29
	30	spinlock_t lock;
	31
	32	char __iomem *fb_base;
	33	unsigned long fb_base_phys;
	34
	35	unsigned long fb8_buf_diff;
	36	unsigned long regs_base_phys;
	37
	38	void __iomem *ramdac;
	39
	40	struct device_node *of_node;
	41
	42	unsigned int width;
	43	unsigned int height;
	44	unsigned int depth;
	45	unsigned int fb_size;
	46
	47	u32 fb_base_reg;
	48	u32 fb8_0_off;
	49	u32 fb8_1_off;
	50
e7e8cc5a	51	u32 pseudo_palette[16];
453e93b3 DM	52	};
453e93b3 DM	53
48c68c4f	54	static int e3d_get_props(struct e3d_info *ep)
453e93b3 DM	55	{
	56	ep->width = of_getintprop_default(ep->of_node, "width", 0);
	57	ep->height = of_getintprop_default(ep->of_node, "height", 0);
	58	ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
	59
	60	if (!ep->width \|\| !ep->height) {
	61	printk(KERN_ERR "e3d: Critical properties missing for %s\n",
	62	pci_name(ep->pdev));
	63	return -EINVAL;
	64	}
	65
	66	return 0;
	67	}
	68
	69	/* My XVR-500 comes up, at 1280x768 and a FB base register value of
	70	* 0x04000000, the following video layout register values:
	71	*
	72	* RAMDAC_VID_WH 0x03ff04ff
	73	* RAMDAC_VID_CFG 0x1a0b0088
	74	* RAMDAC_VID_32FB_0 0x04000000
	75	* RAMDAC_VID_32FB_1 0x04800000
	76	* RAMDAC_VID_8FB_0 0x05000000
	77	* RAMDAC_VID_8FB_1 0x05200000
	78	* RAMDAC_VID_XXXFB 0x05400000
	79	* RAMDAC_VID_YYYFB 0x05c00000
	80	* RAMDAC_VID_ZZZFB 0x05e00000
	81	*/
	82	/* Video layout registers */
	83	#define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 \| (width-1) */
	84	#define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088\|(linesz_log2<<16) */
	85	#define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
	86	#define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
	87	#define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
	88	#define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
	89	#define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */
	90	#define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */
	91	#define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */
	92
	93	/* CLUT registers */
	94	#define RAMDAC_INDEX 0x000000bcUL
	95	#define RAMDAC_DATA 0x000000c0UL
	96
	97	static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
	98	{
	99	void __iomem *ramdac = ep->ramdac;
	100	unsigned long flags;
	101
	102	spin_lock_irqsave(&ep->lock, flags);
	103
	104	writel(index, ramdac + RAMDAC_INDEX);
	105	writel(val, ramdac + RAMDAC_DATA);
	106
	107	spin_unlock_irqrestore(&ep->lock, flags);
	108	}
	109
	110	static int e3d_setcolreg(unsigned regno,
	111	unsigned red, unsigned green, unsigned blue,
	112	unsigned transp, struct fb_info *info)
	113	{
	114	struct e3d_info *ep = info->par;
	115	u32 red_8, green_8, blue_8;
	116	u32 red_10, green_10, blue_10;
	117	u32 value;
	118
119	if (regno >= 256)
120	return 1;
121
122	red_8 = red >> 8;
123	green_8 = green >> 8;
124	blue_8 = blue >> 8;
125
126	value = (blue_8 << 24) \| (green_8 << 16) \| (red_8 << 8);
e7e8cc5a AD	127
	128	if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
	129	((u32 *)info->pseudo_palette)[regno] = value;
453e93b3 DM	130
	131
	132	red_10 = red >> 6;
	133	green_10 = green >> 6;
	134	blue_10 = blue >> 6;
	135
	136	value = (blue_10 << 20) \| (green_10 << 10) \| (red_10 << 0);
	137	e3d_clut_write(ep, regno, value);
	138
	139	return 0;
	140	}
	141
	142	/* XXX This is a bit of a hack. I can't figure out exactly how the
	143	* XXX two 8bpp areas of the framebuffer work. I imagine there is
	144	* XXX a WID attribute somewhere else in the framebuffer which tells
	145	* XXX the ramdac which of the two 8bpp framebuffer regions to take
	146	* XXX the pixel from. So, for now, render into both regions to make
	147	* XXX sure the pixel shows up.
	148	*/
	149	static void e3d_imageblit(struct fb_info info, const struct fb_image image)
	150	{
	151	struct e3d_info *ep = info->par;
	152	unsigned long flags;
	153
	154	spin_lock_irqsave(&ep->lock, flags);
	155	cfb_imageblit(info, image);
	156	info->screen_base += ep->fb8_buf_diff;
	157	cfb_imageblit(info, image);
	158	info->screen_base -= ep->fb8_buf_diff;
	159	spin_unlock_irqrestore(&ep->lock, flags);
	160	}
	161
	162	static void e3d_fillrect(struct fb_info info, const struct fb_fillrect rect)
	163	{
	164	struct e3d_info *ep = info->par;
	165	unsigned long flags;
	166
	167	spin_lock_irqsave(&ep->lock, flags);
	168	cfb_fillrect(info, rect);
	169	info->screen_base += ep->fb8_buf_diff;
	170	cfb_fillrect(info, rect);
	171	info->screen_base -= ep->fb8_buf_diff;
	172	spin_unlock_irqrestore(&ep->lock, flags);
	173	}
	174
	175	static void e3d_copyarea(struct fb_info info, const struct fb_copyarea area)
	176	{
	177	struct e3d_info *ep = info->par;
	178	unsigned long flags;
	179
	180	spin_lock_irqsave(&ep->lock, flags);
	181	cfb_copyarea(info, area);
	182	info->screen_base += ep->fb8_buf_diff;
	183	cfb_copyarea(info, area);
	184	info->screen_base -= ep->fb8_buf_diff;
	185	spin_unlock_irqrestore(&ep->lock, flags);
	186	}
	187
	188	static struct fb_ops e3d_ops = {
	189	.owner = THIS_MODULE,
	190	.fb_setcolreg = e3d_setcolreg,
	191	.fb_fillrect = e3d_fillrect,
	192	.fb_copyarea = e3d_copyarea,
	193	.fb_imageblit = e3d_imageblit,
194	};
195
48c68c4f	196	static int e3d_set_fbinfo(struct e3d_info *ep)
453e93b3 DM	197	{
	198	struct fb_info *info = ep->info;
	199	struct fb_var_screeninfo *var = &info->var;
	200
	201	info->flags = FBINFO_DEFAULT;
	202	info->fbops = &e3d_ops;
	203	info->screen_base = ep->fb_base;
	204	info->screen_size = ep->fb_size;
	205
	206	info->pseudo_palette = ep->pseudo_palette;
	207
	208	/* Fill fix common fields */
	209	strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
	210	info->fix.smem_start = ep->fb_base_phys;
	211	info->fix.smem_len = ep->fb_size;
	212	info->fix.type = FB_TYPE_PACKED_PIXELS;
	213	if (ep->depth == 32 \|\| ep->depth == 24)
	214	info->fix.visual = FB_VISUAL_TRUECOLOR;
	215	else
	216	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	217
	218	var->xres = ep->width;
	219	var->yres = ep->height;
	220	var->xres_virtual = var->xres;
	221	var->yres_virtual = var->yres;
	222	var->bits_per_pixel = ep->depth;
	223
	224	var->red.offset = 8;
	225	var->red.length = 8;
	226	var->green.offset = 16;
	227	var->green.length = 8;
	228	var->blue.offset = 24;
	229	var->blue.length = 8;
	230	var->transp.offset = 0;
	231	var->transp.length = 0;
	232
	233	if (fb_alloc_cmap(&info->cmap, 256, 0)) {
	234	printk(KERN_ERR "e3d: Cannot allocate color map.\n");
	235	return -ENOMEM;
	236	}
	237
	238	return 0;
	239	}
	240
48c68c4f GKH	241	static int e3d_pci_register(struct pci_dev *pdev,
48c68c4f GKH	242	const struct pci_device_id *ent)
453e93b3	243	{
bdd32ce9 DM	244	struct device_node *of_node;
bdd32ce9 DM	245	const char *device_type;
453e93b3 DM	246	struct fb_info *info;
	247	struct e3d_info *ep;
	248	unsigned int line_length;
	249	int err;
	250
bdd32ce9 DM	251	of_node = pci_device_to_OF_node(pdev);
	252	if (!of_node) {
	253	printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
	254	pci_name(pdev));
	255	return -ENODEV;
	256	}
	257
	258	device_type = of_get_property(of_node, "device_type", NULL);
	259	if (!device_type) {
	260	printk(KERN_INFO "e3d: Ignoring secondary output device "
	261	"at %s\n", pci_name(pdev));
	262	return -ENODEV;
	263	}
	264
453e93b3 DM	265	err = pci_enable_device(pdev);
	266	if (err < 0) {
	267	printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
	268	pci_name(pdev));
	269	goto err_out;
	270	}
	271
	272	info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
	273	if (!info) {
	274	printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
	275	err = -ENOMEM;
	276	goto err_disable;
	277	}
	278
	279	ep = info->par;
	280	ep->info = info;
	281	ep->pdev = pdev;
	282	spin_lock_init(&ep->lock);
bdd32ce9	283	ep->of_node = of_node;
453e93b3 DM	284
	285	/* Read the PCI base register of the frame buffer, which we
	286	* need in order to interpret the RAMDAC_VID_FB values in
	287	* the ramdac correctly.
	288	*/
	289	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
	290	&ep->fb_base_reg);
	291	ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
	292
	293	ep->regs_base_phys = pci_resource_start (pdev, 1);
	294	err = pci_request_region(pdev, 1, "e3d regs");
	295	if (err < 0) {
	296	printk("e3d: Cannot request region 1 for %s\n",
	297	pci_name(pdev));
	298	goto err_release_fb;
	299	}
	300	ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
b157dd1c PST	301	if (!ep->ramdac) {
b157dd1c PST	302	err = -ENOMEM;
453e93b3	303	goto err_release_pci1;
b157dd1c	304	}
453e93b3 DM	305
	306	ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
	307	ep->fb8_0_off -= ep->fb_base_reg;
	308
	309	ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
	310	ep->fb8_1_off -= ep->fb_base_reg;
	311
	312	ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
	313
	314	ep->fb_base_phys = pci_resource_start (pdev, 0);
	315	ep->fb_base_phys += ep->fb8_0_off;
	316
	317	err = pci_request_region(pdev, 0, "e3d framebuffer");
	318	if (err < 0) {
	319	printk("e3d: Cannot request region 0 for %s\n",
	320	pci_name(pdev));
	321	goto err_unmap_ramdac;
	322	}
	323
	324	err = e3d_get_props(ep);
	325	if (err)
	326	goto err_release_pci0;
	327
	328	line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
	329	line_length = 1 << line_length;
	330
	331	switch (ep->depth) {
	332	case 8:
	333	info->fix.line_length = line_length;
	334	break;
	335	case 16:
	336	info->fix.line_length = line_length * 2;
	337	break;
	338	case 24:
	339	info->fix.line_length = line_length * 3;
	340	break;
	341	case 32:
	342	info->fix.line_length = line_length * 4;
	343	break;
	344	}
	345	ep->fb_size = info->fix.line_length * ep->height;
	346
	347	ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
b157dd1c PST	348	if (!ep->fb_base) {
b157dd1c PST	349	err = -ENOMEM;
453e93b3	350	goto err_release_pci0;
b157dd1c	351	}
453e93b3 DM	352
	353	err = e3d_set_fbinfo(ep);
	354	if (err)
	355	goto err_unmap_fb;
	356
	357	pci_set_drvdata(pdev, info);
	358
	359	printk("e3d: Found device at %s\n", pci_name(pdev));
	360
	361	err = register_framebuffer(info);
	362	if (err < 0) {
	363	printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
	364	pci_name(pdev));
cc880a71	365	goto err_free_cmap;
453e93b3 DM	366	}
	367
	368	return 0;
	369
cc880a71 AS	370	err_free_cmap:
	371	fb_dealloc_cmap(&info->cmap);
	372
453e93b3 DM	373	err_unmap_fb:
	374	iounmap(ep->fb_base);
	375
	376	err_release_pci0:
	377	pci_release_region(pdev, 0);
	378
	379	err_unmap_ramdac:
	380	iounmap(ep->ramdac);
	381
	382	err_release_pci1:
	383	pci_release_region(pdev, 1);
	384
	385	err_release_fb:
	386	framebuffer_release(info);
	387
	388	err_disable:
	389	pci_disable_device(pdev);
	390
	391	err_out:
	392	return err;
	393	}
	394
48c68c4f	395	static void e3d_pci_unregister(struct pci_dev *pdev)
453e93b3 DM	396	{
	397	struct fb_info *info = pci_get_drvdata(pdev);
	398	struct e3d_info *ep = info->par;
	399
	400	unregister_framebuffer(info);
	401
	402	iounmap(ep->ramdac);
	403	iounmap(ep->fb_base);
	404
	405	pci_release_region(pdev, 0);
	406	pci_release_region(pdev, 1);
	407
cc880a71	408	fb_dealloc_cmap(&info->cmap);
453e93b3 DM	409	framebuffer_release(info);
	410
	411	pci_disable_device(pdev);
	412	}
	413
	414	static struct pci_device_id e3d_pci_table[] = {
	415	{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), },
275143e9	416	{ PCI_DEVICE(0x1091, 0x7a0), },
453e93b3 DM	417	{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), },
	418	{ .vendor = PCI_VENDOR_ID_3DLABS,
	419	.device = PCI_ANY_ID,
	420	.subvendor = PCI_VENDOR_ID_3DLABS,
	421	.subdevice = 0x0108,
	422	},
	423	{ .vendor = PCI_VENDOR_ID_3DLABS,
	424	.device = PCI_ANY_ID,
	425	.subvendor = PCI_VENDOR_ID_3DLABS,
	426	.subdevice = 0x0140,
	427	},
	428	{ .vendor = PCI_VENDOR_ID_3DLABS,
	429	.device = PCI_ANY_ID,
	430	.subvendor = PCI_VENDOR_ID_3DLABS,
	431	.subdevice = 0x1024,
	432	},
	433	{ 0, }
	434	};
	435
	436	static struct pci_driver e3d_driver = {
	437	.name = "e3d",
	438	.id_table = e3d_pci_table,
	439	.probe = e3d_pci_register,
48c68c4f	440	.remove = e3d_pci_unregister,
453e93b3 DM	441	};
	442
	443	static int __init e3d_init(void)
	444	{
	445	if (fb_get_options("e3d", NULL))
	446	return -ENODEV;
	447
	448	return pci_register_driver(&e3d_driver);
	449	}
	450
	451	static void __exit e3d_exit(void)
	452	{
	453	pci_unregister_driver(&e3d_driver);
	454	}
	455
	456	module_init(e3d_init);
	457	module_exit(e3d_exit);
	458
	459	MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
	460	MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
	461	MODULE_VERSION("1.0");
	462	MODULE_LICENSE("GPL");